[gem5-dev] Re: [gem5-users] Assistance Required - Assertion Failure in RegFile
Hi, I believe this has been fixed by the following patch [1] which is currently merged on the develop branch and will be part of v23.0. Let me know if it fixes your problem Kind Regards Giacomo [1]: https://gem5-review.googlesource.com/c/public/gem5/+/70697 From: Alexandra-Nicoleta DAVID via gem5-users Sent: 14 June 2023 11:41 To: gem5-users ; gem5-dev ; 429442672 <429442...@qq.com> Cc: Alexandra-Nicoleta DAVID Subject: [gem5-users] Assistance Required - Assertion Failure in RegFile Dear gem5 Community, I am currently using the gem5 simulator version 22.1.0.0, compiled on June 14, 2023, for my research work and I have encountered an issue that I need help with. During the simulation, the program aborts with an assertion failure in the register file. The error message is: cCopy code gem5.opt: build/ARM/cpu/regfile.hh:75: const Reg& gem5::RegFile::reg(size_t) const [with Reg = long unsigned int; size_t = long unsigned int]: Assertion `sizeof(Reg) == _regBytes && idx < _size' failed. Program aborted at tick 94517000 The command that I used to run the simulation is: bashCopy code ./build/ARM/gem5.opt --debug-flags=MinorExecuteOp --debug-file=fadd1.txt configs/example/arm/starter_se.py --cpu="hpi" --num-cores=1 "/home/david1136/ARM/se-benchmarks/FloatMM" I have tried to diagnose the problem myself, but I haven't been able to identify the root cause. I believe this issue might be related to an incorrect register access, although I am not entirely certain. I have checked my configuration and my setup, and everything appears to be correct. Could you provide me with some guidance on how to troubleshoot this problem, or indicate whether this is a known issue that could be resolved with a patch or an update to the gem5 version I am using? Any help you can provide would be greatly appreciated. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[release-staging-v23-0]: arch-arm: Apply FEAT_IDST to missing ID registers
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/71178?usp=email ) Change subject: arch-arm: Apply FEAT_IDST to missing ID registers .. arch-arm: Apply FEAT_IDST to missing ID registers When FEAT_IDST got implemented [1], we forgot to add the logic for AArch64 ID registers tracking AArch32 state/capabilities [1]: https://gem5-review.googlesource.com/c/public/gem5/+/70723 Signed-off-by: Giacomo Travaglini Change-Id: I19bddf67ecc379a14f91cfede385692536982101 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71178 Reviewed-by: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Richard Cooper Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce Maintainer: Jason Lowe-Power --- M src/arch/arm/regs/misc.cc 1 file changed, 21 insertions(+), 0 deletions(-) Approvals: Bobby Bruce: Looks good to me, approved; Looks good to me, approved Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved Richard Cooper: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index f32aa72..f1c69cc 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3911,83 +3911,104 @@ .mapsTo(MISCREG_MIDR); InitReg(MISCREG_MPIDR_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .mapsTo(MISCREG_MPIDR); InitReg(MISCREG_REVIDR_EL1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid1)) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_PFR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_PFR0); InitReg(MISCREG_ID_PFR1_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_PFR1); InitReg(MISCREG_ID_DFR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_DFR0); InitReg(MISCREG_ID_AFR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_AFR0); InitReg(MISCREG_ID_MMFR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR0); InitReg(MISCREG_ID_MMFR1_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR1); InitReg(MISCREG_ID_MMFR2_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR2); InitReg(MISCREG_ID_MMFR3_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR3); InitReg(MISCREG_ID_MMFR4_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR4); InitReg(MISCREG_ID_ISAR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR0); InitReg(MISCREG_ID_ISAR1_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR1); InitReg(MISCREG_ID_ISAR2_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR2); InitReg(MISCREG_ID_ISAR3_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR3); InitReg(MISCREG_ID_ISAR4_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR4); InitReg(MISCREG_ID_ISAR5_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR5); InitReg(MISCREG_ID_ISAR6_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR6); InitReg(MISCREG_MVFR0_EL1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .allPrivileges().exceptUserMode().writes(0) .mapsTo(MISCREG_MVFR0); InitReg(MISCREG_MVFR1_EL1) + .faultRead
[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Treat GICv3 reserved addresses as RES0
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/71138?usp=email ) Change subject: dev-arm: Treat GICv3 reserved addresses as RES0 .. dev-arm: Treat GICv3 reserved addresses as RES0 According to the GIC specification (IHI0069) reserved addresses in the GIC memory map are treated as RES0. We allow to disable this behaviour and panic instead (reserved_res0 = False, which is what we have been doing so far) to catch development bugs (in gem5 and in the guest SW) Change-Id: I23f98519c2f256c092a52425735b8792bae7a2c7 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71138 Reviewed-by: Richard Cooper Tested-by: kokoro --- M src/dev/arm/Gic.py M src/dev/arm/gic_v3.hh M src/dev/arm/gic_v3_distributor.cc M src/dev/arm/gic_v3_redistributor.cc 4 files changed, 26 insertions(+), 6 deletions(-) Approvals: Richard Cooper: Looks good to me, approved kokoro: Regressions pass Giacomo Travaglini: Looks good to me, approved diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py index 41d602b..6fd8eb2 100644 --- a/src/dev/arm/Gic.py +++ b/src/dev/arm/Gic.py @@ -315,6 +315,15 @@ gicv4 = Param.Bool(False, "GIC is GICv4 compatible") +reserved_is_res0 = Param.Bool( +True, +"According to the GIC specification (IHI0069) " +"reserved addresses in the GIC memory map are treated as RES0. " +"We allow to disable this behaviour and panic instead " +"(reserved_res0 = False) to catch development bugs " +"(in gem5 and in the guest SW)", +) + def interruptCells(self, int_type, int_num, int_trigger, partition=None): """ Interupt cells generation helper: diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh index 2ea6a98..7adb1d0 100644 --- a/src/dev/arm/gic_v3.hh +++ b/src/dev/arm/gic_v3.hh @@ -167,6 +167,17 @@ Tick write(PacketPtr pkt) override; bool supportsVersion(GicVersion version) override; +template +void +reserved(const char* fmt, Args... args) const +{ +if (params().reserved_is_res0) { +warn(fmt, args...); +} else { +panic(fmt, args...); +} +} + public: Gicv3(const Params &p); diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc index 1cb485c..af30692 100644 --- a/src/dev/arm/gic_v3_distributor.cc +++ b/src/dev/arm/gic_v3_distributor.cc @@ -505,8 +505,8 @@ return 0; // RES0 default: -panic("Gicv3Distributor::read(): invalid offset %#x\n", addr); -break; +gic->reserved("Gicv3Distributor::read(): invalid offset %#x\n", addr); +return 0; // RES0 } } @@ -999,7 +999,7 @@ } default: -panic("Gicv3Distributor::write(): invalid offset %#x\n", addr); +gic->reserved("Gicv3Distributor::write(): invalid offset %#x\n", addr); break; } } diff --git a/src/dev/arm/gic_v3_redistributor.cc b/src/dev/arm/gic_v3_redistributor.cc index e4380ef..67d6e42 100644 --- a/src/dev/arm/gic_v3_redistributor.cc +++ b/src/dev/arm/gic_v3_redistributor.cc @@ -377,8 +377,8 @@ return 0; default: -panic("Gicv3Redistributor::read(): invalid offset %#x\n", addr); -break; +gic->reserved("Gicv3Redistributor::read(): invalid offset %#x\n", addr); +return 0; // RES0 } } @@ -704,7 +704,7 @@ } default: -panic("Gicv3Redistributor::write(): invalid offset %#x\n", addr); +gic->reserved("Gicv3Redistributor::write(): invalid offset %#x\n", addr); break; } } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/71138?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I23f98519c2f256c092a52425735b8792bae7a2c7 Gerrit-Change-Number: 71138 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro Gerrit-CC: Bobby Bruce ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] Re: State of Arm SVE2 in gem5
Hi Jason, So far only a subset of SVE2 instructions have been pushed/merged to develop (some by me, some by Prajwal, here CCed) Kind Regards Giacomo From: Jason Lowe-Power Date: Friday, 2 June 2023 at 15:47 To: gem5 Developer List Cc: Giacomo Travaglini Subject: State of Arm SVE2 in gem5 Hi Giacomo, I've noticed that you've been pushing a number of updates to the Arm ISA, some of which are implementing Arm SVE2 instructions (I believe). Could you let us know what the current status is of these instructions? Have all of them been integrated into gem5 or just a subset? Thanks! Jason IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[release-staging-v23-0]: arch-arm: Apply FEAT_IDST to AArch32 state registers
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71178?usp=email ) Change subject: arch-arm: Apply FEAT_IDST to AArch32 state registers .. arch-arm: Apply FEAT_IDST to AArch32 state registers When FEAT_IDST got implemented [1], we forgot to add the logic for ID registers tracking AArch32 state/capabilities [1]: https://gem5-review.googlesource.com/c/public/gem5/+/70723 Signed-off-by: Giacomo Travaglini Change-Id: I19bddf67ecc379a14f91cfede385692536982101 --- M src/arch/arm/regs/misc.cc 1 file changed, 21 insertions(+), 0 deletions(-) diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index f32aa72..f1c69cc 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3911,83 +3911,104 @@ .mapsTo(MISCREG_MIDR); InitReg(MISCREG_MPIDR_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .mapsTo(MISCREG_MPIDR); InitReg(MISCREG_REVIDR_EL1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid1)) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_PFR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_PFR0); InitReg(MISCREG_ID_PFR1_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_PFR1); InitReg(MISCREG_ID_DFR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_DFR0); InitReg(MISCREG_ID_AFR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_AFR0); InitReg(MISCREG_ID_MMFR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR0); InitReg(MISCREG_ID_MMFR1_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR1); InitReg(MISCREG_ID_MMFR2_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR2); InitReg(MISCREG_ID_MMFR3_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR3); InitReg(MISCREG_ID_MMFR4_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR4); InitReg(MISCREG_ID_ISAR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR0); InitReg(MISCREG_ID_ISAR1_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR1); InitReg(MISCREG_ID_ISAR2_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR2); InitReg(MISCREG_ID_ISAR3_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR3); InitReg(MISCREG_ID_ISAR4_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR4); InitReg(MISCREG_ID_ISAR5_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR5); InitReg(MISCREG_ID_ISAR6_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR6); InitReg(MISCREG_MVFR0_EL1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .allPrivileges().exceptUserMode().writes(0) .mapsTo(MISCREG_MVFR0); InitReg(MISCREG_MVFR1_EL1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .allPrivileges().exceptUserMode().writes(0) .mapsTo(MISCREG_MVFR1); InitReg(MISCREG_MVFR2_EL1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_AA64PFR0_EL1) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/71178?usp=email To unsubscribe, or for help writing mail filters
[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Treat GICv3 reserved addresses as RES0
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71138?usp=email ) Change subject: dev-arm: Treat GICv3 reserved addresses as RES0 .. dev-arm: Treat GICv3 reserved addresses as RES0 According to the GIC specification (IHI0069) reserved addresses in the GIC memory map are treated as RES0. We allow to disable this behaviour and panic instead (reserved_res0 = False, which is what we have been doing so far) to catch development bugs (in gem5 and in the guest SW) Change-Id: I23f98519c2f256c092a52425735b8792bae7a2c7 Signed-off-by: Giacomo Travaglini --- M src/dev/arm/Gic.py M src/dev/arm/gic_v3.hh M src/dev/arm/gic_v3_distributor.cc M src/dev/arm/gic_v3_redistributor.cc 4 files changed, 26 insertions(+), 6 deletions(-) diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py index 41d602b..02df33f 100644 --- a/src/dev/arm/Gic.py +++ b/src/dev/arm/Gic.py @@ -315,6 +315,15 @@ gicv4 = Param.Bool(False, "GIC is GICv4 compatible") +reserved_res0 = Param.Bool( +True, +"According to the GIC specification (IHI0069) " +"reserved addresses in the GIC memory map are treated as RES0. " +"We allow to disable this behaviour and panic instead " +"(reserved_res0 = False) to catch development bugs " +"(in gem5 and in the guest SW)", +) + def interruptCells(self, int_type, int_num, int_trigger, partition=None): """ Interupt cells generation helper: diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh index 2ea6a98..80c5afd 100644 --- a/src/dev/arm/gic_v3.hh +++ b/src/dev/arm/gic_v3.hh @@ -167,6 +167,17 @@ Tick write(PacketPtr pkt) override; bool supportsVersion(GicVersion version) override; +template +void +reserved(const char* fmt, Args... args) const +{ +if (params().reserved_res0) { +warn(fmt, args...); +} else { +panic(fmt, args...); +} +} + public: Gicv3(const Params &p); diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc index 1cb485c..af30692 100644 --- a/src/dev/arm/gic_v3_distributor.cc +++ b/src/dev/arm/gic_v3_distributor.cc @@ -505,8 +505,8 @@ return 0; // RES0 default: -panic("Gicv3Distributor::read(): invalid offset %#x\n", addr); -break; +gic->reserved("Gicv3Distributor::read(): invalid offset %#x\n", addr); +return 0; // RES0 } } @@ -999,7 +999,7 @@ } default: -panic("Gicv3Distributor::write(): invalid offset %#x\n", addr); +gic->reserved("Gicv3Distributor::write(): invalid offset %#x\n", addr); break; } } diff --git a/src/dev/arm/gic_v3_redistributor.cc b/src/dev/arm/gic_v3_redistributor.cc index e4380ef..67d6e42 100644 --- a/src/dev/arm/gic_v3_redistributor.cc +++ b/src/dev/arm/gic_v3_redistributor.cc @@ -377,8 +377,8 @@ return 0; default: -panic("Gicv3Redistributor::read(): invalid offset %#x\n", addr); -break; +gic->reserved("Gicv3Redistributor::read(): invalid offset %#x\n", addr); +return 0; // RES0 } } @@ -704,7 +704,7 @@ } default: -panic("Gicv3Redistributor::write(): invalid offset %#x\n", addr); +gic->reserved("Gicv3Redistributor::write(): invalid offset %#x\n", addr); break; } } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/71138?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I23f98519c2f256c092a52425735b8792bae7a2c7 Gerrit-Change-Number: 71138 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add an ArmAllRelease containing every defined extension
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70958?usp=email ) Change subject: arch-arm: Add an ArmAllRelease containing every defined extension .. arch-arm: Add an ArmAllRelease containing every defined extension This is probably the easiest way to instantiate a release containing any implemented extension. It is alternatively possible to use the latest release (e.g. Armv92 as of now). This could be preferrable for consistency across simulations. However if users want to always be up to date with development, using ArmAllRelease will allow them to do so without the need to change their configuration script Change-Id: Ibca629e99da9b571f233de9d05a5a9186d02aa99 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70958 Tested-by: kokoro Reviewed-by: Richard Cooper Maintainer: Jason Lowe-Power --- M src/arch/arm/ArmSystem.py 1 file changed, 12 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass Richard Cooper: Looks good to me, approved diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index b826f0d..c1f5e9f 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -224,6 +224,18 @@ extensions = Armv85.extensions + ["FEAT_SME"] +class ArmAllRelease(ArmRelease): +""" +A release containing any implemented extension. It is alternatively +possible to use the latest release (e.g. Armv92 as of now). This could be +preferrable for consistency across simulations. However if users want to +always be up to date with development, using ArmAllRelease will allow them +to do so without the need to change their configuration script +""" + +extensions = ArmExtension.vals + + class ArmSystem(System): type = "ArmSystem" cxx_header = "arch/arm/system.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70958?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ibca629e99da9b571f233de9d05a5a9186d02aa99 Gerrit-Change-Number: 70958 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add an ArmAllRelease containing every defined extension
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70958?usp=email ) Change subject: arch-arm: Add an ArmAllRelease containing every defined extension .. arch-arm: Add an ArmAllRelease containing every defined extension This is probably the easiest way to instantiate a release containing any implemented extension. It is alternatively possible to use the latest release (e.g. Armv92 as of now). This could be preferrable for consistency across simulations. However if users want to always be up to date with development, using ArmAllRelease will allow them to do so without the need to change their configuration script Change-Id: Ibca629e99da9b571f233de9d05a5a9186d02aa99 Signed-off-by: Giacomo Travaglini --- M src/arch/arm/ArmSystem.py 1 file changed, 12 insertions(+), 0 deletions(-) diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index b826f0d..c1f5e9f 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -224,6 +224,18 @@ extensions = Armv85.extensions + ["FEAT_SME"] +class ArmAllRelease(ArmRelease): +""" +A release containing any implemented extension. It is alternatively +possible to use the latest release (e.g. Armv92 as of now). This could be +preferrable for consistency across simulations. However if users want to +always be up to date with development, using ArmAllRelease will allow them +to do so without the need to change their configuration script +""" + +extensions = ArmExtension.vals + + class ArmSystem(System): type = "ArmSystem" cxx_header = "arch/arm/system.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70958?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ibca629e99da9b571f233de9d05a5a9186d02aa99 Gerrit-Change-Number: 70958 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_EVT
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70938?usp=email ) Change subject: arch-arm: Implement FEAT_EVT .. arch-arm: Implement FEAT_EVT This extension is optional in Armv8.2 but mandatory since Armv8.5 We only implement this for AArch64 Change-Id: I063642ac24d27f0a81ba79b1d38f72468bb130eb Signed-off-by: Giacomo Travaglini --- M src/arch/arm/ArmSystem.py M src/arch/arm/regs/misc.cc 2 files changed, 73 insertions(+), 18 deletions(-) diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index b826f0d..5e45fe4 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -91,6 +91,7 @@ "FEAT_FLAGM2", "FEAT_RNG", "FEAT_RNG_TRAP", +"FEAT_EVT", # Armv9.2 "FEAT_SME", # Optional in Armv9.2 # Others @@ -174,6 +175,7 @@ "FEAT_IDST", # Armv8.5 "FEAT_FLAGM2", +"FEAT_EVT", # Armv9.2 "FEAT_SME", ] @@ -217,6 +219,7 @@ "FEAT_FLAGM2", "FEAT_RNG", "FEAT_RNG_TRAP", +"FEAT_EVT", ] diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 53e9268..c8ea1f2 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -1445,7 +1445,8 @@ } } else if (el2_enabled && !in_host && hcr.tpu) { return inst.generateTrap(EL2); -} else if (el2_enabled && !in_host && hcr.tocu) { +} else if (el2_enabled && !in_host && + HaveExt(tc, ArmExtension::FEAT_EVT) && hcr.tocu) { return inst.generateTrap(EL2); } else if (el2_enabled && in_host && !sctlr2.uci) { return inst.generateTrap(EL2); @@ -1462,7 +1463,8 @@ const bool el2_enabled = EL2Enabled(tc); if (el2_enabled && hcr.tpu) { return inst.generateTrap(EL2); -} else if (el2_enabled && hcr.tocu) { +} else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) && + hcr.tocu) { return inst.generateTrap(EL2); } else { return NoFault; @@ -1477,7 +1479,8 @@ const bool el2_enabled = EL2Enabled(tc); if (el2_enabled && hcr.tpu) { return inst.generateTrap(EL2); -} else if (el2_enabled && hcr.ticab) { +} else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) && + hcr.ticab) { return inst.generateTrap(EL2); } else { return NoFault; @@ -1750,6 +1753,54 @@ } Fault +faultTlbiOsEL1(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); +const bool el2_enabled = EL2Enabled(tc); +if (el2_enabled && hcr.ttlb) { +return inst.generateTrap(EL2); +} else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) && + hcr.ttlbos) { +return inst.generateTrap(EL2); +} else { +return NoFault; +} +} + +Fault +faultTlbiIsEL1(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); +const bool el2_enabled = EL2Enabled(tc); +if (el2_enabled && hcr.ttlb) { +return inst.generateTrap(EL2); +} else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) && + hcr.ttlbis) { +return inst.generateTrap(EL2); +} else { +return NoFault; +} +} + +Fault +faultCacheEL1(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); +const bool el2_enabled = EL2Enabled(tc); +if (el2_enabled && hcr.tid2) { +return inst.generateTrap(EL2); +} else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) && + hcr.tid4) { +return inst.generateTrap(EL2); +} else { +return NoFault; +} +} + +Fault faultPauthEL1(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst) { @@ -4041,6 +4092,7 @@ mmfr2_el1.uao = release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0; mmfr2_el1.varange = release->has(ArmExtension::FEAT_LVA) ? 0x1 : 0x0; mmfr2_el1.ids = release->has(ArmExtension::FEAT_IDST) ? 0x1 : 0x0; + mmfr2_el1.evt = release->has(ArmExtension::FEAT_EVT) ? 0x2 : 0x0; return mmfr2_el1; }()) .faultRead(EL0, faultIdst) @@ -4090,11 +4142,11 @@ InitReg(MISCREG_CCSIDR_EL1) .faultRea
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_HCX
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70939?usp=email ) Change subject: arch-arm: Implement FEAT_HCX .. arch-arm: Implement FEAT_HCX This is just making the HCRX_EL2 register read/writable; trapping behaviour will be implemented with further extensions Change-Id: Id1ec42a754b7d999782edde3a8ec6c6099e3331e Signed-off-by: Giacomo Travaglini --- M src/arch/arm/ArmSystem.py M src/arch/arm/regs/misc.cc M src/arch/arm/regs/misc.hh M src/arch/arm/regs/misc_types.hh 4 files changed, 32 insertions(+), 11 deletions(-) diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 5e45fe4..d57fe80 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -92,6 +92,8 @@ "FEAT_RNG", "FEAT_RNG_TRAP", "FEAT_EVT", +# Armv8.7 +"FEAT_HCX", # Armv9.2 "FEAT_SME", # Optional in Armv9.2 # Others @@ -176,6 +178,8 @@ # Armv8.5 "FEAT_FLAGM2", "FEAT_EVT", +# Armv8.7 +"FEAT_HCX", # Armv9.2 "FEAT_SME", ] @@ -223,8 +227,14 @@ ] -class Armv92(Armv85): -extensions = Armv85.extensions + ["FEAT_SME"] +class Armv87(Armv85): +extensions = Armv85.extensions + [ +"FEAT_HCX", +] + + +class Armv92(Armv87): +extensions = Armv87.extensions + ["FEAT_SME"] class ArmSystem(System): diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index c8ea1f2..375e01a 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -1600,6 +1600,18 @@ } Fault +faultHcrxEL2(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); +if (ArmSystem::haveEL(tc, EL3) && !scr.hxen) { +return inst.generateTrap(EL3); +} else { +return NoFault; +} +} + +Fault faultZcrEL1(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst) { @@ -4081,6 +4093,7 @@ mmfr1_el1.vh = release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0; mmfr1_el1.hpds = release->has(ArmExtension::FEAT_HPDS) ? 0x1 : 0x0; mmfr1_el1.pan = release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0; + mmfr1_el1.hcx = release->has(ArmExtension::FEAT_HCX) ? 0x1 : 0x0; return mmfr1_el1; }()) .faultRead(EL0, faultIdst) @@ -4225,6 +4238,9 @@ InitReg(MISCREG_HCR_EL2) .hyp().mon() .mapsTo(MISCREG_HCR, MISCREG_HCR2); +InitReg(MISCREG_HCRX_EL2) + .hyp().mon() + .fault(EL2, faultHcrxEL2); InitReg(MISCREG_MDCR_EL2) .hyp().mon() .fault(EL2, faultDebugEL2) @@ -5645,11 +5661,6 @@ .warnNotFail() .fault(faultUnimplemented); -// HCX extension (unimplemented) -InitReg(MISCREG_HCRX_EL2) - .unimplemented() - .warnNotFail(); - // FGT extension (unimplemented) InitReg(MISCREG_HFGRTR_EL2) .unimplemented() diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index 429fcb5..cb03841 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -589,6 +589,7 @@ MISCREG_SCTLR_EL2, MISCREG_ACTLR_EL2, MISCREG_HCR_EL2, +MISCREG_HCRX_EL2, MISCREG_MDCR_EL2, MISCREG_CPTR_EL2, MISCREG_HSTR_EL2, @@ -1125,9 +1126,6 @@ MISCREG_VSESR_EL2, MISCREG_VDISR_EL2, -// HCX extension (unimplemented) -MISCREG_HCRX_EL2, - // FGT extension (unimplemented) MISCREG_HFGRTR_EL2, MISCREG_HFGWTR_EL2, @@ -2272,6 +2270,7 @@ "sctlr_el2", "actlr_el2", "hcr_el2", +"hcrx_el2", "mdcr_el2", "cptr_el2", "hstr_el2", @@ -2785,7 +2784,6 @@ "disr_el1", "vsesr_el2", "vdisr_el2", -"hcrx_el2", "hfgrtr_el2", "hfgwtr_el2", diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index b7a1207..d8391d9 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -157,6 +157,7 @@ EndBitUnion(AA64MMFR0) BitUnion64(AA64MMFR1) +Bitfield<43, 40> hcx; Bitfield<31, 28> xnx; Bitfield<27, 24> specsei; Bitfield<23, 20> pan; @@ -360,6 +361,7 @@ BitUnion64(SCR) Bitfield<40> trndr; +Bitfield<38> hxen; Bitfield<21> fien; Bitfield<20> nmea; Bitfield<19> ease; -- To view, visit https://gem5-review.google
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix printing of VecElemClass registers
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70697?usp=email ) Change subject: arch-arm: Fix printing of VecElemClass registers .. arch-arm: Fix printing of VecElemClass registers At the moment it is not possible to trace the value of VecElemClass registers. If a AArch32 SIMD binary is run with tracing on, simulation will fail the following assertion [1]. std::string valString(const void *val, size_t size) const override { assert(size == sizeof(ValueType)); The problem is that Arm VecElems are stored in RegVal (uint64_t), but the VecElem data type (ValueType above) per se is a uint32_t. So valString is getting called with size = 8 (coming from RegVal) but ValueType has size = 4. We fix this problem by using RegVal as a VecElemRegClassOps template parameter to make them match. This is not changing anything from a functionality perspective. The result will be that we will be able to print VecElems as 64bit values. This solution is the most simple one but a bit dirty. I believe in the long term we should make the VecElemClass use the void* interface rather than the RegVal one. In this way we will be able to correctly print the VecElem size as 32bit value. [1]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/cpu/reg_class.hh#L362 Change-Id: Ic3fc252d41449f828b77f938fefc0cd4274b1c57 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70697 Tested-by: kokoro Reviewed-by: Richard Cooper Maintainer: Jason Lowe-Power --- M src/arch/arm/regs/vec.hh 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Richard Cooper: Looks good to me, approved kokoro: Regressions pass Jason Lowe-Power: Looks good to me, approved diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh index 00ab87f..19f37c9 100644 --- a/src/arch/arm/regs/vec.hh +++ b/src/arch/arm/regs/vec.hh @@ -93,7 +93,7 @@ const int PREDREG_FFR = 16; const int PREDREG_UREG0 = 17; -static inline VecElemRegClassOps +static inline VecElemRegClassOps vecRegElemClassOps(NumVecElemPerVecReg); static inline TypedRegClassOps vecRegClassOps; static inline TypedRegClassOps vecPredRegClassOps; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70697?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic3fc252d41449f828b77f938fefc0cd4274b1c57 Gerrit-Change-Number: 70697 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Rename AdvSIMD instruction pool
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Rename AdvSIMD instruction pool .. arch-arm: Rename AdvSIMD instruction pool The decoding function was wrongly named decodeNeon3SameExtra, referring to the "AdvSIMD three same Extra" instruction pool This might be an old name as I can only find the "AdvSIMD *scalar* three same Extra" in the Arm arm. The encoding space reserved to the pool bears the "Advanced SIMD three-register extension" name; we therefore rename the function to decodeNeon3RegExtension Change-Id: I056da8f0c7808935d12a4b05490d30654178071f Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70724 Tested-by: kokoro Maintainer: Jason Lowe-Power --- M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/formats/neon64.isa 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: kokoro: Regressions pass Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 9ad2de2..47d509e 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -2461,7 +2461,7 @@ return new Unknown64(machInst); } } else if (bits(machInst, 15) == 1) { -return decodeNeon3SameExtra(machInst); +return decodeNeon3RegExtension(machInst); } else if (bits(machInst, 10) == 1) { if (bits(machInst, 23, 22)) return new Unknown64(machInst); diff --git a/src/arch/arm/isa/formats/neon64.isa b/src/arch/arm/isa/formats/neon64.isa index 72b7e28..c200da7 100644 --- a/src/arch/arm/isa/formats/neon64.isa +++ b/src/arch/arm/isa/formats/neon64.isa @@ -39,9 +39,9 @@ // AdvSIMD three same template StaticInstPtr decodeNeon3Same(ExtMachInst machInst); -// AdvSIMD three same Extra +// AdvSIMD three register extension template -StaticInstPtr decodeNeon3SameExtra(ExtMachInst machInst); +StaticInstPtr decodeNeon3RegExtension(ExtMachInst machInst); // AdvSIMD three different inline StaticInstPtr decodeNeon3Diff(ExtMachInst machInst); // AdvSIMD two-reg misc @@ -507,7 +507,7 @@ template StaticInstPtr -decodeNeon3SameExtra(ExtMachInst machInst) +decodeNeon3RegExtension(ExtMachInst machInst) { uint8_t q = bits(machInst, 30); uint8_t size = bits(machInst, 23, 22); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I056da8f0c7808935d12a4b05490d30654178071f Gerrit-Change-Number: 70724 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Improve debugging of CC regs accesses
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70718?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Improve debugging of CC regs accesses .. arch-arm: Improve debugging of CC regs accesses As of now we are simply printing the CC reg index which is not particularly helpful. With this patch we actually print the (NZ|C|V) reg name. Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70718 Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/regs/cc.hh 1 file changed, 23 insertions(+), 11 deletions(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/regs/cc.hh b/src/arch/arm/regs/cc.hh index ba75527..474e48e 100644 --- a/src/arch/arm/regs/cc.hh +++ b/src/arch/arm/regs/cc.hh @@ -61,10 +61,31 @@ NumRegs }; +const char * const RegName[NumRegs] = { +"nz", +"c", +"v", +"ge", +"fp", +"zero" +}; + } // namespace cc_reg -inline constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, -cc_reg::NumRegs, debug::CCRegs); +class CCRegClassOps : public RegClassOps +{ + public: +std::string +regName(const RegId &id) const override +{ +return cc_reg::RegName[id.index()]; +} +}; + +static inline CCRegClassOps ccRegClassOps; + +inline constexpr RegClass ccRegClass = RegClass(CCRegClass, CCRegClassName, +cc_reg::NumRegs, debug::CCRegs).ops(ccRegClassOps); namespace cc_reg { @@ -77,15 +98,6 @@ Fp = ccRegClass[_FpIdx], Zero = ccRegClass[_ZeroIdx]; -const char * const RegName[NumRegs] = { -"nz", -"c", -"v", -"ge", -"fp", -"zero" -}; - } // namespace cc_reg enum ConditionCode -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70718?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce Gerrit-Change-Number: 70718 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Define a AA64ZFR0 data type
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70725?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Define a AA64ZFR0 data type .. arch-arm: Define a AA64ZFR0 data type Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70725 Tested-by: kokoro Maintainer: Jason Lowe-Power --- M src/arch/arm/regs/misc_types.hh 1 file changed, 13 insertions(+), 0 deletions(-) Approvals: Richard Cooper: Looks good to me, approved kokoro: Regressions pass Jason Lowe-Power: Looks good to me, approved diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index 214d418..b7a1207 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -203,6 +203,19 @@ Bitfield<3, 0> el0; EndBitUnion(AA64PFR0) +BitUnion64(AA64ZFR0) +Bitfield<59, 56> f64mm; +Bitfield<55, 52> f32mm; +Bitfield<47, 44> i8mm; +Bitfield<43, 40> sm4; +Bitfield<35, 32> sha3; +Bitfield<27, 24> b16b16; +Bitfield<23, 20> bf16; +Bitfield<19, 16> bitPerm; +Bitfield<7, 4> aes; +Bitfield<3, 0> sveVer; +EndBitUnion(AA64ZFR0) + BitUnion64(AA64SMFR0) Bitfield<63> fa64; Bitfield<59, 56> smEver; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70725?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885 Gerrit-Change-Number: 70725 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Define remaining fields of the arm64 AT_HWCAP entry
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70758?usp=email ) Change subject: arch-arm: Define remaining fields of the arm64 AT_HWCAP entry .. arch-arm: Define remaining fields of the arm64 AT_HWCAP entry Change-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70758 Reviewed-by: Richard Cooper Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/process.cc 1 file changed, 6 insertions(+), 2 deletions(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 9770ea6..6b5f69e 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012, 2017-2018 ARM Limited + * Copyright (c) 2010, 2012, 2017-2018, 2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -207,7 +207,11 @@ Arm_Dit = 1 << 24, Arm_Uscat = 1 << 25, Arm_Ilrcpc = 1 << 26, -Arm_Flagm = 1 << 27 +Arm_Flagm = 1 << 27, +Arm_Sbss = 1 << 28, +Arm_Sb = 1 << 29, +Arm_Paca = 1 << 30, +Arm_Pacg = 1 << 31 }; uint32_t hwcap = 0; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70758?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb Gerrit-Change-Number: 70758 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Split decodeDataProcReg into subfunctions
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70717?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Split decodeDataProcReg into subfunctions .. arch-arm: Split decodeDataProcReg into subfunctions This will increase readibility, it will make it easier for devs to add new instructions, and it removes some duplication (some register indexes were read more than once) Change-Id: Ifa03a93cb73de0b2dc93d7784f9011e0e55dfc1e Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70717 Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/isa/formats/aarch64.isa 1 file changed, 361 insertions(+), 309 deletions(-) Approvals: Richard Cooper: Looks good to me, approved kokoro: Regressions pass Jason Lowe-Power: Looks good to me, approved diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 2fd28f8..0aafa9e 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -1958,6 +1958,359 @@ output decoder {{ namespace Aarch64 { + +StaticInstPtr +decodeLogical(ExtMachInst machInst) +{ +uint8_t imm6 = bits(machInst, 15, 10); +bool sf = bits(machInst, 31); +if (!sf && (imm6 & 0x20)) +return new Unknown64(machInst); + +RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0); +RegIndex rdzr = makeZero(rd); +RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5); +RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16); +ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22); + +uint8_t switch_val = (bits(machInst, 21) << 0) | +(bits(machInst, 30, 29) << 1); + +switch (switch_val) { + case 0x0: +return new AndXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x1: +return new BicXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x2: +return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x3: +return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x4: +return new EorXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x5: +return new EonXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x6: +return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type); + case 0x7: +return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type); + default: +GEM5_UNREACHABLE; +} +} + +StaticInstPtr +decodeAddSub(ExtMachInst machInst) +{ +uint8_t switch_val = bits(machInst, 30, 29); +if (bits(machInst, 21) == 0) { +ArmShiftType type = +(ArmShiftType)(uint8_t)bits(machInst, 23, 22); +if (type == ROR) +return new Unknown64(machInst); +uint8_t imm6 = bits(machInst, 15, 10); +if (!bits(machInst, 31) && bits(imm6, 5)) +return new Unknown64(machInst); +RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0); +RegIndex rdzr = makeZero(rd); +RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5); +RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16); +switch (switch_val) { + case 0x0: +return new AddXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x1: +return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type); + case 0x2: +return new SubXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x3: +return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type); + default: +GEM5_UNREACHABLE; +} +} else { +if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4) + return new Unknown64(machInst); +ArmExtendType type = +(ArmExtendType)(uint8_t)bits(machInst, 15, 13); +uint8_t imm3 = bits(machInst, 12, 10); +RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0); +RegIndex rdsp = makeSP(rd); +RegIndex rdzr = makeZero(rd); +RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5); +RegIndex rnsp = makeSP(rn); +RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16); + +switch (switch_val) { + case 0x0: +return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3); + case 0x1: +return new AddXERegCc(mac
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Extend auxiliary vector with AT_HWCAP2 entry
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70760?usp=email ) Change subject: arch-arm: Extend auxiliary vector with AT_HWCAP2 entry .. arch-arm: Extend auxiliary vector with AT_HWCAP2 entry The presence of some of the new extensions is reported via the AT_HWCAP2 entry Change-Id: I7a2d813ea84bf528b1f9df09121f9e97456a11c0 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70760 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Richard Cooper --- M src/arch/arm/process.cc M src/arch/arm/process.hh 2 files changed, 69 insertions(+), 4 deletions(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 02771ae..9b0f3b2 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -261,6 +261,62 @@ return hwcap; } +uint64_t +ArmProcess64::armHwcapImpl2() const +{ +enum ArmCpuFeature : uint64_t +{ +Arm_None = 0, +Arm_Dcpodp = 1ULL << 0, +Arm_Sve2 = 1ULL<< 1, +Arm_Sveaes = 1ULL << 2, +Arm_Svepmull = 1ULL << 3, +Arm_Svebitperm = 1ULL << 4, +Arm_Svesha3 = 1ULL << 5, +Arm_Svesm4 = 1ULL << 6, +Arm_Flagm2 = 1ULL << 7, +Arm_Frint = 1ULL << 8, +Arm_Svei8mm = 1ULL << 9, +Arm_Svef32mm = 1ULL << 10, +Arm_Svef64mm = 1ULL << 11, +Arm_Svebf16 = 1ULL << 12, +Arm_I8mm = 1ULL << 13, +Arm_Bf16 = 1ULL << 14, +Arm_Dgh = 1ULL << 15, +Arm_Rng = 1ULL << 16, +Arm_Bti = 1ULL << 17, +Arm_Mte = 1ULL << 18, +Arm_Ecv = 1ULL << 19, +Arm_Afp = 1ULL << 20, +Arm_Rpres = 1ULL << 21, +Arm_Mte3 = 1ULL << 22, +Arm_Sme = 1ULL << 23, +Arm_Sme_I16i64 = 1ULL << 24, +Arm_Sme_F64f64 = 1ULL << 25, +Arm_Sme_I8i32 = 1ULL << 26, +Arm_Sme_F16f32 = 1ULL << 27, +Arm_Sme_B16f32 = 1ULL << 28, +Arm_Sme_F32f32 = 1ULL << 29, +Arm_Sme_Fa64 = 1ULL << 30, +Arm_Wfxt = 1ULL << 31, +Arm_Ebf16 = 1ULL << 32, +Arm_Sve_Ebf16 = 1ULL << 33, +Arm_Cssc = 1ULL << 34, +Arm_Rprfm = 1ULL << 35, +Arm_Sve2p1 = 1ULL << 36, +Arm_Sme2 = 1ULL << 37, +Arm_Sme2p1 = 1ULL << 38, +Arm_Sme_I16i32 = 1ULL << 39, +Arm_Sme_Bi32i32 = 1ULL << 40, +Arm_Sme_B16b16 = 1ULL << 41, +Arm_Sme_F16f16 = 1ULL << 42 +}; + +uint64_t hwcap = 0; + +return hwcap; +} + template void ArmProcess::argsInit(int pageSize, const RegId &spId) @@ -284,11 +340,10 @@ if (elfObject) { if (objFile->getOpSys() == loader::Linux) { -IntType features = armHwcap(); - //Bits which describe the system hardware capabilities //XXX Figure out what these should be -auxv.emplace_back(gem5::auxv::Hwcap, features); +auxv.emplace_back(gem5::auxv::Hwcap, armHwcap()); +auxv.emplace_back(gem5::auxv::Hwcap2, armHwcap2()); //Frequency at which times() increments auxv.emplace_back(gem5::auxv::Clktck, 0x64); //Whether to enable "secure mode" in the executable diff --git a/src/arch/arm/process.hh b/src/arch/arm/process.hh index 6bdabef..0aee6dc 100644 --- a/src/arch/arm/process.hh +++ b/src/arch/arm/process.hh @@ -1,5 +1,5 @@ /* -* Copyright (c) 2012, 2018 ARM Limited +* Copyright (c) 2012, 2018, 2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -69,10 +69,18 @@ return static_cast(armHwcapImpl()); } +template +IntType +armHwcap2() const +{ +return static_cast(armHwcapImpl2()); +} + /** * AT_HWCAP is 32-bit wide on AArch64 as well so we can * safely return an uint32_t */ virtual uint32_t armHwcapImpl() const = 0; +virtual uint64_t armHwcapImpl2() const = 0; }; class ArmProcess32 : public ArmProcess @@ -86,6 +94,7 @@ /** AArch32 AT_HWCAP */ uint32_t armHwcapImpl() const override; +uint64_t armHwcapImpl2() const override { return 0; } }; class ArmProcess64 : public ArmProcess @@ -99,6 +108,7 @@ /** AArch64 AT_HWCAP */ uint32_t armHwcapImpl() const override; +uint64_t armHwcapImpl2() const override; }; } // namespace gem5 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70760?usp=email To unsubscribe, or for help writing mail filter
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCR to be 64-bit wide
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70720?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Extend SCR to be 64-bit wide .. arch-arm: Extend SCR to be 64-bit wide Change-Id: I9928de3db61957404269d189a15a951fd6707c8a Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70720 Tested-by: kokoro Maintainer: Jason Lowe-Power --- M src/arch/arm/regs/misc_types.hh 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved Richard Cooper: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index c139f1a..71fdd60 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -345,7 +345,7 @@ Bitfield<0> cp0; EndBitUnion(NSACR) -BitUnion32(SCR) +BitUnion64(SCR) Bitfield<21> fien; Bitfield<20> nmea; Bitfield<19> ease; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70720?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9928de3db61957404269d189a15a951fd6707c8a Gerrit-Change-Number: 70720 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Enable FEAT_PAuth in SE mode
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70759?usp=email ) Change subject: arch-arm: Enable FEAT_PAuth in SE mode .. arch-arm: Enable FEAT_PAuth in SE mode It was in theory already possible to use FEAT_PAuth instructions in SE mode, however its presence was hidden to userspace code as the cpu feature was not listed in the auxiliary vectors Change-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70759 Reviewed-by: Richard Cooper Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/process.cc 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 6b5f69e..02771ae 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -251,6 +251,8 @@ hwcap |= (isa_r1.fcma >= 1) ? Arm_Fcma : 0; hwcap |= (isa_r1.lrcpc >= 1) ? Arm_Lrcpc : 0; hwcap |= (isa_r1.lrcpc >= 2) ? Arm_Ilrcpc : 0; +hwcap |= (isa_r1.apa >= 1 || isa_r1.api >= 1) ? Arm_Paca : 0; +hwcap |= (isa_r1.gpa >= 1 || isa_r1.gpi >= 1) ? Arm_Pacg : 0; const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70759?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe Gerrit-Change-Number: 70759 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_FLAGM(2)
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70719?usp=email ) Change subject: arch-arm: Implement FEAT_FLAGM(2) .. arch-arm: Implement FEAT_FLAGM(2) Change-Id: I21f1eb91ad9acb019a776a7d5edd38754571a62e Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70719 Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/insts/misc64.cc M src/arch/arm/insts/misc64.hh M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/insts/misc64.isa M src/arch/arm/isa/templates/misc64.isa M src/arch/arm/process.cc M src/arch/arm/regs/misc.cc 9 files changed, 244 insertions(+), 4 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index e73046d..37970dc 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -58,6 +58,10 @@ "FEAT_FCMA", "FEAT_JSCVT", "FEAT_PAuth", +# Armv8.4 +"FEAT_FLAGM", +# Armv8.5 +"FEAT_FLAGM2", # Armv9.2 "FEAT_SME", # Other diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 9e2da8e..e08108f 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -85,6 +85,9 @@ # Armv8.4 "FEAT_SEL2", "FEAT_TLBIOS", +"FEAT_FLAGM", +# Armv8.5 +"FEAT_FLAGM2", # Armv9.2 "FEAT_SME", # Optional in Armv9.2 # Others @@ -164,6 +167,9 @@ # Armv8.4 "FEAT_SEL2", "FEAT_TLBIOS", +"FEAT_FLAGM", +# Armv8.5 +"FEAT_FLAGM2", # Armv9.2 "FEAT_SME", ] @@ -194,11 +200,15 @@ class Armv84(Armv83): -extensions = Armv83.extensions + ["FEAT_SEL2", "FEAT_TLBIOS"] +extensions = Armv83.extensions + ["FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM"] -class Armv92(Armv84): -extensions = Armv84.extensions + ["FEAT_SME"] +class Armv85(Armv84): +extensions = Armv84.extensions + ["FEAT_FLAGM2"] + + +class Armv92(Armv85): +extensions = Armv85.extensions + ["FEAT_SME"] class ArmSystem(System): diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index c7423d9..4f573fc 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -55,6 +55,27 @@ } std::string +RegOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const +{ +std::stringstream ss; +printMnemonic(ss, "", false); +printIntReg(ss, op1); +return ss.str(); +} + +std::string +RegImmImmOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const +{ +std::stringstream ss; +printMnemonic(ss, "", false); +printIntReg(ss, op1); +ccprintf(ss, "#0x%x", imm1); +ss << ", "; +ccprintf(ss, "#0x%x", imm2); +return ss.str(); +} + +std::string RegRegImmImmOp64::generateDisassembly( Addr pc, const loader::SymbolTable *symtab) const { diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh index b7b66c2..3a67210 100644 --- a/src/arch/arm/insts/misc64.hh +++ b/src/arch/arm/insts/misc64.hh @@ -57,6 +57,38 @@ Addr pc, const loader::SymbolTable *symtab) const override; }; +class RegOp64 : public ArmISA::ArmStaticInst +{ + protected: +RegIndex op1; + +RegOp64(const char *mnem, ArmISA::ExtMachInst _machInst, +OpClass __opClass, RegIndex _op1) : +ArmISA::ArmStaticInst(mnem, _machInst, __opClass), op1(_op1) +{} + +std::string generateDisassembly( +Addr pc, const loader::SymbolTable *symtab) const override; +}; + +class RegImmImmOp64 : public ArmISA::ArmStaticInst +{ + protected: +RegIndex op1; +uint64_t imm1; +uint64_t imm2; + +RegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, + OpClass __opClass, RegIndex _op1, + uint64_t _imm1, uint64_t _imm2) : +ArmISA::ArmStaticInst(mnem, _machInst, __opClass), +op1(_op1), imm1(_imm1), imm2(_imm2) +{} + +std::string generateDisassembly( +Addr pc, const loader::SymbolTable *symtab) const override; +}; + class RegRegImmImmOp64 : public ArmISA::ArmStaticInst { protected: diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 0aafa9e..9ad2de2 100644 --- a/src/arch/arm/isa/fo
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement trapping of SME registers
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70722?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Implement trapping of SME registers .. arch-arm: Implement trapping of SME registers Change-Id: Ic5bcc79a535c928265fbc1db1cd0c85ba1a1b152 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70722 Tested-by: kokoro Maintainer: Jason Lowe-Power --- M src/arch/arm/regs/misc.cc 1 file changed, 80 insertions(+), 1 deletion(-) Approvals: kokoro: Regressions pass Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 0e92e3d..56644e9 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2002,6 +2002,68 @@ } Fault +faultEsm(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3); +if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.esm) { +return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SME, 0); +} else { +return NoFault; +} +} + +Fault +faultTsmSmen(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const HCR hcr_el2 = tc->readMiscReg(MISCREG_HCR_EL2); +const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2); +const bool el2_enabled = EL2Enabled(tc); +if (el2_enabled && !hcr_el2.e2h && cptr_el2.tsm) { +return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0); +} else if (el2_enabled && hcr_el2.e2h && !(cptr_el2.smen & 0b1)) { +return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0); +} else { +return faultEsm(entry, tc, inst); +} +} + +Fault +faultSmenEL1(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); +if (!(cpacr.smen & 0b1)) { +return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SME, 0); +} else { +return faultTsmSmen(entry, tc, inst); +} +} + +Fault +faultSmenEL0(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const bool el2_enabled = EL2Enabled(tc); +const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); +const bool in_host = hcr.e2h && hcr.tge; + +const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); +const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2); +if (!(el2_enabled && in_host) && cpacr.smen != 0b11) { +if (el2_enabled && hcr.tge) +return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0); +else +return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SME, 0); +} else if (el2_enabled && in_host && cptr_el2.smen != 0b11) { +return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0); +} else { +return faultTsmSmen(entry, tc, inst); +} +} + +Fault faultRng(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst) { @@ -5348,6 +5410,7 @@ smfr0_el1.fa64 = 0x1; return smfr0_el1; }()) +.faultRead(EL1, HCR_TRAP(tid3)) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_SVCR) .res0([](){ @@ -5356,6 +5419,10 @@ svcr_mask.za = 1; return ~svcr_mask; }()) +.fault(EL0, faultSmenEL0) +.fault(EL1, faultSmenEL1) +.fault(EL2, faultTsmSmen) +.fault(EL3, faultEsm) .allPrivileges(); InitReg(MISCREG_SMIDR_EL1) .reset([](){ @@ -5365,11 +5432,17 @@ smidr_el1.implementer = 0x41; return smidr_el1; }()) +.faultRead(EL1, HCR_TRAP(tid1)) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_SMPRI_EL1) .res0(mask(63, 4)) -.allPrivileges().exceptUserMode().reads(1); +.fault(EL1, faultEsm) +.fault(EL2, faultEsm) +.fault(EL3, faultEsm) +.allPrivileges().exceptUserMode(); InitReg(MISCREG_SMPRIMAP_EL2) +.fault(EL2, faultEsm) +.fault(EL3, faultEsm) .hyp().mon(); InitReg(MISCREG_SMCR_EL3) .reset([this](){ @@ -5383,6 +5456,7 @@ smcr_el3.len = smeVL - 1; return smcr_el3; }()) +.fault(EL3, faultEsm) .mon(); InitReg(MISCREG_SMCR_EL2) .reset([this](){ @@ -5396,6 +5470,8 @@ smcr_el2.len = smeVL - 1; return smcr_el2; }()) +
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_IDST
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70723?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Implement FEAT_IDST .. arch-arm: Implement FEAT_IDST Change-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70723 Tested-by: kokoro Maintainer: Jason Lowe-Power --- M src/arch/arm/ArmSystem.py M src/arch/arm/regs/misc.cc 2 files changed, 59 insertions(+), 17 deletions(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index c3b3cf6..b826f0d 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -86,6 +86,7 @@ "FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM", +"FEAT_IDST", # Armv8.5 "FEAT_FLAGM2", "FEAT_RNG", @@ -170,6 +171,7 @@ "FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM", +"FEAT_IDST", # Armv8.5 "FEAT_FLAGM2", # Armv9.2 @@ -202,7 +204,12 @@ class Armv84(Armv83): -extensions = Armv83.extensions + ["FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM"] +extensions = Armv83.extensions + [ +"FEAT_SEL2", +"FEAT_TLBIOS", +"FEAT_FLAGM", +"FEAT_IDST", +] class Armv85(Armv84): diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 56644e9..53e9268 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2077,6 +2077,22 @@ } } +Fault +faultIdst(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +if (HaveExt(tc, ArmExtension::FEAT_IDST)) { +const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); +if (EL2Enabled(tc) && hcr.tge) { +return inst.generateTrap(EL2); +} else { +return inst.generateTrap(EL1); +} +} else { +return inst.undefined(); +} +} + } MiscRegIndex @@ -3828,6 +3844,7 @@ // AArch64 registers (Op0=1,3); InitReg(MISCREG_MIDR_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .mapsTo(MISCREG_MIDR); InitReg(MISCREG_MPIDR_EL1) .allPrivileges().exceptUserMode().writes(0) @@ -3923,34 +3940,40 @@ return pfr0_el1; }()) .unserialize(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64PFR1_EL1) .reset(release->has(ArmExtension::FEAT_SME) ? 0x1 << 24 : 0) .unserialize(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64DFR0_EL1) .reset([p](){ AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1; dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3 return dfr0_el1; }()) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64DFR1_EL1) .reset(p.id_aa64dfr1_el1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64AFR0_EL1) .reset(p.id_aa64afr0_el1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64AFR1_EL1) .reset(p.id_aa64afr1_el1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64ISAR0_EL1) .reset([p,release=release](){ AA64ISAR0 isar0_el1 = p.id_aa64isar0_el1; @@ -3975,8 +3998,9 @@ isar0_el1.rndr = release->has(ArmExtension::FEAT_RNG) ? 0x1 : 0x0; return isar0_el1; }()) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64ISAR1_EL1) .reset([p,release=release](){ AA64ISAR1 isar1_el1 = p.id_aa64isar1_el1; @@ -
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_RNG
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70721?usp=email ) Change subject: arch-arm: Implement FEAT_RNG .. arch-arm: Implement FEAT_RNG Change-Id: I9d60d249172ef4bbaf5d9b38ef279eff344b80d8 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70721 Tested-by: kokoro Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power --- M src/arch/arm/ArmSystem.py M src/arch/arm/isa.cc M src/arch/arm/process.cc M src/arch/arm/regs/misc.cc M src/arch/arm/regs/misc.hh M src/arch/arm/regs/misc_types.hh 6 files changed, 64 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index e08108f..c3b3cf6 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -88,6 +88,8 @@ "FEAT_FLAGM", # Armv8.5 "FEAT_FLAGM2", +"FEAT_RNG", +"FEAT_RNG_TRAP", # Armv9.2 "FEAT_SME", # Optional in Armv9.2 # Others @@ -204,7 +206,11 @@ class Armv85(Armv84): -extensions = Armv84.extensions + ["FEAT_FLAGM2"] +extensions = Armv84.extensions + [ +"FEAT_FLAGM2", +"FEAT_RNG", +"FEAT_RNG_TRAP", +] class Armv92(Armv85): diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 9c8e282..0212926 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -49,6 +49,7 @@ #include "arch/arm/utility.hh" #include "arch/generic/decoder.hh" #include "base/cprintf.hh" +#include "base/random.hh" #include "cpu/base.hh" #include "cpu/checker/cpu.hh" #include "cpu/reg_class.hh" @@ -596,6 +597,21 @@ case MISCREG_HIFAR: // alias for secure IFAR return readMiscRegNoEffect(MISCREG_IFAR_S); + case MISCREG_RNDR: +tc->setReg(cc_reg::Nz, (RegVal)0); +tc->setReg(cc_reg::C, (RegVal)0); +tc->setReg(cc_reg::V, (RegVal)0); +return random_mt.random(); + case MISCREG_RNDRRS: +tc->setReg(cc_reg::Nz, (RegVal)0); +tc->setReg(cc_reg::C, (RegVal)0); +tc->setReg(cc_reg::V, (RegVal)0); +// Note: we are not reseeding +// The random number generator already has an hardcoded +// seed for the sake of determinism. There is no point +// in simulating non-determinism here +return random_mt.random(); + // Generic Timer registers case MISCREG_CNTFRQ ... MISCREG_CNTVOFF: case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2: diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index b2378cc..fda9415 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -318,6 +318,7 @@ const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1); hwcap |= (isa_r0.ts >= 2) ? Arm_Flagm2 : Arm_None; +hwcap |= (isa_r0.rndr >= 1) ? Arm_Rng : Arm_None; return hwcap; } diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 9e633c0..0e92e3d 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -1057,6 +1057,8 @@ { MiscRegNum64(3, 2, 0, 0, 0), MISCREG_CSSELR_EL1 }, { MiscRegNum64(3, 3, 0, 0, 1), MISCREG_CTR_EL0 }, { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 }, +{ MiscRegNum64(3, 3, 2, 4, 0), MISCREG_RNDR }, +{ MiscRegNum64(3, 3, 2, 4, 1), MISCREG_RNDRRS }, { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV }, { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF }, { MiscRegNum64(3, 3, 4, 2, 2), MISCREG_SVCR }, @@ -1999,6 +2001,20 @@ } } +Fault +faultRng(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); +if (HaveExt(tc, ArmExtension::FEAT_RNG_TRAP) && scr.trndr) { +return inst.generateTrap(EL3); +} else if (!HaveExt(tc, ArmExtension::FEAT_RNG)) { +return inst.undefined(); +} else { +return NoFault; +} +} + } MiscRegIndex @@ -3894,6 +3910,7 @@ isar0_el1.ts = release->has(ArmExtension::FEAT_FLAGM2) ? 0x2 : release->has(ArmExtension::FEAT_FLAGM) ? 0x1 : 0x0; + isar0_el1.rndr = release->has(ArmExtension::FEAT_RNG) ? 0x1 : 0x0; return isar0_el1; }()) .faultRead(EL1, HCR_TRAP(tid3)) @@ -5400,6 +5417,21 @@ InitReg(MISCREG_MPAMSM_EL1) .allPrivileges().exceptUserMode(); +InitReg(MISCREG_RNDR) +.faultRead(EL0, faultRng) +.faultRead(EL1, faultRng) +.faultRead(EL2, faultRng) +.faultRead(EL3, faultRng)
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Extend auxiliary vector with AT_HWCAP2 entry
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70760?usp=email ) Change subject: arch-arm: Extend auxiliary vector with AT_HWCAP2 entry .. arch-arm: Extend auxiliary vector with AT_HWCAP2 entry The presence of some of the new extensions is reported via the AT_HWCAP2 entry Change-Id: I7a2d813ea84bf528b1f9df09121f9e97456a11c0 Signed-off-by: Giacomo Travaglini --- M src/arch/arm/process.cc M src/arch/arm/process.hh 2 files changed, 69 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 02771ae..9b0f3b2 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -261,6 +261,62 @@ return hwcap; } +uint64_t +ArmProcess64::armHwcapImpl2() const +{ +enum ArmCpuFeature : uint64_t +{ +Arm_None = 0, +Arm_Dcpodp = 1ULL << 0, +Arm_Sve2 = 1ULL<< 1, +Arm_Sveaes = 1ULL << 2, +Arm_Svepmull = 1ULL << 3, +Arm_Svebitperm = 1ULL << 4, +Arm_Svesha3 = 1ULL << 5, +Arm_Svesm4 = 1ULL << 6, +Arm_Flagm2 = 1ULL << 7, +Arm_Frint = 1ULL << 8, +Arm_Svei8mm = 1ULL << 9, +Arm_Svef32mm = 1ULL << 10, +Arm_Svef64mm = 1ULL << 11, +Arm_Svebf16 = 1ULL << 12, +Arm_I8mm = 1ULL << 13, +Arm_Bf16 = 1ULL << 14, +Arm_Dgh = 1ULL << 15, +Arm_Rng = 1ULL << 16, +Arm_Bti = 1ULL << 17, +Arm_Mte = 1ULL << 18, +Arm_Ecv = 1ULL << 19, +Arm_Afp = 1ULL << 20, +Arm_Rpres = 1ULL << 21, +Arm_Mte3 = 1ULL << 22, +Arm_Sme = 1ULL << 23, +Arm_Sme_I16i64 = 1ULL << 24, +Arm_Sme_F64f64 = 1ULL << 25, +Arm_Sme_I8i32 = 1ULL << 26, +Arm_Sme_F16f32 = 1ULL << 27, +Arm_Sme_B16f32 = 1ULL << 28, +Arm_Sme_F32f32 = 1ULL << 29, +Arm_Sme_Fa64 = 1ULL << 30, +Arm_Wfxt = 1ULL << 31, +Arm_Ebf16 = 1ULL << 32, +Arm_Sve_Ebf16 = 1ULL << 33, +Arm_Cssc = 1ULL << 34, +Arm_Rprfm = 1ULL << 35, +Arm_Sve2p1 = 1ULL << 36, +Arm_Sme2 = 1ULL << 37, +Arm_Sme2p1 = 1ULL << 38, +Arm_Sme_I16i32 = 1ULL << 39, +Arm_Sme_Bi32i32 = 1ULL << 40, +Arm_Sme_B16b16 = 1ULL << 41, +Arm_Sme_F16f16 = 1ULL << 42 +}; + +uint64_t hwcap = 0; + +return hwcap; +} + template void ArmProcess::argsInit(int pageSize, const RegId &spId) @@ -284,11 +340,10 @@ if (elfObject) { if (objFile->getOpSys() == loader::Linux) { -IntType features = armHwcap(); - //Bits which describe the system hardware capabilities //XXX Figure out what these should be -auxv.emplace_back(gem5::auxv::Hwcap, features); +auxv.emplace_back(gem5::auxv::Hwcap, armHwcap()); +auxv.emplace_back(gem5::auxv::Hwcap2, armHwcap2()); //Frequency at which times() increments auxv.emplace_back(gem5::auxv::Clktck, 0x64); //Whether to enable "secure mode" in the executable diff --git a/src/arch/arm/process.hh b/src/arch/arm/process.hh index 6bdabef..0aee6dc 100644 --- a/src/arch/arm/process.hh +++ b/src/arch/arm/process.hh @@ -1,5 +1,5 @@ /* -* Copyright (c) 2012, 2018 ARM Limited +* Copyright (c) 2012, 2018, 2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -69,10 +69,18 @@ return static_cast(armHwcapImpl()); } +template +IntType +armHwcap2() const +{ +return static_cast(armHwcapImpl2()); +} + /** * AT_HWCAP is 32-bit wide on AArch64 as well so we can * safely return an uint32_t */ virtual uint32_t armHwcapImpl() const = 0; +virtual uint64_t armHwcapImpl2() const = 0; }; class ArmProcess32 : public ArmProcess @@ -86,6 +94,7 @@ /** AArch32 AT_HWCAP */ uint32_t armHwcapImpl() const override; +uint64_t armHwcapImpl2() const override { return 0; } }; class ArmProcess64 : public ArmProcess @@ -99,6 +108,7 @@ /** AArch64 AT_HWCAP */ uint32_t armHwcapImpl() const override; +uint64_t armHwcapImpl2() const override; }; } // namespace gem5 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70760?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7a2d813ea84bf528b1f9df09121f9e97456a11c0 Gerrit-Change-Number: 70760 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Define remaining fields of the arm64 AT_HWCAP entry
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70758?usp=email ) Change subject: arch-arm: Define remaining fields of the arm64 AT_HWCAP entry .. arch-arm: Define remaining fields of the arm64 AT_HWCAP entry Change-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb Signed-off-by: Giacomo Travaglini --- M src/arch/arm/process.cc 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 9770ea6..6b5f69e 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012, 2017-2018 ARM Limited + * Copyright (c) 2010, 2012, 2017-2018, 2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -207,7 +207,11 @@ Arm_Dit = 1 << 24, Arm_Uscat = 1 << 25, Arm_Ilrcpc = 1 << 26, -Arm_Flagm = 1 << 27 +Arm_Flagm = 1 << 27, +Arm_Sbss = 1 << 28, +Arm_Sb = 1 << 29, +Arm_Paca = 1 << 30, +Arm_Pacg = 1 << 31 }; uint32_t hwcap = 0; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70758?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb Gerrit-Change-Number: 70758 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Enable FEAT_PAuth in SE mode
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70759?usp=email ) Change subject: arch-arm: Enable FEAT_PAuth in SE mode .. arch-arm: Enable FEAT_PAuth in SE mode It was in theory already possible to use FEAT_PAuth instructions in SE mode, however its presence was hidden to userspace code as the cpu feature was not listed in the auxiliary vectors Change-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe Signed-off-by: Giacomo Travaglini --- M src/arch/arm/process.cc 1 file changed, 2 insertions(+), 0 deletions(-) diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 6b5f69e..02771ae 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -251,6 +251,8 @@ hwcap |= (isa_r1.fcma >= 1) ? Arm_Fcma : 0; hwcap |= (isa_r1.lrcpc >= 1) ? Arm_Lrcpc : 0; hwcap |= (isa_r1.lrcpc >= 2) ? Arm_Ilrcpc : 0; +hwcap |= (isa_r1.apa >= 1 || isa_r1.api >= 1) ? Arm_Paca : 0; +hwcap |= (isa_r1.gpa >= 1 || isa_r1.gpi >= 1) ? Arm_Pacg : 0; const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70759?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe Gerrit-Change-Number: 70759 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT insts.
return decodeSveIntegerDotProductIndexed(machInst); + case 0b11: +return decodeSveMixedSignDotProductIndexed(machInst); + default: +return new Unknown64(machInst); +} +} else { +return new Unknown64(machInst); +} +return new Unknown64(machInst); +} } // namespace Aarch64 }}; diff --git a/src/arch/arm/isa/formats/sve_top_level.isa b/src/arch/arm/isa/formats/sve_top_level.isa index 0699637..d4c2a13 100644 --- a/src/arch/arm/isa/formats/sve_top_level.isa +++ b/src/arch/arm/isa/formats/sve_top_level.isa @@ -71,8 +71,10 @@ StaticInstPtr decodeSveIntWideImmUnpred(ExtMachInst machInst); StaticInstPtr decodeSveClamp(ExtMachInst machInst); -StaticInstPtr decodeSveMultiplyAddUnpred(ExtMachInst machInst); -StaticInstPtr decodeSveMultiplyIndexed(ExtMachInst machInst); +StaticInstPtr decodeSveIntegerDotProductUnpred(ExtMachInst machInst); +StaticInstPtr decodeSveIntegerDotProductIndexed(ExtMachInst machInst); +StaticInstPtr decodeSveMixedSignDotProduct(ExtMachInst machInst); +StaticInstPtr decodeSveMixedSignDotProductIndexed(ExtMachInst machInst); StaticInstPtr decodeSveFpFastReduc(ExtMachInst machInst); StaticInstPtr decodeSveFpUnaryUnpred(ExtMachInst machInst); @@ -96,6 +98,8 @@ StaticInstPtr decodeSveMemStore(ExtMachInst machInst); StaticInstPtr decodeSveMisc(ExtMachInst machInst); +StaticInstPtr decodeSveIntegerMulAddUnpred(ExtMachInst machInst); +StaticInstPtr decodeSveMultiplyIndexed(ExtMachInst machInst); } }}; @@ -107,10 +111,31 @@ decodeSveInt(ExtMachInst machInst) { if (bits(machInst, 31, 29) == 0b010) { -if (bits(machInst, 24) == 0b1 && -bits(machInst, 21) == 0b0 && -bits(machInst, 15, 14)==0b10) { -return decodeSveMisc(machInst); +uint8_t op1 = bits(machInst, 24, 23); +switch (op1) { + case 0b00: + case 0b01: + if (bits(machInst, 21) == 0b0) { + if (bits(machInst, 15) == 0b0) { + return decodeSveIntegerMulAddUnpred(machInst); + } else { + return new Unknown64(machInst); + } + } else { + return decodeSveMultiplyIndexed(machInst); + } + break; + case 0b10: + case 0b11: + if (bits(machInst, 21) == 0b0 && + bits(machInst, 15, 14) == 0b10) { + return decodeSveMisc(machInst); + } else { + return new Unknown64(machInst); + } + break; + default: + return new Unknown64(machInst); } } @@ -130,11 +155,10 @@ bits(machInst, 13); switch (b_15_13) { case 0x0: -if (bits(machInst, 30)) { -return decodeSveMultiplyAddUnpred(machInst); -} else { +if (!bits(machInst, 30)) { return decodeSveIntArithBinPred(machInst); } +break; case 0x1: return decodeSveIntReduc(machInst); case 0x2: @@ -155,12 +179,11 @@ if (b_13) { return decodeSveIntLogUnpred(machInst); } else { -if (bits(machInst, 30)) { -return decodeSveMultiplyIndexed(machInst); -} else { +if (!bits(machInst, 30)) { return decodeSveIntArithUnpred(machInst); } } +break; case 0x1: if (b_13) { return new Unknown64(machInst); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70731?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I42b280d4bd1b4ab9d8c633bdc523bd08c281d218 Gerrit-Change-Number: 70731 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Declare support for Armv8.2-F64MM.
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70729?usp=email to review the following change. Change subject: arch-arm: Declare support for Armv8.2-F64MM. .. arch-arm: Declare support for Armv8.2-F64MM. Sets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares support for ARMv8.2-F64MM. This indicates that all pre-requisites for Armv8.2 SVE FP64 double-precision floating-point matrix multiplication instructions have been met. FMMLA, and LD1RO* instructions have been implemented, as well as the 128-bit element variants of TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2. For more information please refer to the "ARM Architecture Reference Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A" (https://developer.arm.com/architectures/cpu-architecture/a-profile/ docs/arm-architecture-reference-manual-supplement-armv8-a) Change-Id: Idac3a3ca590e6eb2beb217a40a8c10af1e917440 Reviewed-by: Richard Cooper --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/regs/misc.cc 3 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index 31ecbcb..fbd93b6 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -54,6 +54,7 @@ "FEAT_RDM", # Armv8.2 "FEAT_F32MM", +"FEAT_F64MM", "FEAT_SVE", # Armv8.3 "FEAT_FCMA", diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 06d1dcc..5517632 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -79,6 +79,7 @@ "FEAT_LVA", # Optional in Armv8.2 "FEAT_LPA", # Optional in Armv8.2 "FEAT_F32MM", # Optional in Armv8.2 +"FEAT_F64MM", # Optional in Armv8.2 # Armv8.3 "FEAT_FCMA", "FEAT_JSCVT", @@ -165,6 +166,7 @@ "FEAT_LPA", "FEAT_SVE", "FEAT_F32MM", +"FEAT_F64MM", # Armv8.3 "FEAT_FCMA", "FEAT_JSCVT", @@ -199,6 +201,7 @@ "FEAT_LPA", "FEAT_SVE", "FEAT_F32MM", +"FEAT_F64MM", ] diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 6cabfca..362f996 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -5405,6 +5405,7 @@ .reset([this](){ AA64ZFR0 zfr0_el1 = 0; zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 : 0; +zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 : 0; return zfr0_el1; }()) .faultRead(EL0, faultIdst) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70729?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Idac3a3ca590e6eb2beb217a40a8c10af1e917440 Gerrit-Change-Number: 70729 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add support for Armv8.2-I8MM NEON extension.
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70737?usp=email to review the following change. Change subject: arch-arm: Add support for Armv8.2-I8MM NEON extension. .. arch-arm: Add support for Armv8.2-I8MM NEON extension. Add support for the Armv8.2-I8MM NEON extension. This provides the SUDOT and USDOT mixed-sign SIMD Dot Product instructions, as well as the SMMLA, UMMLA, and USMMLA SIMD Matrix Multiply-Accumulate instructions. For more information please refer to the Arm Architecture Reference Manual (https://developer.arm.com/documentation/ddi0487/latest/). Additional Contributors: Giacomo Travaglini Change-Id: I6fb9318f67cc9d2737079283e1a095630c4d2ad9 Reviewed-by: Richard Cooper --- M src/arch/arm/isa/formats/neon64.isa M src/arch/arm/isa/insts/neon64.isa M src/arch/arm/regs/misc.cc M src/arch/arm/regs/misc_types.hh 4 files changed, 138 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/isa/formats/neon64.isa b/src/arch/arm/isa/formats/neon64.isa index e083f6f..8d9b74d 100644 --- a/src/arch/arm/isa/formats/neon64.isa +++ b/src/arch/arm/isa/formats/neon64.isa @@ -510,6 +510,7 @@ decodeNeon3RegExtension(ExtMachInst machInst) { uint8_t q = bits(machInst, 30); +uint8_t u = bits(machInst, 29); uint8_t qu = bits(machInst, 30, 29); uint8_t size = bits(machInst, 23, 22); uint8_t opcode = bits(machInst, 15, 11); @@ -546,6 +547,20 @@ default: return new Unknown64(machInst); } + case 0x13: + if (q) { + return new UsdotQX(machInst, vd, vn, vm); + } else { + return new UsdotDX(machInst, vd, vn, vm); + } + case 0x14: + if (u) { + return new UmmlaQX(machInst, vd, vn, vm); + } else { + return new SmmlaQX(machInst, vd, vn, vm); + } + case 0x15: + return new UsmmlaQX(machInst, vd, vn, vm); case 0x18: case 0x19: case 0x1a: @@ -1590,9 +1605,6 @@ return decodeNeonSThreeImmHAndWReg( q, size, machInst, vd, vn, vm, index); - case 0xf: -return decodeNeonSThreeImmHAndWRegSqrdmlshElemQX>( -q, size, machInst, vd, vn, vm, index); case 0xe: switch (qu) { case 0b00: @@ -1610,6 +1622,39 @@ default: return new Unknown64(machInst); } + case 0xf: + if (u) { + // Armv8.2-RDMA SQRDMLSH(elem) + return decodeNeonSThreeImmHAndWReg( + q, size, machInst, vd, vn, vm, index); + } else { + switch (size) { + case 0x0: + if (q) { + return new SudotElemQX( + machInst, vd, vn, vm_dp, index_dp); + } else { + return new SudotElemDX( + machInst, vd, vn, vm_dp, index_dp); + } + case 0x1: + // Armv8.2-BF16 BFDOT(elem) + return new Unknown64(machInst); + case 0x2: + if (q) { + return new UsdotElemQX( + machInst, vd, vn, vm_dp, index_dp); + } else { + return new UsdotElemDX( + machInst, vd, vn, vm_dp, index_dp); + } + case 0x3: + default: + // Armv8.2-BF16 BFMLALB(elem), BFMLALT(elem) + return new Unknown64(machInst); + } + } default: return new Unknown64(machInst); } diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa index 53c0f11..6608f61 100644 --- a/src/arch/arm/isa/insts/neon64.isa +++ b/src/arch/arm/isa/insts/neon64.isa @@ -1146,6 +1146,94 @@ # UDOT (element) intDotInst('udot', 'UdotElemDX', 'SimdAluOp', False, False, False, 2, True) intDotInst('udot', 'UdotElemQX', 'SimdAluOp', False, False, False, 4, True) +# SUDOT (element) +intDotInst('sudot', 'SudotElemDX', 'SimdAluOp', True, True, False, 2, True) +intDotInst('sudot', 'SudotElemQX', 'SimdAluOp', True, True, False, 4, True) +# USDOT (vector) +intDotInst('usdot
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Declare support for Armv8.2-I8MM.
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70733?usp=email to review the following change. Change subject: arch-arm: Declare support for Armv8.2-I8MM. .. arch-arm: Declare support for Armv8.2-I8MM. Sets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares support for ARMv8.2-I8MM. This indicates that all pre-requisites for Armv8.2 SVE Int8 matrix multiplication instructions have been met. SMMLA, SUDOT, UMMLA, USMMLA, and USDOT instructions are implemented. For more information please refer to the "ARM Architecture Reference Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A" (https://developer.arm.com/architectures/cpu-architecture/a-profile/ docs/arm-architecture-reference-manual-supplement-armv8-a) Change-Id: Id97e1c5de8c23a25336a6b323034e9eca8e598e4 Reviewed-by: Richard Cooper --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/regs/misc.cc 3 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index fbd93b6..ffe63eb 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -56,6 +56,7 @@ "FEAT_F32MM", "FEAT_F64MM", "FEAT_SVE", +"FEAT_I8MM", # Armv8.3 "FEAT_FCMA", "FEAT_JSCVT", diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 5517632..9e66ee7 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -80,6 +80,7 @@ "FEAT_LPA", # Optional in Armv8.2 "FEAT_F32MM", # Optional in Armv8.2 "FEAT_F64MM", # Optional in Armv8.2 +"FEAT_I8MM", # Optional in Armv8.2 # Armv8.3 "FEAT_FCMA", "FEAT_JSCVT", @@ -167,6 +168,7 @@ "FEAT_SVE", "FEAT_F32MM", "FEAT_F64MM", +"FEAT_I8MM", # Armv8.3 "FEAT_FCMA", "FEAT_JSCVT", @@ -202,6 +204,7 @@ "FEAT_SVE", "FEAT_F32MM", "FEAT_F64MM", +"FEAT_I8MM", ] diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 362f996..6b299aa 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -5406,6 +5406,7 @@ AA64ZFR0 zfr0_el1 = 0; zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 : 0; zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 : 0; +zfr0_el1.i8mm = release->has(ArmExtension::FEAT_I8MM) ? 1 : 0; return zfr0_el1; }()) .faultRead(EL0, faultIdst) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70733?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id97e1c5de8c23a25336a6b323034e9eca8e598e4 Gerrit-Change-Number: 70733 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Fix too long lines in existing Arm NEON instructons.
;> 1) & 0x1; -// Use division instead of a shift to ensure the sign extension works -// right. The compiler will figure out if it can be a shift. Mask the -// inputs so they get truncated correctly. +// Use division instead of a shift to ensure the sign extension +// works right. The compiler will figure out if it can be a shift. +// Mask the inputs so they get truncated correctly. destElem = (((srcElem1 & ~(Element)1) / 2) - ((srcElem2 & ~(Element)1) / 2)) - borrowBit; ''' @@ -2802,7 +2802,8 @@ FPSCR fpscr = (FPSCR) FpscrQc; destElem = srcElem1; if (srcElem1 < 0 || -((BigElement)destElem & mask(sizeof(Element) * 8)) != srcElem1) { +((BigElement)destElem & mask(sizeof(Element) * 8)) + != srcElem1) { fpscr.qc = 1; destElem = mask(sizeof(Element) * 8); if (srcElem1 < 0) @@ -2821,9 +2822,9 @@ Element carryBit = (((unsigned)srcElem1 & 0x1) + ((unsigned)srcElem2 & 0x1) + 1) >> 1; -// Use division instead of a shift to ensure the sign extension works -// right. The compiler will figure out if it can be a shift. Mask the -// inputs so they get truncated correctly. +// Use division instead of a shift to ensure the sign extension +// works right. The compiler will figure out if it can be a shift. +// Mask the inputs so they get truncated correctly. destElem = (((srcElem1 & ~(Element)1) / 2) + ((srcElem2 & ~(Element)1) / 2)) + carryBit; ''' @@ -3013,7 +3014,8 @@ if (bits(destElem, sizeof(Element) * 8 - 1) == 0) { if (bits(tmp, sizeof(Element) * 8 - 1) == 1 || tmp < srcElem1 || tmp < destElem) { -destElem = (((Element) 1) << (sizeof(Element) * 8 - 1)) - 1; +destElem = (((Element) 1) << (sizeof(Element) * 8 - 1)) + - 1; fpscr.qc = 1; } else { destElem = tmp; @@ -3021,9 +3023,11 @@ } else { Element absDestElem = (~destElem) + 1; if (absDestElem < srcElem1) { -// Still check for positive sat., no need to check for negative sat. +// Still check for positive sat., no need to check for +// negative sat. if (bits(tmp, sizeof(Element) * 8 - 1) == 1) { -destElem = (((Element) 1) << (sizeof(Element) * 8 - 1)) - 1; +destElem = (((Element) 1) << (sizeof(Element) * 8 - 1)) + - 1; fpscr.qc = 1; } else { destElem = tmp; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70735?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I587fcb2d75c4ab9de47fa53b4ae96526a20afe3f Gerrit-Change-Number: 70735 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts
2022 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -72,6 +72,7 @@ static const OpClass SimdMiscOp = enums::SimdMisc; static const OpClass SimdMultOp = enums::SimdMult; static const OpClass SimdMultAccOp = enums::SimdMultAcc; +static const OpClass SimdMatMultAccOp = enums::SimdMatMultAcc; static const OpClass SimdShiftOp = enums::SimdShift; static const OpClass SimdShiftAccOp = enums::SimdShiftAcc; static const OpClass SimdDivOp = enums::SimdDiv; @@ -87,6 +88,7 @@ static const OpClass SimdFloatMiscOp = enums::SimdFloatMisc; static const OpClass SimdFloatMultOp = enums::SimdFloatMult; static const OpClass SimdFloatMultAccOp = enums::SimdFloatMultAcc; +static const OpClass SimdFloatMatMultAccOp = enums::SimdFloatMatMultAcc; static const OpClass SimdFloatSqrtOp = enums::SimdFloatSqrt; static const OpClass SimdFloatReduceCmpOp = enums::SimdFloatReduceCmp; static const OpClass SimdFloatReduceAddOp = enums::SimdFloatReduceAdd; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70734?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ifab63a0efbb0ccfbd272245e0b0b055279f66e3a Gerrit-Change-Number: 70734 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Added 128-bit encodings of SVE TRN, UZP, and ZIP insts.
Op2_x[s - eltsInPairsCount]; } } -for (unsigned i = 0; i < eCount; i++) { +// Fill output vector with pairs of elements +for (unsigned i = 0; i < eltsInPairsCount; i++) { AA64FpDest_x[i] = auxDest[i]; } +// Fill any trailing non-full pairs with zeros +for (unsigned i = eltsInPairsCount; i < eCount; i++) { +AA64FpDest_x[i] = 0; +} ''' -sveBinInst('uzp1', 'Uzp1', 'SimdAluOp', unsignedTypes, '', - customIterCode=uzpIterCode % 0) -sveBinInst('uzp2', 'Uzp2', 'SimdAluOp', unsignedTypes, '', - customIterCode=uzpIterCode % 1) +sveBinInst('uzp1', 'Uzp1', 'SimdAluOp', extendedUnsignedTypes, '', + customIterCode=uzpIterCode % dict(mnemonic='uzp1', part=0)) +sveBinInst('uzp2', 'Uzp2', 'SimdAluOp', extendedUnsignedTypes, '', + customIterCode=uzpIterCode % dict(mnemonic='uzp2', part=1)) # WHILELE (32-bit) whileLECode = ''' cond = srcElem1 <= srcElem2; @@ -5000,22 +5051,35 @@ zipPredIterCode % 1) # ZIP1, ZIP2 (vectors) zipIterCode = ''' +// SVE F64MM support requires that there are at least two elements +// in the vector. +if (eCount < 2) { +return std::make_shared(machInst, false, + "%(mnemonic)s"); +} int s; -int part = %d; +int part = %(part)d; ArmISA::VecRegContainer tmpVecC; auto auxDest = tmpVecC.as(); -for (unsigned i = 0; i < eCount / 2; i++) { -s = i + (part * (eCount / 2)); +const unsigned eltPairsCount = eCount / 2; +const unsigned eltsInPairsCount = eltPairsCount * 2; +for (unsigned i = 0; i < eltPairsCount; i++) { +s = i + (part * (eltsInPairsCount / 2)); auxDest[2 * i] = AA64FpOp1_x[s]; auxDest[2 * i + 1] = AA64FpOp2_x[s]; } -for (unsigned i = 0; i < eCount; i++) { +// Fill output vector with pairs of elements +for (unsigned i = 0; i < eltsInPairsCount; i++) { AA64FpDest_x[i] = auxDest[i]; } +// Fill any trailing non-full pairs with zeros +for (unsigned i = eltsInPairsCount; i < eCount; i++) { +AA64FpDest_x[i] = 0; +} ''' -sveBinInst('zip1', 'Zip1', 'SimdAluOp', unsignedTypes, '', - customIterCode=zipIterCode % 0) -sveBinInst('zip2', 'Zip2', 'SimdAluOp', unsignedTypes, '', - customIterCode=zipIterCode % 1) +sveBinInst('zip1', 'Zip1', 'SimdAluOp', extendedUnsignedTypes, '', + customIterCode=zipIterCode % dict(mnemonic='zip1', part=0)) +sveBinInst('zip2', 'Zip2', 'SimdAluOp', extendedUnsignedTypes, '', + customIterCode=zipIterCode % dict(mnemonic='zip2', part=1)) }}; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70728?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I496576340c48410fedb2cf6fc7d1a02e219b3bd4 Gerrit-Change-Number: 70728 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add support for Arm SVE Integer Matrix instructions.
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70730?usp=email to review the following change. Change subject: arch-arm: Add support for Arm SVE Integer Matrix instructions. .. arch-arm: Add support for Arm SVE Integer Matrix instructions. Add support for the Arm SVE Integer Matrix Multiply-Accumulate (SMMLA, USMMLA, UMMLA) instructions. Because the associated SUDOT and USDOT instructions have not yet been implemented, the SVE Feature ID register 0 (ID_AA64ZFR0_EL1) has not yet been updated to indicate support for SVE Int8 matrix multiplication instructions at this time. For more information please refer to the "ARM Architecture Reference Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A" (https://developer.arm.com/architectures/cpu-architecture/a-profile/ docs/arm-architecture-reference-manual-supplement-armv8-a) Additional Contributors: Giacomo Travaglini Change-Id: Ia50e28fae03634cbe04b42a9900bab65a604817f Reviewed-by: Richard Cooper --- M src/arch/arm/isa/formats/sve_2nd_level.isa M src/arch/arm/isa/formats/sve_top_level.isa M src/arch/arm/isa/insts/sve.isa 3 files changed, 72 insertions(+), 0 deletions(-) diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa index 6add341..e0ab5f9 100644 --- a/src/arch/arm/isa/formats/sve_2nd_level.isa +++ b/src/arch/arm/isa/formats/sve_2nd_level.isa @@ -246,6 +246,33 @@ } // decodeSveIntMulAdd StaticInstPtr +decodeSveIntMatMulAdd(ExtMachInst machInst) +{ +RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0); +RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5); +RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16); + +uint8_t uns = bits(machInst, 23, 22); + +switch (uns) { + case 0x0: +return new SveSmmla( + machInst, zda, zn, zm); + case 0x2: +return new SveUsmmla( + machInst, zda, zn, zm); + case 0x3: +return new SveUmmla( + machInst, zda, zn, zm); + case 0x1: + default: +return new Unknown64(machInst); +} + +return new Unknown64(machInst); +} // decodeSveIntMatMulAdd + +StaticInstPtr decodeSveShiftByImmPred0(ExtMachInst machInst) { RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0); @@ -3763,5 +3790,21 @@ return new Unknown64(machInst); } // decodeSveMemStore +StaticInstPtr +decodeSveMisc(ExtMachInst machInst) { +switch(bits(machInst, 13, 10)) { + case 0b0110: { + return decodeSveIntMatMulAdd(machInst); + break; + } + default: { + return new Unknown64(machInst); + break; + } +} +return new Unknown64(machInst); +} // decodeSveMisc + + } // namespace Aarch64 }}; diff --git a/src/arch/arm/isa/formats/sve_top_level.isa b/src/arch/arm/isa/formats/sve_top_level.isa index 1f3b463..0699637 100644 --- a/src/arch/arm/isa/formats/sve_top_level.isa +++ b/src/arch/arm/isa/formats/sve_top_level.isa @@ -44,6 +44,7 @@ StaticInstPtr decodeSveShiftByImmPred(ExtMachInst machInst); StaticInstPtr decodeSveIntArithUnaryPred(ExtMachInst machInst); StaticInstPtr decodeSveIntMulAdd(ExtMachInst machInst); +StaticInstPtr decodeSveIntMatMulAdd(ExtMachInst machInst); StaticInstPtr decodeSveIntArithUnpred(ExtMachInst machInst); StaticInstPtr decodeSveIntLogUnpred(ExtMachInst machInst); StaticInstPtr decodeSveIndexGen(ExtMachInst machInst); @@ -93,6 +94,8 @@ StaticInstPtr decodeSveMemContigLoad(ExtMachInst machInst); StaticInstPtr decodeSveMemGather64(ExtMachInst machInst); StaticInstPtr decodeSveMemStore(ExtMachInst machInst); + +StaticInstPtr decodeSveMisc(ExtMachInst machInst); } }}; @@ -103,6 +106,14 @@ StaticInstPtr decodeSveInt(ExtMachInst machInst) { +if (bits(machInst, 31, 29) == 0b010) { +if (bits(machInst, 24) == 0b1 && +bits(machInst, 21) == 0b0 && +bits(machInst, 15, 14)==0b10) { +return decodeSveMisc(machInst); +} +} + uint8_t b_29_24_21 = (bits(machInst, 29) << 2) | (bits(machInst, 24) << 1) | bits(machInst, 21); diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa index 30dbeba..f7bf8a3 100644 --- a/src/arch/arm/isa/insts/sve.isa +++ b/src/arch/arm/isa/insts/sve.isa @@ -4192,6 +4192,24 @@ # MLS mlsCode = 'destElem -= srcElem1 * srcElem2;' sveTerIns
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Added Armv8.2-I8MM SVE mixed-sign dot product instrs.
;], isIndexed = False) +# USDOT (indexed) +sveDotInst('usdot', 'Usdoti', 'SimdAluOp', ['uint8_t, int8_t, int32_t'], + isIndexed = True) +# USDOT (vectors) +sveDotInst('usdot', 'Usdotv', 'SimdAluOp', ['uint8_t, int8_t, int32_t'], + isIndexed = False) # UMAX (immediate) sveWideImmInst('umax', 'UmaxImm', 'SimdCmpOp', unsignedTypes, maxCode) # UMAX (vectors) diff --git a/src/arch/arm/isa/templates/sve.isa b/src/arch/arm/isa/templates/sve.isa index 9043e23..7c41b40 100644 --- a/src/arch/arm/isa/templates/sve.isa +++ b/src/arch/arm/isa/templates/sve.isa @@ -1113,17 +1113,22 @@ }}; def template SveWideningTerImmOpDeclare {{ -template +template class %(class_name)s : public %(base_class)s { + static_assert(sizeof(_SElementA) == sizeof(_SElementB), +"Source elements must have the same size."); + private: %(reg_idx_arr_decl)s; protected: typedef _DElement Element; -typedef _SElement SElement; +typedef _SElementA SElementA; +typedef _SElementB SElementB; typedef _DElement DElement; -typedef _SElement TPSElem; +typedef _SElementA TPSrcAElem; +typedef _SElementB TPSrcBElem; typedef _DElement TPDElem; public: @@ -1142,7 +1147,7 @@ }}; def template SveWideningTerOpDeclare {{ -template +template class %(class_name)s : public %(base_class)s { private: @@ -1150,9 +1155,11 @@ protected: typedef _DElement Element; -typedef _SElement SElement; +typedef _SElementA SElementA; +typedef _SElementB SElementB; typedef _DElement DElement; -typedef _SElement TPSElem; +typedef _SElementA TPSrcAElem; +typedef _SElementB TPSrcBElem; typedef _DElement TPDElem; public: @@ -1269,6 +1276,26 @@ } }}; +def template SveWideningTerOpExecute {{ +template +Fault %(class_name)s::execute + (ExecContext *xc, +trace::InstRecord *traceData) const +{ +Fault fault = NoFault; +%(op_decl)s; +%(op_rd)s; + +%(code)s; +if (fault == NoFault) +{ +%(op_wb)s; +} + +return fault; +} +}}; + def template SveNonTemplatedOpExecute {{ Fault %(class_name)s::execute(ExecContext *xc, -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70732?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I83841654cee74b940f967b3a37b99d87c01bd92c Gerrit-Change-Number: 70732 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Support Arm SVE Load-Broadcast Octaword instructions.
''' +''' % dict(memAccessSize=memAccessSize) memAccCode = ''' -__uint128_t qword; -RegElemType* qp = reinterpret_cast(&qword); -for (int i = 0; i < 16/sizeof(RegElemType); ++i) { +// Copy active elements of the data from memory into a temporary +// quadword/octaword +__uint128_t qwords[%(numQwordSegments)d]; +eCount = %(memAccessSize)d/sizeof(RegElemType); +RegElemType* qp = reinterpret_cast(&qwords); +for (int i = 0; i < eCount; ++i) { if (GpOp_x[i]) { qp[i] = memDataView[i]; } else { qp[i] = 0; } } -eCount = ArmStaticInst::getCurSveVecLen<__uint128_t>( +// Repeat the temporary quadword/octaword segment into the +// vector register. Zero fill the remainder for non-full +// octawords. +unsigned numQwords = ArmStaticInst::getCurSveVecLen<__uint128_t>( xc->tcBase()); -for (int i = 0; i < eCount; ++i) { -AA64FpDest_uq[i] = qword; +unsigned numFullQwords = numQwords - + (numQwords %% %(numQwordSegments)d); +for (int i = 0; i < numQwords; ++i) { +if (i < numFullQwords) { +AA64FpDest_uq[i] = qwords[i %% %(numQwordSegments)d]; +} else { +AA64FpDest_uq[i] = 0; +} } -''' -iop = ArmInstObjParams('ld1rq', -'SveLd1RqSI' if offsetIsImm else 'SveLd1RqSS', -'SveContigMemSI' if offsetIsImm else 'SveContigMemSS', +''' % dict(memAccessSize=memAccessSize, + numQwordSegments=numQwordSegments) +iop = ArmInstObjParams( +inst_config.mnemonic, +inst_config.classname, +inst_config.baseclass, {'tpl_header': tplHeader, 'tpl_args': tplArgs, 'rden_code': loadRdEnableCode, @@ -1539,8 +1566,7 @@ SveContigLoadCompleteAcc.subst(iop)) for ttype in ('uint8_t', 'uint16_t', 'uint32_t', 'uint64_t'): substDict = {'tpl_args': '<%s, %s>' % (ttype, ttype), -'class_name': 'SveLd1RqSI' if offsetIsImm - else 'SveLd1RqSS'} + 'class_name': inst_config.classname} exec_output += SveContigMemExecDeclare.subst(substDict) # LD1[S]{B,H,W,D} (scalar plus immediate) @@ -1556,9 +1582,14 @@ emitSveLoadAndRepl() # LD1RQ{B,H,W,D} (scalar plus immediate) -emitSveLoadAndReplQuad(offsetIsImm = True) +emitSveLoadAndReplMulti(offsetIsImm=True, numQwordSegments=1) # LD1RQ{B,H,W,D} (scalar plus scalar) -emitSveLoadAndReplQuad(offsetIsImm = False) +emitSveLoadAndReplMulti(offsetIsImm=False, numQwordSegments=1) + +# LD1RO{B,H,W,D} (scalar plus immediate) +emitSveLoadAndReplMulti(offsetIsImm=True, numQwordSegments=2) +# LD1RO{B,H,W,D} (scalar plus scalar) +emitSveLoadAndReplMulti(offsetIsImm=False, numQwordSegments=2) # LD{2,3,4}{B,H,W,D} (scalar plus immediate) # ST{2,3,4}{B,H,W,D} (scalar plus immediate) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70727?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I98ee4f56c8099bf40c9034baa488d318ae57d3aa Gerrit-Change-Number: 70727 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add support for Armv8.2-DotProd NEON extension.
); +default: + return new Unknown64(machInst); + } default: return new Unknown64(machInst); } diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa index 0da7f06..53c0f11 100644 --- a/src/arch/arm/isa/insts/neon64.isa +++ b/src/arch/arm/isa/insts/neon64.isa @@ -1082,6 +1082,71 @@ complex=True) threeEqualRegInstX("fcmla", "FcmlaQX", "SimdFloatMultAccOp", floatTypes, 4, fcmla_vec, True, complex=True) + +def intDotInst(name, Name, opClass, + destIsSigned, src1IsSigned, src2IsSigned, + rCount, byElem): +destType = "int32_t" if destIsSigned else "uint32_t" +src1Type = "int8_t" if src1IsSigned else "uint8_t" +src2Type = "int8_t" if src2IsSigned else "uint8_t" +dotCode = ''' +using Src1Element = %(src1Type)s; +using Src2Element = %(src2Type)s; + +// Neon dot instructions always generate one output element +// from 4 pairs of source elements. +static_assert(sizeof(Element) == 4 * sizeof(Src1Element)); +static_assert(sizeof(Element) == 4 * sizeof(Src2Element)); + +// Extended source element types to avoid overflow of intermediate +// calculations. +using ExtendedSrc1Element = +typename vector_element_traits:: +extend_element::type; +using ExtendedSrc2Element = +typename vector_element_traits:: +extend_element::type; + +for (unsigned i = 0; i < eCount; ++i) { +Element src1ElemsPacked = letoh(srcReg1.elements[i]); +Element src2ElemsPacked = letoh(srcReg2.elements[%(src2Index)s]); + +Src1Element *src1Elems = +reinterpret_cast(&src1ElemsPacked); +Src2Element *src2Elems = +reinterpret_cast(&src2ElemsPacked); + +// Dot instructions accumulate into the dest reg +Element destElem = letoh(destReg.elements[i]); + +for (unsigned j = 0; j < 4; ++j) { +ExtendedSrc1Element src1Elem = +static_cast(src1Elems[j]); +ExtendedSrc2Element src2Elem = +static_cast(src2Elems[j]); +destElem += src1Elem * src2Elem; +} +destReg.elements[i] = htole(destElem); +} +''' % dict(src1Type=src1Type, src2Type=src2Type, + src2Index="imm" if byElem else "i") +threeEqualRegInstX(name, Name, opClass, (destType,), rCount, + dotCode, readDest=True, byElem=byElem, + complex=True) + +# SDOT (vector) +intDotInst('sdot', 'SdotDX', 'SimdAluOp', True, True, True, 2, False) +intDotInst('sdot', 'SdotQX', 'SimdAluOp', True, True, True, 4, False) +# SDOT (element) +intDotInst('sdot', 'SdotElemDX', 'SimdAluOp', True, True, True, 2, True) +intDotInst('sdot', 'SdotElemQX', 'SimdAluOp', True, True, True, 4, True) +# UDOT (vector) +intDotInst('udot', 'UdotDX', 'SimdAluOp', False, False, False, 2, False) +intDotInst('udot', 'UdotQX', 'SimdAluOp', False, False, False, 4, False) +# UDOT (element) +intDotInst('udot', 'UdotElemDX', 'SimdAluOp', False, False, False, 2, True) +intDotInst('udot', 'UdotElemQX', 'SimdAluOp', False, False, False, 4, True) + # CLS clsCode = ''' unsigned count = 0; diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 6b299aa..3a39137 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3988,6 +3988,7 @@ isar0_el1.sha1 = 0; isar0_el1.aes = 0; } + isar0_el1.dp = release->has(ArmExtension::FEAT_DOTPROD) ? 0x1 : 0x0; isar0_el1.atomic = release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0; isar0_el1.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0; isar0_el1.tme = release->has(ArmExtension::TME) ? 0x1 : 0x0; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70736?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4caa3b97a74c65f32421487c55c3e36427194e61 Gerrit-Change-Number: 70736 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Add support for Arm SVE fmmla instruction.
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70726?usp=email to review the following change. Change subject: arch-arm: Add support for Arm SVE fmmla instruction. .. arch-arm: Add support for Arm SVE fmmla instruction. Add support for the Arm SVE Floating Point Matrix Multiply-Accumulate (FMMLA) instruction. Both 32-bit element (single precision) and 64-bit element (double precision) encodings are implemented, but because the associated required instructions (LD1RO*, etc) have not yet been implemented, the SVE Feature ID register 0 (ID_AA64ZFR0_EL1) has only been updated to indicate 32-bit element support at this time. For more information please refer to the "ARM Architecture Reference Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A" (https://developer.arm.com/architectures/cpu-architecture/a-profile/ docs/arm-architecture-reference-manual-supplement-armv8-a) Additional Contributors: Giacomo Travaglini Change-Id: If3547378ffa48527fe540767399bcc37a5dab524 Reviewed-by: Richard Cooper --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/insts/sve.cc M src/arch/arm/insts/sve.hh A src/arch/arm/insts/vector_element_traits.hh M src/arch/arm/isa/formats/sve_2nd_level.isa M src/arch/arm/isa/formats/sve_top_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/sve.isa M src/arch/arm/isa/operands.isa M src/arch/arm/isa/templates/sve.isa M src/arch/arm/regs/misc.cc 12 files changed, 319 insertions(+), 8 deletions(-) diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index 37970dc..31ecbcb 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -53,6 +53,7 @@ "FEAT_LSE", "FEAT_RDM", # Armv8.2 +"FEAT_F32MM", "FEAT_SVE", # Armv8.3 "FEAT_FCMA", diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index b826f0d..06d1dcc 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -78,6 +78,7 @@ "FEAT_UAO", "FEAT_LVA", # Optional in Armv8.2 "FEAT_LPA", # Optional in Armv8.2 +"FEAT_F32MM", # Optional in Armv8.2 # Armv8.3 "FEAT_FCMA", "FEAT_JSCVT", @@ -163,6 +164,7 @@ "FEAT_LVA", "FEAT_LPA", "FEAT_SVE", +"FEAT_F32MM", # Armv8.3 "FEAT_FCMA", "FEAT_JSCVT", @@ -196,6 +198,7 @@ "FEAT_LVA", "FEAT_LPA", "FEAT_SVE", +"FEAT_F32MM", ] diff --git a/src/arch/arm/insts/sve.cc b/src/arch/arm/insts/sve.cc index 546074c..b2f166e 100644 --- a/src/arch/arm/insts/sve.cc +++ b/src/arch/arm/insts/sve.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 ARM Limited + * Copyright (c) 2017-2020 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -436,6 +436,20 @@ } std::string +SveTerUnpredOp::generateDisassembly( +Addr pc, const loader::SymbolTable *symtab) const +{ +std::stringstream ss; +printMnemonic(ss, "", false); +printVecReg(ss, dest, true); +ccprintf(ss, ", "); +printVecReg(ss, op1, true); +ccprintf(ss, ", "); +printVecReg(ss, op2, true); +return ss.str(); +} + +std::string SveTerImmUnpredOp::generateDisassembly( Addr pc, const loader::SymbolTable *symtab) const { diff --git a/src/arch/arm/insts/sve.hh b/src/arch/arm/insts/sve.hh index 66d82f0..73f4766 100644 --- a/src/arch/arm/insts/sve.hh +++ b/src/arch/arm/insts/sve.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 ARM Limited + * Copyright (c) 2017-2020 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -498,6 +498,22 @@ Addr pc, const loader::SymbolTable *symtab) const override; }; +/// Ternary, destructive, unpredicated SVE instruction. +class SveTerUnpredOp : public ArmStaticInst +{ + protected: +RegIndex dest, op1, op2; + +SveTerUnpredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, + RegIndex _dest, RegIndex _op1, RegIndex _op2) : +ArmStaticInst(mnem, _machInst, __opClass), +dest(_dest), op1(_op1), op2(_op2) +{} + +std::string generateDisassembly( +Addr pc, const loader::SymbolTable *symtab) const override; +}; + /// Ternary with immediate, destructive, unpredicated SVE instruction. class SveTerImmUnpredOp : public ArmStaticInst { diff --git a/src/arch/arm/insts/vector_element_traits.hh b/src/arch/arm/insts/
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Rename AdvSIMD instruction pool
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email to review the following change. Change subject: arch-arm: Rename AdvSIMD instruction pool .. arch-arm: Rename AdvSIMD instruction pool The decoding function was wrongly named decodeNeon3SameExtra, referring to the "AdvSIMD three same Extra" instruction pool This might be an old name as I can only find the "AdvSIMD *scalar* three same Extra" in the Arm arm. The encoding space reserved to the pool bears the "Advanced SIMD three-register extension" name; we therefore rename the function to decodeNeon3RegExtension Change-Id: I056da8f0c7808935d12a4b05490d30654178071f Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/formats/neon64.isa 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 9ad2de2..47d509e 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -2461,7 +2461,7 @@ return new Unknown64(machInst); } } else if (bits(machInst, 15) == 1) { -return decodeNeon3SameExtra(machInst); +return decodeNeon3RegExtension(machInst); } else if (bits(machInst, 10) == 1) { if (bits(machInst, 23, 22)) return new Unknown64(machInst); diff --git a/src/arch/arm/isa/formats/neon64.isa b/src/arch/arm/isa/formats/neon64.isa index 72b7e28..c200da7 100644 --- a/src/arch/arm/isa/formats/neon64.isa +++ b/src/arch/arm/isa/formats/neon64.isa @@ -39,9 +39,9 @@ // AdvSIMD three same template StaticInstPtr decodeNeon3Same(ExtMachInst machInst); -// AdvSIMD three same Extra +// AdvSIMD three register extension template -StaticInstPtr decodeNeon3SameExtra(ExtMachInst machInst); +StaticInstPtr decodeNeon3RegExtension(ExtMachInst machInst); // AdvSIMD three different inline StaticInstPtr decodeNeon3Diff(ExtMachInst machInst); // AdvSIMD two-reg misc @@ -507,7 +507,7 @@ template StaticInstPtr -decodeNeon3SameExtra(ExtMachInst machInst) +decodeNeon3RegExtension(ExtMachInst machInst) { uint8_t q = bits(machInst, 30); uint8_t size = bits(machInst, 23, 22); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I056da8f0c7808935d12a4b05490d30654178071f Gerrit-Change-Number: 70724 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_FLAGM(2)
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70719?usp=email to review the following change. Change subject: arch-arm: Implement FEAT_FLAGM(2) .. arch-arm: Implement FEAT_FLAGM(2) Change-Id: I21f1eb91ad9acb019a776a7d5edd38754571a62e Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/insts/misc64.cc M src/arch/arm/insts/misc64.hh M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/insts/misc64.isa M src/arch/arm/isa/templates/misc64.isa M src/arch/arm/regs/misc.cc 8 files changed, 239 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index e73046d..37970dc 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -58,6 +58,10 @@ "FEAT_FCMA", "FEAT_JSCVT", "FEAT_PAuth", +# Armv8.4 +"FEAT_FLAGM", +# Armv8.5 +"FEAT_FLAGM2", # Armv9.2 "FEAT_SME", # Other diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 9e2da8e..e08108f 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -85,6 +85,9 @@ # Armv8.4 "FEAT_SEL2", "FEAT_TLBIOS", +"FEAT_FLAGM", +# Armv8.5 +"FEAT_FLAGM2", # Armv9.2 "FEAT_SME", # Optional in Armv9.2 # Others @@ -164,6 +167,9 @@ # Armv8.4 "FEAT_SEL2", "FEAT_TLBIOS", +"FEAT_FLAGM", +# Armv8.5 +"FEAT_FLAGM2", # Armv9.2 "FEAT_SME", ] @@ -194,11 +200,15 @@ class Armv84(Armv83): -extensions = Armv83.extensions + ["FEAT_SEL2", "FEAT_TLBIOS"] +extensions = Armv83.extensions + ["FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM"] -class Armv92(Armv84): -extensions = Armv84.extensions + ["FEAT_SME"] +class Armv85(Armv84): +extensions = Armv84.extensions + ["FEAT_FLAGM2"] + + +class Armv92(Armv85): +extensions = Armv85.extensions + ["FEAT_SME"] class ArmSystem(System): diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index c7423d9..4f573fc 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -55,6 +55,27 @@ } std::string +RegOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const +{ +std::stringstream ss; +printMnemonic(ss, "", false); +printIntReg(ss, op1); +return ss.str(); +} + +std::string +RegImmImmOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const +{ +std::stringstream ss; +printMnemonic(ss, "", false); +printIntReg(ss, op1); +ccprintf(ss, "#0x%x", imm1); +ss << ", "; +ccprintf(ss, "#0x%x", imm2); +return ss.str(); +} + +std::string RegRegImmImmOp64::generateDisassembly( Addr pc, const loader::SymbolTable *symtab) const { diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh index b7b66c2..3a67210 100644 --- a/src/arch/arm/insts/misc64.hh +++ b/src/arch/arm/insts/misc64.hh @@ -57,6 +57,38 @@ Addr pc, const loader::SymbolTable *symtab) const override; }; +class RegOp64 : public ArmISA::ArmStaticInst +{ + protected: +RegIndex op1; + +RegOp64(const char *mnem, ArmISA::ExtMachInst _machInst, +OpClass __opClass, RegIndex _op1) : +ArmISA::ArmStaticInst(mnem, _machInst, __opClass), op1(_op1) +{} + +std::string generateDisassembly( +Addr pc, const loader::SymbolTable *symtab) const override; +}; + +class RegImmImmOp64 : public ArmISA::ArmStaticInst +{ + protected: +RegIndex op1; +uint64_t imm1; +uint64_t imm2; + +RegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, + OpClass __opClass, RegIndex _op1, + uint64_t _imm1, uint64_t _imm2) : +ArmISA::ArmStaticInst(mnem, _machInst, __opClass), +op1(_op1), imm1(_imm1), imm2(_imm2) +{} + +std::string generateDisassembly( +Addr pc, const loader::SymbolTable *symtab) const override; +}; + class RegRegImmImmOp64 : public ArmISA::ArmStaticInst { protected: diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 0aafa9e..9ad2de2 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -424,6 +424,15 @@ // MSR immediate: moving immediate value to selected
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Improve debugging of CC regs accesses
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70718?usp=email to review the following change. Change subject: arch-arm: Improve debugging of CC regs accesses .. arch-arm: Improve debugging of CC regs accesses As of now we are simply printing the CC reg index which is not particularly helpful. With this patch we actually print the (NZ|C|V) reg name. Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/regs/cc.hh 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/src/arch/arm/regs/cc.hh b/src/arch/arm/regs/cc.hh index ba75527..474e48e 100644 --- a/src/arch/arm/regs/cc.hh +++ b/src/arch/arm/regs/cc.hh @@ -61,10 +61,31 @@ NumRegs }; +const char * const RegName[NumRegs] = { +"nz", +"c", +"v", +"ge", +"fp", +"zero" +}; + } // namespace cc_reg -inline constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, -cc_reg::NumRegs, debug::CCRegs); +class CCRegClassOps : public RegClassOps +{ + public: +std::string +regName(const RegId &id) const override +{ +return cc_reg::RegName[id.index()]; +} +}; + +static inline CCRegClassOps ccRegClassOps; + +inline constexpr RegClass ccRegClass = RegClass(CCRegClass, CCRegClassName, +cc_reg::NumRegs, debug::CCRegs).ops(ccRegClassOps); namespace cc_reg { @@ -77,15 +98,6 @@ Fp = ccRegClass[_FpIdx], Zero = ccRegClass[_ZeroIdx]; -const char * const RegName[NumRegs] = { -"nz", -"c", -"v", -"ge", -"fp", -"zero" -}; - } // namespace cc_reg enum ConditionCode -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70718?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce Gerrit-Change-Number: 70718 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement trapping of SME registers
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70722?usp=email to review the following change. Change subject: arch-arm: Implement trapping of SME registers .. arch-arm: Implement trapping of SME registers Change-Id: Ic5bcc79a535c928265fbc1db1cd0c85ba1a1b152 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/regs/misc.cc 1 file changed, 80 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index df1f6db..10b7d38 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2002,6 +2002,68 @@ } Fault +faultEsm(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3); +if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.esm) { +return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SME, 0); +} else { +return NoFault; +} +} + +Fault +faultTsmSmen(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const HCR hcr_el2 = tc->readMiscReg(MISCREG_HCR_EL2); +const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2); +const bool el2_enabled = EL2Enabled(tc); +if (el2_enabled && !hcr_el2.e2h && cptr_el2.tsm) { +return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0); +} else if (el2_enabled && hcr_el2.e2h && !(cptr_el2.smen & 0b1)) { +return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0); +} else { +return faultEsm(entry, tc, inst); +} +} + +Fault +faultSmenEL1(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); +if (!(cpacr.smen & 0b1)) { +return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SME, 0); +} else { +return faultTsmSmen(entry, tc, inst); +} +} + +Fault +faultSmenEL0(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const bool el2_enabled = EL2Enabled(tc); +const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); +const bool in_host = hcr.e2h && hcr.tge; + +const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); +const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2); +if (!(el2_enabled && in_host) && cpacr.smen != 0b11) { +if (el2_enabled && hcr.tge) +return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0); +else +return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SME, 0); +} else if (el2_enabled && in_host && cptr_el2.smen != 0b11) { +return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0); +} else { +return faultTsmSmen(entry, tc, inst); +} +} + +Fault faultRng(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst) { @@ -5347,6 +5409,7 @@ smfr0_el1.fa64 = 0x1; return smfr0_el1; }()) +.faultRead(EL1, HCR_TRAP(tid3)) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_SVCR) .res0([](){ @@ -5355,6 +5418,10 @@ svcr_mask.za = 1; return ~svcr_mask; }()) +.fault(EL0, faultSmenEL0) +.fault(EL1, faultSmenEL1) +.fault(EL2, faultTsmSmen) +.fault(EL3, faultEsm) .allPrivileges(); InitReg(MISCREG_SMIDR_EL1) .reset([](){ @@ -5364,11 +5431,17 @@ smidr_el1.implementer = 0x41; return smidr_el1; }()) +.faultRead(EL1, HCR_TRAP(tid1)) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_SMPRI_EL1) .res0(mask(63, 4)) -.allPrivileges().exceptUserMode().reads(1); +.fault(EL1, faultEsm) +.fault(EL2, faultEsm) +.fault(EL3, faultEsm) +.allPrivileges().exceptUserMode(); InitReg(MISCREG_SMPRIMAP_EL2) +.fault(EL2, faultEsm) +.fault(EL3, faultEsm) .hyp().mon(); InitReg(MISCREG_SMCR_EL3) .reset([this](){ @@ -5382,6 +5455,7 @@ smcr_el3.len = smeVL - 1; return smcr_el3; }()) +.fault(EL3, faultEsm) .mon(); InitReg(MISCREG_SMCR_EL2) .reset([this](){ @@ -5395,6 +5469,8 @@ smcr_el2.len = smeVL - 1; return smcr_el2; }()) +.fault(EL2, faultTsmSmen) +.fault(EL3, faultEsm) .hyp().mon(); InitReg(MISCREG_SMCR_EL12) .allPrivileges().exceptUserMode(); @@ -5410,6 +5486,9 @@ smcr_el1.len = smeVL - 1; return smcr_el1;
[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Split decodeDataProcReg into subfunctions
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70717?usp=email to review the following change. Change subject: arch-arm: Split decodeDataProcReg into subfunctions .. arch-arm: Split decodeDataProcReg into subfunctions This will increase readibility, it will make it easier for devs to add new instructions, and it removes some duplication (some register indexes were read more than once) Change-Id: Ifa03a93cb73de0b2dc93d7784f9011e0e55dfc1e Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/isa/formats/aarch64.isa 1 file changed, 361 insertions(+), 309 deletions(-) diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 2fd28f8..0aafa9e 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -1958,6 +1958,359 @@ output decoder {{ namespace Aarch64 { + +StaticInstPtr +decodeLogical(ExtMachInst machInst) +{ +uint8_t imm6 = bits(machInst, 15, 10); +bool sf = bits(machInst, 31); +if (!sf && (imm6 & 0x20)) +return new Unknown64(machInst); + +RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0); +RegIndex rdzr = makeZero(rd); +RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5); +RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16); +ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22); + +uint8_t switch_val = (bits(machInst, 21) << 0) | +(bits(machInst, 30, 29) << 1); + +switch (switch_val) { + case 0x0: +return new AndXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x1: +return new BicXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x2: +return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x3: +return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x4: +return new EorXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x5: +return new EonXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x6: +return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type); + case 0x7: +return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type); + default: +GEM5_UNREACHABLE; +} +} + +StaticInstPtr +decodeAddSub(ExtMachInst machInst) +{ +uint8_t switch_val = bits(machInst, 30, 29); +if (bits(machInst, 21) == 0) { +ArmShiftType type = +(ArmShiftType)(uint8_t)bits(machInst, 23, 22); +if (type == ROR) +return new Unknown64(machInst); +uint8_t imm6 = bits(machInst, 15, 10); +if (!bits(machInst, 31) && bits(imm6, 5)) +return new Unknown64(machInst); +RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0); +RegIndex rdzr = makeZero(rd); +RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5); +RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16); +switch (switch_val) { + case 0x0: +return new AddXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x1: +return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type); + case 0x2: +return new SubXSReg(machInst, rdzr, rn, rm, imm6, type); + case 0x3: +return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type); + default: +GEM5_UNREACHABLE; +} +} else { +if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4) + return new Unknown64(machInst); +ArmExtendType type = +(ArmExtendType)(uint8_t)bits(machInst, 15, 13); +uint8_t imm3 = bits(machInst, 12, 10); +RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0); +RegIndex rdsp = makeSP(rd); +RegIndex rdzr = makeZero(rd); +RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5); +RegIndex rnsp = makeSP(rn); +RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16); + +switch (switch_val) { + case 0x0: +return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3); + case 0x1: +return new AddXERegCc(machInst, rdzr, rnsp, rm, type, imm3); + case 0x2: +return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3); + case 0x3: +return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3); + de
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Define a AA64ZFR0 data type
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70725?usp=email to review the following change. Change subject: arch-arm: Define a AA64ZFR0 data type .. arch-arm: Define a AA64ZFR0 data type Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/regs/misc_types.hh 1 file changed, 13 insertions(+), 0 deletions(-) diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index 214d418..b7a1207 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -203,6 +203,19 @@ Bitfield<3, 0> el0; EndBitUnion(AA64PFR0) +BitUnion64(AA64ZFR0) +Bitfield<59, 56> f64mm; +Bitfield<55, 52> f32mm; +Bitfield<47, 44> i8mm; +Bitfield<43, 40> sm4; +Bitfield<35, 32> sha3; +Bitfield<27, 24> b16b16; +Bitfield<23, 20> bf16; +Bitfield<19, 16> bitPerm; +Bitfield<7, 4> aes; +Bitfield<3, 0> sveVer; +EndBitUnion(AA64ZFR0) + BitUnion64(AA64SMFR0) Bitfield<63> fa64; Bitfield<59, 56> smEver; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70725?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885 Gerrit-Change-Number: 70725 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_RNG
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70721?usp=email to review the following change. Change subject: arch-arm: Implement FEAT_RNG .. arch-arm: Implement FEAT_RNG Change-Id: I9d60d249172ef4bbaf5d9b38ef279eff344b80d8 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/ArmSystem.py M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc M src/arch/arm/regs/misc.hh M src/arch/arm/regs/misc_types.hh 5 files changed, 62 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index e08108f..c3b3cf6 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -88,6 +88,8 @@ "FEAT_FLAGM", # Armv8.5 "FEAT_FLAGM2", +"FEAT_RNG", +"FEAT_RNG_TRAP", # Armv9.2 "FEAT_SME", # Optional in Armv9.2 # Others @@ -204,7 +206,11 @@ class Armv85(Armv84): -extensions = Armv84.extensions + ["FEAT_FLAGM2"] +extensions = Armv84.extensions + [ +"FEAT_FLAGM2", +"FEAT_RNG", +"FEAT_RNG_TRAP", +] class Armv92(Armv85): diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 9c8e282..0212926 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -49,6 +49,7 @@ #include "arch/arm/utility.hh" #include "arch/generic/decoder.hh" #include "base/cprintf.hh" +#include "base/random.hh" #include "cpu/base.hh" #include "cpu/checker/cpu.hh" #include "cpu/reg_class.hh" @@ -596,6 +597,21 @@ case MISCREG_HIFAR: // alias for secure IFAR return readMiscRegNoEffect(MISCREG_IFAR_S); + case MISCREG_RNDR: +tc->setReg(cc_reg::Nz, (RegVal)0); +tc->setReg(cc_reg::C, (RegVal)0); +tc->setReg(cc_reg::V, (RegVal)0); +return random_mt.random(); + case MISCREG_RNDRRS: +tc->setReg(cc_reg::Nz, (RegVal)0); +tc->setReg(cc_reg::C, (RegVal)0); +tc->setReg(cc_reg::V, (RegVal)0); +// Note: we are not reseeding +// The random number generator already has an hardcoded +// seed for the sake of determinism. There is no point +// in simulating non-determinism here +return random_mt.random(); + // Generic Timer registers case MISCREG_CNTFRQ ... MISCREG_CNTVOFF: case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2: diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 9e633c0..df1f6db 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -1057,6 +1057,8 @@ { MiscRegNum64(3, 2, 0, 0, 0), MISCREG_CSSELR_EL1 }, { MiscRegNum64(3, 3, 0, 0, 1), MISCREG_CTR_EL0 }, { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 }, +{ MiscRegNum64(3, 3, 2, 4, 0), MISCREG_RNDR }, +{ MiscRegNum64(3, 3, 2, 4, 1), MISCREG_RNDRRS }, { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV }, { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF }, { MiscRegNum64(3, 3, 4, 2, 2), MISCREG_SVCR }, @@ -1999,6 +2001,20 @@ } } +Fault +faultRng(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); +if (HaveExt(tc, ArmExtension::FEAT_RNG_TRAP) && scr.trndr) { +return inst.generateTrap(EL3); +} else if (!HaveExt(tc, ArmExtension::FEAT_RNG)) { +return inst.undefined(); +} else { +return NoFault; +} +} + } MiscRegIndex @@ -5400,6 +5416,21 @@ InitReg(MISCREG_MPAMSM_EL1) .allPrivileges().exceptUserMode(); +InitReg(MISCREG_RNDR) +.faultRead(EL0, faultRng) +.faultRead(EL1, faultRng) +.faultRead(EL2, faultRng) +.faultRead(EL3, faultRng) +.unverifiable() +.allPrivileges().writes(0); +InitReg(MISCREG_RNDRRS) +.faultRead(EL0, faultRng) +.faultRead(EL1, faultRng) +.faultRead(EL2, faultRng) +.faultRead(EL3, faultRng) +.unverifiable() +.allPrivileges().writes(0); + // Dummy registers InitReg(MISCREG_NOP) .allPrivileges(); diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index c43cf74..429fcb5 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -1091,6 +1091,10 @@ MISCREG_TPIDR2_EL0, MISCREG_MPAMSM_EL1, +// FEAT_RNG +MISCREG_RNDR, +MISCREG_RNDRRS, + // NUM_PHYS_MISCREGS specifies the number of actual physical // registers, not considering the following pseudo-registers // (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL. @@ -2760,6 +2764,
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_IDST
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70723?usp=email to review the following change. Change subject: arch-arm: Implement FEAT_IDST .. arch-arm: Implement FEAT_IDST Change-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/ArmSystem.py M src/arch/arm/regs/misc.cc 2 files changed, 59 insertions(+), 17 deletions(-) diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index c3b3cf6..b826f0d 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -86,6 +86,7 @@ "FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM", +"FEAT_IDST", # Armv8.5 "FEAT_FLAGM2", "FEAT_RNG", @@ -170,6 +171,7 @@ "FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM", +"FEAT_IDST", # Armv8.5 "FEAT_FLAGM2", # Armv9.2 @@ -202,7 +204,12 @@ class Armv84(Armv83): -extensions = Armv83.extensions + ["FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM"] +extensions = Armv83.extensions + [ +"FEAT_SEL2", +"FEAT_TLBIOS", +"FEAT_FLAGM", +"FEAT_IDST", +] class Armv85(Armv84): diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 10b7d38..a151177 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2077,6 +2077,22 @@ } } +Fault +faultIdst(const MiscRegLUTEntry &entry, +ThreadContext *tc, const MiscRegOp64 &inst) +{ +if (HaveExt(tc, ArmExtension::FEAT_IDST)) { +const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); +if (EL2Enabled(tc) && hcr.tge) { +return inst.generateTrap(EL2); +} else { +return inst.generateTrap(EL1); +} +} else { +return inst.undefined(); +} +} + } MiscRegIndex @@ -3828,6 +3844,7 @@ // AArch64 registers (Op0=1,3); InitReg(MISCREG_MIDR_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .mapsTo(MISCREG_MIDR); InitReg(MISCREG_MPIDR_EL1) .allPrivileges().exceptUserMode().writes(0) @@ -3923,34 +3940,40 @@ return pfr0_el1; }()) .unserialize(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64PFR1_EL1) .reset(release->has(ArmExtension::FEAT_SME) ? 0x1 << 24 : 0) .unserialize(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64DFR0_EL1) .reset([p](){ AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1; dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3 return dfr0_el1; }()) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64DFR1_EL1) .reset(p.id_aa64dfr1_el1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64AFR0_EL1) .reset(p.id_aa64afr0_el1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64AFR1_EL1) .reset(p.id_aa64afr1_el1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64ISAR0_EL1) .reset([p,release=release](){ AA64ISAR0 isar0_el1 = p.id_aa64isar0_el1; @@ -3974,8 +3997,9 @@ 0x1 : 0x0; return isar0_el1; }()) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().writes(0); InitReg(MISCREG_ID_AA64ISAR1_EL1) .reset([p,release=release](){ AA64ISAR1 isar1_el1 = p.id_aa64isar1_el1; @@ -3985,8 +4009,9 @@ isar1_el1.gpa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0; return isar1_el1; }()) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().write
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCR to be 64-bit wide
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70720?usp=email to review the following change. Change subject: arch-arm: Extend SCR to be 64-bit wide .. arch-arm: Extend SCR to be 64-bit wide Change-Id: I9928de3db61957404269d189a15a951fd6707c8a Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/regs/misc_types.hh 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index c139f1a..71fdd60 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -345,7 +345,7 @@ Bitfield<0> cp0; EndBitUnion(NSACR) -BitUnion32(SCR) +BitUnion64(SCR) Bitfield<21> fien; Bitfield<20> nmea; Bitfield<19> ease; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70720?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9928de3db61957404269d189a15a951fd6707c8a Gerrit-Change-Number: 70720 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix printing of VecElemClass registers
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70697?usp=email ) Change subject: arch-arm: Fix printing of VecElemClass registers .. arch-arm: Fix printing of VecElemClass registers At the moment it is not possible to trace the value of VecElemClass registers. If a AArch32 SIMD binary is run with tracing on, simulation will fail the following assertion [1]. std::string valString(const void *val, size_t size) const override { assert(size == sizeof(ValueType)); The problem is that Arm VecElems are stored in RegVal (uint64_t), but the VecElem data type (ValueType above) per se is a uint32_t. So valString is getting called with size = 8 (coming from RegVal) but ValueType has size = 4. We fix this problem by using RegVal as a VecElemRegClassOps template parameter to make them match. This is not changing anything from a functionality perspective. The result will be that we will be able to print VecElems as 64bit values. This solution is the most simple one but a bit dirty. I believe in the long term we should make the VecElemClass use the void* interface rather than the RegVal one. In this way we will be able to correctly print the VecElem size as 32bit value. [1]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/cpu/reg_class.hh#L362 Change-Id: Ic3fc252d41449f828b77f938fefc0cd4274b1c57 Signed-off-by: Giacomo Travaglini --- M src/arch/arm/regs/vec.hh 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh index 00ab87f..19f37c9 100644 --- a/src/arch/arm/regs/vec.hh +++ b/src/arch/arm/regs/vec.hh @@ -93,7 +93,7 @@ const int PREDREG_FFR = 16; const int PREDREG_UREG0 = 17; -static inline VecElemRegClassOps +static inline VecElemRegClassOps vecRegElemClassOps(NumVecElemPerVecReg); static inline TypedRegClassOps vecRegClassOps; static inline TypedRegClassOps vecPredRegClassOps; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70697?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic3fc252d41449f828b77f938fefc0cd4274b1c57 Gerrit-Change-Number: 70697 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_TLBIOS
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70567?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Implement FEAT_TLBIOS .. arch-arm: Implement FEAT_TLBIOS This feature is mandatory in Armv8.4 We are currently not distinguishing Inner and Outer domains. We therefore implement TLBIOS instructions as TLBIIS Change-Id: I2198e6155f1eea7c5f8083c6ffb178d3a3d163d3 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70567 Tested-by: kokoro Maintainer: Jason Lowe-Power --- M src/arch/arm/ArmSystem.py M src/arch/arm/insts/misc64.cc M src/arch/arm/regs/misc.cc M src/arch/arm/regs/misc.hh 4 files changed, 151 insertions(+), 1 deletion(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 7367d80..9e2da8e 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -84,6 +84,7 @@ "FEAT_PAuth", # Armv8.4 "FEAT_SEL2", +"FEAT_TLBIOS", # Armv9.2 "FEAT_SME", # Optional in Armv9.2 # Others @@ -162,6 +163,7 @@ "FEAT_PAuth", # Armv8.4 "FEAT_SEL2", +"FEAT_TLBIOS", # Armv9.2 "FEAT_SME", ] @@ -192,7 +194,7 @@ class Armv84(Armv83): -extensions = Armv83.extensions + ["FEAT_SEL2"] +extensions = Armv83.extensions + ["FEAT_SEL2", "FEAT_TLBIOS"] class Armv92(Armv84): diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 40a6ca4..c7423d9 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -241,6 +241,10 @@ } // AArch64 TLB Invalidate All, EL3, Inner Shareable case MISCREG_TLBI_ALLE3IS: + // AArch64 TLB Invalidate All, EL3, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_ALLE3OS: { TLBIALLEL tlbiOp(EL3, true); tlbiOp.broadcast(tc); @@ -258,6 +262,10 @@ } // AArch64 TLB Invalidate All, EL2, Inner Shareable case MISCREG_TLBI_ALLE2IS: + // AArch64 TLB Invalidate All, EL2, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_ALLE2OS: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -278,6 +286,10 @@ } // AArch64 TLB Invalidate All, EL1, Inner Shareable case MISCREG_TLBI_ALLE1IS: + // AArch64 TLB Invalidate All, EL1, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_ALLE1OS: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -313,6 +325,9 @@ return; } case MISCREG_TLBI_VMALLS12E1IS: + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VMALLS12E1OS: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -322,6 +337,9 @@ return; } case MISCREG_TLBI_VMALLE1IS: + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VMALLE1OS: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -360,6 +378,10 @@ } // AArch64 TLB Invalidate by VA, EL3, Inner Shareable case MISCREG_TLBI_VAE3IS_Xt: + // AArch64 TLB Invalidate by VA, EL3, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VAE3OS_Xt: { TLBIMVAA tlbiOp(EL3, true, static_cast(bits(value, 43, 0)) << 12, @@ -370,6 +392,10 @@ } // AArch64 TLB Invalidate by VA, Last Level, EL3, Inner Shareable case MISCREG_TLBI_VALE3IS_Xt: + // AArch64 TLB Invalidate by VA, Last Level, EL3, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VALE3OS_Xt: { TLBIMVAA tlbiOp(EL3, true, static_cast(bit
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add UNSERIALIZE flag to address cpt compatibility
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70557?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Add UNSERIALIZE flag to address cpt compatibility .. arch-arm: Add UNSERIALIZE flag to address cpt compatibility This patch is adding the MISCREG_UNSERIALIZE flag to expose the user to the following checkpoint compatibility problem: What happens when a checkpoint is restored with a different architectural configuration? The current behaviour is to silently restore the checkpoint and to populate the ISA registers accordingly. However some of these restored values will be used and some of them will be actually discarded. For example the value of the MISCREG_ID_AA64ISAR0_EL1 register (initially configured at construction time [1]) will be overwritten by the checkpointed value in ISA::unserialize (checkpointed params win over current params). On the other hand we "discard" the checkpointed value for registers handled in the ISA::readMiscReg method (not accessing the storage) like MISCREG_ID_AA64PFR0_EL1 [2] (current params win over checkpointed params). In other words some registers will be unserialized while some others will discard the checkpointed value in favour of the current configuration setup. This categorization is currently implicit and it ultimately depends on whether or not a register read access its storage (see MISCREG_ID_AA64PFR0_EL1 above). With this patch we formalize this distinction. We allow the developer to be explict on which register should not be unserialized and should instead use the new simulation parameters. If there is a mismatch between the reset value of such register and the checkpointed one, we warn the user and we undo the unserialization for such register. [1]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/arch/arm/isa.cc#L437 [2]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/arch/arm/isa.cc#L1019 Change-Id: Icea6563ee5816b14a097926b5734f2fce10530c7 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70557 Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.hh 2 files changed, 20 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved Richard Cooper: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index ffd9cfc..f55235d 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1879,6 +1879,18 @@ { DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n"); UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS); + +for (auto idx = 0; idx < NUM_MISCREGS; idx++) { +if (!lookUpMiscReg[idx].info[MISCREG_UNSERIALIZE] && +miscRegs[idx] != lookUpMiscReg[idx].reset()) { +warn("Checkpoint value for register %s does not match " + "current configuration (checkpointed: %#x, current: %#x)", + miscRegName[idx], miscRegs[idx], + lookUpMiscReg[idx].reset()); +miscRegs[idx] = lookUpMiscReg[idx].reset(); +} +} + CPSR tmp_cpsr = miscRegs[MISCREG_CPSR]; updateRegMap(tmp_cpsr); } diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index 265a697..3a32623 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -1125,6 +1125,7 @@ MISCREG_IMPLEMENTED, MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a // arch generic counter) +MISCREG_UNSERIALIZE,// Should the checkpointed value be restored? MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it // tells whether the instruction should raise a // warning or fail @@ -1277,6 +1278,12 @@ return *this; } chain +unserialize(bool v = true) const +{ +entry.info[MISCREG_UNSERIALIZE] = v; +return *this; +} +chain warnNotFail(bool v = true) const { entry.info[MISCREG_WARN_NOT_FAIL] = v; @@ -1595,7 +1602,7 @@ : entry(e) { // force unimplemented registers to be thusly declared -implemented(1); +implemented(1).unserialize(1); } }; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70557?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project:
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement RES0/RES1 with miscreg specifiers
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70563?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Implement RES0/RES1 with miscreg specifiers .. arch-arm: Implement RES0/RES1 with miscreg specifiers Change-Id: Ic2caea121e02f63f069f1576760c849bcbdac894 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70563 Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 29 insertions(+), 73 deletions(-) Approvals: Richard Cooper: Looks good to me, approved kokoro: Regressions pass Jason Lowe-Power: Looks good to me, approved diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index bef2db5..ab6e3f7 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -421,11 +421,6 @@ idx = redirectRegVHE(idx); switch (unflattenMiscReg(idx)) { - case MISCREG_HCR: - case MISCREG_HCR2: -if (!release->has(ArmExtension::VIRTUALIZATION)) -return 0; -break; case MISCREG_CPACR: { const uint32_t ones = (uint32_t)(-1); @@ -456,10 +451,6 @@ case MISCREG_MPIDR: case MISCREG_MPIDR_EL1: return readMPIDR(system, tc); - case MISCREG_VMPIDR: - case MISCREG_VMPIDR_EL2: -// top bit defined as RES1 -return readMiscRegNoEffect(idx) | 0x8000; case MISCREG_ID_AFR0: // not implemented, so alias MIDR case MISCREG_REVIDR: // not implemented, so alias MIDR case MISCREG_MIDR: @@ -568,10 +559,6 @@ { return miscRegs[MISCREG_CPSR] & 0x80; } - case MISCREG_SVCR: -{ -return miscRegs[MISCREG_SVCR]; -} case MISCREG_L2CTLR: { // mostly unimplemented, just set NumCPUs field from sim and return @@ -594,20 +581,17 @@ } case MISCREG_HCPTR: { -RegVal val = readMiscRegNoEffect(idx); -// The trap bit associated with CP14 is defined as RAZ -val &= ~(1 << 14); -// If a CP bit in NSACR is 0 then the corresponding bit in -// HCPTR is RAO/WI +HCPTR val = readMiscRegNoEffect(idx); bool secure_lookup = release->has(ArmExtension::SECURITY) && isSecure(tc); if (!secure_lookup) { -RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); -val |= (mask ^ 0x7FFF) & 0xBFFF; +NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); +if (!nsacr.cp10) { +val.tcp10 = 1; +val.tcp11 = 1; +} } -// Set the bits for unimplemented coprocessors to RAO/WI -val |= 0x33FF; -return (val); +return val; } case MISCREG_HDFAR: // alias for secure DFAR return readMiscRegNoEffect(MISCREG_DFAR_S); @@ -934,16 +918,10 @@ (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); } break; - case MISCREG_HCR2: -if (!release->has(ArmExtension::VIRTUALIZATION)) -return; -break; case MISCREG_HCR: { const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); selfDebug->setenableTDETGE((HCR)val, mdcr); -if (!release->has(ArmExtension::VIRTUALIZATION)) -return; } break; @@ -1016,31 +994,6 @@ case MISCREG_DBGWCR0_EL1 ... MISCREG_DBGWCR15_EL1: selfDebug->updateDBGWCR(idx - MISCREG_DBGWCR0_EL1, val); break; - case MISCREG_IFSR: -{ -// ARM ARM (ARM DDI 0406C.b) B4.1.96 -const uint32_t ifsrMask = -mask(31, 13) | mask(11, 11) | mask(8, 6); -newVal = newVal & ~ifsrMask; -} -break; - case MISCREG_DFSR: -{ -// ARM ARM (ARM DDI 0406C.b) B4.1.52 -const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); -newVal = newVal & ~dfsrMask; -} -break; - case MISCREG_AMAIR0: - case MISCREG_AMAIR1: -{ -// ARM ARM (ARM DDI 0406C.b) B4.1.5 -// Valid only with LPAE -if (!release->has(ArmExtension::LPAE)) -return; -DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); -} -break;
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70561?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch .. arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70561 Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/regs/misc.cc 1 file changed, 1 insertion(+), 4 deletions(-) Approvals: Richard Cooper: Looks good to me, approved kokoro: Regressions pass Jason Lowe-Power: Looks good to me, approved diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 6c5a9dd..6f918b2 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2273,10 +2273,7 @@ // AArch32 CP14 registers InitReg(MISCREG_DBGDIDR) - /* For now just implement the version number. - * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) - */ - .reset(0x5 << 16) + .reset(0x6 << 16) // Armv8 Debug architecture .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); InitReg(MISCREG_DBGDSCRint) .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70561?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51 Gerrit-Change-Number: 70561 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Implement RAZ/WI with raz specifier
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70560?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Implement RAZ/WI with raz specifier .. arch-arm: Implement RAZ/WI with raz specifier Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70560 Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 5 insertions(+), 6 deletions(-) Approvals: Richard Cooper: Looks good to me, approved kokoro: Regressions pass Jason Lowe-Power: Looks good to me, approved diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 14349b1..7df8978 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -470,12 +470,6 @@ return readMiscRegNoEffect(idx); } break; - case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI - case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI - case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI - case MISCREG_AIDR: // AUX ID set to 0 - case MISCREG_TCMTR: // No TCM's -return 0; case MISCREG_CLIDR: warn_once("The clidr register always reports 0 caches.\n"); diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 960c2be..6c5a9dd 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2505,12 +2505,15 @@ .unimplemented() .allPrivileges(); InitReg(MISCREG_JIDR) + .raz() // Jazelle trivial implementation, RAZ/WI .allPrivileges(); InitReg(MISCREG_TEEHBR) .allPrivileges(); InitReg(MISCREG_JOSCR) + .raz() // Jazelle trivial implementation, RAZ/WI .allPrivileges(); InitReg(MISCREG_JMCR) + .raz() // Jazelle trivial implementation, RAZ/WI .allPrivileges(); // AArch32 CP15 registers @@ -2548,6 +2551,7 @@ .unserialize(0) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_TCMTR) + .raz() // No TCM's .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_TLBTR) .reset(1) // Separate Instruction and Data TLBs @@ -2646,6 +2650,7 @@ InitReg(MISCREG_CLIDR) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_AIDR) + .raz() // AUX ID set to 0 .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_CSSELR) .banked(); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70560?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5 Gerrit-Change-Number: 70560 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Provide default mask for raz/rao helpers
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70559?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Provide default mask for raz/rao helpers .. arch-arm: Provide default mask for raz/rao helpers Rather than forcing raz registers to write something like: .raz(uint64_t(-1)) we provide a shorter version where if no bitmask is specified we assume the entire register is raz/rao. This won't be probably used by rao but I am striving for symmetry and providing a default won't probably hurt Change-Id: I309e345fc8336df3a74474f8f9202bf7e2095b41 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70559 Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/regs/misc.hh 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass Richard Cooper: Looks good to me, approved diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index 3a32623..abbd1c6 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -1249,13 +1249,13 @@ return *this; } chain -raz(uint64_t mask) const +raz(uint64_t mask = (uint64_t)-1) const { entry._raz = mask; return *this; } chain -rao(uint64_t mask) const +rao(uint64_t mask = (uint64_t)-1) const { entry._rao = mask; return *this; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70559?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I309e345fc8336df3a74474f8f9202bf7e2095b41 Gerrit-Change-Number: 70559 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Simplify FPSCR writes
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Simplify FPSCR writes .. arch-arm: Simplify FPSCR writes The old logic was setting up a mask which was covering pretty much the entire register, except for the FPSCR[14:13] and FPSCR[6:5] register fields. Those RES0 fields were treated as WI. We simplify this by explicitly marking them as RES0 at construction time Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70565 Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 2 insertions(+), 32 deletions(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 83df61f..9c8e282 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -815,38 +815,7 @@ return; case MISCREG_FPSCR: -{ -const uint32_t ones = (uint32_t)(-1); -FPSCR fpscrMask = 0; -fpscrMask.ioc = ones; -fpscrMask.dzc = ones; -fpscrMask.ofc = ones; -fpscrMask.ufc = ones; -fpscrMask.ixc = ones; -fpscrMask.idc = ones; -fpscrMask.ioe = ones; -fpscrMask.dze = ones; -fpscrMask.ofe = ones; -fpscrMask.ufe = ones; -fpscrMask.ixe = ones; -fpscrMask.ide = ones; -fpscrMask.len = ones; -fpscrMask.fz16 = ones; -fpscrMask.stride = ones; -fpscrMask.rMode = ones; -fpscrMask.fz = ones; -fpscrMask.dn = ones; -fpscrMask.ahp = ones; -fpscrMask.qc = ones; -fpscrMask.v = ones; -fpscrMask.c = ones; -fpscrMask.z = ones; -fpscrMask.n = ones; -newVal = (newVal & (uint32_t)fpscrMask) | - (readMiscRegNoEffect(MISCREG_FPSCR) & - ~(uint32_t)fpscrMask); -tc->getDecoderPtr()->as().setContext(newVal); -} +tc->getDecoderPtr()->as().setContext(newVal); break; case MISCREG_FPSR: { diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 9203810..2d76143 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2199,6 +2199,7 @@ .reset(p.fpsid) .allPrivileges(); InitReg(MISCREG_FPSCR) + .res0(mask(14, 13) | mask(6, 5)) .allPrivileges(); InitReg(MISCREG_MVFR1) .reset([] () { -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95 Gerrit-Change-Number: 70565 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCTLR to be 64-bit wide
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70566?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Extend SCTLR to be 64-bit wide .. arch-arm: Extend SCTLR to be 64-bit wide In AArch64 SCTLR_EL1/_EL2/_EL3 is 64-bit wide Change-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70566 Tested-by: kokoro Maintainer: Jason Lowe-Power --- M src/arch/arm/regs/misc_types.hh 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: kokoro: Regressions pass Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index e6f7e40..c139f1a 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -371,7 +371,7 @@ Bitfield<0> ns; EndBitUnion(SCR) -BitUnion32(SCTLR) +BitUnion64(SCTLR) Bitfield<31> enia;// ARMv8.3 PAuth Bitfield<30> enib;// ARMv8.3 PAuth Bitfield<30> te; // Thumb Exception Enable (AArch32 only) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70566?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371 Gerrit-Change-Number: 70566 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move RO values from ISA::read to the reset field
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70558?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Move RO values from ISA::read to the reset field .. arch-arm: Move RO values from ISA::read to the reset field This is simplyfying the ISA::readMiscReg, and it is stopping us from recomputing values that won't change throughout the simulation Change-Id: I62270cdb59f39b8a143e9554c8beaa8cd15824aa Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70558 Tested-by: kokoro Maintainer: Jason Lowe-Power --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 49 insertions(+), 66 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Richard Cooper: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index f55235d..14349b1 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -486,35 +486,6 @@ warn_once("The ccsidr register isn't implemented and " "always reads as 0.\n"); break; - case MISCREG_CTR: // AArch32, ARMv7, top bit set - case MISCREG_CTR_EL0: // AArch64 -{ -//all caches have the same line size in gem5 -//4 byte words in ARM -unsigned lineSizeWords = -tc->getSystemPtr()->cacheLineSize() / 4; -unsigned log2LineSizeWords = 0; - -while (lineSizeWords >>= 1) { -++log2LineSizeWords; -} - -CTR ctr = 0; -//log2 of minimun i-cache line size (words) -ctr.iCacheLineSize = log2LineSizeWords; -//b11 - gem5 uses pipt -ctr.l1IndexPolicy = 0x3; -//log2 of minimum d-cache line size (words) -ctr.dCacheLineSize = log2LineSizeWords; -//log2 of max reservation size (words) -ctr.erg = log2LineSizeWords; -//log2 of max writeback size (words) -ctr.cwg = log2LineSizeWords; -//b100 - gem5 format is ARMv7 -ctr.format = 0x4; - -return ctr; -} case MISCREG_ACTLR: warn("Not doing anything for miscreg ACTLR\n"); break; @@ -615,11 +586,6 @@ l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1; return l2ctlr; } - case MISCREG_DBGDIDR: -/* For now just implement the version number. - * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) - */ -return 0x5 << 16; case MISCREG_DBGDSCRint: return readMiscRegNoEffect(MISCREG_DBGDSCRint); case MISCREG_ISR: @@ -632,8 +598,6 @@ readMiscRegNoEffect(MISCREG_CPSR), readMiscRegNoEffect(MISCREG_SCR_EL3)); } - case MISCREG_DCZID_EL0: -return 0x04; // DC ZVA clear 64-byte chunks case MISCREG_HCPTR: { RegVal val = readMiscRegNoEffect(idx); @@ -656,36 +620,6 @@ case MISCREG_HIFAR: // alias for secure IFAR return readMiscRegNoEffect(MISCREG_IFAR_S); - case MISCREG_ID_PFR0: -// !ThumbEE | !Jazelle | Thumb | ARM -return 0x0031; - case MISCREG_ID_PFR1: -{ // Timer | Virti | !M Profile | TrustZone | ARMv4 -bool have_timer = (system->getGenericTimer() != nullptr); -return 0x0001 | -(release->has(ArmExtension::SECURITY) ? -0x0010 : 0x0) | -(release->has(ArmExtension::VIRTUALIZATION) ? -0x1000 : 0x0) | -(have_timer ? 0x0001 : 0x0); -} - case MISCREG_ID_AA64PFR0_EL1: -return 0x0002 | // AArch{64,32} supported at EL0 - 0x0020 | // EL1 - (release->has(ArmExtension::VIRTUALIZATION) ? -0x0200 : 0) | // EL2 - (release->has(ArmExtension::SECURITY) ? -0x2000 : 0) | // EL3 - (release->has(ArmExtension::FEAT_SVE) ? -0x0001 : 0) | // SVE - (release->has(ArmExtension::FEAT_SEL2) ? -0x0010 : 0) | // SecEL2 - (gicv3CpuInterface ? 0x0100 : 0); - case MISCREG_ID_AA64PFR1_EL1: -return 0x0 | - (release->has(ArmExtension::FEAT_SME) ? -0x1 << 24 : 0); // SME - // Generic Timer registers case MISCREG_CNTFRQ ... MISCREG_CNTVOFF: case MISCR
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Group self hosted debug writes in ISA switch
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70562?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Group self hosted debug writes in ISA switch .. arch-arm: Group self hosted debug writes in ISA switch Change-Id: If9c0675743856b603e7b5ec1898f5cdd650f3ce6 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70562 Tested-by: kokoro Maintainer: Jason Lowe-Power --- M src/arch/arm/isa.cc 1 file changed, 8 insertions(+), 188 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Richard Cooper: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 7df8978..bef2db5 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -962,101 +962,11 @@ tc->setMiscReg(MISCREG_DBGOSLSR, r); } break; - case MISCREG_DBGBCR0: -selfDebug->updateDBGBCR(0, val); + case MISCREG_DBGBCR0 ... MISCREG_DBGBCR15: +selfDebug->updateDBGBCR(idx - MISCREG_DBGBCR0, val); break; - case MISCREG_DBGBCR1: -selfDebug->updateDBGBCR(1, val); -break; - case MISCREG_DBGBCR2: -selfDebug->updateDBGBCR(2, val); -break; - case MISCREG_DBGBCR3: -selfDebug->updateDBGBCR(3, val); -break; - case MISCREG_DBGBCR4: -selfDebug->updateDBGBCR(4, val); -break; - case MISCREG_DBGBCR5: -selfDebug->updateDBGBCR(5, val); -break; - case MISCREG_DBGBCR6: -selfDebug->updateDBGBCR(6, val); -break; - case MISCREG_DBGBCR7: -selfDebug->updateDBGBCR(7, val); -break; - case MISCREG_DBGBCR8: -selfDebug->updateDBGBCR(8, val); -break; - case MISCREG_DBGBCR9: -selfDebug->updateDBGBCR(9, val); -break; - case MISCREG_DBGBCR10: -selfDebug->updateDBGBCR(10, val); -break; - case MISCREG_DBGBCR11: -selfDebug->updateDBGBCR(11, val); -break; - case MISCREG_DBGBCR12: -selfDebug->updateDBGBCR(12, val); -break; - case MISCREG_DBGBCR13: -selfDebug->updateDBGBCR(13, val); -break; - case MISCREG_DBGBCR14: -selfDebug->updateDBGBCR(14, val); -break; - case MISCREG_DBGBCR15: -selfDebug->updateDBGBCR(15, val); -break; - case MISCREG_DBGWCR0: -selfDebug->updateDBGWCR(0, val); -break; - case MISCREG_DBGWCR1: -selfDebug->updateDBGWCR(1, val); -break; - case MISCREG_DBGWCR2: -selfDebug->updateDBGWCR(2, val); -break; - case MISCREG_DBGWCR3: -selfDebug->updateDBGWCR(3, val); -break; - case MISCREG_DBGWCR4: -selfDebug->updateDBGWCR(4, val); -break; - case MISCREG_DBGWCR5: -selfDebug->updateDBGWCR(5, val); -break; - case MISCREG_DBGWCR6: -selfDebug->updateDBGWCR(6, val); -break; - case MISCREG_DBGWCR7: -selfDebug->updateDBGWCR(7, val); -break; - case MISCREG_DBGWCR8: -selfDebug->updateDBGWCR(8, val); -break; - case MISCREG_DBGWCR9: -selfDebug->updateDBGWCR(9, val); -break; - case MISCREG_DBGWCR10: -selfDebug->updateDBGWCR(10, val); -break; - case MISCREG_DBGWCR11: -selfDebug->updateDBGWCR(11, val); -break; - case MISCREG_DBGWCR12: -selfDebug->updateDBGWCR(12, val); -break; - case MISCREG_DBGWCR13: -selfDebug->updateDBGWCR(13, val); -break; - case MISCREG_DBGWCR14: -selfDebug->updateDBGWCR(14, val); -break; - case MISCREG_DBGWCR15: -selfDebug->updateDBGWCR(15, val); + case MISCREG_DBGWCR0 ... MISCREG_DBGWCR15: +selfDebug->updateDBGWCR(idx - MISCREG_DBGWCR0, val); break; case MISCREG_MDCR_EL2: @@ -1100,101 +1010,11 @@ } break; - case MISCREG_DBGBCR0_EL1: -selfDebug->updateDBGBCR(0, val); + case MISCREG_DBGBCR0_EL1 ... MISCREG_DBGBCR15_EL1: +selfDebug->updateDBGBCR(idx - MISCREG_DBGBCR0_
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Remove unnecessary case in ISA::readMiscReg
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70564?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Remove unnecessary case in ISA::readMiscReg .. arch-arm: Remove unnecessary case in ISA::readMiscReg Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70564 Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/isa.cc 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: kokoro: Regressions pass Jason Lowe-Power: Looks good to me, approved Richard Cooper: Looks good to me, approved diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index ab6e3f7..83df61f 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -567,8 +567,6 @@ l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1; return l2ctlr; } - case MISCREG_DBGDSCRint: -return readMiscRegNoEffect(MISCREG_DBGDSCRint); case MISCREG_ISR: case MISCREG_ISR_EL1: { -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70564?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f Gerrit-Change-Number: 70564 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix position of AA64ISAR0.AES bitfield
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70637?usp=email ) Change subject: arch-arm: Fix position of AA64ISAR0.AES bitfield .. arch-arm: Fix position of AA64ISAR0.AES bitfield The bitfield was wrongly [1] placed in the LSBs of the register [1]: https://developer.arm.com/documentation/ddi0601/2022-03/\ AArch64-Registers/\ ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0 Change-Id: I577a79e16931a0e1334a9b24459553e2899341f0 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70637 Reviewed-by: Richard Cooper Tested-by: kokoro --- M src/arch/arm/regs/misc_types.hh 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Giacomo Travaglini: Looks good to me, approved Richard Cooper: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index e446ce5..e6f7e40 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -123,7 +123,7 @@ Bitfield<19, 16> crc32; Bitfield<15, 12> sha2; Bitfield<11, 8> sha1; -Bitfield<3, 0> aes; +Bitfield<7, 4> aes; EndBitUnion(AA64ISAR0) BitUnion64(AA64ISAR1) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70637?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I577a79e16931a0e1334a9b24459553e2899341f0 Gerrit-Change-Number: 70637 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix position of AA64ISAR0.AES bitfield
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70637?usp=email ) Change subject: arch-arm: Fix position of AA64ISAR0.AES bitfield .. arch-arm: Fix position of AA64ISAR0.AES bitfield The bitfield was wrongly [1] placed in the LSBs of the register [1]: https://developer.arm.com/documentation/ddi0601/2022-03/\ AArch64-Registers/\ ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0 Change-Id: I577a79e16931a0e1334a9b24459553e2899341f0 Signed-off-by: Giacomo Travaglini --- M src/arch/arm/regs/misc_types.hh 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index e446ce5..e6f7e40 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -123,7 +123,7 @@ Bitfield<19, 16> crc32; Bitfield<15, 12> sha2; Bitfield<11, 8> sha1; -Bitfield<3, 0> aes; +Bitfield<7, 4> aes; EndBitUnion(AA64ISAR0) BitUnion64(AA64ISAR1) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70637?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I577a79e16931a0e1334a9b24459553e2899341f0 Gerrit-Change-Number: 70637 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_TLBIOS
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70567?usp=email to review the following change. Change subject: arch-arm: Implement FEAT_TLBIOS .. arch-arm: Implement FEAT_TLBIOS This feature is mandatory in Armv8.4 We are currently not distinguishing Inner and Outer domains. We therefore implement TLBIOS instructions as TLBIIS Change-Id: I2198e6155f1eea7c5f8083c6ffb178d3a3d163d3 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/ArmSystem.py M src/arch/arm/insts/misc64.cc M src/arch/arm/regs/misc.cc M src/arch/arm/regs/misc.hh 4 files changed, 151 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 7367d80..9e2da8e 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -84,6 +84,7 @@ "FEAT_PAuth", # Armv8.4 "FEAT_SEL2", +"FEAT_TLBIOS", # Armv9.2 "FEAT_SME", # Optional in Armv9.2 # Others @@ -162,6 +163,7 @@ "FEAT_PAuth", # Armv8.4 "FEAT_SEL2", +"FEAT_TLBIOS", # Armv9.2 "FEAT_SME", ] @@ -192,7 +194,7 @@ class Armv84(Armv83): -extensions = Armv83.extensions + ["FEAT_SEL2"] +extensions = Armv83.extensions + ["FEAT_SEL2", "FEAT_TLBIOS"] class Armv92(Armv84): diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 40a6ca4..c7423d9 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -241,6 +241,10 @@ } // AArch64 TLB Invalidate All, EL3, Inner Shareable case MISCREG_TLBI_ALLE3IS: + // AArch64 TLB Invalidate All, EL3, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_ALLE3OS: { TLBIALLEL tlbiOp(EL3, true); tlbiOp.broadcast(tc); @@ -258,6 +262,10 @@ } // AArch64 TLB Invalidate All, EL2, Inner Shareable case MISCREG_TLBI_ALLE2IS: + // AArch64 TLB Invalidate All, EL2, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_ALLE2OS: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -278,6 +286,10 @@ } // AArch64 TLB Invalidate All, EL1, Inner Shareable case MISCREG_TLBI_ALLE1IS: + // AArch64 TLB Invalidate All, EL1, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_ALLE1OS: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -313,6 +325,9 @@ return; } case MISCREG_TLBI_VMALLS12E1IS: + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VMALLS12E1OS: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -322,6 +337,9 @@ return; } case MISCREG_TLBI_VMALLE1IS: + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VMALLE1OS: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -360,6 +378,10 @@ } // AArch64 TLB Invalidate by VA, EL3, Inner Shareable case MISCREG_TLBI_VAE3IS_Xt: + // AArch64 TLB Invalidate by VA, EL3, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VAE3OS_Xt: { TLBIMVAA tlbiOp(EL3, true, static_cast(bits(value, 43, 0)) << 12, @@ -370,6 +392,10 @@ } // AArch64 TLB Invalidate by VA, Last Level, EL3, Inner Shareable case MISCREG_TLBI_VALE3IS_Xt: + // AArch64 TLB Invalidate by VA, Last Level, EL3, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VALE3OS_Xt: { TLBIMVAA tlbiOp(EL3, true, static_cast(bits(value, 43, 0)) << 12, @@ -430,6 +456,10 @@ } // AArch64 TLB Invalidate by VA, EL2, Inner Shareable case MISCREG_TLBI_VAE2IS_Xt: + // AArch64 TLB Invalidate by VA, EL2, Outer Shareable + // We are currently no
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement RES0/RES1 with miscreg specifiers
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70563?usp=email to review the following change. Change subject: arch-arm: Implement RES0/RES1 with miscreg specifiers .. arch-arm: Implement RES0/RES1 with miscreg specifiers Change-Id: Ic2caea121e02f63f069f1576760c849bcbdac894 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 29 insertions(+), 73 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index bef2db5..ab6e3f7 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -421,11 +421,6 @@ idx = redirectRegVHE(idx); switch (unflattenMiscReg(idx)) { - case MISCREG_HCR: - case MISCREG_HCR2: -if (!release->has(ArmExtension::VIRTUALIZATION)) -return 0; -break; case MISCREG_CPACR: { const uint32_t ones = (uint32_t)(-1); @@ -456,10 +451,6 @@ case MISCREG_MPIDR: case MISCREG_MPIDR_EL1: return readMPIDR(system, tc); - case MISCREG_VMPIDR: - case MISCREG_VMPIDR_EL2: -// top bit defined as RES1 -return readMiscRegNoEffect(idx) | 0x8000; case MISCREG_ID_AFR0: // not implemented, so alias MIDR case MISCREG_REVIDR: // not implemented, so alias MIDR case MISCREG_MIDR: @@ -568,10 +559,6 @@ { return miscRegs[MISCREG_CPSR] & 0x80; } - case MISCREG_SVCR: -{ -return miscRegs[MISCREG_SVCR]; -} case MISCREG_L2CTLR: { // mostly unimplemented, just set NumCPUs field from sim and return @@ -594,20 +581,17 @@ } case MISCREG_HCPTR: { -RegVal val = readMiscRegNoEffect(idx); -// The trap bit associated with CP14 is defined as RAZ -val &= ~(1 << 14); -// If a CP bit in NSACR is 0 then the corresponding bit in -// HCPTR is RAO/WI +HCPTR val = readMiscRegNoEffect(idx); bool secure_lookup = release->has(ArmExtension::SECURITY) && isSecure(tc); if (!secure_lookup) { -RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); -val |= (mask ^ 0x7FFF) & 0xBFFF; +NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); +if (!nsacr.cp10) { +val.tcp10 = 1; +val.tcp11 = 1; +} } -// Set the bits for unimplemented coprocessors to RAO/WI -val |= 0x33FF; -return (val); +return val; } case MISCREG_HDFAR: // alias for secure DFAR return readMiscRegNoEffect(MISCREG_DFAR_S); @@ -934,16 +918,10 @@ (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); } break; - case MISCREG_HCR2: -if (!release->has(ArmExtension::VIRTUALIZATION)) -return; -break; case MISCREG_HCR: { const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); selfDebug->setenableTDETGE((HCR)val, mdcr); -if (!release->has(ArmExtension::VIRTUALIZATION)) -return; } break; @@ -1016,31 +994,6 @@ case MISCREG_DBGWCR0_EL1 ... MISCREG_DBGWCR15_EL1: selfDebug->updateDBGWCR(idx - MISCREG_DBGWCR0_EL1, val); break; - case MISCREG_IFSR: -{ -// ARM ARM (ARM DDI 0406C.b) B4.1.96 -const uint32_t ifsrMask = -mask(31, 13) | mask(11, 11) | mask(8, 6); -newVal = newVal & ~ifsrMask; -} -break; - case MISCREG_DFSR: -{ -// ARM ARM (ARM DDI 0406C.b) B4.1.52 -const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); -newVal = newVal & ~dfsrMask; -} -break; - case MISCREG_AMAIR0: - case MISCREG_AMAIR1: -{ -// ARM ARM (ARM DDI 0406C.b) B4.1.5 -// Valid only with LPAE -if (!release->has(ArmExtension::LPAE)) -return; -DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); -} -break; case MISCREG_SCR: getMMUPtr(tc)->invalidateMiscReg(); break; @@ -1327,21 +1280,6 @@ idx = MISCREG_CPSR; } break; - case MISCREG_SVCR: -{ -
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Provide default mask for raz/rao helpers
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70559?usp=email to review the following change. Change subject: arch-arm: Provide default mask for raz/rao helpers .. arch-arm: Provide default mask for raz/rao helpers Rather than forcing raz registers to write something like: .raz(uint64_t(-1)) we provide a shorter version where if no bitmask is specified we assume the entire register is raz/rao. This won't be probably used by rao but I am striving for symmetry and providing a default won't probably hurt Change-Id: I309e345fc8336df3a74474f8f9202bf7e2095b41 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/regs/misc.hh 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index 3a32623..abbd1c6 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -1249,13 +1249,13 @@ return *this; } chain -raz(uint64_t mask) const +raz(uint64_t mask = (uint64_t)-1) const { entry._raz = mask; return *this; } chain -rao(uint64_t mask) const +rao(uint64_t mask = (uint64_t)-1) const { entry._rao = mask; return *this; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70559?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I309e345fc8336df3a74474f8f9202bf7e2095b41 Gerrit-Change-Number: 70559 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70561?usp=email to review the following change. Change subject: arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch .. arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/regs/misc.cc 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 6c5a9dd..6f918b2 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2273,10 +2273,7 @@ // AArch32 CP14 registers InitReg(MISCREG_DBGDIDR) - /* For now just implement the version number. - * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) - */ - .reset(0x5 << 16) + .reset(0x6 << 16) // Armv8 Debug architecture .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); InitReg(MISCREG_DBGDSCRint) .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70561?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51 Gerrit-Change-Number: 70561 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add UNSERIALIZE flag to address cpt compatibility
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70557?usp=email to review the following change. Change subject: arch-arm: Add UNSERIALIZE flag to address cpt compatibility .. arch-arm: Add UNSERIALIZE flag to address cpt compatibility This patch is adding the MISCREG_UNSERIALIZE flag to expose the user to the following checkpoint compatibility problem: What happens when a checkpoint is restored with a different architectural configuration? The current behaviour is to silently restore the checkpoint and to populate the ISA registers accordingly. However some of these restored values will be used and some of them will be actually discarded. For example the value of the MISCREG_ID_AA64ISAR0_EL1 register (initially configured at construction time [1]) will be overwritten by the checkpointed value in ISA::unserialize (checkpointed params win over current params). On the other hand we "discard" the checkpointed value for registers handled in the ISA::readMiscReg method (not accessing the storage) like MISCREG_ID_AA64PFR0_EL1 [2] (current params win over checkpointed params). In other words some registers will be unserialized while some others will discard the checkpointed value in favour of the current configuration setup. This categorization is currently implicit and it ultimately depends on whether or not a register read access its storage (see MISCREG_ID_AA64PFR0_EL1 above). With this patch we formalize this distinction. We allow the developer to be explict on which register should not be unserialized and should instead use the new simulation parameters. If there is a mismatch between the reset value of such register and the checkpointed one, we warn the user and we undo the unserialization for such register. [1]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/arch/arm/isa.cc#L437 [2]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/arch/arm/isa.cc#L1019 Change-Id: Icea6563ee5816b14a097926b5734f2fce10530c7 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.hh 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index ffd9cfc..f55235d 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1879,6 +1879,18 @@ { DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n"); UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS); + +for (auto idx = 0; idx < NUM_MISCREGS; idx++) { +if (!lookUpMiscReg[idx].info[MISCREG_UNSERIALIZE] && +miscRegs[idx] != lookUpMiscReg[idx].reset()) { +warn("Checkpoint value for register %s does not match " + "current configuration (checkpointed: %#x, current: %#x)", + miscRegName[idx], miscRegs[idx], + lookUpMiscReg[idx].reset()); +miscRegs[idx] = lookUpMiscReg[idx].reset(); +} +} + CPSR tmp_cpsr = miscRegs[MISCREG_CPSR]; updateRegMap(tmp_cpsr); } diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index 265a697..3a32623 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -1125,6 +1125,7 @@ MISCREG_IMPLEMENTED, MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a // arch generic counter) +MISCREG_UNSERIALIZE,// Should the checkpointed value be restored? MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it // tells whether the instruction should raise a // warning or fail @@ -1277,6 +1278,12 @@ return *this; } chain +unserialize(bool v = true) const +{ +entry.info[MISCREG_UNSERIALIZE] = v; +return *this; +} +chain warnNotFail(bool v = true) const { entry.info[MISCREG_WARN_NOT_FAIL] = v; @@ -1595,7 +1602,7 @@ : entry(e) { // force unimplemented registers to be thusly declared -implemented(1); +implemented(1).unserialize(1); } }; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70557?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Icea6563ee5816b14a097926b5734f2fce10530c7 Gerrit-Change-Number: 70557 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ g
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCTLR to be 64-bit wide
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70566?usp=email to review the following change. Change subject: arch-arm: Extend SCTLR to be 64-bit wide .. arch-arm: Extend SCTLR to be 64-bit wide In AArch64 SCTLR_EL1/_EL2/_EL3 is 64-bit wide Change-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/regs/misc_types.hh 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index e446ce5..7e7ff67 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -371,7 +371,7 @@ Bitfield<0> ns; EndBitUnion(SCR) -BitUnion32(SCTLR) +BitUnion64(SCTLR) Bitfield<31> enia;// ARMv8.3 PAuth Bitfield<30> enib;// ARMv8.3 PAuth Bitfield<30> te; // Thumb Exception Enable (AArch32 only) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70566?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371 Gerrit-Change-Number: 70566 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move RO values from ISA::read to the reset field
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70558?usp=email to review the following change. Change subject: arch-arm: Move RO values from ISA::read to the reset field .. arch-arm: Move RO values from ISA::read to the reset field This is simplyfying the ISA::readMiscReg, and it is stopping us from recomputing values that won't change throughout the simulation Change-Id: I62270cdb59f39b8a143e9554c8beaa8cd15824aa Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 49 insertions(+), 66 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index f55235d..14349b1 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -486,35 +486,6 @@ warn_once("The ccsidr register isn't implemented and " "always reads as 0.\n"); break; - case MISCREG_CTR: // AArch32, ARMv7, top bit set - case MISCREG_CTR_EL0: // AArch64 -{ -//all caches have the same line size in gem5 -//4 byte words in ARM -unsigned lineSizeWords = -tc->getSystemPtr()->cacheLineSize() / 4; -unsigned log2LineSizeWords = 0; - -while (lineSizeWords >>= 1) { -++log2LineSizeWords; -} - -CTR ctr = 0; -//log2 of minimun i-cache line size (words) -ctr.iCacheLineSize = log2LineSizeWords; -//b11 - gem5 uses pipt -ctr.l1IndexPolicy = 0x3; -//log2 of minimum d-cache line size (words) -ctr.dCacheLineSize = log2LineSizeWords; -//log2 of max reservation size (words) -ctr.erg = log2LineSizeWords; -//log2 of max writeback size (words) -ctr.cwg = log2LineSizeWords; -//b100 - gem5 format is ARMv7 -ctr.format = 0x4; - -return ctr; -} case MISCREG_ACTLR: warn("Not doing anything for miscreg ACTLR\n"); break; @@ -615,11 +586,6 @@ l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1; return l2ctlr; } - case MISCREG_DBGDIDR: -/* For now just implement the version number. - * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) - */ -return 0x5 << 16; case MISCREG_DBGDSCRint: return readMiscRegNoEffect(MISCREG_DBGDSCRint); case MISCREG_ISR: @@ -632,8 +598,6 @@ readMiscRegNoEffect(MISCREG_CPSR), readMiscRegNoEffect(MISCREG_SCR_EL3)); } - case MISCREG_DCZID_EL0: -return 0x04; // DC ZVA clear 64-byte chunks case MISCREG_HCPTR: { RegVal val = readMiscRegNoEffect(idx); @@ -656,36 +620,6 @@ case MISCREG_HIFAR: // alias for secure IFAR return readMiscRegNoEffect(MISCREG_IFAR_S); - case MISCREG_ID_PFR0: -// !ThumbEE | !Jazelle | Thumb | ARM -return 0x0031; - case MISCREG_ID_PFR1: -{ // Timer | Virti | !M Profile | TrustZone | ARMv4 -bool have_timer = (system->getGenericTimer() != nullptr); -return 0x0001 | -(release->has(ArmExtension::SECURITY) ? -0x0010 : 0x0) | -(release->has(ArmExtension::VIRTUALIZATION) ? -0x1000 : 0x0) | -(have_timer ? 0x0001 : 0x0); -} - case MISCREG_ID_AA64PFR0_EL1: -return 0x0002 | // AArch{64,32} supported at EL0 - 0x0020 | // EL1 - (release->has(ArmExtension::VIRTUALIZATION) ? -0x0200 : 0) | // EL2 - (release->has(ArmExtension::SECURITY) ? -0x2000 : 0) | // EL3 - (release->has(ArmExtension::FEAT_SVE) ? -0x0001 : 0) | // SVE - (release->has(ArmExtension::FEAT_SEL2) ? -0x0010 : 0) | // SecEL2 - (gicv3CpuInterface ? 0x0100 : 0); - case MISCREG_ID_AA64PFR1_EL1: -return 0x0 | - (release->has(ArmExtension::FEAT_SME) ? -0x1 << 24 : 0); // SME - // Generic Timer registers case MISCREG_CNTFRQ ... MISCREG_CNTVOFF: case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2: diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 7a06da1..960c2be 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2273,6 +2273,10 @@ // AArch32 CP14 registers Ini
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Simplify FPSCR writes
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email to review the following change. Change subject: arch-arm: Simplify FPSCR writes .. arch-arm: Simplify FPSCR writes The old logic was setting up a mask which was covering pretty much the entire register, except for the FPSCR[14:13] and FPSCR[6:5] register fields. Those RES0 fields were treated as WI. We simplify this by explicitly marking them as RES0 at construction time Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 2 insertions(+), 32 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 83df61f..9c8e282 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -815,38 +815,7 @@ return; case MISCREG_FPSCR: -{ -const uint32_t ones = (uint32_t)(-1); -FPSCR fpscrMask = 0; -fpscrMask.ioc = ones; -fpscrMask.dzc = ones; -fpscrMask.ofc = ones; -fpscrMask.ufc = ones; -fpscrMask.ixc = ones; -fpscrMask.idc = ones; -fpscrMask.ioe = ones; -fpscrMask.dze = ones; -fpscrMask.ofe = ones; -fpscrMask.ufe = ones; -fpscrMask.ixe = ones; -fpscrMask.ide = ones; -fpscrMask.len = ones; -fpscrMask.fz16 = ones; -fpscrMask.stride = ones; -fpscrMask.rMode = ones; -fpscrMask.fz = ones; -fpscrMask.dn = ones; -fpscrMask.ahp = ones; -fpscrMask.qc = ones; -fpscrMask.v = ones; -fpscrMask.c = ones; -fpscrMask.z = ones; -fpscrMask.n = ones; -newVal = (newVal & (uint32_t)fpscrMask) | - (readMiscRegNoEffect(MISCREG_FPSCR) & - ~(uint32_t)fpscrMask); -tc->getDecoderPtr()->as().setContext(newVal); -} +tc->getDecoderPtr()->as().setContext(newVal); break; case MISCREG_FPSR: { diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 9203810..2d76143 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2199,6 +2199,7 @@ .reset(p.fpsid) .allPrivileges(); InitReg(MISCREG_FPSCR) + .res0(mask(14, 13) | mask(6, 5)) .allPrivileges(); InitReg(MISCREG_MVFR1) .reset([] () { -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95 Gerrit-Change-Number: 70565 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Remove unnecessary case in ISA::readMiscReg
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70564?usp=email to review the following change. Change subject: arch-arm: Remove unnecessary case in ISA::readMiscReg .. arch-arm: Remove unnecessary case in ISA::readMiscReg Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc 1 file changed, 0 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index ab6e3f7..83df61f 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -567,8 +567,6 @@ l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1; return l2ctlr; } - case MISCREG_DBGDSCRint: -return readMiscRegNoEffect(MISCREG_DBGDSCRint); case MISCREG_ISR: case MISCREG_ISR_EL1: { -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70564?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f Gerrit-Change-Number: 70564 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Implement RAZ/WI with raz specifier
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70560?usp=email to review the following change. Change subject: arch-arm: Implement RAZ/WI with raz specifier .. arch-arm: Implement RAZ/WI with raz specifier Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 14349b1..7df8978 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -470,12 +470,6 @@ return readMiscRegNoEffect(idx); } break; - case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI - case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI - case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI - case MISCREG_AIDR: // AUX ID set to 0 - case MISCREG_TCMTR: // No TCM's -return 0; case MISCREG_CLIDR: warn_once("The clidr register always reports 0 caches.\n"); diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 960c2be..6c5a9dd 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2505,12 +2505,15 @@ .unimplemented() .allPrivileges(); InitReg(MISCREG_JIDR) + .raz() // Jazelle trivial implementation, RAZ/WI .allPrivileges(); InitReg(MISCREG_TEEHBR) .allPrivileges(); InitReg(MISCREG_JOSCR) + .raz() // Jazelle trivial implementation, RAZ/WI .allPrivileges(); InitReg(MISCREG_JMCR) + .raz() // Jazelle trivial implementation, RAZ/WI .allPrivileges(); // AArch32 CP15 registers @@ -2548,6 +2551,7 @@ .unserialize(0) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_TCMTR) + .raz() // No TCM's .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_TLBTR) .reset(1) // Separate Instruction and Data TLBs @@ -2646,6 +2650,7 @@ InitReg(MISCREG_CLIDR) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_AIDR) + .raz() // AUX ID set to 0 .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_CSSELR) .banked(); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70560?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5 Gerrit-Change-Number: 70560 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Group self hosted debug writes in ISA switch
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70562?usp=email to review the following change. Change subject: arch-arm: Group self hosted debug writes in ISA switch .. arch-arm: Group self hosted debug writes in ISA switch Change-Id: If9c0675743856b603e7b5ec1898f5cdd650f3ce6 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc 1 file changed, 8 insertions(+), 188 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 7df8978..bef2db5 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -962,101 +962,11 @@ tc->setMiscReg(MISCREG_DBGOSLSR, r); } break; - case MISCREG_DBGBCR0: -selfDebug->updateDBGBCR(0, val); + case MISCREG_DBGBCR0 ... MISCREG_DBGBCR15: +selfDebug->updateDBGBCR(idx - MISCREG_DBGBCR0, val); break; - case MISCREG_DBGBCR1: -selfDebug->updateDBGBCR(1, val); -break; - case MISCREG_DBGBCR2: -selfDebug->updateDBGBCR(2, val); -break; - case MISCREG_DBGBCR3: -selfDebug->updateDBGBCR(3, val); -break; - case MISCREG_DBGBCR4: -selfDebug->updateDBGBCR(4, val); -break; - case MISCREG_DBGBCR5: -selfDebug->updateDBGBCR(5, val); -break; - case MISCREG_DBGBCR6: -selfDebug->updateDBGBCR(6, val); -break; - case MISCREG_DBGBCR7: -selfDebug->updateDBGBCR(7, val); -break; - case MISCREG_DBGBCR8: -selfDebug->updateDBGBCR(8, val); -break; - case MISCREG_DBGBCR9: -selfDebug->updateDBGBCR(9, val); -break; - case MISCREG_DBGBCR10: -selfDebug->updateDBGBCR(10, val); -break; - case MISCREG_DBGBCR11: -selfDebug->updateDBGBCR(11, val); -break; - case MISCREG_DBGBCR12: -selfDebug->updateDBGBCR(12, val); -break; - case MISCREG_DBGBCR13: -selfDebug->updateDBGBCR(13, val); -break; - case MISCREG_DBGBCR14: -selfDebug->updateDBGBCR(14, val); -break; - case MISCREG_DBGBCR15: -selfDebug->updateDBGBCR(15, val); -break; - case MISCREG_DBGWCR0: -selfDebug->updateDBGWCR(0, val); -break; - case MISCREG_DBGWCR1: -selfDebug->updateDBGWCR(1, val); -break; - case MISCREG_DBGWCR2: -selfDebug->updateDBGWCR(2, val); -break; - case MISCREG_DBGWCR3: -selfDebug->updateDBGWCR(3, val); -break; - case MISCREG_DBGWCR4: -selfDebug->updateDBGWCR(4, val); -break; - case MISCREG_DBGWCR5: -selfDebug->updateDBGWCR(5, val); -break; - case MISCREG_DBGWCR6: -selfDebug->updateDBGWCR(6, val); -break; - case MISCREG_DBGWCR7: -selfDebug->updateDBGWCR(7, val); -break; - case MISCREG_DBGWCR8: -selfDebug->updateDBGWCR(8, val); -break; - case MISCREG_DBGWCR9: -selfDebug->updateDBGWCR(9, val); -break; - case MISCREG_DBGWCR10: -selfDebug->updateDBGWCR(10, val); -break; - case MISCREG_DBGWCR11: -selfDebug->updateDBGWCR(11, val); -break; - case MISCREG_DBGWCR12: -selfDebug->updateDBGWCR(12, val); -break; - case MISCREG_DBGWCR13: -selfDebug->updateDBGWCR(13, val); -break; - case MISCREG_DBGWCR14: -selfDebug->updateDBGWCR(14, val); -break; - case MISCREG_DBGWCR15: -selfDebug->updateDBGWCR(15, val); + case MISCREG_DBGWCR0 ... MISCREG_DBGWCR15: +selfDebug->updateDBGWCR(idx - MISCREG_DBGWCR0, val); break; case MISCREG_MDCR_EL2: @@ -1100,101 +1010,11 @@ } break; - case MISCREG_DBGBCR0_EL1: -selfDebug->updateDBGBCR(0, val); + case MISCREG_DBGBCR0_EL1 ... MISCREG_DBGBCR15_EL1: +selfDebug->updateDBGBCR(idx - MISCREG_DBGBCR0_EL1, val); break; - case MISCREG_DBGBCR1_EL1: -selfDebug->updateDBGBCR(1, val); -break; - case MISCREG_DBGBCR2_EL1: -selfDebug->updateDBGBCR(2, val); -break; - case
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove clear32/64 methods
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70470?usp=email ) Change subject: arch-arm: Remove clear32/64 methods .. arch-arm: Remove clear32/64 methods Change-Id: I62d2dc0612298fdb4cdc3bf368e080c8ebebe23a Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70470 Tested-by: kokoro --- M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/regs/misc.cc 3 files changed, 78 insertions(+), 111 deletions(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index d87e9c5..ffd9cfc 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -131,8 +131,6 @@ void ISA::clear() { -const Params &p(params()); - // Invalidate cached copies of miscregs in the TLBs if (tc) { getMMUPtr(tc)->invalidateMiscReg(); @@ -142,111 +140,7 @@ miscRegs[idx] = lookUpMiscReg[idx].reset(); } -if (FullSystem && system->highestELIs64()) { -// Initialize AArch64 state -clear64(p); -return; -} - -// Initialize AArch32 state... -clear32(p); -} - -void -ISA::clear32(const ArmISAParams &p) -{ -CPSR cpsr = 0; -cpsr.mode = MODE_USER; - -if (FullSystem) { -miscRegs[MISCREG_MVBAR] = system->resetAddr(); -} - -miscRegs[MISCREG_CPSR] = cpsr; -updateRegMap(cpsr); - -SCTLR sctlr = 0; -sctlr.u = 1; -sctlr.xp = 1; -sctlr.rao2 = 1; -sctlr.rao3 = 1; -sctlr.rao4 = 0xf; // SCTLR[6:3] -sctlr.uci = 1; -sctlr.dze = 1; -miscRegs[MISCREG_SCTLR_NS] = sctlr; -miscRegs[MISCREG_HCPTR] = 0; - -miscRegs[MISCREG_CPACR] = 0; - -miscRegs[MISCREG_FPSID] = p.fpsid; - -if (release->has(ArmExtension::LPAE)) { -TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; -ttbcr.eae = 0; -miscRegs[MISCREG_TTBCR_NS] = ttbcr; -// Enforce consistency with system-level settings -miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; -} - -if (release->has(ArmExtension::SECURITY)) { -miscRegs[MISCREG_SCTLR_S] = sctlr; -miscRegs[MISCREG_SCR] = 0; -miscRegs[MISCREG_VBAR_S] = 0; -} else { -// we're always non-secure -miscRegs[MISCREG_SCR] = 1; -} - -//XXX We need to initialize the rest of the state. -} - -void -ISA::clear64(const ArmISAParams &p) -{ -CPSR cpsr = 0; -Addr rvbar = system->resetAddr(); -switch (system->highestEL()) { -// Set initial EL to highest implemented EL using associated stack -// pointer (SP_ELx); set RVBAR_ELx to implementation defined reset -// value - case EL3: -cpsr.mode = MODE_EL3H; -miscRegs[MISCREG_RVBAR_EL3] = rvbar; -break; - case EL2: -cpsr.mode = MODE_EL2H; -miscRegs[MISCREG_RVBAR_EL2] = rvbar; -break; - case EL1: -cpsr.mode = MODE_EL1H; -miscRegs[MISCREG_RVBAR_EL1] = rvbar; -break; - default: -panic("Invalid highest implemented exception level"); -break; -} - -// Initialize rest of CPSR -cpsr.daif = 0xf; // Mask all interrupts -cpsr.ss = 0; -cpsr.il = 0; -miscRegs[MISCREG_CPSR] = cpsr; -updateRegMap(cpsr); - -// Initialize other control registers -miscRegs[MISCREG_MPIDR_EL1] = 0x8000; -if (release->has(ArmExtension::SECURITY)) { -miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; -miscRegs[MISCREG_SCR_EL3] = 0x0030; // RES1 fields -} else if (release->has(ArmExtension::VIRTUALIZATION)) { -// also MISCREG_SCTLR_EL2 (by mapping) -miscRegs[MISCREG_HSCTLR] = 0x30c50830; -} else { -// also MISCREG_SCTLR_EL1 (by mapping) -miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init -// Always non-secure -miscRegs[MISCREG_SCR_EL3] = 1; -} +updateRegMap(miscRegs[MISCREG_CPSR]); } void diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 55fbd03..8ed37ba 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -170,9 +170,6 @@ void clear() override; protected: -void clear32(const ArmISAParams &p); -void clear64(const ArmISAParams &p); - void addressTranslation(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val); void addressTranslation64(MMU::ArmTranslationType tran_type, diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index ef5d741..7a06da1 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2079,6 +2079,38 @@ return *this; } +static CPSR
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID64
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70469?usp=email ) Change subject: arch-arm: Remove ISA::initID64 .. arch-arm: Remove ISA::initID64 Signed-off-by: Giacomo Travaglini Change-Id: I3d03ee15df46fa7d9a9ec439b26e99baf33cbb5e Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70469 Tested-by: kokoro --- M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/regs/misc.cc 3 files changed, 123 insertions(+), 125 deletions(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index b1e463a..d87e9c5 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -142,12 +142,6 @@ miscRegs[idx] = lookUpMiscReg[idx].reset(); } -// We always initialize AArch64 ID registers even -// if we are in AArch32. This is done since if we -// are in SE mode we don't know if our ArmProcess is -// AArch32 or AArch64 -initID64(p); - if (FullSystem && system->highestELIs64()) { // Initialize AArch64 state clear64(p); @@ -256,124 +250,6 @@ } void -ISA::initID64(const ArmISAParams &p) -{ -// Initialize configurable id registers -miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1; -miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1; - -AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1; -dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3 -miscRegs[MISCREG_ID_AA64DFR0_EL1] = dfr0_el1; - -miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1; - -// SVE -miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0 -if (release->has(ArmExtension::SECURITY)) { -miscRegs[MISCREG_ZCR_EL3] = sveVL - 1; -} else if (release->has(ArmExtension::VIRTUALIZATION)) { -miscRegs[MISCREG_ZCR_EL2] = sveVL - 1; -} else { -miscRegs[MISCREG_ZCR_EL1] = sveVL - 1; -} - -// SME - -// Set up the SME SMIDR -// [63:32] RES0 -// [31:24] Implementer - default this to Arm Limited -// [23:16] SMCU Revision - set to 0 as we don't model an SMCU -// [15]SMPS - We don't do priorities in gem5, so disable -// [14:12] RES0 -// [11:0] Affinity - we implement per-CPU SME, so set to 0 (no SMCU) -SMIDR smidr_el1 = 0; -smidr_el1.affinity = 0; -smidr_el1.smps = 0; -smidr_el1.implementer = 0x41; -miscRegs[MISCREG_SMIDR_EL1] = smidr_el1; - -AA64SMFR0 smfr0_el1 = 0; -smfr0_el1.f32f32 = 0x1; -// The following BF16F32 is actually not implemented due to a lack -// of BF16 support in gem5's fplib. However, as per the SME spec the -// _only_ allowed value is 0x1. -smfr0_el1.b16f32 = 0x1; -smfr0_el1.f16f32 = 0x1; -smfr0_el1.i8i32 = 0xF; -smfr0_el1.f64f64 = 0x1; -smfr0_el1.i16i64 = 0xF; -smfr0_el1.smEver = 0; -smfr0_el1.fa64 = 0x1; -miscRegs[MISCREG_ID_AA64SMFR0_EL1] = smfr0_el1; - -// We want to support FEAT_SME_FA64. Therefore, we enable it in all -// SMCR_ELx registers by default. Runtime software might change this -// later, but given that gem5 doesn't disable instructions based on -// this flag we default to the most representative value. -miscRegs[MISCREG_SMCR_EL3] = 0x1 << 31; -miscRegs[MISCREG_SMCR_EL2] = 0x1 << 31; -miscRegs[MISCREG_SMCR_EL1] = 0x1 << 31; - -// Set the vector default vector length -if (release->has(ArmExtension::SECURITY)) { -miscRegs[MISCREG_SMCR_EL3] |= ((smeVL - 1) & 0xF); -} else if (release->has(ArmExtension::VIRTUALIZATION)) { -miscRegs[MISCREG_SMCR_EL2] |= ((smeVL - 1) & 0xF); -} else { -miscRegs[MISCREG_SMCR_EL1] |= ((smeVL - 1) & 0xF); -} - -AA64PFR0 pfr0_el1 = 0; -pfr0_el1.el3 = release->has(ArmExtension::SECURITY) ? 0x2 : 0x0; -pfr0_el1.el2 = release->has(ArmExtension::VIRTUALIZATION) ? 0x2 : 0x0; -pfr0_el1.sve = release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0; -pfr0_el1.sel2 = release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0; -miscRegs[MISCREG_ID_AA64PFR0_EL1] = pfr0_el1; - -AA64MMFR0 mmfr0_el1 = p.id_aa64mmfr0_el1; -mmfr0_el1.asidbits = haveLargeAsid64 ? 0x2 : 0x0; -mmfr0_el1.parange = encodePhysAddrRange64(physAddrRange); -miscRegs[MISCREG_ID_AA64MMFR0_EL1] = mmfr0_el1; - -AA64ISAR0 isar0_el1 = p.id_aa64isar0_el1; -if (release->has(ArmExtension::CRYPTO)) { -isar0_el1.crc32 = 1; -isar0_el1.sha2 = 1; -isar0_el1.sha1 = 1; -isar0_el1.aes = 2; -} else { -isar0_el1.crc32 = 0; -isar0_el1.sha2 = 0; -isar0_el1.sha1 = 0; -isar0_el1.aes = 0; -} -isar0_el1.atomic = release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0; -isar0_el1.rdm = r
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID64 using BitUnions
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70468?usp=email ) Change subject: arch-arm: Rewrite ISA::initID64 using BitUnions .. arch-arm: Rewrite ISA::initID64 using BitUnions Signed-off-by: Giacomo Travaglini Change-Id: I3e8c7bdcf86c01eccbd90fccaa2d4306a501ed13 Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70468 Tested-by: kokoro --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc M src/arch/arm/regs/misc_types.hh 3 files changed, 74 insertions(+), 117 deletions(-) Approvals: kokoro: Regressions pass Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 8424db5..b1e463a 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -261,21 +261,12 @@ // Initialize configurable id registers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1; miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1; -miscRegs[MISCREG_ID_AA64DFR0_EL1] = -(p.id_aa64dfr0_el1 & 0xf0ffULL) | -(p.pmu ? 0x0100ULL : 0); // Enable PMUv3 + +AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1; +dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3 +miscRegs[MISCREG_ID_AA64DFR0_EL1] = dfr0_el1; miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1; -miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p.id_aa64isar0_el1; -miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p.id_aa64isar1_el1; -miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p.id_aa64mmfr0_el1; -miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p.id_aa64mmfr1_el1; -miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p.id_aa64mmfr2_el1; - -miscRegs[MISCREG_ID_DFR0_EL1] = -(p.pmu ? 0x0300ULL : 0); // Enable PMUv3 - -miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; // SVE miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0 @@ -296,22 +287,25 @@ // [15]SMPS - We don't do priorities in gem5, so disable // [14:12] RES0 // [11:0] Affinity - we implement per-CPU SME, so set to 0 (no SMCU) -miscRegs[MISCREG_SMIDR_EL1] = 0 | // Affinity -0 << 15 | // SMPS -0x41 << 24; // Implementer +SMIDR smidr_el1 = 0; +smidr_el1.affinity = 0; +smidr_el1.smps = 0; +smidr_el1.implementer = 0x41; +miscRegs[MISCREG_SMIDR_EL1] = smidr_el1; -miscRegs[MISCREG_ID_AA64SMFR0_EL1] = 0; -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 32; // F32F32 +AA64SMFR0 smfr0_el1 = 0; +smfr0_el1.f32f32 = 0x1; // The following BF16F32 is actually not implemented due to a lack // of BF16 support in gem5's fplib. However, as per the SME spec the // _only_ allowed value is 0x1. -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 34; // BF16F32 -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 35; // F16F32 -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0xFUL << 36; // I8I32 -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 48; // F64F64 -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0xFUL << 52; // I16I64 -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x0UL << 56; // SMEver -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 32; // FA64 +smfr0_el1.b16f32 = 0x1; +smfr0_el1.f16f32 = 0x1; +smfr0_el1.i8i32 = 0xF; +smfr0_el1.f64f64 = 0x1; +smfr0_el1.i16i64 = 0xF; +smfr0_el1.smEver = 0; +smfr0_el1.fa64 = 0x1; +miscRegs[MISCREG_ID_AA64SMFR0_EL1] = smfr0_el1; // We want to support FEAT_SME_FA64. Therefore, we enable it in all // SMCR_ELx registers by default. Runtime software might change this @@ -330,103 +324,53 @@ miscRegs[MISCREG_SMCR_EL1] |= ((smeVL - 1) & 0xF); } -// Enforce consistency with system-level settings... +AA64PFR0 pfr0_el1 = 0; +pfr0_el1.el3 = release->has(ArmExtension::SECURITY) ? 0x2 : 0x0; +pfr0_el1.el2 = release->has(ArmExtension::VIRTUALIZATION) ? 0x2 : 0x0; +pfr0_el1.sve = release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0; +pfr0_el1.sel2 = release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0; +miscRegs[MISCREG_ID_AA64PFR0_EL1] = pfr0_el1; -// EL3 -miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( -miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, -release->has(ArmExtension::SECURITY) ? 0x2 : 0x0); -// EL2 -miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( -miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, -release->has(ArmExtension::VIRTUALIZATION) ? 0x2 : 0x0); -// SVE -miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( -miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32, -release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0); -// SME -miscRegs[MISCREG_ID_AA64PFR1_EL1] = insertBits( -miscRegs[MISCREG_ID_AA64PFR1_EL1
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: VMPIDR_EL2 can be used in secure mode as well
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70471?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: VMPIDR_EL2 can be used in secure mode as well .. arch-arm: VMPIDR_EL2 can be used in secure mode as well This was some old code still assuming EL2 is not implemented in secure mode. This is wrong since the introduction of FEAT_SEL2 in gem5 Change-Id: Ie7e112a83e64f33a98885e88504c2d6bc5070218 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70471 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- M src/arch/arm/utility.cc 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass Richard Cooper: Looks good to me, approved diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 6764569..05d1cab 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -139,8 +139,6 @@ { const ExceptionLevel current_el = currEL(tc); -const bool is_secure = isSecureBelowEL3(tc); - switch (current_el) { case EL0: // Note: in MsrMrs instruction we read the register value before @@ -150,7 +148,7 @@ warn_once("Trying to read MPIDR at EL0\n"); [[fallthrough]]; case EL1: -if (ArmSystem::haveEL(tc, EL2) && !is_secure) +if (EL2Enabled(tc)) return tc->readMiscReg(MISCREG_VMPIDR_EL2); else return getMPIDR(arm_sys, tc); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70471?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ie7e112a83e64f33a98885e88504c2d6bc5070218 Gerrit-Change-Number: 70471 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID32
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70467?usp=email ) Change subject: arch-arm: Remove ISA::initID32 .. arch-arm: Remove ISA::initID32 Signed-off-by: Giacomo Travaglini Change-Id: I70cce0b9d99ed5fe146e64c6ee55fa8cedf98ac6 Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70467 Tested-by: kokoro Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power --- M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/regs/misc.cc 3 files changed, 46 insertions(+), 54 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved Richard Cooper: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 4033d0f..8424db5 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -142,8 +142,6 @@ miscRegs[idx] = lookUpMiscReg[idx].reset(); } -initID32(p); - // We always initialize AArch64 ID registers even // if we are in AArch32. This is done since if we // are in SE mode we don't know if our ArmProcess is @@ -258,57 +256,6 @@ } void -ISA::initID32(const ArmISAParams &p) -{ -// Initialize configurable default values - -uint32_t midr; -if (p.midr != 0x0) -midr = p.midr; -else if (highestELIs64) -// Cortex-A57 TRM r0p0 MIDR -midr = 0x410fd070; -else -// Cortex-A15 TRM r0p0 MIDR -midr = 0x410fc0f0; - -miscRegs[MISCREG_MIDR] = midr; -miscRegs[MISCREG_VPIDR] = midr; - -miscRegs[MISCREG_ID_ISAR0] = p.id_isar0; -miscRegs[MISCREG_ID_ISAR1] = p.id_isar1; -miscRegs[MISCREG_ID_ISAR2] = p.id_isar2; -miscRegs[MISCREG_ID_ISAR3] = p.id_isar3; -miscRegs[MISCREG_ID_ISAR4] = p.id_isar4; - -miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0; -miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1; -miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2; -miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3; -miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4; - -ISAR5 isar5 = p.id_isar5; -if (release->has(ArmExtension::CRYPTO)) { -isar5.crc32 = 1; -isar5.sha2 = 1; -isar5.sha1 = 1; -isar5.aes = 2; -} else { -isar5.crc32 = 0; -isar5.sha2 = 0; -isar5.sha1 = 0; -isar5.aes = 0; -} -isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0; -isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0; -miscRegs[MISCREG_ID_ISAR5] = isar5; - -ISAR6 isar6 = p.id_isar6; -isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0; -miscRegs[MISCREG_ID_ISAR6] = isar6; -} - -void ISA::initID64(const ArmISAParams &p) { // Initialize configurable id registers diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 5dd1b38..8419641 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -172,7 +172,6 @@ protected: void clear32(const ArmISAParams &p); void clear64(const ArmISAParams &p); -void initID32(const ArmISAParams &p); void initID64(const ArmISAParams &p); void addressTranslation(MMU::ArmTranslationType tran_type, diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 3b23a20..f5e2502 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -45,6 +45,7 @@ #include "cpu/thread_context.hh" #include "dev/arm/gic_v3_cpu_interface.hh" #include "sim/full_system.hh" +#include "params/ArmISA.hh" namespace gem5 { @@ -2116,6 +2117,17 @@ const bool vhe_implemented = release->has(ArmExtension::FEAT_VHE); const bool sel2_implemented = release->has(ArmExtension::FEAT_SEL2); +const Params &p(params()); + +uint32_t midr; +if (p.midr != 0x0) +midr = p.midr; +else if (highestELIs64) +// Cortex-A57 TRM r0p0 MIDR +midr = 0x410fd070; +else +// Cortex-A15 TRM r0p0 MIDR +midr = 0x410fc0f0; /** * Some registers alias with others, and therefore need to be translated. @@ -2465,6 +2477,7 @@ // AArch32 CP15 registers InitReg(MISCREG_MIDR) + .reset(midr) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_CTR) .allPrivileges().exceptUserMode().writes(0); @@ -2488,28 +2501,60 @@ InitReg(MISCREG_ID_AFR0) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR0) + .reset(p.id_mmfr0) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR1) + .reset(p.id_mmfr1) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR2) + .reset(p.id_mmfr2) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR3) + .reset(p.id_mmfr3)
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70460?usp=email ) Change subject: arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version .. arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version Signed-off-by: Giacomo Travaglini Change-Id: I28753de7b437be58e5ac891ac2e549bbab6b53b0 Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70460 Tested-by: kokoro Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power --- M src/arch/arm/regs/misc.cc 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Richard Cooper: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index e984164..4221a15 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3579,10 +3579,12 @@ .mapsTo(MISCREG_ID_ISAR6); InitReg(MISCREG_MVFR0_EL1) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_MVFR0); InitReg(MISCREG_MVFR1_EL1) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_MVFR1); InitReg(MISCREG_MVFR2_EL1) .faultRead(EL1, HCR_TRAP(tid3)) .allPrivileges().exceptUserMode().writes(0); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70460?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I28753de7b437be58e5ac891ac2e549bbab6b53b0 Gerrit-Change-Number: 70460 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Make MISCREGs reset value configurable
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70458?usp=email ) Change subject: arch-arm: Make MISCREGs reset value configurable .. arch-arm: Make MISCREGs reset value configurable Signed-off-by: Giacomo Travaglini Change-Id: I536065a2de5faeb8ab64391f8ca2aa83fb2cc82f Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70458 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/regs/misc.hh 1 file changed, 7 insertions(+), 1 deletion(-) Approvals: Richard Cooper: Looks good to me, approved kokoro: Regressions pass Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index bf25ea3..69d1461 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2022 Arm Limited + * Copyright (c) 2010-2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -1231,6 +1231,12 @@ return *this; } chain +reset(uint64_t res_val) const +{ +entry._reset = res_val; +return *this; +} +chain res0(uint64_t mask) const { entry._res0 = mask; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70458?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I536065a2de5faeb8ab64391f8ca2aa83fb2cc82f Gerrit-Change-Number: 70458 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID32 using BitUnions
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70466?usp=email ) Change subject: arch-arm: Rewrite ISA::initID32 using BitUnions .. arch-arm: Rewrite ISA::initID32 using BitUnions Signed-off-by: Giacomo Travaglini Change-Id: I38460766bb5ed363b176bc6faca8e770a8a5e4c6 Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70466 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Jason Lowe-Power --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc_types.hh 2 files changed, 39 insertions(+), 19 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved Richard Cooper: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index a66a938..4033d0f 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -280,8 +280,6 @@ miscRegs[MISCREG_ID_ISAR2] = p.id_isar2; miscRegs[MISCREG_ID_ISAR3] = p.id_isar3; miscRegs[MISCREG_ID_ISAR4] = p.id_isar4; -miscRegs[MISCREG_ID_ISAR5] = p.id_isar5; -miscRegs[MISCREG_ID_ISAR6] = p.id_isar6; miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0; miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1; @@ -289,24 +287,25 @@ miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3; miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4; -/** MISCREG_ID_ISAR5 */ -// Crypto -miscRegs[MISCREG_ID_ISAR5] = insertBits( -miscRegs[MISCREG_ID_ISAR5], 19, 4, -release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0); -// RDM -miscRegs[MISCREG_ID_ISAR5] = insertBits( -miscRegs[MISCREG_ID_ISAR5], 27, 24, -release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0); -// FCMA -miscRegs[MISCREG_ID_ISAR5] = insertBits( -miscRegs[MISCREG_ID_ISAR5], 31, 28, -release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0); +ISAR5 isar5 = p.id_isar5; +if (release->has(ArmExtension::CRYPTO)) { +isar5.crc32 = 1; +isar5.sha2 = 1; +isar5.sha1 = 1; +isar5.aes = 2; +} else { +isar5.crc32 = 0; +isar5.sha2 = 0; +isar5.sha1 = 0; +isar5.aes = 0; +} +isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0; +isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0; +miscRegs[MISCREG_ID_ISAR5] = isar5; -/** ID_ISAR6 */ -miscRegs[MISCREG_ID_ISAR6] = insertBits( -miscRegs[MISCREG_ID_ISAR6], 3, 0, -release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0); +ISAR6 isar6 = p.id_isar6; +isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0; +miscRegs[MISCREG_ID_ISAR6] = isar6; } void diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index 0fe5a00..9af5337 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -75,6 +75,27 @@ Bitfield<0> sp; // AArch64 EndBitUnion(CPSR) +BitUnion32(ISAR5) +Bitfield<31, 28> vcma; +Bitfield<27, 24> rdm; +Bitfield<19, 16> crc32; +Bitfield<15, 12> sha2; +Bitfield<11, 8> sha1; +Bitfield<7, 4> aes; +Bitfield<3, 0> sevl; +EndBitUnion(ISAR5) + +BitUnion32(ISAR6) +Bitfield<31, 28> clrbhb; +Bitfield<27, 24> i8mm; +Bitfield<23, 20> bf16; +Bitfield<19, 16> specres; +Bitfield<15, 12> sb; +Bitfield<11, 8> fhm; +Bitfield<7, 4> dp; +Bitfield<3, 0> jscvt; +EndBitUnion(ISAR6) + BitUnion64(AA64DFR0) Bitfield<43, 40> tracefilt; Bitfield<39, 36> doublelock; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70466?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I38460766bb5ed363b176bc6faca8e770a8a5e4c6 Gerrit-Change-Number: 70466 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map CTR_EL0 to AArch32 version
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70463?usp=email ) Change subject: arch-arm: Map CTR_EL0 to AArch32 version .. arch-arm: Map CTR_EL0 to AArch32 version Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70463 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Jason Lowe-Power --- M src/arch/arm/regs/misc.cc 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass Richard Cooper: Looks good to me, approved diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 706716e..a31b6de 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3681,7 +3681,8 @@ InitReg(MISCREG_CTR_EL0) .faultRead(EL0, faultCtrEL0) .faultRead(EL1, HCR_TRAP(tid2)) - .reads(1); + .reads(1) + .mapsTo(MISCREG_CTR); InitReg(MISCREG_DCZID_EL0) .reads(1); InitReg(MISCREG_VPIDR_EL2) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70463?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8 Gerrit-Change-Number: 70463 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Replace 0ing of miscRegs with assignment of reset value
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70457?usp=email ) Change subject: arch-arm: Replace 0ing of miscRegs with assignment of reset value .. arch-arm: Replace 0ing of miscRegs with assignment of reset value The reset variable in the MiscRegLUTEntry class defines the per-register reset value. Rather than simply zeroing the misc registers we should assign them their reset value when clearing them. As of now the reset variable is unused so using it is functionally equivalent of calling memset. This will however change once we start using the reset field Signed-off-by: Giacomo Travaglini Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79 Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70457 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- M src/arch/arm/isa.cc 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index aec8243..5a0dec5 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -141,7 +141,9 @@ } SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; -memset(miscRegs, 0, sizeof(miscRegs)); +for (auto idx = 0; idx < NUM_MISCREGS; idx++) { +miscRegs[idx] = lookUpMiscReg[idx].reset(); +} initID32(p); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70457?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79 Gerrit-Change-Number: 70457 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix read redirection for MIDR register
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70464?usp=email ) Change subject: arch-arm: Fix read redirection for MIDR register .. arch-arm: Fix read redirection for MIDR register This patch is fixing read redirection for the MIDR register in the following ways: 1) Is allowing a virtualization of the register (via VPIDR) even in secure mode (available with FEAT_SEL2) 2) Is extending this logic to the AArch64 version (MIDR_EL1) It is also rewriting the base logic using Armv8 terminology (checking the EL rather than the mode as an example). Signed-off-by: Giacomo Travaglini Change-Id: I5cf09240206287cab877ea7ff6e46cf823aa8c35 Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70464 Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/isa.cc 1 file changed, 4 insertions(+), 5 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Richard Cooper: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 65d8b97..da23e0b 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -864,12 +864,11 @@ case MISCREG_ID_AFR0: // not implemented, so alias MIDR case MISCREG_REVIDR: // not implemented, so alias MIDR case MISCREG_MIDR: -cpsr = readMiscRegNoEffect(MISCREG_CPSR); -scr = readMiscRegNoEffect(MISCREG_SCR_EL3); -if ((cpsr.mode == MODE_HYP) || isSecure(tc)) { -return readMiscRegNoEffect(idx); -} else { + case MISCREG_MIDR_EL1: +if (currEL() == EL1 && EL2Enabled(tc)) { return readMiscRegNoEffect(MISCREG_VPIDR); +} else { +return readMiscRegNoEffect(idx); } break; case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70464?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I5cf09240206287cab877ea7ff6e46cf823aa8c35 Gerrit-Change-Number: 70464 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MIDR_EL1 to AArch32 version
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70461?usp=email ) Change subject: arch-arm: Map MIDR_EL1 to AArch32 version .. arch-arm: Map MIDR_EL1 to AArch32 version Signed-off-by: Giacomo Travaglini Change-Id: Id3ddc18ebfc296389bed6dc7615899bef83178ea Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70461 Reviewed-by: Jason Lowe-Power Tested-by: kokoro Maintainer: Jason Lowe-Power --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass Richard Cooper: Looks good to me, approved diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index b0a856e..65d8b97 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -334,7 +334,6 @@ midr = 0x410fc0f0; miscRegs[MISCREG_MIDR] = midr; -miscRegs[MISCREG_MIDR_EL1] = midr; miscRegs[MISCREG_VPIDR] = midr; miscRegs[MISCREG_ID_ISAR0] = p.id_isar0; diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 4221a15..000124c 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3507,7 +3507,8 @@ // AArch64 registers (Op0=1,3); InitReg(MISCREG_MIDR_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_MIDR); InitReg(MISCREG_MPIDR_EL1) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_REVIDR_EL1) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70461?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id3ddc18ebfc296389bed6dc7615899bef83178ea Gerrit-Change-Number: 70461 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move MISCREG init logic from ISA to reset field
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70465?usp=email ) Change subject: arch-arm: Move MISCREG init logic from ISA to reset field .. arch-arm: Move MISCREG init logic from ISA to reset field Rather than recomputing the reset value every time a system reset happens (and the ISA::clear method gets called), we calculate it once and construction time. We when simply apply the pre-computed reset value to the miscReg storage, as implemented by a previous patch [1] [1]: Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79 Signed-off-by: Giacomo Travaglini Change-Id: Iec4878217c38707be4ce7d4746ff95a208b4 Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70465 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 55 insertions(+), 62 deletions(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index da23e0b..a66a938 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -150,67 +150,6 @@ // AArch32 or AArch64 initID64(p); -// Start with an event in the mailbox -miscRegs[MISCREG_SEV_MAILBOX] = 1; - -// Separate Instruction and Data TLBs -miscRegs[MISCREG_TLBTR] = 1; - -MVFR0 mvfr0 = 0; -mvfr0.advSimdRegisters = 2; -mvfr0.singlePrecision = 2; -mvfr0.doublePrecision = 2; -mvfr0.vfpExceptionTrapping = 0; -mvfr0.divide = 1; -mvfr0.squareRoot = 1; -mvfr0.shortVectors = 1; -mvfr0.roundingModes = 1; -miscRegs[MISCREG_MVFR0] = mvfr0; - -MVFR1 mvfr1 = 0; -mvfr1.flushToZero = 1; -mvfr1.defaultNaN = 1; -mvfr1.advSimdLoadStore = 1; -mvfr1.advSimdInteger = 1; -mvfr1.advSimdSinglePrecision = 1; -mvfr1.advSimdHalfPrecision = 1; -mvfr1.vfpHalfPrecision = 1; -miscRegs[MISCREG_MVFR1] = mvfr1; - -// Reset values of PRRR and NMRR are implementation dependent - -// @todo: PRRR and NMRR in secure state? -miscRegs[MISCREG_PRRR_NS] = -(1 << 19) | // 19 -(0 << 18) | // 18 -(0 << 17) | // 17 -(1 << 16) | // 16 -(2 << 14) | // 15:14 -(0 << 12) | // 13:12 -(2 << 10) | // 11:10 -(2 << 8) | // 9:8 -(2 << 6) | // 7:6 -(2 << 4) | // 5:4 -(1 << 2) | // 3:2 -0; // 1:0 - -miscRegs[MISCREG_NMRR_NS] = -(1 << 30) | // 31:30 -(0 << 26) | // 27:26 -(0 << 24) | // 25:24 -(3 << 22) | // 23:22 -(2 << 20) | // 21:20 -(0 << 18) | // 19:18 -(0 << 16) | // 17:16 -(1 << 14) | // 15:14 -(0 << 12) | // 13:12 -(2 << 10) | // 11:10 -(0 << 8) | // 9:8 -(3 << 6) | // 7:6 -(2 << 4) | // 5:4 -(0 << 2) | // 3:2 -0; // 1:0 - if (FullSystem && system->highestELIs64()) { // Initialize AArch64 state clear64(p); diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index a31b6de..3b23a20 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, 2015-2022 Arm Limited + * Copyright (c) 2010-2013, 2015-2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -2155,8 +2155,31 @@ InitReg(MISCREG_FPSCR) .allPrivileges(); InitReg(MISCREG_MVFR1) + .reset([] () { +MVFR1 mvfr1 = 0; +mvfr1.flushToZero = 1; +mvfr1.defaultNaN = 1; +mvfr1.advSimdLoadStore = 1; +mvfr1.advSimdInteger = 1; +mvfr1.advSimdSinglePrecision = 1; +mvfr1.advSimdHalfPrecision = 1; +mvfr1.vfpHalfPrecision = 1; +return mvfr1; + }()) .allPrivileges(); InitReg(MISCREG_MVFR0) + .reset([] () { +MVFR0 mvfr0 = 0; +mvfr0.advSimdRegisters = 2; +mvfr0.singlePrecision = 2; +mvfr0.doublePrecision = 2; +mvfr0.vfpExceptionTrapping = 0; +mvfr0.divide = 1; +mvfr0.squareRoot = 1; +mvfr0.shortVectors = 1; +mvfr0.roundingModes = 1; +return mvfr0; + }()) .allPrivileges(); InitReg(MISCREG_FPEXC) .allPrivileges(); @@ -2197,6 +2220,7 @@ InitReg(MISCREG_PMXEVTYPER_PMCCFILTR) .mutex(); InitReg(MISCREG_SEV_MAILBOX) + .reset(1) // Start with an event in the mailbox .allPrivileges(); InitReg(MISCREG_TLBINEEDSYNC) .allPrivileges().ex
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MPIDR_EL1 to AArch32 version
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70462?usp=email ) Change subject: arch-arm: Map MPIDR_EL1 to AArch32 version .. arch-arm: Map MPIDR_EL1 to AArch32 version As of now the mapping is not actually needed: the MPIDR and MPIDR_EL1 registes are both read using the same helper (readMPIDR). In the future we could store the getMPIDR result in the AArch32 version without the need to re-calculate the fix affinity numbers Change-Id: Id42d1994cdd1722f07874ffa7364154cf011e00a Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70462 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/arm/regs/misc.cc 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 000124c..706716e 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3510,7 +3510,8 @@ .allPrivileges().exceptUserMode().writes(0) .mapsTo(MISCREG_MIDR); InitReg(MISCREG_MPIDR_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_MPIDR); InitReg(MISCREG_REVIDR_EL1) .faultRead(EL1, HCR_TRAP(tid1)) .allPrivileges().exceptUserMode().writes(0); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70462?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id42d1994cdd1722f07874ffa7364154cf011e00a Gerrit-Change-Number: 70462 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Generalize SCTLR_RST behaviour
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70459?usp=email ) Change subject: arch-arm: Generalize SCTLR_RST behaviour .. arch-arm: Generalize SCTLR_RST behaviour This is supposed to be employed as a reset value for SCTLR. Rather than implementing this misc reg specific feature, we provide a more general logic for changing the reset value of any register. Signed-off-by: Giacomo Travaglini Change-Id: Ib61019ec499b35382289fe18740c90eee5de4907 Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70459 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/regs/misc.cc M src/arch/arm/regs/misc.hh 4 files changed, 22 insertions(+), 16 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved kokoro: Regressions pass Richard Cooper: Looks good to me, approved diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 5a0dec5..b0a856e 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2022 Arm Limited + * Copyright (c) 2010-2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -91,8 +91,6 @@ _regClasses.push_back(&ccRegClass); _regClasses.push_back(&miscRegClass); -miscRegs[MISCREG_SCTLR_RST] = 0; - // Hook up a dummy device if we haven't been configured with a // real PMU. By using a dummy device, we don't need to check that // the PMU exist every time we try to access a PMU register. @@ -140,7 +138,6 @@ getMMUPtr(tc)->invalidateMiscReg(); } -SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; for (auto idx = 0; idx < NUM_MISCREGS; idx++) { miscRegs[idx] = lookUpMiscReg[idx].reset(); } @@ -221,11 +218,11 @@ } // Initialize AArch32 state... -clear32(p, sctlr_rst); +clear32(p); } void -ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst) +ISA::clear32(const ArmISAParams &p) { CPSR cpsr = 0; cpsr.mode = MODE_USER; @@ -238,9 +235,6 @@ updateRegMap(cpsr); SCTLR sctlr = 0; -sctlr.te = (bool) sctlr_rst.te; -sctlr.nmfi = (bool) sctlr_rst.nmfi; -sctlr.v = (bool) sctlr_rst.v; sctlr.u = 1; sctlr.xp = 1; sctlr.rao2 = 1; @@ -249,7 +243,6 @@ sctlr.uci = 1; sctlr.dze = 1; miscRegs[MISCREG_SCTLR_NS] = sctlr; -miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; miscRegs[MISCREG_HCPTR] = 0; miscRegs[MISCREG_CPACR] = 0; @@ -2084,6 +2077,20 @@ } } +RegVal +ISA::readMiscRegReset(RegIndex idx) const +{ +int flat_idx = flattenMiscIndex(idx); +return lookUpMiscReg[flat_idx].reset(); +} + +void +ISA::setMiscRegReset(RegIndex idx, RegVal val) +{ +int flat_idx = flattenMiscIndex(idx); +InitReg(flat_idx).reset(val); +} + BaseISADevice & ISA::getGenericTimer() { diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 512799f..5dd1b38 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2022 ARM Limited + * Copyright (c) 2010, 2012-2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -170,7 +170,7 @@ void clear() override; protected: -void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst); +void clear32(const ArmISAParams &p); void clear64(const ArmISAParams &p); void initID32(const ArmISAParams &p); void initID64(const ArmISAParams &p); @@ -201,6 +201,9 @@ void setMiscRegNoEffect(RegIndex idx, RegVal val) override; void setMiscReg(RegIndex, RegVal val) override; +RegVal readMiscRegReset(RegIndex) const; +void setMiscRegReset(RegIndex, RegVal val); + int flattenMiscIndex(int reg) const { diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 382b63e..e984164 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2196,8 +2196,6 @@ .bankedChild(); InitReg(MISCREG_PMXEVTYPER_PMCCFILTR) .mutex(); -InitReg(MISCREG_SCTLR_RST) - .allPrivileges(); InitReg(MISCREG_SEV_MAILBOX) .allPrivileges(); InitReg(MISCREG_TLBINEEDSYNC) diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index 69d1461..265a697 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -93,7 +93,6 @@ MISCREG_NMRR_MAIR1_NS, MISCREG_NMRR_MAIR1_S, MISCREG_PMXEVTYPER_PMCCFILTR, -MISCREG_SCTLR_RST, MISCREG_SEV_MAILBOX, MISCREG_TLBINEEDSYNC, @@ -17
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove clear32/64 methods
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70470?usp=email to review the following change. Change subject: arch-arm: Remove clear32/64 methods .. arch-arm: Remove clear32/64 methods Change-Id: I62d2dc0612298fdb4cdc3bf368e080c8ebebe23a Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/regs/misc.cc 3 files changed, 74 insertions(+), 111 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index d87e9c5..ffd9cfc 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -131,8 +131,6 @@ void ISA::clear() { -const Params &p(params()); - // Invalidate cached copies of miscregs in the TLBs if (tc) { getMMUPtr(tc)->invalidateMiscReg(); @@ -142,111 +140,7 @@ miscRegs[idx] = lookUpMiscReg[idx].reset(); } -if (FullSystem && system->highestELIs64()) { -// Initialize AArch64 state -clear64(p); -return; -} - -// Initialize AArch32 state... -clear32(p); -} - -void -ISA::clear32(const ArmISAParams &p) -{ -CPSR cpsr = 0; -cpsr.mode = MODE_USER; - -if (FullSystem) { -miscRegs[MISCREG_MVBAR] = system->resetAddr(); -} - -miscRegs[MISCREG_CPSR] = cpsr; -updateRegMap(cpsr); - -SCTLR sctlr = 0; -sctlr.u = 1; -sctlr.xp = 1; -sctlr.rao2 = 1; -sctlr.rao3 = 1; -sctlr.rao4 = 0xf; // SCTLR[6:3] -sctlr.uci = 1; -sctlr.dze = 1; -miscRegs[MISCREG_SCTLR_NS] = sctlr; -miscRegs[MISCREG_HCPTR] = 0; - -miscRegs[MISCREG_CPACR] = 0; - -miscRegs[MISCREG_FPSID] = p.fpsid; - -if (release->has(ArmExtension::LPAE)) { -TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; -ttbcr.eae = 0; -miscRegs[MISCREG_TTBCR_NS] = ttbcr; -// Enforce consistency with system-level settings -miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; -} - -if (release->has(ArmExtension::SECURITY)) { -miscRegs[MISCREG_SCTLR_S] = sctlr; -miscRegs[MISCREG_SCR] = 0; -miscRegs[MISCREG_VBAR_S] = 0; -} else { -// we're always non-secure -miscRegs[MISCREG_SCR] = 1; -} - -//XXX We need to initialize the rest of the state. -} - -void -ISA::clear64(const ArmISAParams &p) -{ -CPSR cpsr = 0; -Addr rvbar = system->resetAddr(); -switch (system->highestEL()) { -// Set initial EL to highest implemented EL using associated stack -// pointer (SP_ELx); set RVBAR_ELx to implementation defined reset -// value - case EL3: -cpsr.mode = MODE_EL3H; -miscRegs[MISCREG_RVBAR_EL3] = rvbar; -break; - case EL2: -cpsr.mode = MODE_EL2H; -miscRegs[MISCREG_RVBAR_EL2] = rvbar; -break; - case EL1: -cpsr.mode = MODE_EL1H; -miscRegs[MISCREG_RVBAR_EL1] = rvbar; -break; - default: -panic("Invalid highest implemented exception level"); -break; -} - -// Initialize rest of CPSR -cpsr.daif = 0xf; // Mask all interrupts -cpsr.ss = 0; -cpsr.il = 0; -miscRegs[MISCREG_CPSR] = cpsr; -updateRegMap(cpsr); - -// Initialize other control registers -miscRegs[MISCREG_MPIDR_EL1] = 0x8000; -if (release->has(ArmExtension::SECURITY)) { -miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; -miscRegs[MISCREG_SCR_EL3] = 0x0030; // RES1 fields -} else if (release->has(ArmExtension::VIRTUALIZATION)) { -// also MISCREG_SCTLR_EL2 (by mapping) -miscRegs[MISCREG_HSCTLR] = 0x30c50830; -} else { -// also MISCREG_SCTLR_EL1 (by mapping) -miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init -// Always non-secure -miscRegs[MISCREG_SCR_EL3] = 1; -} +updateRegMap(miscRegs[MISCREG_CPSR]); } void diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 55fbd03..8ed37ba 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -170,9 +170,6 @@ void clear() override; protected: -void clear32(const ArmISAParams &p); -void clear64(const ArmISAParams &p); - void addressTranslation(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val); void addressTranslation64(MMU::ArmTranslationType tran_type, diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 2995177..8edbadc 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2079,6 +2079,34 @@ return *this; } +static CPSR +resetCPSR(ArmSystem *system) +{ +CPSR cpsr = 0; +switch (system->highestE
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID64 using BitUnions
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70468?usp=email to review the following change. Change subject: arch-arm: Rewrite ISA::initID64 using BitUnions .. arch-arm: Rewrite ISA::initID64 using BitUnions Signed-off-by: Giacomo Travaglini Change-Id: I3e8c7bdcf86c01eccbd90fccaa2d4306a501ed13 Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc M src/arch/arm/regs/misc_types.hh 3 files changed, 74 insertions(+), 117 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 8424db5..cc4078a 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -261,21 +261,12 @@ // Initialize configurable id registers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1; miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1; -miscRegs[MISCREG_ID_AA64DFR0_EL1] = -(p.id_aa64dfr0_el1 & 0xf0ffULL) | -(p.pmu ? 0x0100ULL : 0); // Enable PMUv3 + +AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1; +dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3 +miscRegs[MISCREG_ID_AA64DFR0_EL1] = dfr0_el1; miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1; -miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p.id_aa64isar0_el1; -miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p.id_aa64isar1_el1; -miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p.id_aa64mmfr0_el1; -miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p.id_aa64mmfr1_el1; -miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p.id_aa64mmfr2_el1; - -miscRegs[MISCREG_ID_DFR0_EL1] = -(p.pmu ? 0x0300ULL : 0); // Enable PMUv3 - -miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; // SVE miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0 @@ -296,22 +287,25 @@ // [15]SMPS - We don't do priorities in gem5, so disable // [14:12] RES0 // [11:0] Affinity - we implement per-CPU SME, so set to 0 (no SMCU) -miscRegs[MISCREG_SMIDR_EL1] = 0 | // Affinity -0 << 15 | // SMPS -0x41 << 24; // Implementer +SMIDR smidr_el1 = 0; +smidr_el1.affinity = 0; +smidr_el1.smps = 0; +smidr_el1.implementer = 0x41; +miscRegs[MISCREG_SMIDR_EL1] = smidr_el1; -miscRegs[MISCREG_ID_AA64SMFR0_EL1] = 0; -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 32; // F32F32 +AA64SMFR0 smfr0_el1 = 0; +smfr0_el1.f32f32 = 0x1; // The following BF16F32 is actually not implemented due to a lack // of BF16 support in gem5's fplib. However, as per the SME spec the // _only_ allowed value is 0x1. -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 34; // BF16F32 -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 35; // F16F32 -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0xFUL << 36; // I8I32 -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 48; // F64F64 -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0xFUL << 52; // I16I64 -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x0UL << 56; // SMEver -miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 32; // FA64 +smfr0_el1.b16f32 = 0x1; +smfr0_el1.f16f32 = 0x1; +smfr0_el1.i8i32 = 0xF; +smfr0_el1.f64f64 = 0x1; +smfr0_el1.i16i64 = 0xF; +smfr0_el1.smEver = 0; +smfr0_el1.fa64 = 0x1; +miscRegs[MISCREG_ID_AA64SMFR0_EL1] = smfr0_el1; // We want to support FEAT_SME_FA64. Therefore, we enable it in all // SMCR_ELx registers by default. Runtime software might change this @@ -330,103 +324,53 @@ miscRegs[MISCREG_SMCR_EL1] |= ((smeVL - 1) & 0xF); } -// Enforce consistency with system-level settings... +AA64PFR0 pfr0_el1 = 0; +pfr0_el1.el3 = release->has(ArmExtension::SECURITY) ? 0x2 : 0x0; +pfr0_el1.el2 = release->has(ArmExtension::VIRTUALIZATION) ? 0x2 : 0x0; +pfr0_el1.sve = release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0; +pfr0_el1.sel2 = release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0; +miscRegs[MISCREG_ID_AA64PFR0_EL1] = pfr0_el1; -// EL3 -miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( -miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, -release->has(ArmExtension::SECURITY) ? 0x2 : 0x0); -// EL2 -miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( -miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, -release->has(ArmExtension::VIRTUALIZATION) ? 0x2 : 0x0); -// SVE -miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( -miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32, -release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0); -// SME -miscRegs[MISCREG_ID_AA64PFR1_EL1] = insertBits( -miscRegs[MISCREG_ID_AA64PFR1_EL1], 27, 24, -release->has(ArmExtension::FEAT_SME) ? 0x1 : 0x0); -// Sec
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: VMPIDR_EL2 can be used in secure mode as well
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70471?usp=email to review the following change. Change subject: arch-arm: VMPIDR_EL2 can be used in secure mode as well .. arch-arm: VMPIDR_EL2 can be used in secure mode as well This was some old code still assuming EL2 is not implemented in secure mode. This is wrong since the introduction of FEAT_SEL2 in gem5 Change-Id: Ie7e112a83e64f33a98885e88504c2d6bc5070218 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/utility.cc 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 6764569..05d1cab 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -139,8 +139,6 @@ { const ExceptionLevel current_el = currEL(tc); -const bool is_secure = isSecureBelowEL3(tc); - switch (current_el) { case EL0: // Note: in MsrMrs instruction we read the register value before @@ -150,7 +148,7 @@ warn_once("Trying to read MPIDR at EL0\n"); [[fallthrough]]; case EL1: -if (ArmSystem::haveEL(tc, EL2) && !is_secure) +if (EL2Enabled(tc)) return tc->readMiscReg(MISCREG_VMPIDR_EL2); else return getMPIDR(arm_sys, tc); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70471?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ie7e112a83e64f33a98885e88504c2d6bc5070218 Gerrit-Change-Number: 70471 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID64
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70469?usp=email to review the following change. Change subject: arch-arm: Remove ISA::initID64 .. arch-arm: Remove ISA::initID64 Signed-off-by: Giacomo Travaglini Change-Id: I3d03ee15df46fa7d9a9ec439b26e99baf33cbb5e Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/regs/misc.cc 3 files changed, 123 insertions(+), 125 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index cc4078a..d87e9c5 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -142,12 +142,6 @@ miscRegs[idx] = lookUpMiscReg[idx].reset(); } -// We always initialize AArch64 ID registers even -// if we are in AArch32. This is done since if we -// are in SE mode we don't know if our ArmProcess is -// AArch32 or AArch64 -initID64(p); - if (FullSystem && system->highestELIs64()) { // Initialize AArch64 state clear64(p); @@ -256,124 +250,6 @@ } void -ISA::initID64(const ArmISAParams &p) -{ -// Initialize configurable id registers -miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1; -miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1; - -AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1; -dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3 -miscRegs[MISCREG_ID_AA64DFR0_EL1] = dfr0_el1; - -miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1; - -// SVE -miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0 -if (release->has(ArmExtension::SECURITY)) { -miscRegs[MISCREG_ZCR_EL3] = sveVL - 1; -} else if (release->has(ArmExtension::VIRTUALIZATION)) { -miscRegs[MISCREG_ZCR_EL2] = sveVL - 1; -} else { -miscRegs[MISCREG_ZCR_EL1] = sveVL - 1; -} - -// SME - -// Set up the SME SMIDR -// [63:32] RES0 -// [31:24] Implementer - default this to Arm Limited -// [23:16] SMCU Revision - set to 0 as we don't model an SMCU -// [15]SMPS - We don't do priorities in gem5, so disable -// [14:12] RES0 -// [11:0] Affinity - we implement per-CPU SME, so set to 0 (no SMCU) -SMIDR smidr_el1 = 0; -smidr_el1.affinity = 0; -smidr_el1.smps = 0; -smidr_el1.implementer = 0x41; -miscRegs[MISCREG_SMIDR_EL1] = smidr_el1; - -AA64SMFR0 smfr0_el1 = 0; -smfr0_el1.f32f32 = 0x1; -// The following BF16F32 is actually not implemented due to a lack -// of BF16 support in gem5's fplib. However, as per the SME spec the -// _only_ allowed value is 0x1. -smfr0_el1.b16f32 = 0x1; -smfr0_el1.f16f32 = 0x1; -smfr0_el1.i8i32 = 0xF; -smfr0_el1.f64f64 = 0x1; -smfr0_el1.i16i64 = 0xF; -smfr0_el1.smEver = 0; -smfr0_el1.fa64 = 0x1; -miscRegs[MISCREG_ID_AA64SMFR0_EL1] = smfr0_el1; - -// We want to support FEAT_SME_FA64. Therefore, we enable it in all -// SMCR_ELx registers by default. Runtime software might change this -// later, but given that gem5 doesn't disable instructions based on -// this flag we default to the most representative value. -miscRegs[MISCREG_SMCR_EL3] = 0x1 << 31; -miscRegs[MISCREG_SMCR_EL2] = 0x1 << 31; -miscRegs[MISCREG_SMCR_EL1] = 0x1 << 31; - -// Set the vector default vector length -if (release->has(ArmExtension::SECURITY)) { -miscRegs[MISCREG_SMCR_EL3] |= ((smeVL - 1) & 0xF); -} else if (release->has(ArmExtension::VIRTUALIZATION)) { -miscRegs[MISCREG_SMCR_EL2] |= ((smeVL - 1) & 0xF); -} else { -miscRegs[MISCREG_SMCR_EL1] |= ((smeVL - 1) & 0xF); -} - -AA64PFR0 pfr0_el1 = 0; -pfr0_el1.el3 = release->has(ArmExtension::SECURITY) ? 0x2 : 0x0; -pfr0_el1.el2 = release->has(ArmExtension::VIRTUALIZATION) ? 0x2 : 0x0; -pfr0_el1.sve = release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0; -pfr0_el1.sel2 = release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0; -miscRegs[MISCREG_ID_AA64PFR0_EL1] = pfr0_el1; - -AA64MMFR0 mmfr0_el1 = p.id_aa64mmfr0_el1; -mmfr0_el1.asidbits = haveLargeAsid64 ? 0x2 : 0x0; -mmfr0_el1.parange = encodePhysAddrRange64(physAddrRange); -miscRegs[MISCREG_ID_AA64MMFR0_EL1] = mmfr0_el1; - -AA64ISAR0 isar0_el1 = p.id_aa64isar0_el1; -if (release->has(ArmExtension::CRYPTO)) { -isar0_el1.crc32 = 1; -isar0_el1.sha2 = 1; -isar0_el1.sha1 = 1; -isar0_el1.aes = 2; -} else { -isar0_el1.crc32 = 0; -isar0_el1.sha2 = 0; -isar0_el1.sha1 = 0; -isar0_el1.aes = 0; -} -isar0_el1.atomic = release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0; -isar0_el1.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0; -isar0_el1.tme = release->has(
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID32
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70467?usp=email to review the following change. Change subject: arch-arm: Remove ISA::initID32 .. arch-arm: Remove ISA::initID32 Signed-off-by: Giacomo Travaglini Change-Id: I70cce0b9d99ed5fe146e64c6ee55fa8cedf98ac6 Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/regs/misc.cc 3 files changed, 46 insertions(+), 54 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 4033d0f..8424db5 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -142,8 +142,6 @@ miscRegs[idx] = lookUpMiscReg[idx].reset(); } -initID32(p); - // We always initialize AArch64 ID registers even // if we are in AArch32. This is done since if we // are in SE mode we don't know if our ArmProcess is @@ -258,57 +256,6 @@ } void -ISA::initID32(const ArmISAParams &p) -{ -// Initialize configurable default values - -uint32_t midr; -if (p.midr != 0x0) -midr = p.midr; -else if (highestELIs64) -// Cortex-A57 TRM r0p0 MIDR -midr = 0x410fd070; -else -// Cortex-A15 TRM r0p0 MIDR -midr = 0x410fc0f0; - -miscRegs[MISCREG_MIDR] = midr; -miscRegs[MISCREG_VPIDR] = midr; - -miscRegs[MISCREG_ID_ISAR0] = p.id_isar0; -miscRegs[MISCREG_ID_ISAR1] = p.id_isar1; -miscRegs[MISCREG_ID_ISAR2] = p.id_isar2; -miscRegs[MISCREG_ID_ISAR3] = p.id_isar3; -miscRegs[MISCREG_ID_ISAR4] = p.id_isar4; - -miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0; -miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1; -miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2; -miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3; -miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4; - -ISAR5 isar5 = p.id_isar5; -if (release->has(ArmExtension::CRYPTO)) { -isar5.crc32 = 1; -isar5.sha2 = 1; -isar5.sha1 = 1; -isar5.aes = 2; -} else { -isar5.crc32 = 0; -isar5.sha2 = 0; -isar5.sha1 = 0; -isar5.aes = 0; -} -isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0; -isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0; -miscRegs[MISCREG_ID_ISAR5] = isar5; - -ISAR6 isar6 = p.id_isar6; -isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0; -miscRegs[MISCREG_ID_ISAR6] = isar6; -} - -void ISA::initID64(const ArmISAParams &p) { // Initialize configurable id registers diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 5dd1b38..8419641 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -172,7 +172,6 @@ protected: void clear32(const ArmISAParams &p); void clear64(const ArmISAParams &p); -void initID32(const ArmISAParams &p); void initID64(const ArmISAParams &p); void addressTranslation(MMU::ArmTranslationType tran_type, diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 3b23a20..f5e2502 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -45,6 +45,7 @@ #include "cpu/thread_context.hh" #include "dev/arm/gic_v3_cpu_interface.hh" #include "sim/full_system.hh" +#include "params/ArmISA.hh" namespace gem5 { @@ -2116,6 +2117,17 @@ const bool vhe_implemented = release->has(ArmExtension::FEAT_VHE); const bool sel2_implemented = release->has(ArmExtension::FEAT_SEL2); +const Params &p(params()); + +uint32_t midr; +if (p.midr != 0x0) +midr = p.midr; +else if (highestELIs64) +// Cortex-A57 TRM r0p0 MIDR +midr = 0x410fd070; +else +// Cortex-A15 TRM r0p0 MIDR +midr = 0x410fc0f0; /** * Some registers alias with others, and therefore need to be translated. @@ -2465,6 +2477,7 @@ // AArch32 CP15 registers InitReg(MISCREG_MIDR) + .reset(midr) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_CTR) .allPrivileges().exceptUserMode().writes(0); @@ -2488,28 +2501,60 @@ InitReg(MISCREG_ID_AFR0) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR0) + .reset(p.id_mmfr0) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR1) + .reset(p.id_mmfr1) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR2) + .reset(p.id_mmfr2) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR3) + .reset(p.id_mmfr3) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR4) + .reset(p.id_mmfr4) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_ISAR0) + .reset(p.id_isar0)
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MIDR_EL1 to AArch32 version
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70461?usp=email to review the following change. Change subject: arch-arm: Map MIDR_EL1 to AArch32 version .. arch-arm: Map MIDR_EL1 to AArch32 version Signed-off-by: Giacomo Travaglini Change-Id: Id3ddc18ebfc296389bed6dc7615899bef83178ea Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index b0a856e..65d8b97 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -334,7 +334,6 @@ midr = 0x410fc0f0; miscRegs[MISCREG_MIDR] = midr; -miscRegs[MISCREG_MIDR_EL1] = midr; miscRegs[MISCREG_VPIDR] = midr; miscRegs[MISCREG_ID_ISAR0] = p.id_isar0; diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 4221a15..000124c 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3507,7 +3507,8 @@ // AArch64 registers (Op0=1,3); InitReg(MISCREG_MIDR_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_MIDR); InitReg(MISCREG_MPIDR_EL1) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_REVIDR_EL1) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70461?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id3ddc18ebfc296389bed6dc7615899bef83178ea Gerrit-Change-Number: 70461 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix read redirection for MIDR register
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70464?usp=email to review the following change. Change subject: arch-arm: Fix read redirection for MIDR register .. arch-arm: Fix read redirection for MIDR register This patch is fixing read redirection for the MIDR register in the following ways: 1) Is allowing a virtualization of the register (via VPIDR) even in secure mode (available with FEAT_SEL2) 2) Is extending this logic to the AArch64 version (MIDR_EL1) It is also rewriting the base logic using Armv8 terminology (checking the EL rather than the mode as an example). Signed-off-by: Giacomo Travaglini Change-Id: I5cf09240206287cab877ea7ff6e46cf823aa8c35 Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 65d8b97..da23e0b 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -864,12 +864,11 @@ case MISCREG_ID_AFR0: // not implemented, so alias MIDR case MISCREG_REVIDR: // not implemented, so alias MIDR case MISCREG_MIDR: -cpsr = readMiscRegNoEffect(MISCREG_CPSR); -scr = readMiscRegNoEffect(MISCREG_SCR_EL3); -if ((cpsr.mode == MODE_HYP) || isSecure(tc)) { -return readMiscRegNoEffect(idx); -} else { + case MISCREG_MIDR_EL1: +if (currEL() == EL1 && EL2Enabled(tc)) { return readMiscRegNoEffect(MISCREG_VPIDR); +} else { +return readMiscRegNoEffect(idx); } break; case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70464?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I5cf09240206287cab877ea7ff6e46cf823aa8c35 Gerrit-Change-Number: 70464 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move MISCREG init logic from ISA to reset field
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70465?usp=email to review the following change. Change subject: arch-arm: Move MISCREG init logic from ISA to reset field .. arch-arm: Move MISCREG init logic from ISA to reset field Rather than recomputing the reset value every time a system reset happens (and the ISA::clear method gets called), we calculate it once and construction time. We when simply apply the pre-computed reset value to the miscReg storage, as implemented by a previous patch [1] [1]: Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79 Signed-off-by: Giacomo Travaglini Change-Id: Iec4878217c38707be4ce7d4746ff95a208b4 Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 55 insertions(+), 62 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index da23e0b..a66a938 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -150,67 +150,6 @@ // AArch32 or AArch64 initID64(p); -// Start with an event in the mailbox -miscRegs[MISCREG_SEV_MAILBOX] = 1; - -// Separate Instruction and Data TLBs -miscRegs[MISCREG_TLBTR] = 1; - -MVFR0 mvfr0 = 0; -mvfr0.advSimdRegisters = 2; -mvfr0.singlePrecision = 2; -mvfr0.doublePrecision = 2; -mvfr0.vfpExceptionTrapping = 0; -mvfr0.divide = 1; -mvfr0.squareRoot = 1; -mvfr0.shortVectors = 1; -mvfr0.roundingModes = 1; -miscRegs[MISCREG_MVFR0] = mvfr0; - -MVFR1 mvfr1 = 0; -mvfr1.flushToZero = 1; -mvfr1.defaultNaN = 1; -mvfr1.advSimdLoadStore = 1; -mvfr1.advSimdInteger = 1; -mvfr1.advSimdSinglePrecision = 1; -mvfr1.advSimdHalfPrecision = 1; -mvfr1.vfpHalfPrecision = 1; -miscRegs[MISCREG_MVFR1] = mvfr1; - -// Reset values of PRRR and NMRR are implementation dependent - -// @todo: PRRR and NMRR in secure state? -miscRegs[MISCREG_PRRR_NS] = -(1 << 19) | // 19 -(0 << 18) | // 18 -(0 << 17) | // 17 -(1 << 16) | // 16 -(2 << 14) | // 15:14 -(0 << 12) | // 13:12 -(2 << 10) | // 11:10 -(2 << 8) | // 9:8 -(2 << 6) | // 7:6 -(2 << 4) | // 5:4 -(1 << 2) | // 3:2 -0; // 1:0 - -miscRegs[MISCREG_NMRR_NS] = -(1 << 30) | // 31:30 -(0 << 26) | // 27:26 -(0 << 24) | // 25:24 -(3 << 22) | // 23:22 -(2 << 20) | // 21:20 -(0 << 18) | // 19:18 -(0 << 16) | // 17:16 -(1 << 14) | // 15:14 -(0 << 12) | // 13:12 -(2 << 10) | // 11:10 -(0 << 8) | // 9:8 -(3 << 6) | // 7:6 -(2 << 4) | // 5:4 -(0 << 2) | // 3:2 -0; // 1:0 - if (FullSystem && system->highestELIs64()) { // Initialize AArch64 state clear64(p); diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index a31b6de..3b23a20 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, 2015-2022 Arm Limited + * Copyright (c) 2010-2013, 2015-2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -2155,8 +2155,31 @@ InitReg(MISCREG_FPSCR) .allPrivileges(); InitReg(MISCREG_MVFR1) + .reset([] () { +MVFR1 mvfr1 = 0; +mvfr1.flushToZero = 1; +mvfr1.defaultNaN = 1; +mvfr1.advSimdLoadStore = 1; +mvfr1.advSimdInteger = 1; +mvfr1.advSimdSinglePrecision = 1; +mvfr1.advSimdHalfPrecision = 1; +mvfr1.vfpHalfPrecision = 1; +return mvfr1; + }()) .allPrivileges(); InitReg(MISCREG_MVFR0) + .reset([] () { +MVFR0 mvfr0 = 0; +mvfr0.advSimdRegisters = 2; +mvfr0.singlePrecision = 2; +mvfr0.doublePrecision = 2; +mvfr0.vfpExceptionTrapping = 0; +mvfr0.divide = 1; +mvfr0.squareRoot = 1; +mvfr0.shortVectors = 1; +mvfr0.roundingModes = 1; +return mvfr0; + }()) .allPrivileges(); InitReg(MISCREG_FPEXC) .allPrivileges(); @@ -2197,6 +2220,7 @@ InitReg(MISCREG_PMXEVTYPER_PMCCFILTR) .mutex(); InitReg(MISCREG_SEV_MAILBOX) + .reset(1) // Start with an event in the mailbox .allPrivileges(); InitReg(MISCREG_TLBINEEDSYNC) .allPrivileges().exceptUserMode(); @@ -2447,6 +2471,7 @@ InitReg(MISCREG_TCMTR) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_TLBTR) + .reset(1) // Separate Instruction and Data TLBs .allPrivileg
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MPIDR_EL1 to AArch32 version
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70462?usp=email to review the following change. Change subject: arch-arm: Map MPIDR_EL1 to AArch32 version .. arch-arm: Map MPIDR_EL1 to AArch32 version As of now the mapping is not actually needed: the MPIDR and MPIDR_EL1 registes are both read using the same helper (readMPIDR). In the future we could store the getMPIDR result in the AArch32 version without the need to re-calculate the fix affinity numbers Change-Id: Id42d1994cdd1722f07874ffa7364154cf011e00a Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/regs/misc.cc 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 000124c..706716e 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3510,7 +3510,8 @@ .allPrivileges().exceptUserMode().writes(0) .mapsTo(MISCREG_MIDR); InitReg(MISCREG_MPIDR_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_MPIDR); InitReg(MISCREG_REVIDR_EL1) .faultRead(EL1, HCR_TRAP(tid1)) .allPrivileges().exceptUserMode().writes(0); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70462?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id42d1994cdd1722f07874ffa7364154cf011e00a Gerrit-Change-Number: 70462 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70460?usp=email to review the following change. Change subject: arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version .. arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version Signed-off-by: Giacomo Travaglini Change-Id: I28753de7b437be58e5ac891ac2e549bbab6b53b0 Reviewed-by: Richard Cooper --- M src/arch/arm/regs/misc.cc 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index e984164..4221a15 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3579,10 +3579,12 @@ .mapsTo(MISCREG_ID_ISAR6); InitReg(MISCREG_MVFR0_EL1) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_MVFR0); InitReg(MISCREG_MVFR1_EL1) .faultRead(EL1, HCR_TRAP(tid3)) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_MVFR1); InitReg(MISCREG_MVFR2_EL1) .faultRead(EL1, HCR_TRAP(tid3)) .allPrivileges().exceptUserMode().writes(0); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70460?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I28753de7b437be58e5ac891ac2e549bbab6b53b0 Gerrit-Change-Number: 70460 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map CTR_EL0 to AArch32 version
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70463?usp=email to review the following change. Change subject: arch-arm: Map CTR_EL0 to AArch32 version .. arch-arm: Map CTR_EL0 to AArch32 version Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M src/arch/arm/regs/misc.cc 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 706716e..a31b6de 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3681,7 +3681,8 @@ InitReg(MISCREG_CTR_EL0) .faultRead(EL0, faultCtrEL0) .faultRead(EL1, HCR_TRAP(tid2)) - .reads(1); + .reads(1) + .mapsTo(MISCREG_CTR); InitReg(MISCREG_DCZID_EL0) .reads(1); InitReg(MISCREG_VPIDR_EL2) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70463?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8 Gerrit-Change-Number: 70463 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Generalize SCTLR_RST behaviour
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70459?usp=email to review the following change. Change subject: arch-arm: Generalize SCTLR_RST behaviour .. arch-arm: Generalize SCTLR_RST behaviour This is supposed to be employed as a reset value for SCTLR. Rather than implementing this misc reg specific feature, we provide a more general logic for changing the reset value of any register. Signed-off-by: Giacomo Travaglini Change-Id: Ib61019ec499b35382289fe18740c90eee5de4907 Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/regs/misc.cc M src/arch/arm/regs/misc.hh 4 files changed, 22 insertions(+), 16 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 5a0dec5..b0a856e 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2022 Arm Limited + * Copyright (c) 2010-2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -91,8 +91,6 @@ _regClasses.push_back(&ccRegClass); _regClasses.push_back(&miscRegClass); -miscRegs[MISCREG_SCTLR_RST] = 0; - // Hook up a dummy device if we haven't been configured with a // real PMU. By using a dummy device, we don't need to check that // the PMU exist every time we try to access a PMU register. @@ -140,7 +138,6 @@ getMMUPtr(tc)->invalidateMiscReg(); } -SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; for (auto idx = 0; idx < NUM_MISCREGS; idx++) { miscRegs[idx] = lookUpMiscReg[idx].reset(); } @@ -221,11 +218,11 @@ } // Initialize AArch32 state... -clear32(p, sctlr_rst); +clear32(p); } void -ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst) +ISA::clear32(const ArmISAParams &p) { CPSR cpsr = 0; cpsr.mode = MODE_USER; @@ -238,9 +235,6 @@ updateRegMap(cpsr); SCTLR sctlr = 0; -sctlr.te = (bool) sctlr_rst.te; -sctlr.nmfi = (bool) sctlr_rst.nmfi; -sctlr.v = (bool) sctlr_rst.v; sctlr.u = 1; sctlr.xp = 1; sctlr.rao2 = 1; @@ -249,7 +243,6 @@ sctlr.uci = 1; sctlr.dze = 1; miscRegs[MISCREG_SCTLR_NS] = sctlr; -miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; miscRegs[MISCREG_HCPTR] = 0; miscRegs[MISCREG_CPACR] = 0; @@ -2084,6 +2077,20 @@ } } +RegVal +ISA::readMiscRegReset(RegIndex idx) const +{ +int flat_idx = flattenMiscIndex(idx); +return lookUpMiscReg[flat_idx].reset(); +} + +void +ISA::setMiscRegReset(RegIndex idx, RegVal val) +{ +int flat_idx = flattenMiscIndex(idx); +InitReg(flat_idx).reset(val); +} + BaseISADevice & ISA::getGenericTimer() { diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 512799f..5dd1b38 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2022 ARM Limited + * Copyright (c) 2010, 2012-2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -170,7 +170,7 @@ void clear() override; protected: -void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst); +void clear32(const ArmISAParams &p); void clear64(const ArmISAParams &p); void initID32(const ArmISAParams &p); void initID64(const ArmISAParams &p); @@ -201,6 +201,9 @@ void setMiscRegNoEffect(RegIndex idx, RegVal val) override; void setMiscReg(RegIndex, RegVal val) override; +RegVal readMiscRegReset(RegIndex) const; +void setMiscRegReset(RegIndex, RegVal val); + int flattenMiscIndex(int reg) const { diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 382b63e..e984164 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2196,8 +2196,6 @@ .bankedChild(); InitReg(MISCREG_PMXEVTYPER_PMCCFILTR) .mutex(); -InitReg(MISCREG_SCTLR_RST) - .allPrivileges(); InitReg(MISCREG_SEV_MAILBOX) .allPrivileges(); InitReg(MISCREG_TLBINEEDSYNC) diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index 69d1461..265a697 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -93,7 +93,6 @@ MISCREG_NMRR_MAIR1_NS, MISCREG_NMRR_MAIR1_S, MISCREG_PMXEVTYPER_PMCCFILTR, -MISCREG_SCTLR_RST, MISCREG_SEV_MAILBOX, MISCREG_TLBINEEDSYNC, @@ -1752,7 +1751,6 @@ "nmrr_mair1_ns", "nmrr_mair1_s", "pmxevtyper_pmccfiltr", -"sctlr_rst", "sev_mailbox", "tlbi_needsync", -- To vi
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID32 using BitUnions
Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70466?usp=email to review the following change. Change subject: arch-arm: Rewrite ISA::initID32 using BitUnions .. arch-arm: Rewrite ISA::initID32 using BitUnions Signed-off-by: Giacomo Travaglini Change-Id: I38460766bb5ed363b176bc6faca8e770a8a5e4c6 Reviewed-by: Richard Cooper --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc_types.hh 2 files changed, 39 insertions(+), 19 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index a66a938..4033d0f 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -280,8 +280,6 @@ miscRegs[MISCREG_ID_ISAR2] = p.id_isar2; miscRegs[MISCREG_ID_ISAR3] = p.id_isar3; miscRegs[MISCREG_ID_ISAR4] = p.id_isar4; -miscRegs[MISCREG_ID_ISAR5] = p.id_isar5; -miscRegs[MISCREG_ID_ISAR6] = p.id_isar6; miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0; miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1; @@ -289,24 +287,25 @@ miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3; miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4; -/** MISCREG_ID_ISAR5 */ -// Crypto -miscRegs[MISCREG_ID_ISAR5] = insertBits( -miscRegs[MISCREG_ID_ISAR5], 19, 4, -release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0); -// RDM -miscRegs[MISCREG_ID_ISAR5] = insertBits( -miscRegs[MISCREG_ID_ISAR5], 27, 24, -release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0); -// FCMA -miscRegs[MISCREG_ID_ISAR5] = insertBits( -miscRegs[MISCREG_ID_ISAR5], 31, 28, -release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0); +ISAR5 isar5 = p.id_isar5; +if (release->has(ArmExtension::CRYPTO)) { +isar5.crc32 = 1; +isar5.sha2 = 1; +isar5.sha1 = 1; +isar5.aes = 2; +} else { +isar5.crc32 = 0; +isar5.sha2 = 0; +isar5.sha1 = 0; +isar5.aes = 0; +} +isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0; +isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0; +miscRegs[MISCREG_ID_ISAR5] = isar5; -/** ID_ISAR6 */ -miscRegs[MISCREG_ID_ISAR6] = insertBits( -miscRegs[MISCREG_ID_ISAR6], 3, 0, -release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0); +ISAR6 isar6 = p.id_isar6; +isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0; +miscRegs[MISCREG_ID_ISAR6] = isar6; } void diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index 0fe5a00..9af5337 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -75,6 +75,27 @@ Bitfield<0> sp; // AArch64 EndBitUnion(CPSR) +BitUnion32(ISAR5) +Bitfield<31, 28> vcma; +Bitfield<27, 24> rdm; +Bitfield<19, 16> crc32; +Bitfield<15, 12> sha2; +Bitfield<11, 8> sha1; +Bitfield<7, 4> aes; +Bitfield<3, 0> sevl; +EndBitUnion(ISAR5) + +BitUnion32(ISAR6) +Bitfield<31, 28> clrbhb; +Bitfield<27, 24> i8mm; +Bitfield<23, 20> bf16; +Bitfield<19, 16> specres; +Bitfield<15, 12> sb; +Bitfield<11, 8> fhm; +Bitfield<7, 4> dp; +Bitfield<3, 0> jscvt; +EndBitUnion(ISAR6) + BitUnion64(AA64DFR0) Bitfield<43, 40> tracefilt; Bitfield<39, 36> doublelock; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70466?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I38460766bb5ed363b176bc6faca8e770a8a5e4c6 Gerrit-Change-Number: 70466 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org