[gem5-dev] [L] Change in gem5/gem5[develop]: stdlib: Add a prebuilt MESI_Three_Level cache

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71598?usp=email )


Change subject: stdlib: Add a prebuilt MESI_Three_Level cache
..

stdlib: Add a prebuilt MESI_Three_Level cache

The cache is modeled after an AMD EPYC cache, but not exactly
like AMD EPYC cache.
- K cores per core complex (CCD), each core has one private split L1,
and one private L2.
- K cores in the same CCD share 1 slice of L3 cache, which is not
a victim cache.
- There can be multiple CCDs, which communicate with each other via
Cross-CCD router. The Cross-CCD rounter is also connected to
directory controllers and dma controllers.
- All links latency are set to 1.

Change-Id: Ib64248bed9155b8e48e5158ffdeebf1f2d770754
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71598
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/python/SConscript
A  
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/__init__.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/core_complex.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi_network.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/ruby_network_components.py

6 files changed, 717 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/SConscript b/src/python/SConscript
index f98b570..ea9d3d4 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -154,6 +154,18 @@
 PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
 'gem5/components/cachehierarchies/ruby/caches/mesi_three_level/'
 'l3_cache.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
+'octopi.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
+'core_complex.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
+'octopi_network.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
+'ruby_network_components.py')
 PySource('gem5.components.cachehierarchies.ruby.caches.mi_example',
 'gem5/components/cachehierarchies/ruby/caches/mi_example/__init__.py')
 PySource('gem5.components.cachehierarchies.ruby.caches.mi_example',
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/__init__.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/__init__.py

new file mode 100644
index 000..b08f46b
--- /dev/null
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/__init__.py

@@ -0,0 +1,25 @@
+# Copyright (c) 2022-2023 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/core_complex.py  

[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Add example configuration for OctopiCache

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71618?usp=email )


Change subject: configs: Add example configuration for OctopiCache
..

configs: Add example configuration for OctopiCache

Change-Id: Ia78dd63e63808ebad40052d2a7cdb67cc7179e44
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71618
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
A configs/example/gem5_library/caches/octopi-cache-example.py
1 file changed, 100 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/caches/octopi-cache-example.py  
b/configs/example/gem5_library/caches/octopi-cache-example.py

new file mode 100644
index 000..1b39a8b
--- /dev/null
+++ b/configs/example/gem5_library/caches/octopi-cache-example.py
@@ -0,0 +1,100 @@
+# Copyright (c) 2023 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This script boots Ubuntu 20.04 with 8 timing cores in 1 CCD.
+
+Usage
+-
+
+```
+scons build/ARM_MESI_Three_Level/gem5.opt -j `nproc`
+./build/ARM_MESI_Three_Level/gem5.opt \
+configs/example/gem5_library/caches/octopi-cache-example.py
+```
+"""
+
+
+from m5.objects import ArmDefaultRelease, VExpress_GEM5_Foundation
+
+from gem5.utils.requires import requires
+from gem5.components.boards.arm_board import ArmBoard
+from gem5.components.memory import DualChannelDDR4_2400
+from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.octopi  
import (

+OctopiCache,
+)
+from gem5.isas import ISA
+from gem5.coherence_protocol import CoherenceProtocol
+from gem5.simulate.simulator import Simulator
+from gem5.resources.workload import Workload
+
+num_ccds = 1  # CCDs
+num_cores_per_ccd = 8  # 8 cores/CCD
+
+# OctopiCache is built on top of gem5's MESI_Three_Level cache coherence
+# protocol
+requires(coherence_protocol_required=CoherenceProtocol.MESI_THREE_LEVEL)
+cache_hierarchy = OctopiCache(
+l1i_size="32KiB",
+l1i_assoc=8,
+l1d_size="32KiB",
+l1d_assoc=8,
+l2_size="512KiB",
+l2_assoc=8,
+l3_size="32MiB",
+l3_assoc=16,
+num_core_complexes=num_ccds,
+is_fullsystem=True,
+)
+
+memory = DualChannelDDR4_2400(size="16GB")
+
+# The number of cores must be consistent with
+# num_core_complexes and num_cores_per_core_complexes
+processor = SimpleProcessor(
+cpu_type=CPUTypes.TIMING,
+isa=ISA.ARM,
+num_cores=num_ccds * num_cores_per_ccd,
+)
+
+release = ArmDefaultRelease()
+platform = VExpress_GEM5_Foundation()
+
+board = ArmBoard(
+clk_freq="4GHz",
+processor=processor,
+memory=memory,
+cache_hierarchy=cache_hierarchy,
+release=release,
+platform=platform,
+)
+
+board.set_workload(Workload("arm64-ubuntu-20.04-boot"))
+
+simulator = Simulator(board=board)
+simulator.run()

--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia78dd63e63808ebad40052d2a7cdb67cc7179e44

[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Add OctopiCache to long tests

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71619?usp=email )



Change subject: tests: Add OctopiCache to long tests
..

tests: Add OctopiCache to long tests

Change-Id: I40c948023a28f9bf4dde4de214bdd68894050317
Signed-off-by: Hoa Nguyen 
---
M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
1 file changed, 19 insertions(+), 0 deletions(-)



diff --git  
a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py  
b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py

index e43d461..aa8be15 100644
--- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
+++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
@@ -292,6 +292,25 @@
 )

 gem5_verify_config(
+name="test-gem5-library-example-octopi-cache-test",
+fixtures=(),
+verifiers=(),
+config=joinpath(
+config.base_dir,
+"configs",
+"example",
+"gem5_library",
+"caches",
+"octopi-cache-example.py",
+),
+config_args=[],
+protocol="MESI_Three_Level",
+valid_isas=(constants.all_compiled_tag,),
+valid_hosts=constants.supported_hosts,
+length=constants.long_tag,
+)
+
+gem5_verify_config(
 name="test-gem5-library-example-riscvmatched-hello",
 fixtures=(),
 verifiers=(),

--
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Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Add example configuration for OctopiCache

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71618?usp=email )



Change subject: configs: Add example configuration for OctopiCache
..

configs: Add example configuration for OctopiCache

Change-Id: Ia78dd63e63808ebad40052d2a7cdb67cc7179e44
Signed-off-by: Hoa Nguyen 
---
A configs/example/gem5_library/caches/octopi-cache-example.py
1 file changed, 95 insertions(+), 0 deletions(-)



diff --git a/configs/example/gem5_library/caches/octopi-cache-example.py  
b/configs/example/gem5_library/caches/octopi-cache-example.py

new file mode 100644
index 000..5bfe536
--- /dev/null
+++ b/configs/example/gem5_library/caches/octopi-cache-example.py
@@ -0,0 +1,95 @@
+# Copyright (c) 2023 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This script boots Ubuntu 20.04 with 8 timing cores in 1 CCD.
+
+Usage
+-
+
+```
+scons build/ARM_MESI_Three_Level/gem5.opt
+./build/ARM_MESI_Three_Level/gem5.opt  
configs/example/gem5_library/caches/octopi-cache-example.py

+```
+"""
+
+
+import m5
+from m5.objects import Root
+
+from gem5.utils.requires import requires
+from gem5.components.boards.arm_board import ArmBoard
+from gem5.components.memory import DualChannelDDR4_2400
+from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.Octopi  
import (

+OctopiCache,
+)
+from gem5.isas import ISA
+from gem5.coherence_protocol import CoherenceProtocol
+from gem5.resources.resource import Resource, CustomResource,  
DiskImageResource

+from gem5.simulate.simulator import Simulator
+from gem5.resources.workload import Workload
+
+num_core_complexes = 1  # CCDs
+num_cores_per_core_complexes = 8  # 8 cores/CCD
+
+# OctopiCache is built on top of the gem5's MESI_Three_Level cache  
coherence protocol

+requires(coherence_protocol_required=CoherenceProtocol.MESI_THREE_LEVEL)
+cache_hierarchy = OctopiCache(
+l1i_size="32KiB",
+l1i_assoc=8,
+l1d_size="32KiB",
+l1d_assoc=8,
+l2_size="512KiB",
+l2_assoc=8,
+l3_size="32MiB",
+l3_assoc=16,
+num_core_complexes=1,
+is_fullsystem=True,
+)
+
+memory = DualChannelDDR4_2400(size="16GB")
+
+# The number of cores must be consistent with
+# num_core_complexes and num_cores_per_core_complexes
+processor = SimpleProcessor(
+cpu_type=CPUTypes.TIMING,
+isa=ISA.ARM,
+num_cores=num_core_complexes * num_cores_per_core_complexes,
+)
+
+board = ArmBoard(
+clk_freq="4GHz",
+processor=processor,
+memory=memory,
+cache_hierarchy=cache_hierarchy,
+)
+
+board.set_workload(Workload("arm64-ubuntu-20.04-boot"))
+
+simulator = Simulator(board=board)
+simulator.run()

--
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[gem5-dev] [L] Change in gem5/gem5[develop]: stdlib: Add a prebuilt MESI_Three_Level cache

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71598?usp=email )



Change subject: stdlib: Add a prebuilt MESI_Three_Level cache
..

stdlib: Add a prebuilt MESI_Three_Level cache

The cache is modeled after an AMD EPYC cache, but not exactly
like AMD EPYC cache.
- K cores per core complex (CCD), each core has one private split L1,
and one private L2.
- K cores in the same CCD share 1 slice of L3 cache, which is not
a victim cache.
- There can be multiple CCDs, which communicate with each other via
Cross-CCD router. The Cross-CCD rounter is also connected to
directory controllers and dma controllers.
- All links latency are set to 1.

Change-Id: Ib64248bed9155b8e48e5158ffdeebf1f2d770754
Signed-off-by: Hoa Nguyen 
---
M src/python/SConscript
A  
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/Octopi.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/__init__.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/core_complex.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi_network.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/ruby_network_components.py
M  
src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py

7 files changed, 616 insertions(+), 1 deletion(-)



diff --git a/src/python/SConscript b/src/python/SConscript
index f98b570..47901fd 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -154,6 +154,18 @@
 PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
 'gem5/components/cachehierarchies/ruby/caches/mesi_three_level/'
 'l3_cache.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
+'Octopi.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
+'core_complex.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
+'octopi_network.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
+'ruby_network_components.py')
 PySource('gem5.components.cachehierarchies.ruby.caches.mi_example',
 'gem5/components/cachehierarchies/ruby/caches/mi_example/__init__.py')
 PySource('gem5.components.cachehierarchies.ruby.caches.mi_example',
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/Octopi.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/Octopi.py

new file mode 100644
index 000..96a68da
--- /dev/null
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/Octopi.py

@@ -0,0 +1,237 @@
+from ...abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
+from abstract_three_level_cache_hierarchy import (
+AbstractThreeLevelCacheHierarchy,
+)
+from ..coherence_protocol import CoherenceProtocol
+from ..isas import ISA
+from ..components.boards.abstract_board import AbstractBoard
+from ..utils.requires import requires
+
+from ..components.cachehierarchies.ruby.caches.mesi_three_level.directory  
import  
(

+Directory,
+)
+from ..components.cachehierarchies.ruby.caches.mesi_three_level.dma_controller  
import  
(

+DMAController,
+)
+
+from m5.objects import RubySystem, DMASequencer, RubyPortProxy
+
+from .core_complex import CoreComplex
+from .octopi_network import OctopiNetwork
+from .ruby_network_components import (
+RubyNetworkComponent,
+RubyRouter,
+RubyExtLink,
+RubyIntLink,
+)
+
+# CoreComplex sub-systems own the L1, L2, L3 controllers
+# OctopiCache owns the directory controllers
+# RubySystem owns the DMA Controllers
+class OctopiCache(
+AbstractRubyCacheHierarchy, AbstractThreeLevelCacheHierarchy
+):
+def __init__(
+self,
+l1i_size: str,
+l1i_assoc: int,
+l1d_size: str,
+l1d_assoc: int,
+l2_size: str,
+l2_assoc: int,
+l3_size: str,
+l3_assoc: int,
+num_core_complexes: int,
+is_fullsystem: bool,
+):
+AbstractRubyCacheHierarchy.__init__(self=self)
+AbstractThreeLevelCacheHierarchy.__init__(
+self=self,
+l1i_size=l1i_size,
+l1i_assoc=l1i_assoc,
+l1d_size=l1d_size,
+l1d_assoc=l1d_assoc,
+l2_size=l2_size,
+l2_assoc=l2_assoc,
+l3_size=l3_size,
+l3_assoc=l3_assoc,
+)
+
+self._directory_controllers = []
+

[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: write device tree after setting up bootloader in ARMBoard

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70017?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: stdlib: write device tree after setting up bootloader in  
ARMBoard

..

stdlib: write device tree after setting up bootloader in ARMBoard

The generation of the device tree in an arm system requires knowing
cpu-release-addr property, which is only available after setting up
the bootloader.

cpu-release-addr specifies where the secondary CPUs spin/sleep(?) before
being waken up by the kernel.

The incorrect cpu-release-addr causes booting an arm system using the
standard library with the arm's provided bootloader+linux_kernel to
fail to regconize more than 1 core.

Change-Id: Ice0e38492e2f77020b0e30c42dd4e8b7ee58e598
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70017
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Richard Cooper 
---
M src/python/gem5/components/boards/arm_board.py
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved
  Richard Cooper: Looks good to me, but someone else must approve




diff --git a/src/python/gem5/components/boards/arm_board.py  
b/src/python/gem5/components/boards/arm_board.py

index 10e2c0e..b439edf 100644
--- a/src/python/gem5/components/boards/arm_board.py
+++ b/src/python/gem5/components/boards/arm_board.py
@@ -320,10 +320,6 @@
 # The workload needs to know the dtb_file.
 self.workload.dtb_filename = self._get_dtb_filename()

-# Calling generateDtb from class ArmSystem to add memory  
information to

-# the dtb file.
-self.generateDtb(self._get_dtb_filename())
-
 # Finally we need to setup the bootloader for the ArmBoard. An ARM
 # system requires three inputs to simulate a full system: a disk  
image,

 # the kernel file and the bootloader file(s).
@@ -331,6 +327,10 @@
 self, self._get_dtb_filename(), self._bootloader
 )

+# Calling generateDtb from class ArmSystem to add memory  
information to

+# the dtb file.
+self.generateDtb(self._get_dtb_filename())
+
 def _get_dtb_filename(self) -> str:
 """Returns the dtb file location.


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Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: write device tree after setting up bootloader in ARMBoard

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70017?usp=email )



Change subject: stdlib: write device tree after setting up bootloader in  
ARMBoard

..

stdlib: write device tree after setting up bootloader in ARMBoard

The generation of the device tree in an arm system requires knowing
cpu-release-addr property, which is only available after setting up
the bootloader.

cpu-release-addr specifies where the secondary CPUs spin/sleep(?) before
being waken up by the kernel.

The incorrect cpu-release-addr causes booting an arm system using the
standard library with the arm's provided bootloader+linux_kernel to
fail to regconize more than 1 core.

Change-Id: Ice0e38492e2f77020b0e30c42dd4e8b7ee58e598
Signed-off-by: Hoa Nguyen 
---
M src/python/gem5/components/boards/arm_board.py
1 file changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/python/gem5/components/boards/arm_board.py  
b/src/python/gem5/components/boards/arm_board.py

index 10e2c0e..b439edf 100644
--- a/src/python/gem5/components/boards/arm_board.py
+++ b/src/python/gem5/components/boards/arm_board.py
@@ -320,10 +320,6 @@
 # The workload needs to know the dtb_file.
 self.workload.dtb_filename = self._get_dtb_filename()

-# Calling generateDtb from class ArmSystem to add memory  
information to

-# the dtb file.
-self.generateDtb(self._get_dtb_filename())
-
 # Finally we need to setup the bootloader for the ArmBoard. An ARM
 # system requires three inputs to simulate a full system: a disk  
image,

 # the kernel file and the bootloader file(s).
@@ -331,6 +327,10 @@
 self, self._get_dtb_filename(), self._bootloader
 )

+# Calling generateDtb from class ArmSystem to add memory  
information to

+# the dtb file.
+self.generateDtb(self._get_dtb_filename())
+
 def _get_dtb_filename(self) -> str:
 """Returns the dtb file location.


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[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: Not flushing data to memory when there's no dirty block

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69897?usp=email )


Change subject: mem-ruby: Not flushing data to memory when there's no dirty  
block

..

mem-ruby: Not flushing data to memory when there's no dirty block

Currently, taking a checkpoint with a ruby cache involves moving all
the dirty data in cache to memory. This is done by keeping **only**
simulating the cache until all dirty data are flushed to the memory
before taking the checkpoint.

However, when the cache does not have dirty data, it is a problem if
we keep simulating the cache. E.g., calling checkpoint caused the gem5
"empty event queue" assertion fault when running the ruby cache in
atomic_noncaching mode. Since the mode bypasses the cache, all blocks
are invalid and do not contain dirty data. Subsequently, there is no
event placed to the event queue when we keep **only** simulating the
cache before taking the checkpoint.

This patch fixes this problem by checking if there is any actionable
item when trying to move dirty data to memory. If there is no block
contains dirty data, we simply choose not to continue simulating the
cache before taking the checkpoint.

Change-Id: Idfa09be51274c7fc8a340e9e33167f5b32d1b866
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69897
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Bobby Bruce 
---
M src/mem/ruby/system/CacheRecorder.cc
M src/mem/ruby/system/CacheRecorder.hh
M src/mem/ruby/system/RubySystem.cc
3 files changed, 15 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/ruby/system/CacheRecorder.cc  
b/src/mem/ruby/system/CacheRecorder.cc

index e87b3f2..20a8a30 100644
--- a/src/mem/ruby/system/CacheRecorder.cc
+++ b/src/mem/ruby/system/CacheRecorder.cc
@@ -207,5 +207,11 @@
 return current_size;
 }

+uint64_t
+CacheRecorder::getNumRecords() const
+{
+return m_records.size();
+}
+
 } // namespace ruby
 } // namespace gem5
diff --git a/src/mem/ruby/system/CacheRecorder.hh  
b/src/mem/ruby/system/CacheRecorder.hh

index 8dbd67f..be95590 100644
--- a/src/mem/ruby/system/CacheRecorder.hh
+++ b/src/mem/ruby/system/CacheRecorder.hh
@@ -85,6 +85,8 @@

 uint64_t aggregateRecords(uint8_t **data, uint64_t size);

+uint64_t getNumRecords() const;
+
 /*!
  * Function for flushing the memory contents of the caches to the
  * main memory. It goes through the recorded contents of the caches,
diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index 5a81513..b38c903 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -218,6 +218,13 @@
 }
 DPRINTF(RubyCacheTrace, "Cache Trace Complete\n");

+// If there is no dirty block, we don't need to flush the cache
+if (m_cache_recorder->getNumRecords() == 0)
+{
+m_cooldown_enabled = false;
+return;
+}
+
 // save the current tick value
 Tick curtick_original = curTick();
 DPRINTF(RubyCacheTrace, "Recording current tick %ld\n",  
curtick_original);


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Gerrit-Change-Id: Idfa09be51274c7fc8a340e9e33167f5b32d1b866
Gerrit-Change-Number: 69897
Gerrit-PatchSet: 6
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [M] Change in gem5/gem5[develop]: mem-ruby: Not draining cache without drainable actions

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69897?usp=email )



Change subject: mem-ruby: Not draining cache without drainable actions
..

mem-ruby: Not draining cache without drainable actions

Currently, taking a checkpoint with a ruby cache involves moving all
the cache blocks that are in transient states to stable states. This
is done by keeping **only** simulating the cache still all blocks are
in the stable states before taking the checkpoint.

However, when all blocks are in stable states, it is a problem if we
keep simulating the cache. E.g., calling checkpoint caused the gem5
"empty event queue" assertion fault when running the ruby cache in
atomic_noncaching mode. Since the mode bypasses the cache, all blocks
in the cache are in a stable state. Subsequently, there is no event
placed to the event queue when we keep **only** simulating the cache
before taking the checkpoint.

This patch fixes this problem by checking if there is any actionable
item when trying to moving all cache blocks to stable states. If
there is no block needed to be transitioned to a stable state, we
simply choose not to continue simulating the cache before taking the
checkpoint.

Change-Id: Idfa09be51274c7fc8a340e9e33167f5b32d1b866
Signed-off-by: Hoa Nguyen 
---
M src/mem/ruby/system/CacheRecorder.cc
M src/mem/ruby/system/CacheRecorder.hh
M src/mem/ruby/system/RubySystem.cc
3 files changed, 46 insertions(+), 34 deletions(-)



diff --git a/src/mem/ruby/system/CacheRecorder.cc  
b/src/mem/ruby/system/CacheRecorder.cc

index e87b3f2..20a8a30 100644
--- a/src/mem/ruby/system/CacheRecorder.cc
+++ b/src/mem/ruby/system/CacheRecorder.cc
@@ -207,5 +207,11 @@
 return current_size;
 }

+uint64_t
+CacheRecorder::getNumRecords() const
+{
+return m_records.size();
+}
+
 } // namespace ruby
 } // namespace gem5
diff --git a/src/mem/ruby/system/CacheRecorder.hh  
b/src/mem/ruby/system/CacheRecorder.hh

index 8dbd67f..be95590 100644
--- a/src/mem/ruby/system/CacheRecorder.hh
+++ b/src/mem/ruby/system/CacheRecorder.hh
@@ -85,6 +85,8 @@

 uint64_t aggregateRecords(uint8_t **data, uint64_t size);

+uint64_t getNumRecords() const;
+
 /*!
  * Function for flushing the memory contents of the caches to the
  * main memory. It goes through the recorded contents of the caches,
diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index 5a81513..4a01c20 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -218,46 +218,50 @@
 }
 DPRINTF(RubyCacheTrace, "Cache Trace Complete\n");

-// save the current tick value
-Tick curtick_original = curTick();
-DPRINTF(RubyCacheTrace, "Recording current tick %ld\n",  
curtick_original);

+if (m_cache_recorder->getNumRecords() != 0)
+{
+// save the current tick value
+Tick curtick_original = curTick();
+DPRINTF(RubyCacheTrace, "Recording current tick %ld\n",
+curtick_original);

-// Deschedule all prior events on the event queue, but record the tick  
they

-// were scheduled at so they can be restored correctly later.
-std::list > original_events;
-while (!eventq->empty()) {
-Event *curr_head = eventq->getHead();
-if (curr_head->isAutoDelete()) {
-DPRINTF(RubyCacheTrace, "Event %s auto-deletes when  
descheduled,"

-" not recording\n", curr_head->name());
-} else {
-original_events.push_back(
-std::make_pair(curr_head, curr_head->when()));
+// Deschedule all prior events on the event queue, but record the  
tick

+// they were scheduled at so they can be restored correctly later.
+std::list > original_events;
+while (!eventq->empty()) {
+Event *curr_head = eventq->getHead();
+if (curr_head->isAutoDelete()) {
+DPRINTF(RubyCacheTrace, "Event %s auto-deletes when
+"descheduled, not recording\n", curr_head->name());
+} else {
+original_events.push_back(
+std::make_pair(curr_head, curr_head->when()));
+}
+eventq->deschedule(curr_head);
 }
-eventq->deschedule(curr_head);
-}

-// Schedule an event to start cache cooldown
-DPRINTF(RubyCacheTrace, "Starting cache flush\n");
-enqueueRubyEvent(curTick());
-simulate();
-DPRINTF(RubyCacheTrace, "Cache flush complete\n");
+// Schedule an event to start cache cooldown
+DPRINTF(RubyCacheTrace, "Starting cache flush\n");
+enqueueRubyEvent(curTick());
+simulate();
+DPRINTF(RubyCacheTrace, "Cache flush complete\n");

-// Deschedule any events left on the event queue.
-while (!eventq->empty()) {
-

[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: Add a function returning non-current switchable cores

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69838?usp=email )



Change subject: stdlib: Add a function returning non-current switchable  
cores

..

stdlib: Add a function returning non-current switchable cores

Change-Id: I8c670ae4a8dcd5b4de504c182c477e998c82c75c
Signed-off-by: Hoa Nguyen 
---
M src/python/gem5/components/processors/switchable_processor.py
1 file changed, 6 insertions(+), 0 deletions(-)



diff --git a/src/python/gem5/components/processors/switchable_processor.py  
b/src/python/gem5/components/processors/switchable_processor.py

index 036e391..bd04a73 100644
--- a/src/python/gem5/components/processors/switchable_processor.py
+++ b/src/python/gem5/components/processors/switchable_processor.py
@@ -117,6 +117,12 @@
 def get_cores(self) -> List[AbstractCore]:
 return self._current_cores

+def get_switch_to_cores(self) -> List[AbstractCore]:
+for name, core_list in self._switchable_cores.items():
+for core in core_list:
+if not core in self._current_cores:
+yield core
+
 def _all_cores(self):
 for core_list in self._switchable_cores.values():
 for core in core_list:

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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Add is_switchable() abstract method to AbstractProcessor

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69837?usp=email )



Change subject: stdlib: Add is_switchable() abstract method to  
AbstractProcessor

..

stdlib: Add is_switchable() abstract method to AbstractProcessor

Allows other components to know where the processor is a switchable one.

Change-Id: I2174f2493dc1514a3370b99e2fbb8711ad5a9edd
Signed-off-by: Hoa Nguyen 
---
M src/python/gem5/components/processors/abstract_processor.py
M src/python/gem5/components/processors/base_cpu_processor.py
M src/python/gem5/components/processors/switchable_processor.py
3 files changed, 12 insertions(+), 0 deletions(-)



diff --git a/src/python/gem5/components/processors/abstract_processor.py  
b/src/python/gem5/components/processors/abstract_processor.py

index a0f8b5c..f62f454 100644
--- a/src/python/gem5/components/processors/abstract_processor.py
+++ b/src/python/gem5/components/processors/abstract_processor.py
@@ -72,6 +72,10 @@
 return self._isa

 @abstractmethod
+def is_switchable(self) -> bool:
+raise NotImplementedError
+
+@abstractmethod
 def incorporate_processor(self, board: AbstractBoard) -> None:
 raise NotImplementedError

diff --git a/src/python/gem5/components/processors/base_cpu_processor.py  
b/src/python/gem5/components/processors/base_cpu_processor.py

index 9a75615..8b169b7 100644
--- a/src/python/gem5/components/processors/base_cpu_processor.py
+++ b/src/python/gem5/components/processors/base_cpu_processor.py
@@ -70,6 +70,10 @@
 self.kvm_vm = KvmVM()

 @overrides(AbstractProcessor)
+def is_switchable(self) -> bool:
+return False
+
+@overrides(AbstractProcessor)
 def incorporate_processor(self, board: AbstractBoard) -> None:

 if any(core.is_kvm_core() for core in self.get_cores()):
diff --git a/src/python/gem5/components/processors/switchable_processor.py  
b/src/python/gem5/components/processors/switchable_processor.py

index 20754fb..036e391 100644
--- a/src/python/gem5/components/processors/switchable_processor.py
+++ b/src/python/gem5/components/processors/switchable_processor.py
@@ -84,6 +84,10 @@
 self.kvm_vm = KvmVM()

 @overrides(AbstractProcessor)
+def is_switchable(self):
+return True
+
+@overrides(AbstractProcessor)
 def incorporate_processor(self, board: AbstractBoard) -> None:

 # This is a bit of a hack. The `m5.switchCpus` function, used in  
the


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[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: Assign the workload to the non-starting cores

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69839?usp=email )



Change subject: stdlib: Assign the workload to the non-starting cores
..

stdlib: Assign the workload to the non-starting cores

This causes problems at instantiation time where gem5 couldn't find
the workload for the non-starting cores.

Change-Id: Ibd4f8985100a0ceb3339135a6a454f37403f587c
Signed-off-by: Hoa Nguyen 
---
M src/python/gem5/components/boards/se_binary_workload.py
1 file changed, 3 insertions(+), 0 deletions(-)



diff --git a/src/python/gem5/components/boards/se_binary_workload.py  
b/src/python/gem5/components/boards/se_binary_workload.py

index 98fe840..a88e25c 100644
--- a/src/python/gem5/components/boards/se_binary_workload.py
+++ b/src/python/gem5/components/boards/se_binary_workload.py
@@ -114,6 +114,9 @@

 for core in self.get_processor().get_cores():
 core.set_workload(process)
+if self.get_processor().is_switchable():
+for core in self.get_processor().get_switch_to_cores():
+core.set_workload(process)

 # Set whether to exit on work items for the se_workload
 self.exit_on_work_items = exit_on_work_items

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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Add "--no-duplicate-sources" option to SConstruct in util/

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69797?usp=email )


Change subject: scons: Add "--no-duplicate-sources" option to SConstruct in  
util/

..

scons: Add "--no-duplicate-sources" option to SConstruct in util/

Patch [1] caused building util/m5 to fail due to the flag was not
an option in the SConstruct file. It is apparently the case for other
programs in util/ relying on scons.

This patch fixes the above problem, and also adheres to the default
behavior introduced by [2].

[1] This patch introduced the "--no-duplicate-sources" flag to the
scons build in util/
https://gem5-review.googlesource.com/c/public/gem5/+/68518

[2] This patch turns this flag off by default,
https://gem5-review.googlesource.com/c/public/gem5/+/69717

Change-Id: I51376f7b3bf06438b7bc7ff84bc599deecac5bd1
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69797
Maintainer: Bobby Bruce 
Reviewed-by: Alex Richardson 
Tested-by: kokoro 
Reviewed-by: Ayaz Akram 
---
M util/m5/SConstruct
M util/statetrace/SConstruct
M util/tlm/SConstruct
3 files changed, 15 insertions(+), 0 deletions(-)

Approvals:
  kokoro: Regressions pass
  Alex Richardson: Looks good to me, but someone else must approve
  Bobby Bruce: Looks good to me, approved
  Ayaz Akram: Looks good to me, approved




diff --git a/util/m5/SConstruct b/util/m5/SConstruct
index c2c4a50..7f07b94 100644
--- a/util/m5/SConstruct
+++ b/util/m5/SConstruct
@@ -49,6 +49,9 @@
 AddOption('--run-tests', dest='run_tests', action='store_true',
   help='Enable test output xml files as build targets.')
 AddOption('--verbose', dest='verbose', action='store_true')
+AddOption('--no-duplicate-sources', action='store_false', default=True,
+  dest='duplicate_sources',
+  help='Do not create symlinks to sources in the build directory')

 # Universal settings.
 if GetOption('debug_build'):
diff --git a/util/statetrace/SConstruct b/util/statetrace/SConstruct
index 945976e..2e1a631 100644
--- a/util/statetrace/SConstruct
+++ b/util/statetrace/SConstruct
@@ -57,6 +57,12 @@

 main['CXX'] = ARGUMENTS.get('CXX', main['CXX'])

+# An option not to link source files in the build directory.
+# Not enabled by default.
+AddOption('--no-duplicate-sources', action='store_false', default=True,
+  dest='duplicate_sources',
+  help='Do not create symlinks to sources in the build directory')
+
 for arch in arches:
 env = main.Clone()
 env['CXX'] = ARGUMENTS.get(arch.upper() + 'CXX', env['CXX'])
diff --git a/util/tlm/SConstruct b/util/tlm/SConstruct
index 6c65cfd..3f4abf8 100644
--- a/util/tlm/SConstruct
+++ b/util/tlm/SConstruct
@@ -80,6 +80,12 @@
 AddOption('--no-colors', dest='use_colors', action='store_false',
   help="Don't add color to abbreviated scons output")

+# An option not to link source files in the build directory.
+# Not enabled by default.
+AddOption('--no-duplicate-sources', action='store_false', default=True,
+  dest='duplicate_sources',
+  help='Do not create symlinks to sources in the build directory')
+
 env.SConsignFile('build/systemc/sconsign')
 SConscript(gem5_root + '/ext/systemc/SConscript',
variant_dir='build/systemc',

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I51376f7b3bf06438b7bc7ff84bc599deecac5bd1
Gerrit-Change-Number: 69797
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Alex Richardson 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Add "--no-duplicate-sources" option to SConstruct in util/

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69797?usp=email )



Change subject: scons: Add "--no-duplicate-sources" option to SConstruct in  
util/

..

scons: Add "--no-duplicate-sources" option to SConstruct in util/

Patch [1] caused building util/m5 to fail due to the flag was not
an option in the SConstruct file. It is apparently the case for other
programs in util/ relying on scons.

This patch fixes the above problem, and also adheres to the default
behavior introduced by [2].

[1] This patch introduced the "--no-duplicate-sources" flag to the
scons build in util/
https://gem5-review.googlesource.com/c/public/gem5/+/68518

[2] This patch enabled this flag by default,
https://gem5-review.googlesource.com/c/public/gem5/+/69717

Change-Id: I51376f7b3bf06438b7bc7ff84bc599deecac5bd1
Signed-off-by: Hoa Nguyen 
---
M util/m5/SConstruct
M util/statetrace/SConstruct
M util/tlm/SConstruct
3 files changed, 15 insertions(+), 0 deletions(-)



diff --git a/util/m5/SConstruct b/util/m5/SConstruct
index c2c4a50..7f07b94 100644
--- a/util/m5/SConstruct
+++ b/util/m5/SConstruct
@@ -49,6 +49,9 @@
 AddOption('--run-tests', dest='run_tests', action='store_true',
   help='Enable test output xml files as build targets.')
 AddOption('--verbose', dest='verbose', action='store_true')
+AddOption('--no-duplicate-sources', action='store_false', default=True,
+  dest='duplicate_sources',
+  help='Do not create symlinks to sources in the build directory')

 # Universal settings.
 if GetOption('debug_build'):
diff --git a/util/statetrace/SConstruct b/util/statetrace/SConstruct
index 945976e..2e1a631 100644
--- a/util/statetrace/SConstruct
+++ b/util/statetrace/SConstruct
@@ -57,6 +57,12 @@

 main['CXX'] = ARGUMENTS.get('CXX', main['CXX'])

+# An option not to link source files in the build directory.
+# Not enabled by default.
+AddOption('--no-duplicate-sources', action='store_false', default=True,
+  dest='duplicate_sources',
+  help='Do not create symlinks to sources in the build directory')
+
 for arch in arches:
 env = main.Clone()
 env['CXX'] = ARGUMENTS.get(arch.upper() + 'CXX', env['CXX'])
diff --git a/util/tlm/SConstruct b/util/tlm/SConstruct
index 6c65cfd..3f4abf8 100644
--- a/util/tlm/SConstruct
+++ b/util/tlm/SConstruct
@@ -80,6 +80,12 @@
 AddOption('--no-colors', dest='use_colors', action='store_false',
   help="Don't add color to abbreviated scons output")

+# An option not to link source files in the build directory.
+# Not enabled by default.
+AddOption('--no-duplicate-sources', action='store_false', default=True,
+  dest='duplicate_sources',
+  help='Do not create symlinks to sources in the build directory')
+
 env.SConsignFile('build/systemc/sconsign')
 SConscript(gem5_root + '/ext/systemc/SConscript',
variant_dir='build/systemc',

--
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Gerrit-Change-Id: I51376f7b3bf06438b7bc7ff84bc599deecac5bd1
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Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: Fix bug in MESI_Three_Level_Cache initialization

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68857?usp=email )


Change subject: stdlib: Fix bug in MESI_Three_Level_Cache initialization
..

stdlib: Fix bug in MESI_Three_Level_Cache initialization

Change-Id: I2d06c842955aa1868053a0d852fc523392480154
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68857
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

2 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Hoa Nguyen: Looks good to me, approved
  kokoro: Regressions pass




diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

index 9f47e41..b485481 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

@@ -68,14 +68,14 @@
 self.Icache = RubyCache(
 size=l1i_size,
 assoc=l1i_assoc,
-start_index_bit=self.getBlockSizeBits(cache_line_size.value),
+start_index_bit=self.getBlockSizeBits(cache_line_size),
 is_icache=True,
 replacement_policy=LRURP(),
 )
 self.Dcache = RubyCache(
 size=l1d_size,
 assoc=l1d_assoc,
-start_index_bit=self.getBlockSizeBits(cache_line_size.value),
+start_index_bit=self.getBlockSizeBits(cache_line_size),
 is_icache=False,
 replacement_policy=LRURP(),
 )
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

index d8c9659..d54e1ab 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

@@ -67,7 +67,7 @@
 self.cache = RubyCache(
 size=l2_size,
 assoc=l2_assoc,
-start_index_bit=self.getBlockSizeBits(cache_line_size.value),
+start_index_bit=self.getBlockSizeBits(cache_line_size),
 is_icache=False,
 )
 # l2_select_num_bits is ruby backend terminology.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2d06c842955aa1868053a0d852fc523392480154
Gerrit-Change-Number: 68857
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: use atomic_noncaching when using AtomicSimpleCPU with Ruby

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68877?usp=email )


Change subject: stdlib: use atomic_noncaching when using AtomicSimpleCPU  
with Ruby

..

stdlib: use atomic_noncaching when using AtomicSimpleCPU with Ruby

mem_mode is supposed to be atomic_noncaching when running
AtomicSimpleCPU with Ruby cache.

Change-Id: Icb419f9370038f5c1f80dd879b187338279a5b93
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68877
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/gem5/components/processors/base_cpu_processor.py
M src/python/gem5/components/processors/simple_switchable_processor.py
2 files changed, 11 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/processors/base_cpu_processor.py  
b/src/python/gem5/components/processors/base_cpu_processor.py

index d311a0f..9a75615 100644
--- a/src/python/gem5/components/processors/base_cpu_processor.py
+++ b/src/python/gem5/components/processors/base_cpu_processor.py
@@ -97,6 +97,7 @@
 "'atomic_noncaching' memory mode. This will skip  
caching "

 "completely."
 )
+board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
 else:
 board.set_mem_mode(MemMode.ATOMIC)
 else:
diff --git  
a/src/python/gem5/components/processors/simple_switchable_processor.py  
b/src/python/gem5/components/processors/simple_switchable_processor.py

index 56603fa..e397841 100644
--- a/src/python/gem5/components/processors/simple_switchable_processor.py
+++ b/src/python/gem5/components/processors/simple_switchable_processor.py
@@ -103,6 +103,16 @@
 def incorporate_processor(self, board: AbstractBoard) -> None:
 super().incorporate_processor(board=board)

+if (
+board.get_cache_hierarchy().is_ruby()
+and self._mem_mode == MemMode.ATOMIC
+):
+warn(
+"Using an atomic core with Ruby will result in "
+"'atomic_noncaching' memory mode. This will skip caching "
+"completely."
+)
+self._mem_mode = MemMode.ATOMIC_NONCACHING
 board.set_mem_mode(self._mem_mode)

 def switch(self):

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icb419f9370038f5c1f80dd879b187338279a5b93
Gerrit-Change-Number: 68877
Gerrit-PatchSet: 4
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: use atomic_noncaching when using AtomicSimpleCPU with Ruby

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68877?usp=email )



Change subject: stdlib: use atomic_noncaching when using AtomicSimpleCPU  
with Ruby

..

stdlib: use atomic_noncaching when using AtomicSimpleCPU with Ruby

mem_mode is supposed to be atomic_noncaching when running
AtomicSimpleCPU with Ruby cache.

Change-Id: Icb419f9370038f5c1f80dd879b187338279a5b93
Signed-off-by: Hoa Nguyen 
---
M src/python/gem5/components/processors/base_cpu_processor.py
M src/python/gem5/components/processors/simple_switchable_processor.py
2 files changed, 6 insertions(+), 0 deletions(-)



diff --git a/src/python/gem5/components/processors/base_cpu_processor.py  
b/src/python/gem5/components/processors/base_cpu_processor.py

index d311a0f..9a75615 100644
--- a/src/python/gem5/components/processors/base_cpu_processor.py
+++ b/src/python/gem5/components/processors/base_cpu_processor.py
@@ -97,6 +97,7 @@
 "'atomic_noncaching' memory mode. This will skip  
caching "

 "completely."
 )
+board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
 else:
 board.set_mem_mode(MemMode.ATOMIC)
 else:
diff --git  
a/src/python/gem5/components/processors/simple_switchable_processor.py  
b/src/python/gem5/components/processors/simple_switchable_processor.py

index 56603fa..bfeb9bc 100644
--- a/src/python/gem5/components/processors/simple_switchable_processor.py
+++ b/src/python/gem5/components/processors/simple_switchable_processor.py
@@ -103,6 +103,11 @@
 def incorporate_processor(self, board: AbstractBoard) -> None:
 super().incorporate_processor(board=board)

+# special case:
+# ruby cache doesn't support "atomic" mem mode; however, ruby cache
+# supports "atomic_noncaching" mem mode, which bypasses the cache.
+if board.get_cache_hierarchy().is_ruby() and self._mem_mode =  
MemMode.ATOMIC:

+self._mem_mode = MemMode.ATOMIC_NONCACHING
 board.set_mem_mode(self._mem_mode)

 def switch(self):

--
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Gerrit-Change-Id: Icb419f9370038f5c1f80dd879b187338279a5b93
Gerrit-Change-Number: 68877
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Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: Fix bug in MESI_Three_Level_Cache initialization

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68857?usp=email )



Change subject: stdlib: Fix bug in MESI_Three_Level_Cache initialization
..

stdlib: Fix bug in MESI_Three_Level_Cache initialization

Change-Id: I2d06c842955aa1868053a0d852fc523392480154
Signed-off-by: Hoa Nguyen 
---
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

2 files changed, 3 insertions(+), 3 deletions(-)



diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

index 9f47e41..b485481 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

@@ -68,14 +68,14 @@
 self.Icache = RubyCache(
 size=l1i_size,
 assoc=l1i_assoc,
-start_index_bit=self.getBlockSizeBits(cache_line_size.value),
+start_index_bit=self.getBlockSizeBits(cache_line_size),
 is_icache=True,
 replacement_policy=LRURP(),
 )
 self.Dcache = RubyCache(
 size=l1d_size,
 assoc=l1d_assoc,
-start_index_bit=self.getBlockSizeBits(cache_line_size.value),
+start_index_bit=self.getBlockSizeBits(cache_line_size),
 is_icache=False,
 replacement_policy=LRURP(),
 )
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

index d8c9659..d54e1ab 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

@@ -67,7 +67,7 @@
 self.cache = RubyCache(
 size=l2_size,
 assoc=l2_assoc,
-start_index_bit=self.getBlockSizeBits(cache_line_size.value),
+start_index_bit=self.getBlockSizeBits(cache_line_size),
 is_icache=False,
 )
 # l2_select_num_bits is ruby backend terminology.

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I2d06c842955aa1868053a0d852fc523392480154
Gerrit-Change-Number: 68857
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66771?usp=email )


Change subject: stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy
..

stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy

Change-Id: I60ae47f4336cb1b54bcca3fce3bdd13858daa92a
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66771
Reviewed-by: Matt Sinclair 
Reviewed-by: Jason Lowe-Power 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py

4 files changed, 47 insertions(+), 19 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass




diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py

index ab76d4c..f731869 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py

@@ -25,16 +25,26 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from ..utils.override import overrides
-from ..abstract_dma_controller import AbstractDMAController

-from m5.objects import MessageBuffer
+from m5.objects import MessageBuffer, DMA_Controller


-class DMAController(AbstractDMAController):
-def __init__(self, network, cache_line_size):
-super().__init__(network, cache_line_size)
+class DMAController(DMA_Controller):
+_version = 0

-@overrides(AbstractDMAController)
+@classmethod
+def _get_version(cls):
+cls._version += 1
+return cls._version - 1
+
+def __init__(self, dma_sequencer, ruby_system):
+super().__init__(
+version=self._get_version(),
+dma_sequencer=dma_sequencer,
+ruby_system=ruby_system,
+)
+self.connectQueues(self.ruby_system.network)
+
 def connectQueues(self, network):
 self.mandatoryQueue = MessageBuffer()
 self.responseFromDir = MessageBuffer(ordered=True)
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

index 2ce13d3..9f47e41 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

@@ -68,14 +68,14 @@
 self.Icache = RubyCache(
 size=l1i_size,
 assoc=l1i_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=self.getBlockSizeBits(cache_line_size.value),
 is_icache=True,
 replacement_policy=LRURP(),
 )
 self.Dcache = RubyCache(
 size=l1d_size,
 assoc=l1d_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=self.getBlockSizeBits(cache_line_size.value),
 is_icache=False,
 replacement_policy=LRURP(),
 )
@@ -88,12 +88,11 @@
 self.response_latency = 2

 self.version = self.versionCount()
-self._cache_line_size = cache_line_size
 self.connectQueues(network)

-def getBlockSizeBits(self):
-bits = int(math.log(self._cache_line_size, 2))
-if 2**bits != self._cache_line_size.value:
+def getBlockSizeBits(self, cache_line_size):
+bits = int(math.log(cache_line_size, 2))
+if 2**bits != cache_line_size:
 raise Exception("Cache line size is not a power of 2!")
 return bits

diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

index e29f566..d8c9659 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

@@ -67,7 +67,7 @@
 self.cache = RubyCache(
 size=l2_size,
 assoc=l2_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=self.getBlockSizeBits(cache_line_size.value),
 is_icache=False,
 )
 # l2_select_num_bits is ruby backend 

[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66771?usp=email )



Change subject: stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy
..

stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy

Change-Id: I60ae47f4336cb1b54bcca3fce3bdd13858daa92a
Signed-off-by: Hoa Nguyen 
---
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py

4 files changed, 31 insertions(+), 19 deletions(-)



diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py

index ab76d4c..f731869 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py

@@ -25,16 +25,26 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from ..utils.override import overrides
-from ..abstract_dma_controller import AbstractDMAController

-from m5.objects import MessageBuffer
+from m5.objects import MessageBuffer, DMA_Controller


-class DMAController(AbstractDMAController):
-def __init__(self, network, cache_line_size):
-super().__init__(network, cache_line_size)
+class DMAController(DMA_Controller):
+_version = 0

-@overrides(AbstractDMAController)
+@classmethod
+def _get_version(cls):
+cls._version += 1
+return cls._version - 1
+
+def __init__(self, dma_sequencer, ruby_system):
+super().__init__(
+version=self._get_version(),
+dma_sequencer=dma_sequencer,
+ruby_system=ruby_system,
+)
+self.connectQueues(self.ruby_system.network)
+
 def connectQueues(self, network):
 self.mandatoryQueue = MessageBuffer()
 self.responseFromDir = MessageBuffer(ordered=True)
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

index 2ce13d3..9d68550 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

@@ -68,14 +68,14 @@
 self.Icache = RubyCache(
 size=l1i_size,
 assoc=l1i_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=int(math.log(cache_line_size, 2)),
 is_icache=True,
 replacement_policy=LRURP(),
 )
 self.Dcache = RubyCache(
 size=l1d_size,
 assoc=l1d_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=int(math.log(cache_line_size, 2)),
 is_icache=False,
 replacement_policy=LRURP(),
 )
@@ -88,15 +88,8 @@
 self.response_latency = 2

 self.version = self.versionCount()
-self._cache_line_size = cache_line_size
 self.connectQueues(network)

-def getBlockSizeBits(self):
-bits = int(math.log(self._cache_line_size, 2))
-if 2**bits != self._cache_line_size.value:
-raise Exception("Cache line size is not a power of 2!")
-return bits
-
 def connectQueues(self, network):
 self.prefetchQueue = MessageBuffer()
 self.mandatoryQueue = MessageBuffer()
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

index e29f566..e9f7270 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

@@ -67,7 +67,7 @@
 self.cache = RubyCache(
 size=l2_size,
 assoc=l2_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=int(math.log(cache_line_size, 2)),
 is_icache=False,
 )
 # l2_select_num_bits is ruby backend terminology.
@@ -86,7 +86,6 @@
 self.to_l2_latency = 1

 self.version = self.versionCount()
-self._cache_line_size = cache_line_size
 self.connectQueues(network)

 def connectQueues(self, network):
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py  

[gem5-dev] [L] Change in gem5/gem5[develop]: stdlib: Add MESI Three Level cache hierarchy

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65591?usp=email )


Change subject: stdlib: Add MESI Three Level cache hierarchy
..

stdlib: Add MESI Three Level cache hierarchy

Change-Id: Ibea6b71d62b71f7817f6860bbceed9e1915bb002
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65591
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/python/SConscript
A  
src/python/gem5/components/cachehierarchies/abstract_three_level_cache_hierarchy.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/__init__.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/directory.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
A  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py
A  
src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py

9 files changed, 720 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/SConscript b/src/python/SConscript
index e7e464e..aeeb892 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -61,6 +61,8 @@
 'gem5/components/cachehierarchies/abstract_cache_hierarchy.py')
 PySource('gem5.components.cachehierarchies',
 'gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py')
+PySource('gem5.components.cachehierarchies',
+'gem5/components/cachehierarchies/abstract_three_level_cache_hierarchy.py')
 PySource('gem5.components.cachehierarchies.chi',
 'gem5/components/cachehierarchies/chi/__init__.py')
 PySource('gem5.components.cachehierarchies.chi',
@@ -109,6 +111,9 @@
 PySource('gem5.components.cachehierarchies.ruby',
 'gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py')
 PySource('gem5.components.cachehierarchies.ruby',
+'gem5/components/cachehierarchies/ruby/'
+'mesi_three_level_cache_hierarchy.py')
+PySource('gem5.components.cachehierarchies.ruby',
 'gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py')
 PySource('gem5.components.cachehierarchies.ruby.caches',
 'gem5/components/cachehierarchies/ruby/caches/__init__.py')
@@ -131,6 +136,24 @@
 'gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py')
 PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level',
 'gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/mesi_three_level/'
+'__init__.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/mesi_three_level/'
+'directory.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/mesi_three_level/'
+'dma_controller.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/mesi_three_level/'
+'l1_cache.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/mesi_three_level/'
+'l2_cache.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/mesi_three_level/'
+'l3_cache.py')
 PySource('gem5.components.cachehierarchies.ruby.caches.mi_example',
 'gem5/components/cachehierarchies/ruby/caches/mi_example/__init__.py')
 PySource('gem5.components.cachehierarchies.ruby.caches.mi_example',
diff --git  
a/src/python/gem5/components/cachehierarchies/abstract_three_level_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/abstract_three_level_cache_hierarchy.py

new file mode 100644
index 000..4d2f21a
--- /dev/null
+++  
b/src/python/gem5/components/cachehierarchies/abstract_three_level_cache_hierarchy.py

@@ -0,0 +1,52 @@
+# Copyright (c) 2022 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials 

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Clean up Ruby cache directory

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65571?usp=email )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: stdlib: Clean up Ruby cache directory
..

stdlib: Clean up Ruby cache directory

- Fix typos.
- Fix type inconsistencies.

Change-Id: I98d82ec7e62130abb09295c5ec6cde86b1f7fa27
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65571
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M  
src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py

2 files changed, 20 insertions(+), 5 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git  
a/src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py

index 17cae4a..d6a035f 100644
---  
a/src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py

@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-# from .abstract_cache_hierarchy import AbstractCacheHierarchy
-

 class AbstractTwoLevelCacheHierarchy:
 """
@@ -51,9 +49,9 @@

 :type l1i_assoc: int

-:param l1dsize: The size of the LL1 Data cache (e.g. "32kB").
+:param l1d_size: The size of the L1 Data cache (e.g. "32kB").

-:type l1dsize: str
+:type l1d_size: str

 :param l1d_assoc:

diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py

index 56cb5b2..81ef4db 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py

@@ -45,7 +45,7 @@
 start_index_bit=self.getIndexBit(num_l2Caches),
 )

-self.transitions_per_cycle = "4"
+self.transitions_per_cycle = 4

 def getIndexBit(self, num_l2caches):
 l2_bits = int(math.log(num_l2caches, 2))

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I98d82ec7e62130abb09295c5ec6cde86b1f7fa27
Gerrit-Change-Number: 65571
Gerrit-PatchSet: 4
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Change #virtual_networks of mesi_two_level to 3

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65592?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: stdlib: Change #virtual_networks of mesi_two_level to 3
..

stdlib: Change #virtual_networks of mesi_two_level to 3

A grep of "virtual_network" in src/mem/ruby/protocol shows that
files in MESI_Two_Level.slicc utilizes at 3 virtual networks.

Change-Id: I3e8dd09dd82b9c802fdf91145c6d998bc6db541b
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65592
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M  
src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

1 file changed, 20 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

index 82089a5..79c8b0a 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

@@ -83,11 +83,11 @@

 self.ruby_system = RubySystem()

-# MESI_Two_Level needs 5 virtual networks
-self.ruby_system.number_of_virtual_networks = 5
+# MESI_Two_Level needs 3 virtual networks
+self.ruby_system.number_of_virtual_networks = 3

 self.ruby_system.network = SimplePt2Pt(self.ruby_system)
-self.ruby_system.network.number_of_virtual_networks = 5
+self.ruby_system.network.number_of_virtual_networks = 3

 self._l1_controllers = []
 for i, core in enumerate(board.get_processor().get_cores()):

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3e8dd09dd82b9c802fdf91145c6d998bc6db541b
Gerrit-Change-Number: 65592
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: More helpful message for the filelock error

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66091?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: stdlib: More helpful message for the filelock error
..

stdlib: More helpful message for the filelock error

Change-Id: Ib8e3bc9fc145a9604670e8288209ac62bfbd7932
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66091
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
Tested-by: kokoro 
---
M src/python/gem5/utils/filelock.py
1 file changed, 26 insertions(+), 2 deletions(-)

Approvals:
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved




diff --git a/src/python/gem5/utils/filelock.py  
b/src/python/gem5/utils/filelock.py

index 82e1122..a6798e9 100644
--- a/src/python/gem5/utils/filelock.py
+++ b/src/python/gem5/utils/filelock.py
@@ -69,12 +69,22 @@
 except OSError as e:
 if e.errno != errno.EEXIST:
 raise
+solution_message = (
+"This is likely due to the existence"
+" of the lock file '{}'. If there's no other process"
+" the lock file, you can manually delete the lock file  
and"

+" rerun the script.".format(self.lockfile)
+)
 if self.timeout is None:
 raise FileLockException(
-"Could not acquire lock on  
{}".format(self.file_name)

+"Could not acquire lock on {}. {}".format(
+self.file_name, solution_message
+)
 )
 if (time.time() - start_time) >= self.timeout:
-raise FileLockException("Timeout occured.")
+raise FileLockException(
+"Timeout occured. {}".format(solution_message)
+)
 time.sleep(self.delay)

 #self.is_locked = True

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ib8e3bc9fc145a9604670e8288209ac62bfbd7932
Gerrit-Change-Number: 66091
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Make the Matched board a package

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65331?usp=email )


Change subject: stdlib: Make the Matched board a package
..

stdlib: Make the Matched board a package

So that the board and its components can be reused.

Change-Id: Idae1a4493fbb4d826ac8da76532692a985f8025f
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65331
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/python/SConscript
A src/python/gem5/prebuilt/riscvmatched/__init__.py
2 files changed, 18 insertions(+), 0 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/python/SConscript b/src/python/SConscript
index 66e9842..e7e464e 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -225,6 +225,8 @@
 PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/__init__.py')
 PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/x86_demo_board.py')
 PySource('gem5.prebuilt.riscvmatched',
+'gem5/prebuilt/riscvmatched/__init__.py')
+PySource('gem5.prebuilt.riscvmatched',
 'gem5/prebuilt/riscvmatched/riscvmatched_board.py')
 PySource('gem5.prebuilt.riscvmatched',
 'gem5/prebuilt/riscvmatched/riscvmatched_cache.py')
diff --git a/src/python/gem5/prebuilt/riscvmatched/__init__.py  
b/src/python/gem5/prebuilt/riscvmatched/__init__.py

new file mode 100644
index 000..e69de29
--- /dev/null
+++ b/src/python/gem5/prebuilt/riscvmatched/__init__.py

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idae1a4493fbb4d826ac8da76532692a985f8025f
Gerrit-Change-Number: 65331
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Make the Matched board a package

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65331?usp=email )



Change subject: stdlib: Make the Matched board a package
..

stdlib: Make the Matched board a package

So that the board and its components can be reused.

Change-Id: Idae1a4493fbb4d826ac8da76532692a985f8025f
Signed-off-by: Hoa Nguyen 
---
M src/python/SConscript
A src/python/gem5/prebuilt/riscvmatched/__init__.py
2 files changed, 14 insertions(+), 0 deletions(-)



diff --git a/src/python/SConscript b/src/python/SConscript
index 66e9842..e7e464e 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -225,6 +225,8 @@
 PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/__init__.py')
 PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/x86_demo_board.py')
 PySource('gem5.prebuilt.riscvmatched',
+'gem5/prebuilt/riscvmatched/__init__.py')
+PySource('gem5.prebuilt.riscvmatched',
 'gem5/prebuilt/riscvmatched/riscvmatched_board.py')
 PySource('gem5.prebuilt.riscvmatched',
 'gem5/prebuilt/riscvmatched/riscvmatched_cache.py')
diff --git a/src/python/gem5/prebuilt/riscvmatched/__init__.py  
b/src/python/gem5/prebuilt/riscvmatched/__init__.py

new file mode 100644
index 000..e69de29
--- /dev/null
+++ b/src/python/gem5/prebuilt/riscvmatched/__init__.py

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Gerrit-Change-Id: Idae1a4493fbb4d826ac8da76532692a985f8025f
Gerrit-Change-Number: 65331
Gerrit-PatchSet: 1
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Updating the SD bit of mstatus upon the register read

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65273?usp=email )


Change subject: arch-riscv: Updating the SD bit of mstatus upon the  
register read

..

arch-riscv: Updating the SD bit of mstatus upon the register read

Per RISC-V ISA Manual, vol II, section 3.1.6.6, page 26, the SD bit is
a read-only bit indicating whether any of FS, VS, and XS fields being
in the respective dirty state.

Per section 3.1.6, page 20, the SD bit is the most significant bit of
the mstatus register for both RV32 and RV64.

Per section 3.1.6.6, page 29, the explicit formula for updating the SD is,
SD = ((FS==DIRTY) | (XS==DIRTY) | (VS==DIRTY))

Previously in gem5, this bit is not updated anywhere in the gem5
implementation. This cause an issue of incorrectly saving the context
before entering the system call and consequently, incorecttly restoring
the context after a system call as described here [1].

Ideally, we want to update the SD after every relevant instruction;
however, lazily updating the Status register upon its read produces
the same effect.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/65272/

Change-Id: I1db0cc619d43bc5bacb1d03f6f214345d9d90e28
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65273
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa.cc
1 file changed, 58 insertions(+), 0 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index e215e24..c76bb2b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -348,6 +348,29 @@
 else
 return mbits(val, 63, 1);
 }
+  case MISCREG_STATUS:
+{
+// Updating the SD bit.
+// . Per RISC-V ISA Manual, vol II, section 3.1.6.6, page 26,
+// the SD bit is a read-only bit indicating whether any of
+// FS, VS, and XS fields being in the respective dirty state.
+// . Per section 3.1.6, page 20, the SD bit is the most
+// significant bit of the MSTATUS CSR for both RV32 and RV64.
+// . Per section 3.1.6.6, page 29, the explicit formula for
+// updating the SD is,
+//   SD = ((FS==DIRTY) | (XS==DIRTY) | (VS==DIRTY))
+// . Ideally, we want to update the SD after every relevant
+// instruction, however, lazily updating the Status register
+// upon its read produces the same effect as well.
+STATUS status = readMiscRegNoEffect(idx);
+uint64_t sd_bit = \
+(status.xs == 3) || (status.fs == 3) || (status.vs == 3);
+// We assume RV64 here, updating the SD bit at index 63.
+status.sd = sd_bit;
+setMiscRegNoEffect(idx, status);
+
+return readMiscRegNoEffect(idx);
+}
   default:
 // Try reading HPM counters
 // As a placeholder, all HPM counters are just cycle counters

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Gerrit-Change-Number: 65273
Gerrit-PatchSet: 6
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Gerrit-Reviewer: kokoro 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Update FS field of mstatus register where approriate.

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65272?usp=email )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch-riscv: Update FS field of mstatus register where  
approriate.

..

arch-riscv: Update FS field of mstatus register where approriate.

Per RISC-V ISA Manual, vol II, section 3.1.6.6, page 25, the
FS field of the mstatus register encodes the status of the floating
point unit, including the floating point registers. Per page 27,
microarchitecture can choose to set the FS field to Dirty even if
the floating point unit has not been modified.

Per section 3.1.6, page 20, the FS field is located at bits 14..13
of the mstatus register.

Per section 3.1.6.6, page 27, the FS field is used for saving
context.

Upon a system call, the Linux kernel relies on mstatus for
choosing registers to save for switching to kernel code.
In particular, if the SD bit (updating this bit is also a bug
in gem5 and will be explained in the next commit) is not set
properly due to the FS field being incorrect, the process of saving
the context and restoring the context result in the floating
point registers being zeroed out. I.e., upon the saving context
function call, the floating point registers are not saved, while
in restore context function call, the floating point registers
are overwritten with zero bits.

Previously, in gem5 RISC-V ISA, the FS field is not updated upon
floating point instruction execution. This caused issue on context
saving described above.

This change conservatively updates the FS field to Dirty on
the execution of any floating point instruction.

Change-Id: I8b3b4922e8da483cff3a2210ee80c163cace182a
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65272
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa/formats/fp.isa
1 file changed, 47 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa/formats/fp.isa  
b/src/arch/riscv/isa/formats/fp.isa

index 65e81cd..d0bd245 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -40,6 +40,9 @@
 if (status.fs == FPUStatus::OFF)
 return std::make_shared("FPU is off",  
machInst);


+status.fs = FPUStatus::DIRTY;
+xc->setMiscReg(MISCREG_STATUS, status);
+
 %(op_decl)s;
 %(op_rd)s;


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Gerrit-Change-Number: 65272
Gerrit-PatchSet: 4
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Gerrit-Reviewer: kokoro 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add VS field to the STATUS CSR

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65274?usp=email )


Change subject: arch-riscv: Add VS field to the STATUS CSR
..

arch-riscv: Add VS field to the STATUS CSR

Per RISC-V ISA Manual, vol II, section 3.1.6, page 20, the VS field
is located at bits 10..9 of mstatus. Per section 4.1.1, page 63,
the VS field is located at the same bits of sstatus.

Change-Id: Ifda1c551a23ed892fb8ac7ef31fa98f0b6db
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65274
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/regs/misc.hh
1 file changed, 30 insertions(+), 10 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh
index cb8c907..5f07447 100644
--- a/src/arch/riscv/regs/misc.hh
+++ b/src/arch/riscv/regs/misc.hh
@@ -562,6 +562,7 @@
 Bitfield<16, 15> xs;
 Bitfield<14, 13> fs;
 Bitfield<12, 11> mpp;
+Bitfield<10, 9> vs;
 Bitfield<8> spp;
 Bitfield<7> mpie;
 Bitfield<5> spie;
@@ -612,6 +613,7 @@
 const RegVal STATUS_XS_MASK = 3ULL << 15;
 const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET;
 const RegVal STATUS_MPP_MASK = 3ULL << 11;
+const RegVal STATUS_VS_MASK = 3ULL << 9;
 const RegVal STATUS_SPP_MASK = 1ULL << 8;
 const RegVal STATUS_MPIE_MASK = 1ULL << 7;
 const RegVal STATUS_SPIE_MASK = 1ULL << 5;
@@ -624,21 +626,21 @@
 STATUS_TW_MASK | STATUS_TVM_MASK |
 STATUS_MXR_MASK | STATUS_SUM_MASK |
 STATUS_MPRV_MASK | STATUS_XS_MASK |
-STATUS_FS_MASK | STATUS_MPP_MASK |
-STATUS_SPP_MASK | STATUS_MPIE_MASK |
-STATUS_SPIE_MASK | STATUS_UPIE_MASK |
-STATUS_MIE_MASK | STATUS_SIE_MASK |
-STATUS_UIE_MASK;
+STATUS_FS_MASK | STATUS_VS_MASK |
+STATUS_MPP_MASK | STATUS_SPP_MASK |
+STATUS_MPIE_MASK | STATUS_SPIE_MASK |
+STATUS_UPIE_MASK | STATUS_MIE_MASK |
+STATUS_SIE_MASK | STATUS_UIE_MASK;
 const RegVal SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
 STATUS_MXR_MASK | STATUS_SUM_MASK |
 STATUS_XS_MASK | STATUS_FS_MASK |
-STATUS_SPP_MASK | STATUS_SPIE_MASK |
-STATUS_UPIE_MASK | STATUS_SIE_MASK |
-STATUS_UIE_MASK;
+STATUS_VS_MASK | STATUS_SPP_MASK |
+STATUS_SPIE_MASK | STATUS_UPIE_MASK |
+STATUS_SIE_MASK | STATUS_UIE_MASK;
 const RegVal USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
 STATUS_SUM_MASK | STATUS_XS_MASK |
-STATUS_FS_MASK | STATUS_UPIE_MASK |
-STATUS_UIE_MASK;
+STATUS_FS_MASK | STATUS_VS_MASK |
+STATUS_UPIE_MASK | STATUS_UIE_MASK;

 const RegVal MEI_MASK = 1ULL << 11;
 const RegVal SEI_MASK = 1ULL << 9;

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Gerrit-Change-Number: 65274
Gerrit-PatchSet: 2
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Gerrit-Reviewer: Hoa Nguyen 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Change the default kernel boot param from "ro" to "rw"

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65194?usp=email )


Change subject: stdlib: Change the default kernel boot param from "ro"  
to "rw"

..

stdlib: Change the default kernel boot param from "ro" to "rw"

Running workloads likely causes some content to be written to
the disk image, e.g., `m5 readfile`. However, on riscv boards,
the default kernel param specifies the disk image to be read-only.

This change changes this param so that the disk image is
read-write by default.

Change-Id: I414e483ad11d747f34433560e32a8f91a425ce7e
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65194
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/gem5/components/boards/experimental/lupv_board.py
M src/python/gem5/components/boards/riscv_board.py
M src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
3 files changed, 24 insertions(+), 3 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/python/gem5/components/boards/experimental/lupv_board.py  
b/src/python/gem5/components/boards/experimental/lupv_board.py

index ba65ccb..5624712 100644
--- a/src/python/gem5/components/boards/experimental/lupv_board.py
+++ b/src/python/gem5/components/boards/experimental/lupv_board.py
@@ -536,7 +536,7 @@

 @overrides(KernelDiskWorkload)
 def get_default_kernel_args(self) -> List[str]:
-return ["console=ttyLIO0", "root={root_value}", "ro"]
+return ["console=ttyLIO0", "root={root_value}", "rw"]

 @overrides(KernelDiskWorkload)
 def get_disk_device(self) -> str:
diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index d83b85e..15ec57a 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -494,4 +494,4 @@

 @overrides(KernelDiskWorkload)
 def get_default_kernel_args(self) -> List[str]:
-return ["console=ttyS0", "root={root_value}", "ro"]
+return ["console=ttyS0", "root={root_value}", "rw"]
diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py  
b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py

index 469010c..4148c0a 100644
--- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
+++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
@@ -566,7 +566,7 @@

 @overrides(KernelDiskWorkload)
 def get_default_kernel_args(self) -> List[str]:
-return ["console=ttyS0", "root={root_value}", "ro"]
+return ["console=ttyS0", "root={root_value}", "rw"]

 @overrides(KernelDiskWorkload)
 def set_kernel_disk_workload(

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Gerrit-Change-Number: 65194
Gerrit-PatchSet: 2
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Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add VS field to the STATUS CSR

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65274?usp=email )



Change subject: arch-riscv: Add VS field to the STATUS CSR
..

arch-riscv: Add VS field to the STATUS CSR

Per RISC-V ISA Manual, vol II, section 3.1.6, page 20, the VS field
is located at bits 10..9 of mstatus. Per section 4.1.1, page 63,
the VS field is located at the same bits of sstatus.

Change-Id: Ifda1c551a23ed892fb8ac7ef31fa98f0b6db
Signed-off-by: Hoa Nguyen 
---
M src/arch/riscv/regs/misc.hh
1 file changed, 26 insertions(+), 10 deletions(-)



diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh
index cb8c907..5f07447 100644
--- a/src/arch/riscv/regs/misc.hh
+++ b/src/arch/riscv/regs/misc.hh
@@ -562,6 +562,7 @@
 Bitfield<16, 15> xs;
 Bitfield<14, 13> fs;
 Bitfield<12, 11> mpp;
+Bitfield<10, 9> vs;
 Bitfield<8> spp;
 Bitfield<7> mpie;
 Bitfield<5> spie;
@@ -612,6 +613,7 @@
 const RegVal STATUS_XS_MASK = 3ULL << 15;
 const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET;
 const RegVal STATUS_MPP_MASK = 3ULL << 11;
+const RegVal STATUS_VS_MASK = 3ULL << 9;
 const RegVal STATUS_SPP_MASK = 1ULL << 8;
 const RegVal STATUS_MPIE_MASK = 1ULL << 7;
 const RegVal STATUS_SPIE_MASK = 1ULL << 5;
@@ -624,21 +626,21 @@
 STATUS_TW_MASK | STATUS_TVM_MASK |
 STATUS_MXR_MASK | STATUS_SUM_MASK |
 STATUS_MPRV_MASK | STATUS_XS_MASK |
-STATUS_FS_MASK | STATUS_MPP_MASK |
-STATUS_SPP_MASK | STATUS_MPIE_MASK |
-STATUS_SPIE_MASK | STATUS_UPIE_MASK |
-STATUS_MIE_MASK | STATUS_SIE_MASK |
-STATUS_UIE_MASK;
+STATUS_FS_MASK | STATUS_VS_MASK |
+STATUS_MPP_MASK | STATUS_SPP_MASK |
+STATUS_MPIE_MASK | STATUS_SPIE_MASK |
+STATUS_UPIE_MASK | STATUS_MIE_MASK |
+STATUS_SIE_MASK | STATUS_UIE_MASK;
 const RegVal SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
 STATUS_MXR_MASK | STATUS_SUM_MASK |
 STATUS_XS_MASK | STATUS_FS_MASK |
-STATUS_SPP_MASK | STATUS_SPIE_MASK |
-STATUS_UPIE_MASK | STATUS_SIE_MASK |
-STATUS_UIE_MASK;
+STATUS_VS_MASK | STATUS_SPP_MASK |
+STATUS_SPIE_MASK | STATUS_UPIE_MASK |
+STATUS_SIE_MASK | STATUS_UIE_MASK;
 const RegVal USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
 STATUS_SUM_MASK | STATUS_XS_MASK |
-STATUS_FS_MASK | STATUS_UPIE_MASK |
-STATUS_UIE_MASK;
+STATUS_FS_MASK | STATUS_VS_MASK |
+STATUS_UPIE_MASK | STATUS_UIE_MASK;

 const RegVal MEI_MASK = 1ULL << 11;
 const RegVal SEI_MASK = 1ULL << 9;

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Updating the SD bit of mstatus upon the register read

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65273?usp=email )



Change subject: arch-riscv: Updating the SD bit of mstatus upon the  
register read

..

arch-riscv: Updating the SD bit of mstatus upon the register read

Per RISC-V ISA Manual, vol II, section 3.1.6.6, page 26, the SD bit is
a read-only bit indicating whether any of FS, VS, and XS fields being
in the respective dirty state.

Per section 3.1.6, page 20, the SD bit is the most significant bit of
the mstatus register for both RV32 and RV64.

Per section 3.1.6.6, page 29, the explicit formula for updating the SD is,
SD = ((FS==DIRTY) | (XS==DIRTY) | (VS==DIRTY))

Previously in gem5, this bit is not updated anywhere in the gem5
implementation. This cause an issue of incorrectly saving the context
before entering the system call and consequently, incorecttly restoring
the context after a system call as described here [1].

Ideally, we want to update the SD after every relevant instruction;
however, lazily updating the Status register upon its read produces
the same effect.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/65272/

Change-Id: I1db0cc619d43bc5bacb1d03f6f214345d9d90e28
Signed-off-by: Hoa Nguyen 
---
M src/arch/riscv/isa.cc
1 file changed, 57 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index e215e24..15a0beb 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -348,6 +348,32 @@
 else
 return mbits(val, 63, 1);
 }
+  case MISCREG_STATUS:
+{
+// Updating the SD bit.
+// . Per RISC-V ISA Manual, vol II, section 3.1.6.6, page 26,
+// the SD bit is a read-only bit indicating whether any of
+// FS, VS, and XS fields being in the respective dirty state.
+// . Per section 3.1.6, page 20, the SD bit is the most
+// significant bit of the MSTATUS CSR for both RV32 and RV64.
+// . Per section 3.1.6.6, page 29, the explicit formula for
+// updating the SD is,
+//   SD = ((FS==DIRTY) | (XS==DIRTY) | (VS==DIRTY))
+// . Ideally, we want to update the SD after every relevant
+// instruction, however, lazily updating the Status register
+// upon its read produces the same effect as well.
+auto status = readMiscRegNoEffect(idx);
+uint64_t xs_bits = bits(status, 16, 15);
+uint64_t fs_bits = bits(status, 14, 13);
+uint64_t vs_bits = bits(status, 10, 9);
+uint64_t sd_bit = \
+(xs_bits == 3) | (fs_bits == 3) | (vs_bits == 3);
+// We assume RV64 here, updating the SD bit at index 63.
+replaceBits(status, 63, 63, sd_bit);
+setMiscReg(idx, status)
+
+return readMiscRegNoEffect(idx);
+}
   default:
 // Try reading HPM counters
 // As a placeholder, all HPM counters are just cycle counters

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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Update FS field of mstatus register where approriate.

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65272?usp=email )



Change subject: arch-riscv: Update FS field of mstatus register where  
approriate.

..

arch-riscv: Update FS field of mstatus register where approriate.

Per RISC-V ISA Manual, vol II, section 3.1.6.6, page 25, the
FS field of the mstatus register encodes the status of the floating
point unit, including the floating point registers. Per page 27,
microarchitecture can choose to set the FS field to Dirty even if
the floating point unit has not been modified.

Per section 3.1.6, page 20, the FS field is located at bits 14..13
of the mstatus register.

Per section 3.1.6.6, page 27, the FS field is used for saving
context.

Upon a system call, the Linux kernel relies on mstatus for
choosing registers to save for switching to kernel code.
In particular, if the SD bit (updating this bit is also a bug
in gem5 and will be explained in the next commit) is not set
properly due to the FS field is incorrect, the process of saving
the context and restoring the context result in the floating
point registers being zeroed out. I.e., upon the saving context
function call, the floating point registers are not saved, while
in restore context function call, the floating point registers
are overwritten with zero bits.

Previously, in gem5 RISC-V ISA, the FS field is not updated upon
floating point instruction execution. This caused issue on context
saving described above.

This change conservatively updates the FS field to Dirty on
the execution of any floating point instruction.

Change-Id: I8b3b4922e8da483cff3a2210ee80c163cace182a
Signed-off-by: Hoa Nguyen 
---
M src/arch/riscv/isa/formats/fp.isa
1 file changed, 43 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/isa/formats/fp.isa  
b/src/arch/riscv/isa/formats/fp.isa

index 65e81cd..d0bd245 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -40,6 +40,9 @@
 if (status.fs == FPUStatus::OFF)
 return std::make_shared("FPU is off",  
machInst);


+status.fs = FPUStatus::DIRTY;
+xc->setMiscReg(MISCREG_STATUS, status);
+
 %(op_decl)s;
 %(op_rd)s;


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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Change the default kernel boot param from "ro" to "rw"

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65194?usp=email )



Change subject: stdlib: Change the default kernel boot param from "ro"  
to "rw"

..

stdlib: Change the default kernel boot param from "ro" to "rw"

Running workloads likely causes some content to be written to
the disk image, e.g., `m5 readfile`. However, on riscv boards,
the default kernel param specifies the disk image to be read-only.

This change changes this param so that the disk image is
read-write by default.

Change-Id: I414e483ad11d747f34433560e32a8f91a425ce7e
Signed-off-by: Hoa Nguyen 
---
M src/python/gem5/components/boards/experimental/lupv_board.py
M src/python/gem5/components/boards/riscv_board.py
M src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
3 files changed, 20 insertions(+), 3 deletions(-)



diff --git a/src/python/gem5/components/boards/experimental/lupv_board.py  
b/src/python/gem5/components/boards/experimental/lupv_board.py

index ba65ccb..5624712 100644
--- a/src/python/gem5/components/boards/experimental/lupv_board.py
+++ b/src/python/gem5/components/boards/experimental/lupv_board.py
@@ -536,7 +536,7 @@

 @overrides(KernelDiskWorkload)
 def get_default_kernel_args(self) -> List[str]:
-return ["console=ttyLIO0", "root={root_value}", "ro"]
+return ["console=ttyLIO0", "root={root_value}", "rw"]

 @overrides(KernelDiskWorkload)
 def get_disk_device(self) -> str:
diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index d83b85e..15ec57a 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -494,4 +494,4 @@

 @overrides(KernelDiskWorkload)
 def get_default_kernel_args(self) -> List[str]:
-return ["console=ttyS0", "root={root_value}", "ro"]
+return ["console=ttyS0", "root={root_value}", "rw"]
diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py  
b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py

index 469010c..4148c0a 100644
--- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
+++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
@@ -566,7 +566,7 @@

 @overrides(KernelDiskWorkload)
 def get_default_kernel_args(self) -> List[str]:
-return ["console=ttyS0", "root={root_value}", "ro"]
+return ["console=ttyS0", "root={root_value}", "rw"]

 @overrides(KernelDiskWorkload)
 def set_kernel_disk_workload(

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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: Fix the command in the comment of arm-hello.py

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58830 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: configs: Fix the command in the comment of arm-hello.py
..

configs: Fix the command in the comment of arm-hello.py

Change-Id: I5e020e066c0f6792077fbf2ef65b7f90bb9c37f9
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58830
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M configs/example/gem5_library/arm-hello.py
1 file changed, 15 insertions(+), 1 deletion(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/arm-hello.py  
b/configs/example/gem5_library/arm-hello.py

index 3faa3ed..264731f 100644
--- a/configs/example/gem5_library/arm-hello.py
+++ b/configs/example/gem5_library/arm-hello.py
@@ -37,7 +37,7 @@

 ```
 scons build/ARM/gem5.opt
-./build/ARM/gem5.opt configs/gem5_library/arm-hello.py
+./build/ARM/gem5.opt configs/example/gem5_library/arm-hello.py
 ```
 """


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Gerrit-Change-Number: 58830
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
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Gerrit-Reviewer: Hoa Nguyen 
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib, configs: Fix riscv-ubuntu-run error

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58889 )


Change subject: stdlib, configs: Fix riscv-ubuntu-run error
..

stdlib, configs: Fix riscv-ubuntu-run error

This change,
https://gem5-review.googlesource.com/c/public/gem5/+/58790,
mistakenly constructs the root object outside of the
Simulator object, which would create another Root object.

The correct usage of a Simulator object is to pass the board to
the object without defining the root.

Change-Id: Iaa9aabe058a00abd964bf935b1b3f05456713275
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58889
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/example/gem5_library/riscv-ubuntu-run.py
1 file changed, 22 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/riscv-ubuntu-run.py  
b/configs/example/gem5_library/riscv-ubuntu-run.py

index 1c95d3f..f3e6d13 100644
--- a/configs/example/gem5_library/riscv-ubuntu-run.py
+++ b/configs/example/gem5_library/riscv-ubuntu-run.py
@@ -115,7 +115,5 @@
 ),
 )

-root = Root(full_system=True, system=board)
-
 simulator = Simulator(board=board)
 simulator.run()

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Gerrit-Change-Number: 58889
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib, configs: Fix riscv-ubuntu-run error

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58889 )



Change subject: stdlib, configs: Fix riscv-ubuntu-run error
..

stdlib, configs: Fix riscv-ubuntu-run error

This change,
https://gem5-review.googlesource.com/c/public/gem5/+/58790,
mistakenly constructs the root object outside of the
Simulator object, which would create another Root object.

The correct usage of a Simulator object is to pass the board to
the object without defining the root.

Change-Id: Iaa9aabe058a00abd964bf935b1b3f05456713275
Signed-off-by: Hoa Nguyen 
---
M configs/example/gem5_library/riscv-ubuntu-run.py
1 file changed, 18 insertions(+), 2 deletions(-)



diff --git a/configs/example/gem5_library/riscv-ubuntu-run.py  
b/configs/example/gem5_library/riscv-ubuntu-run.py

index 1c95d3f..f3e6d13 100644
--- a/configs/example/gem5_library/riscv-ubuntu-run.py
+++ b/configs/example/gem5_library/riscv-ubuntu-run.py
@@ -115,7 +115,5 @@
 ),
 )

-root = Root(full_system=True, system=board)
-
 simulator = Simulator(board=board)
 simulator.run()

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Gerrit-Change-Id: Iaa9aabe058a00abd964bf935b1b3f05456713275
Gerrit-Change-Number: 58889
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Allow riscv-board to take more than 1 disk image

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58791 )



Change subject: stdlib: Allow riscv-board to take more than 1 disk image
..

stdlib: Allow riscv-board to take more than 1 disk image

This is done by,
- Decoupling (PIO/VirtIO devices connection/device tree generation) and
the (set disk image workload function).
- Creating an abstract method for finializing all connections and device
tree generation in KernelDiskWorkload.
- The board now takes the `addtional_disk_array` parameter, which contains
a list of disk image resources. Those images should not be mounted during
kernel booting.
- The old `disk_image` parameter will now become the root disk image param.
This disk image should be mounted as '/' by the kernel.

Change-Id: I560496a4db5b4d91d3e3e90901487d8d40bf581b
Signed-off-by: Hoa Nguyen 
---
M src/python/gem5/components/boards/kernel_disk_workload.py
M src/python/gem5/components/boards/riscv_board.py
2 files changed, 85 insertions(+), 26 deletions(-)



diff --git a/src/python/gem5/components/boards/kernel_disk_workload.py  
b/src/python/gem5/components/boards/kernel_disk_workload.py

index 031fc60..bfd5aa6 100644
--- a/src/python/gem5/components/boards/kernel_disk_workload.py
+++ b/src/python/gem5/components/boards/kernel_disk_workload.py
@@ -97,6 +97,17 @@
 """
 raise NotImplementedError

+@abstractmethod
+def _finalize_workload(self) -> None:
+"""
+Finalizes the board setup dependent on the workload.
+This function connects the IO devices to the board, generates the
+device tree and expose the location of the dtb to the gem5's  
workload
+object. This function should be called after all IO devices are  
set up

+(e.g. disk images, PIO devices.)
+"""
+raise NotImplementedError
+
 def get_disk_root_partition(
 cls, disk_image: AbstractResource
 ) -> Optional[str]:
@@ -132,7 +143,8 @@
 def set_kernel_disk_workload(
 self,
 kernel: AbstractResource,
-disk_image: AbstractResource,
+root_disk_image: AbstractResource,
+additional_disk_array: List[AbstractResource],
 readfile: Optional[str] = None,
 readfile_contents: Optional[str] = None,
 kernel_args: Optional[List[str]] = None,
@@ -143,7 +155,10 @@
 and a disk image.

 :param kernel: The kernel to boot.
-:param disk_image: The disk image to mount.
+:param root_disk_image: The disk image containing the '/' mount  
point.

+:param additional_disk_array: An array of disk images to be mount
+manually (they are not mounted at durring the Linux kernel booting
+process).
 :param readfile: An optional parameter stating the file to be read  
by

 by `m5 readfile`.
 :param readfile_contents: An optional parameter stating the  
contents of

@@ -163,7 +178,9 @@
 self.workload.command_line = (
 " ".join(kernel_args or self.get_default_kernel_args())
 ).format(
- 
root_value=self.get_default_kernel_root_val(disk_image=disk_image)

+root_value=self.get_default_kernel_root_val(
+disk_image=root_disk_image
+)
 )

 # Set the readfile.
@@ -178,7 +195,12 @@
 file.write(readfile_contents)
 file.close()

-self._add_disk_to_board(disk_image=disk_image)
+self._add_disk_to_board(disk_image=root_disk_image)
+for disk_image in additional_disk_array:
+self._add_disk_to_board(disk_image=disk_image)
+
+# Finalize the setup after all components of the workload are set.
+self._finalize_workload()

 # Set whether to exit on work items.
-self.exit_on_work_items = exit_on_work_items
\ No newline at end of file
+self.exit_on_work_items = exit_on_work_items
diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index f72b31d..b227b39 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -116,12 +116,7 @@
 self.iobus.default = self.iobus.badaddr_responder.pio

 # The virtio disk
-self.disk = RiscvMmioVirtIO(
-vio=VirtIOBlock(),
-interrupt_id=0x8,
-pio_size=4096,
-pio_addr=0x10008000,
-)
+self.disk_array = []

 # The virtio rng
 self.rng = RiscvMmioVirtIO(
@@ -134,7 +129,8 @@
 # Note: This overrides the platform's code because the platform  
isn't

 # general enough.
 self._on_chip_devices = [self.platform.clint, self.platform.plic]
-self._off_chip_devices = [self.platform.uart, self.disk, self.rng]
+self._off_chip_devices = [self.platform.uart, 

[gem5-dev] [S] Change in gem5/gem5[develop]: configs: Fix the command in the comment of arm-hello.py

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58830 )



Change subject: configs: Fix the command in the comment of arm-hello.py
..

configs: Fix the command in the comment of arm-hello.py

Change-Id: I5e020e066c0f6792077fbf2ef65b7f90bb9c37f9
Signed-off-by: Hoa Nguyen 
---
M configs/example/gem5_library/arm-hello.py
1 file changed, 11 insertions(+), 1 deletion(-)



diff --git a/configs/example/gem5_library/arm-hello.py  
b/configs/example/gem5_library/arm-hello.py

index 3faa3ed..264731f 100644
--- a/configs/example/gem5_library/arm-hello.py
+++ b/configs/example/gem5_library/arm-hello.py
@@ -37,7 +37,7 @@

 ```
 scons build/ARM/gem5.opt
-./build/ARM/gem5.opt configs/gem5_library/arm-hello.py
+./build/ARM/gem5.opt configs/example/gem5_library/arm-hello.py
 ```
 """


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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib, configs: Add examples of saving/restoring checkpoints

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58829 )



Change subject: stdlib, configs: Add examples of saving/restoring  
checkpoints

..

stdlib, configs: Add examples of saving/restoring checkpoints

This change consists of two scripts,
- riscv-hello-save-checkpoint.py: runs the first million ticks of the
simulation and save a checkpoint.
- riscv-hello-load-checkpoint.py: loads the above checkpoint, and runs
the rest of the simulation.

Change-Id: I7bd97ba953fab52f298cbbcf213f2ea5c185cc38
Signed-off-by: Hoa Nguyen 
---
A configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py
A configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
2 files changed, 231 insertions(+), 0 deletions(-)



diff --git  
a/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py  
b/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py

new file mode 100644
index 000..a7e1d52
--- /dev/null
+++  
b/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py

@@ -0,0 +1,108 @@
+# Copyright (c) 2022 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This gem5 configuation script creates a simple board sharing the same
+structure as the one in
+configs/example/gem5_library/checkpoint/riscv-hello-save-checkpoint.py.
+This script restores the checkpoint generated by the above script, and
+runs the rest of "riscv-hello" binary simulation.
+This configuration serves as an example of restoring a checkpoint.
+
+This is setup is the close to the simplest setup possible using the gem5
+library. It does not contain any kind of caching, IO, or any non-essential
+components.
+
+Usage
+-
+
+```
+scons build/RISCV/gem5.opt
+./build/RISCV/gem5.opt \
+ 
configs/example/gem5_library/checkpoint/riscv-hello-restore-checkpoint.py

+```
+"""
+
+from gem5.isas import ISA
+from gem5.utils.requires import requires
+from gem5.resources.resource import Resource
+from gem5.components.memory import SingleChannelDDR3_1600
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.boards.simple_board import SimpleBoard
+from gem5.components.cachehierarchies.classic.no_cache import NoCache
+from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.simulate.simulator import Simulator
+
+# This check ensures the gem5 binary is compiled to the RISCV ISA target.
+# If not, an exception will be thrown.
+requires(isa_required=ISA.RISCV)
+
+# In this setup we don't have a cache. `NoCache` can be used for such  
setups.

+cache_hierarchy = NoCache()
+
+# We use a single channel DDR3_1600 memory system
+memory = SingleChannelDDR3_1600(size="32MB")
+
+# We use a simple Timing processor with one core.
+processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.RISCV,
+num_cores=1)
+
+# The gem5 library simble board which can be used to run simple SE-mode
+# simulations.
+board = SimpleBoard(
+clk_freq="3GHz",
+processor=processor,
+memory=memory,
+cache_hierarchy=cache_hierarchy,
+)
+
+# Here we set the workload. In this case we want to run a simple "Hello  
World!"
+# program compiled to the RISCV ISA. The `Resource` class will  
automatically
+# download the binary from the gem5 Resources cloud bucket if it's not  
already

+# present.
+board.set_se_binary_workload(
+   

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib, configs: Migrate riscv-ubuntu-run example to Simulator

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58790 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: stdlib, configs: Migrate riscv-ubuntu-run example to  
Simulator

..

stdlib, configs: Migrate riscv-ubuntu-run example to Simulator

Change-Id: Ie08fcf46139871bc98b9bf783d0b4d9913eace3e
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58790
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Bobby Bruce 
Maintainer: Jason Lowe-Power 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M configs/example/gem5_library/riscv-ubuntu-run.py
1 file changed, 19 insertions(+), 29 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/riscv-ubuntu-run.py  
b/configs/example/gem5_library/riscv-ubuntu-run.py

index d54fa90..1c95d3f 100644
--- a/configs/example/gem5_library/riscv-ubuntu-run.py
+++ b/configs/example/gem5_library/riscv-ubuntu-run.py
@@ -53,6 +53,7 @@
 from gem5.isas import ISA
 from gem5.coherence_protocol import CoherenceProtocol
 from gem5.resources.resource import Resource
+from gem5.simulate.simulator import Simulator

 # This runs a check to ensure the gem5 binary is compiled for RISCV.

@@ -116,32 +117,5 @@

 root = Root(full_system=True, system=board)

-m5.instantiate()
-
-# We simulate the system till we encounter `m5_exit instruction  
encountered`.

-
-exit_event = m5.simulate()
-
-# We check whether the simulation ended with `m5_exit instruction  
encountered`

-
-if exit_event.getCause() == "m5_exit instruction encountered":
-# We acknowledge the user that the boot was successful.
-
-print("Successfully completed booting!")
-else:
-# `m5_exit instruction encountered` was never encountered. We exit the
-# program unsuccessfully.
-
-print("The startup was not completed successfully!",)
-print(
-"Exiting @ tick {} because {}."\
-.format(m5.curTick(), exit_event.getCause())
-)
-exit(-1)
-
-# We are done with the simulation. We exit the program now.
-
-print(
-"Exiting @ tick {} because {}."\
-.format(m5.curTick(), exit_event.getCause())
-)
+simulator = Simulator(board=board)
+simulator.run()

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie08fcf46139871bc98b9bf783d0b4d9913eace3e
Gerrit-Change-Number: 58790
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib, configs: Migrate riscv-ubuntu-run example to Simulator

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58790 )



Change subject: stdlib, configs: Migrate riscv-ubuntu-run example to  
Simulator

..

stdlib, configs: Migrate riscv-ubuntu-run example to Simulator

Change-Id: Ie08fcf46139871bc98b9bf783d0b4d9913eace3e
Signed-off-by: Hoa Nguyen 
---
M configs/example/gem5_library/riscv-ubuntu-run.py
1 file changed, 13 insertions(+), 29 deletions(-)



diff --git a/configs/example/gem5_library/riscv-ubuntu-run.py  
b/configs/example/gem5_library/riscv-ubuntu-run.py

index d54fa90..1c95d3f 100644
--- a/configs/example/gem5_library/riscv-ubuntu-run.py
+++ b/configs/example/gem5_library/riscv-ubuntu-run.py
@@ -53,6 +53,7 @@
 from gem5.isas import ISA
 from gem5.coherence_protocol import CoherenceProtocol
 from gem5.resources.resource import Resource
+from gem5.simulate.simulator import Simulator

 # This runs a check to ensure the gem5 binary is compiled for RISCV.

@@ -116,32 +117,5 @@

 root = Root(full_system=True, system=board)

-m5.instantiate()
-
-# We simulate the system till we encounter `m5_exit instruction  
encountered`.

-
-exit_event = m5.simulate()
-
-# We check whether the simulation ended with `m5_exit instruction  
encountered`

-
-if exit_event.getCause() == "m5_exit instruction encountered":
-# We acknowledge the user that the boot was successful.
-
-print("Successfully completed booting!")
-else:
-# `m5_exit instruction encountered` was never encountered. We exit the
-# program unsuccessfully.
-
-print("The startup was not completed successfully!",)
-print(
-"Exiting @ tick {} because {}."\
-.format(m5.curTick(), exit_event.getCause())
-)
-exit(-1)
-
-# We are done with the simulation. We exit the program now.
-
-print(
-"Exiting @ tick {} because {}."\
-.format(m5.curTick(), exit_event.getCause())
-)
+simulator = Simulator(board=board)
+simulator.run()

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ie08fcf46139871bc98b9bf783d0b4d9913eace3e
Gerrit-Change-Number: 58790
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Add checkpoint to Simulator

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58789 )



Change subject: stdlib: Add checkpoint to Simulator
..

stdlib: Add checkpoint to Simulator

Change-Id: I58b686b6b4f69260ab45709c6ef0bddf4539f0c4
Signed-off-by: Hoa Nguyen 
---
M src/python/gem5/simulate/simulator.py
1 file changed, 22 insertions(+), 1 deletion(-)



diff --git a/src/python/gem5/simulate/simulator.py  
b/src/python/gem5/simulate/simulator.py

index 1645dfc..7e5db87 100644
--- a/src/python/gem5/simulate/simulator.py
+++ b/src/python/gem5/simulate/simulator.py
@@ -32,6 +32,7 @@
 from m5.util import warn

 import os
+from pathlib import Path
 from typing import Optional, List, Tuple, Dict, Generator, Union

 from .exit_event_generators import (
@@ -76,6 +77,7 @@
 Dict[Union[str, ExitEvent], Generator[Optional[bool], None,  
None]]

 ] = None,
 expected_execution_order: Optional[List[ExitEvent]] = None,
+checkpoint_path: Optional[Path] = None,
 ) -> None:
 """
 :param board: The board to be simulated.
@@ -177,6 +179,8 @@
 self._last_exit_event = None
 self._exit_event_count = 0

+self._checkpoint_path = checkpoint_path
+
 def get_stats(self) -> Dict:
 """
 Obtain the current simulation statistics as a Dictionary,  
conforming

@@ -277,7 +281,10 @@
 m5.ticks.fixGlobalFrequency()
 root.sim_quantum = m5.ticks.fromSeconds(0.001)

-m5.instantiate()
+if self._checkpoint_path:
+m5.instantiate(self._checkpoint_path)
+else:
+m5.instantiate()
 self._instantiated = True

 def run(self, max_ticks: int = m5.MaxTick) -> None:
@@ -347,3 +354,7 @@
 # run loop.
 if exit_on_completion:
 return
+
+def save_checkpoint(self, checkpoint_folder: Path) -> None:
+m5.checkpoint(str(checkpoint_folder))
+

--
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Gerrit-Branch: develop
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Gerrit-Change-Number: 58789
Gerrit-PatchSet: 1
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[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add docker container for building riscv target

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57609 )


Change subject: util-docker: Add docker container for building riscv target
..

util-docker: Add docker container for building riscv target

This container comes with LLVM/Clang riscv cross-compiler
with linker, libraries, and libc headers from
riscv-gnu-toolchain[1].

Adapted from [2].

[1] https://github.com/lowRISC/riscv-llvm
[2] https://github.com/sifive/riscv-llvm/blob/dev/README.md

Signed-off-by: Hoa Nguyen 
Change-Id: I0bc310e1ae3ca9257fbde95a864c2b48009cd897
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57609
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M util/dockerfiles/docker-compose.yaml
A util/dockerfiles/llvm-gnu-cross-compiler-riscv64/Dockerfile
2 files changed, 102 insertions(+), 1 deletion(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/util/dockerfiles/docker-compose.yaml  
b/util/dockerfiles/docker-compose.yaml

index bcae58a..cbc8987 100644
--- a/util/dockerfiles/docker-compose.yaml
+++ b/util/dockerfiles/docker-compose.yaml
@@ -110,4 +110,8 @@
 args:
 - version=12
 image: gcr.io/gem5-test/clang-version-12
-
+llvm-gnu-cross-compiler-riscv64:
+build:
+context: llvm-gnu-cross-compiler-riscv64
+dockerfile: Dockerfile
+image: gcr.io/gem5-test/llvm-gnu-cross-compiler-riscv64
diff --git a/util/dockerfiles/llvm-gnu-cross-compiler-riscv64/Dockerfile  
b/util/dockerfiles/llvm-gnu-cross-compiler-riscv64/Dockerfile

new file mode 100644
index 000..ed06bf7
--- /dev/null
+++ b/util/dockerfiles/llvm-gnu-cross-compiler-riscv64/Dockerfile
@@ -0,0 +1,74 @@
+# Copyright (c) 2022 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+# stage 1: download the dependencies
+FROM ubuntu:20.04 AS stage1
+
+ENV DEBIAN_FRONTEND=noninteractive
+RUN apt -y update
+RUN apt -y upgrade
+RUN apt -y install \
+  binutils build-essential libtool texinfo gzip zip unzip patchutils curl  
git \

+  make cmake ninja-build automake bison flex gperf grep sed gawk bc \
+  zlib1g-dev libexpat1-dev libmpc-dev libglib2.0-dev libfdt-dev  
libpixman-1-dev

+
+# stage 2: download the compilers and compile them
+FROM stage1 AS stage2
+RUN mkdir -p /riscv/_install
+WORKDIR /riscv
+ENV PATH=`/riscv/_install/bin:$PATH`
+RUN git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
+WORKDIR /riscv/riscv-gnu-toolchain
+RUN git checkout --recurse-submodules  
051b9f7ddb7d136777505ea19c70a41926842b96

+RUN ./configure --prefix=/riscv/_install --enable-multilib
+RUN make linux -j`nproc`
+RUN make install
+
+WORKDIR /riscv
+RUN git clone https://github.com/llvm/llvm-project.git riscv-llvm
+WORKDIR /riscv/riscv-llvm
+RUN git checkout 2ef95efb414e215490a222de05cafdffb8054758
+RUN ln -s ../../clang llvm/tools || true
+RUN mkdir _build
+WORKDIR /riscv/riscv-llvm/_build
+RUN cmake -G Ninja -DCMAKE_BUILD_TYPE="Release" \
+  -DBUILD_SHARED_LIBS=True -DLLVM_USE_SPLIT_DWARF=True \
+  -DCMAKE_INSTALL_PREFIX="/riscv/_install" \
+  -DLLVM_OPTIMIZED_TABLEGEN=True -DLLVM_BUILD_TESTS=False \
+  -DDEFAULT_SYSROOT="/riscv/_install/sysroot" \
+  -DLLVM_DEFAULT_TARGET_TRIPLE="riscv64-unknown-linux-gnu" \
+  -DLLVM_TARGETS_TO_BUILD="RISCV" \
+  ../llvm
+RUN cmake --build . --target install -j`nproc`

[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add docker container for building riscv target

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57609 )



Change subject: util-docker: Add docker container for building riscv target
..

util-docker: Add docker container for building riscv target

This container comes with clang main branch and with
riscv-gnu-toolchain main branch as the back-end.

Signed-off-by: Hoa Nguyen 
Change-Id: I0bc310e1ae3ca9257fbde95a864c2b48009cd897
---
M util/dockerfiles/docker-compose.yaml
A util/dockerfiles/llvm-riscv-target/Dockerfile
2 files changed, 100 insertions(+), 1 deletion(-)



diff --git a/util/dockerfiles/docker-compose.yaml  
b/util/dockerfiles/docker-compose.yaml

index bcae58a..f25a021 100644
--- a/util/dockerfiles/docker-compose.yaml
+++ b/util/dockerfiles/docker-compose.yaml
@@ -110,4 +110,10 @@
 args:
 - version=12
 image: gcr.io/gem5-test/clang-version-12
-
+clang-dev-riscv-target:
+build:
+context: ubuntu-20.04_clang-version
+dockerfile: Dockerfile
+args:
+- version=dev-riscv-target
+image: gcr.io/gem5-test/clang-dev-riscv-target
diff --git a/util/dockerfiles/llvm-riscv-target/Dockerfile  
b/util/dockerfiles/llvm-riscv-target/Dockerfile

new file mode 100644
index 000..e403f5a
--- /dev/null
+++ b/util/dockerfiles/llvm-riscv-target/Dockerfile
@@ -0,0 +1,80 @@
+# Copyright (c) 2022 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+# stage 1: download the compilers and compile them
+FROM ubuntu:20.04 AS stage1
+
+ENV DEBIAN_FRONTEND=noninteractive
+RUN apt -y update
+RUN apt -y upgrade
+RUN apt -y install \
+  binutils build-essential libtool texinfo gzip zip unzip patchutils curl  
git \

+  make cmake ninja-build automake bison flex gperf grep sed gawk bc \
+  zlib1g-dev libexpat1-dev libmpc-dev libglib2.0-dev libfdt-dev  
libpixman-1-dev

+
+RUN mkdir -p /riscv/_install
+WORKDIR /riscv
+ENV PATH=`/riscv/_install/bin:$PATH`
+RUN git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
+WORKDIR /riscv/riscv-gnu-toolchain
+RUN ./configure --prefix=/riscv/_install --enable-multilib
+RUN make linux -j`nproc`
+RUN make install
+
+WORKDIR /riscv
+RUN git clone https://github.com/llvm/llvm-project.git riscv-llvm
+WORKDIR /riscv/riscv-llvm
+RUN ln -s ../../clang llvm/tools || true
+RUN mkdir _build
+WORKDIR /riscv/riscv-llvm/_build
+RUN cmake -G Ninja -DCMAKE_BUILD_TYPE="Release" \
+  -DBUILD_SHARED_LIBS=True -DLLVM_USE_SPLIT_DWARF=True \
+  -DCMAKE_INSTALL_PREFIX="/riscv/_install" \
+  -DLLVM_OPTIMIZED_TABLEGEN=True -DLLVM_BUILD_TESTS=False \
+  -DDEFAULT_SYSROOT="/riscv/_install/sysroot" \
+  -DLLVM_DEFAULT_TARGET_TRIPLE="riscv64-unknown-linux-gnu" \
+  -DLLVM_TARGETS_TO_BUILD="RISCV" \
+  ../llvm
+RUN cmake --build . --target install -j`nproc`
+
+
+
+# stage 2: create a new container with the compiled cross-compilers only
+FROM ubuntu:20.04
+ENV DEBIAN_FRONTEND=noninteractive
+RUN apt -y update
+RUN apt -y upgrade
+RUN apt -y install \
+  binutils build-essential libtool texinfo gzip zip unzip patchutils curl  
git \

+  make cmake ninja-build automake bison flex gperf grep sed gawk bc \
+  zlib1g-dev libexpat1-dev libmpc-dev libglib2.0-dev libfdt-dev  
libpixman-1-dev

+
+RUN mkdir -p /riscv/
+COPY --from=stage1 /riscv/_install/ /riscv/_install
+ENV PATH=/riscv/_install/bin:$PATH
+
+RUN mkdir -p /workdir

--
To view, visit 

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fix unit inconsistencies in base cache stats

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56989 )


Change subject: mem-cache: Fix unit inconsistencies in base cache stats
..

mem-cache: Fix unit inconsistencies in base cache stats

Most latency stats are described to have Cycle unit in the comments.
However, most of them are calculated from Tick.

Also, the unit of `demandAvgMissLatency` is incorrect.

Change-Id: Ib1b9b7c6fa4404cecb3982b3799753df19774623
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56989
Reviewed-by: Daniel Carvalho 
Maintainer: Daniel Carvalho 
Tested-by: kokoro 
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
2 files changed, 36 insertions(+), 17 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 435684a..cf6c9fe 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -,10 +,10 @@
 ADD_STAT(overallMissRate, statistics::units::Ratio::get(),
  "miss rate for overall accesses"),
 ADD_STAT(demandAvgMissLatency, statistics::units::Rate<
-statistics::units::Cycle, statistics::units::Count>::get(),
- "average overall miss latency"),
+statistics::units::Tick, statistics::units::Count>::get(),
+ "average overall miss latency in ticks"),
 ADD_STAT(overallAvgMissLatency, statistics::units::Rate<
-statistics::units::Cycle, statistics::units::Count>::get(),
+statistics::units::Tick, statistics::units::Count>::get(),
  "average overall miss latency"),
 ADD_STAT(blockedCycles, statistics::units::Cycle::get(),
 "number of cycles access was blocked"),
@@ -2257,13 +2257,13 @@
 ADD_STAT(overallMshrMissRate, statistics::units::Ratio::get(),
  "mshr miss ratio for overall accesses"),
 ADD_STAT(demandAvgMshrMissLatency, statistics::units::Rate<
-statistics::units::Cycle, statistics::units::Count>::get(),
+statistics::units::Tick, statistics::units::Count>::get(),
  "average overall mshr miss latency"),
 ADD_STAT(overallAvgMshrMissLatency, statistics::units::Rate<
-statistics::units::Cycle, statistics::units::Count>::get(),
+statistics::units::Tick, statistics::units::Count>::get(),
  "average overall mshr miss latency"),
 ADD_STAT(overallAvgMshrUncacheableLatency, statistics::units::Rate<
-statistics::units::Cycle, statistics::units::Count>::get(),
+statistics::units::Tick, statistics::units::Count>::get(),
  "average overall mshr uncacheable latency"),
 ADD_STAT(replacements, statistics::units::Count::get(),
  "number of replacements"),
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 0dc64e1..6fc7628 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -1006,12 +1006,12 @@
 @sa Packet::Command */
 statistics::Vector misses;
 /**
- * Total number of cycles per thread/command spent waiting for a  
hit.
+ * Total number of ticks per thread/command spent waiting for a  
hit.

  * Used to calculate the average hit latency.
  */
 statistics::Vector hitLatency;
 /**
- * Total number of cycles per thread/command spent waiting for a  
miss.
+ * Total number of ticks per thread/command spent waiting for a  
miss.

  * Used to calculate the average miss latency.
  */
 statistics::Vector missLatency;
@@ -1027,9 +1027,9 @@
 statistics::Vector mshrMisses;
 /** Number of misses that miss in the MSHRs, per command and  
thread. */

 statistics::Vector mshrUncacheable;
-/** Total cycle latency of each MSHR miss, per command and thread.  
*/
+/** Total tick latency of each MSHR miss, per command and thread.  
*/

 statistics::Vector mshrMissLatency;
-/** Total cycle latency of each MSHR miss, per command and thread.  
*/
+/** Total tick latency of each MSHR miss, per command and thread.  
*/

 statistics::Vector mshrUncacheableLatency;
 /** The miss rate in the MSHRs pre command and thread. */
 statistics::Formula mshrMissRate;
@@ -1055,9 +1055,9 @@
 statistics::Formula demandHits;
 /** Number of hit for all accesses. */
 statistics::Formula overallHits;
-/** Total number of cycles spent waiting for demand hits. */
+/** Total number of ticks spent waiting for demand hits. */
 statistics::Formula demandHitLatency;
-/** Total number of cycles spent waiting for all hits. */
+/** Total number of ticks spent waiting for all hits. */
 

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Remove unused stats

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57029 )



Change subject: mem-cache: Remove unused stats
..

mem-cache: Remove unused stats

hitLatency, demandHitLatency, and overallHitLatency are not used.

Change-Id: I55f4e3f357b8fba28ad878697260fddb38c9208e
Signed-off-by: Hoa Nguyen 
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
2 files changed, 12 insertions(+), 35 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index e268ae7..58a0f6c 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -2028,8 +2028,6 @@
("number of " + name + " hits").c_str()),
   ADD_STAT(misses, statistics::units::Count::get(),
("number of " + name + " misses").c_str()),
-  ADD_STAT(hitLatency, statistics::units::Tick::get(),
-   ("number of " + name + " hit ticks").c_str()),
   ADD_STAT(missLatency, statistics::units::Tick::get(),
("number of " + name + " miss ticks").c_str()),
   ADD_STAT(accesses, statistics::units::Count::get(),
@@ -2086,15 +2084,6 @@
 misses.subname(i, system->getRequestorName(i));
 }

-// Hit latency statistics
-hitLatency
-.init(max_requestors)
-.flags(total | nozero | nonan)
-;
-for (int i = 0; i < max_requestors; i++) {
-hitLatency.subname(i, system->getRequestorName(i));
-}
-
 // Miss latency statistics
 missLatency
 .init(max_requestors)
@@ -2201,10 +2190,6 @@
  "number of demand (read+write) hits"),
 ADD_STAT(overallHits, statistics::units::Count::get(),
  "number of overall hits"),
-ADD_STAT(demandHitLatency, statistics::units::Tick::get(),
- "number of demand (read+write) hit ticks"),
-ADD_STAT(overallHitLatency, statistics::units::Tick::get(),
-"number of overall hit ticks"),
 ADD_STAT(demandMisses, statistics::units::Count::get(),
  "number of demand (read+write) misses"),
 ADD_STAT(overallMisses, statistics::units::Count::get(),
@@ -2339,17 +2324,6 @@
 overallMissLatency.subname(i, system->getRequestorName(i));
 }

-demandHitLatency.flags(total | nozero | nonan);
-demandHitLatency = SUM_DEMAND(hitLatency);
-for (int i = 0; i < max_requestors; i++) {
-demandHitLatency.subname(i, system->getRequestorName(i));
-}
-overallHitLatency.flags(total | nozero | nonan);
-overallHitLatency = demandHitLatency + SUM_NON_DEMAND(hitLatency);
-for (int i = 0; i < max_requestors; i++) {
-overallHitLatency.subname(i, system->getRequestorName(i));
-}
-
 demandAccesses.flags(total | nozero | nonan);
 demandAccesses = demandHits + demandMisses;
 for (int i = 0; i < max_requestors; i++) {
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 6fc7628..51cd2d1 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -1006,11 +1006,6 @@
 @sa Packet::Command */
 statistics::Vector misses;
 /**
- * Total number of ticks per thread/command spent waiting for a  
hit.

- * Used to calculate the average hit latency.
- */
-statistics::Vector hitLatency;
-/**
  * Total number of ticks per thread/command spent waiting for a  
miss.

  * Used to calculate the average miss latency.
  */
@@ -1055,10 +1050,6 @@
 statistics::Formula demandHits;
 /** Number of hit for all accesses. */
 statistics::Formula overallHits;
-/** Total number of ticks spent waiting for demand hits. */
-statistics::Formula demandHitLatency;
-/** Total number of ticks spent waiting for all hits. */
-statistics::Formula overallHitLatency;

 /** Number of misses for demand accesses. */
 statistics::Formula demandMisses;

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I55f4e3f357b8fba28ad878697260fddb38c9208e
Gerrit-Change-Number: 57029
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[develop]: dev: Make VirtIORng device use gem5's rng instead of C++'s

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56889 )


Change subject: dev: Make VirtIORng device use gem5's rng instead of C++'s
..

dev: Make VirtIORng device use gem5's rng instead of C++'s

Currently, VirtIORng uses C++'s RNG. This causes nondeterminism
across simulations using this device. One example is the example RISC-V
board booting Ubuntu,

configs/example/gem5_library/riscv-ubuntu-run.py

JIRA: https://gem5.atlassian.net/browse/GEM5-1193

Change-Id: I299e72eb891819007b4260390f5c2ba94d2dec7b
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56889
Maintainer: Bobby Bruce 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/dev/virtio/VirtIORng.py
M src/dev/virtio/rng.cc
M src/dev/virtio/rng.hh
3 files changed, 29 insertions(+), 36 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/virtio/VirtIORng.py b/src/dev/virtio/VirtIORng.py
index 54848ee..13df059 100644
--- a/src/dev/virtio/VirtIORng.py
+++ b/src/dev/virtio/VirtIORng.py
@@ -46,5 +46,3 @@
 cxx_class = 'gem5::VirtIORng'

 qSize = Param.Unsigned(16, "Request queue size")
-
-entropy_source = Param.String("/dev/random", "The source of entropy")
diff --git a/src/dev/virtio/rng.cc b/src/dev/virtio/rng.cc
index 50a747c..c26568e 100644
--- a/src/dev/virtio/rng.cc
+++ b/src/dev/virtio/rng.cc
@@ -38,9 +38,7 @@

 #include "dev/virtio/rng.hh"

-#include 
-#include 
-
+#include "base/random.hh"
 #include "debug/VIORng.hh"
 #include "params/VirtIORng.hh"
 #include "sim/system.hh"
@@ -50,8 +48,7 @@

 VirtIORng::VirtIORng(const Params )
 : VirtIODeviceBase(params, ID_RNG, 0, 0),
-  qReq(params.system->physProxy, byteOrder, params.qSize,
-   params.entropy_source, *this)
+  qReq(params.system->physProxy, byteOrder, params.qSize, *this)
 {
 registerQueue(qReq);
 }
@@ -60,16 +57,10 @@
 {
 }

-VirtIORng::RngQueue::RngQueue(PortProxy , ByteOrder bo,
-uint16_t size, const std::string _file_path,
+VirtIORng::RngQueue::RngQueue(PortProxy , ByteOrder bo, uint16_t  
size,

 VirtIORng &_parent)
-: VirtQueue(proxy, bo, size), parent(_parent), dist(0,255)
+: VirtQueue(proxy, bo, size), parent(_parent)
 {
-rng_fd = open(rng_file_path.c_str(), O_RDONLY);
-if (rng_fd < 0) {
-DPRINTF(VIORng, "error when open entropy source: %s\n",
-rng_file_path.c_str());
-}
 }

 void
@@ -89,16 +80,7 @@
 DPRINTF(VIORng, "Got descriptor (len: %i)\n", d->size());
 size_t len = 0;
 while (len < d->size()) {
-uint8_t byte = 0;
-bool rng_read_success = false;
-if (rng_fd >= 0) {
-ssize_t result = read(rng_fd, , sizeof(uint8_t));
-rng_read_success = (result > 0);
-}
-if (!rng_read_success) {
-// fallback to C++ std rng generator
-byte = dist(rd_device);
-}
+uint8_t byte = gem5::random_mt.random();
 d->chainWrite(len, , sizeof(uint8_t));
 ++len;
 }
diff --git a/src/dev/virtio/rng.hh b/src/dev/virtio/rng.hh
index 50a3723..7be2354 100644
--- a/src/dev/virtio/rng.hh
+++ b/src/dev/virtio/rng.hh
@@ -39,8 +39,6 @@
 #ifndef __DEV_VIRTIO_RNG_HH__
 #define __DEV_VIRTIO_RNG_HH__

-#include 
-
 #include "base/compiler.hh"
 #include "dev/virtio/base.hh"

@@ -76,9 +74,8 @@
 : public VirtQueue
 {
   public:
-RngQueue(PortProxy , ByteOrder bo,
-uint16_t size, const std::string _file_path,
-VirtIORng &_parent);
+RngQueue(PortProxy , ByteOrder bo, uint16_t size,
+ VirtIORng &_parent);
 virtual ~RngQueue() {}

 void onNotify() { trySend(); }
@@ -90,12 +87,6 @@

   protected:
 VirtIORng 
-  private:
-// system's special file for generating random number
-int rng_fd;
-// fallback random number generator
-std::random_device rd_device;
-std::uniform_int_distribution dist;
 };
 /** Receive queue for port 0 */
 RngQueue qReq;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I299e72eb891819007b4260390f5c2ba94d2dec7b
Gerrit-Change-Number: 56889
Gerrit-PatchSet: 4
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Luming Wang 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fix stats in src/mem/cache/base.cc

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56989 )



Change subject: mem-cache: Fix stats in src/mem/cache/base.cc
..

mem-cache: Fix stats in src/mem/cache/base.cc

Most latency stats are described to have a unit of Tick.

However, the unit should be cycles.

Change-Id: Ib1b9b7c6fa4404cecb3982b3799753df19774623
Signed-off-by: Hoa Nguyen 
---
M src/mem/cache/base.cc
1 file changed, 39 insertions(+), 25 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 435684a..bfdce0c 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -2028,16 +2028,16 @@
("number of " + name + " hits").c_str()),
   ADD_STAT(misses, statistics::units::Count::get(),
("number of " + name + " misses").c_str()),
-  ADD_STAT(hitLatency, statistics::units::Tick::get(),
-   ("number of " + name + " hit ticks").c_str()),
-  ADD_STAT(missLatency, statistics::units::Tick::get(),
-   ("number of " + name + " miss ticks").c_str()),
+  ADD_STAT(hitLatency, statistics::units::Cycle::get(),
+   ("number of " + name + " hit cycles").c_str()),
+  ADD_STAT(missLatency, statistics::units::Cycle::get(),
+   ("number of " + name + " miss cycles").c_str()),
   ADD_STAT(accesses, statistics::units::Count::get(),
("number of " + name + " accesses(hits+misses)").c_str()),
   ADD_STAT(missRate, statistics::units::Ratio::get(),
("miss rate for " + name + " accesses").c_str()),
   ADD_STAT(avgMissLatency, statistics::units::Rate<
-statistics::units::Tick,  
statistics::units::Count>::get(),
+statistics::units::Cycle,  
statistics::units::Count>::get(),

("average " + name + " miss latency").c_str()),
   ADD_STAT(mshrHits, statistics::units::Count::get(),
("number of " + name + " MSHR hits").c_str()),
@@ -2045,17 +2045,17 @@
("number of " + name + " MSHR misses").c_str()),
   ADD_STAT(mshrUncacheable, statistics::units::Count::get(),
("number of " + name + " MSHR uncacheable").c_str()),
-  ADD_STAT(mshrMissLatency, statistics::units::Tick::get(),
-   ("number of " + name + " MSHR miss ticks").c_str()),
-  ADD_STAT(mshrUncacheableLatency, statistics::units::Tick::get(),
-   ("number of " + name + " MSHR uncacheable ticks").c_str()),
+  ADD_STAT(mshrMissLatency, statistics::units::Cycle::get(),
+   ("number of " + name + " MSHR miss cycles").c_str()),
+  ADD_STAT(mshrUncacheableLatency, statistics::units::Cycle::get(),
+   ("number of " + name + " MSHR uncacheable cycles").c_str()),
   ADD_STAT(mshrMissRate, statistics::units::Ratio::get(),
("mshr miss rate for " + name + " accesses").c_str()),
   ADD_STAT(avgMshrMissLatency, statistics::units::Rate<
-statistics::units::Tick,  
statistics::units::Count>::get(),
+statistics::units::Cycle,  
statistics::units::Count>::get(),

("average " + name + " mshr miss latency").c_str()),
   ADD_STAT(avgMshrUncacheableLatency, statistics::units::Rate<
-statistics::units::Tick,  
statistics::units::Count>::get(),
+statistics::units::Cycle,  
statistics::units::Count>::get(),

("average " + name + " mshr uncacheable latency").c_str())
 {
 }
@@ -2201,18 +2201,18 @@
  "number of demand (read+write) hits"),
 ADD_STAT(overallHits, statistics::units::Count::get(),
  "number of overall hits"),
-ADD_STAT(demandHitLatency, statistics::units::Tick::get(),
- "number of demand (read+write) hit ticks"),
-ADD_STAT(overallHitLatency, statistics::units::Tick::get(),
-"number of overall hit ticks"),
+ADD_STAT(demandHitLatency, statistics::units::Cycle::get(),
+ "number of demand (read+write) hit cycles"),
+ADD_STAT(overallHitLatency, statistics::units::Cycle::get(),
+"number of overall hit cycles"),
 ADD_STAT(demandMisses, statistics::units::Count::get(),
  "number of demand (read+write) misses"),
 ADD_STAT(overallMisses, statistics::units::Count::get(),
  "number of overall misses"),
-ADD_STAT(demandMissLatency, statistics::units::Tick::get(),
- "number of demand (read+write) miss ticks"),
-ADD_STAT(overallMissLatency, statistics::units::Tick::get(),
- "number of overall miss ticks"),
+ADD_STAT(demandMissLatency, statistics::units::Cycle::get(),
+ "number of demand (read+write) miss cycles"),
+ADD_STAT(overallMissLatency, statistics::units::Cycle::get(),
+ "number of overall miss cycles"),
 ADD_STAT(demandAccesses, 

[gem5-dev] Change in gem5/gem5[develop]: dev: Make VirtIORng device use gem5's rng instead of C++'s

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56889 )



Change subject: dev: Make VirtIORng device use gem5's rng instead of C++'s
..

dev: Make VirtIORng device use gem5's rng instead of C++'s

Currently, VirtIORng uses C++'s RNG. This causes nondeterminism
across simulations using this device. One example is the example RISC-V
board booting Ubuntu,

configs/example/gem5_library/riscv-ubuntu-run.py

JIRA: https://gem5.atlassian.net/browse/GEM5-1193

Change-Id: I299e72eb891819007b4260390f5c2ba94d2dec7b
Signed-off-by: Hoa Nguyen 
---
M src/dev/virtio/rng.cc
M src/dev/virtio/rng.hh
2 files changed, 21 insertions(+), 7 deletions(-)



diff --git a/src/dev/virtio/rng.cc b/src/dev/virtio/rng.cc
index 50a747c..6123589 100644
--- a/src/dev/virtio/rng.cc
+++ b/src/dev/virtio/rng.cc
@@ -41,6 +41,7 @@
 #include 
 #include 

+#include "base/random.hh"
 #include "debug/VIORng.hh"
 #include "params/VirtIORng.hh"
 #include "sim/system.hh"
@@ -63,7 +64,7 @@
 VirtIORng::RngQueue::RngQueue(PortProxy , ByteOrder bo,
 uint16_t size, const std::string _file_path,
 VirtIORng &_parent)
-: VirtQueue(proxy, bo, size), parent(_parent), dist(0,255)
+: VirtQueue(proxy, bo, size), parent(_parent)
 {
 rng_fd = open(rng_file_path.c_str(), O_RDONLY);
 if (rng_fd < 0) {
@@ -97,7 +98,7 @@
 }
 if (!rng_read_success) {
 // fallback to C++ std rng generator
-byte = dist(rd_device);
+byte = gem5::random_mt.random();
 }
 d->chainWrite(len, , sizeof(uint8_t));
 ++len;
diff --git a/src/dev/virtio/rng.hh b/src/dev/virtio/rng.hh
index 50a3723..631e353 100644
--- a/src/dev/virtio/rng.hh
+++ b/src/dev/virtio/rng.hh
@@ -39,8 +39,6 @@
 #ifndef __DEV_VIRTIO_RNG_HH__
 #define __DEV_VIRTIO_RNG_HH__

-#include 
-
 #include "base/compiler.hh"
 #include "dev/virtio/base.hh"

@@ -93,9 +91,6 @@
   private:
 // system's special file for generating random number
 int rng_fd;
-// fallback random number generator
-std::random_device rd_device;
-std::uniform_int_distribution dist;
 };
 /** Receive queue for port 0 */
 RngQueue qReq;

--
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Gerrit-Change-Number: 56889
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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Remove final decorator from abstract board

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55863 )


Change subject: stdlib: Remove final decorator from abstract board
..

stdlib: Remove final decorator from abstract board

@typing.final was not introduced until python3.8.

Change-Id: I65a5f4b5655d2ad80f7b566f9cea8e2371b3be62
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55863
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/gem5/components/boards/abstract_board.py
1 file changed, 17 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index a27cecd..30fbfca 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -37,7 +37,7 @@
 VoltageDomain,
 )

-from typing import List, final
+from typing import List


 class AbstractBoard(System):
@@ -236,7 +236,6 @@
 """
 raise NotImplementedError

-@final
 def _connect_things(self) -> None:
 """Connects all the components to the board.


--
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Gerrit-Branch: develop
Gerrit-Change-Id: I65a5f4b5655d2ad80f7b566f9cea8e2371b3be62
Gerrit-Change-Number: 55863
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Remove final decorator from abstract board

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55863 )



Change subject: stdlib: Remove final decorator from abstract board
..

stdlib: Remove final decorator from abstract board

@typing.final was not introduced until python3.8.

Change-Id: I65a5f4b5655d2ad80f7b566f9cea8e2371b3be62
Signed-off-by: Hoa Nguyen 
---
M src/python/gem5/components/boards/abstract_board.py
1 file changed, 13 insertions(+), 2 deletions(-)



diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index a27cecd..30fbfca 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -37,7 +37,7 @@
 VoltageDomain,
 )

-from typing import List, final
+from typing import List


 class AbstractBoard(System):
@@ -236,7 +236,6 @@
 """
 raise NotImplementedError

-@final
 def _connect_things(self) -> None:
 """Connects all the components to the board.


--
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[gem5-dev] Change in gem5/gem5[release-staging-v21-2]: ext: Fix dumping stats error at the end of simulation

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54343 )



Change subject: ext: Fix dumping stats error at the end of simulation
..

ext: Fix dumping stats error at the end of simulation

A missing comma causing two commands to be one, which resulted in
a Python interpreter syntax error.

Change-Id: Ieb0e3c620c175731084ff0e2040388b15364691e
Signed-off-by: Hoa Nguyen 
---
M ext/sst/gem5.cc
1 file changed, 14 insertions(+), 1 deletion(-)



diff --git a/ext/sst/gem5.cc b/ext/sst/gem5.cc
index 8eab6281..7af0eed 100644
--- a/ext/sst/gem5.cc
+++ b/ext/sst/gem5.cc
@@ -262,7 +262,7 @@
 );
 // output gem5 stats
 const std::vector output_stats_commands = {
-"import m5.stats"
+"import m5.stats",
 "m5.stats.dump()"
 };
 execPythonCommands(output_stats_commands);

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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-2
Gerrit-Change-Id: Ieb0e3c620c175731084ff0e2040388b15364691e
Gerrit-Change-Number: 54343
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Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[develop]: ext: Update ext/sst/INSTALL.md

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53463 )


Change subject: ext: Update ext/sst/INSTALL.md
..

ext: Update ext/sst/INSTALL.md

Currently, the installation instructions are for installing
SST-core and SST-elements version 11.0.0. This change updates
instructions to the current SST-core and SST-element version,
11.1.0.

This change also reflects that manually downloading the
`bbl-busybox-boot-exit` is no longer necessary as the example
gem5 config will download automatically.

Change-Id: I616ca38316213dcbd71b6eab121b5ac89eed1962
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53463
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M ext/sst/INSTALL.md
1 file changed, 35 insertions(+), 15 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/ext/sst/INSTALL.md b/ext/sst/INSTALL.md
index 4268724..46ff4f0 100644
--- a/ext/sst/INSTALL.md
+++ b/ext/sst/INSTALL.md
@@ -11,14 +11,14 @@
 ### Downloading the SST-Core Source Code

 ```sh
-wget  
https://github.com/sstsimulator/sst-core/releases/download/v11.0.0_Final/sstcore-11.0.0.tar.gz

-tar xf sstcore-11.0.0.tar.gz
+wget  
https://github.com/sstsimulator/sst-core/releases/download/v11.1.0_Final/sstcore-11.1.0.tar.gz

+tar xf sstcore-11.1.0.tar.gz
 ```

 ### Installing SST-Core

 ```sh
-cd sstcore-11.0.0
+cd sstcore-11.1.0
 ./configure --prefix=$SST_CORE_HOME --with-python=/usr/bin/python3-config \
 --disable-mpi # optional, used when MPI is not available.
 make all -j$(nproc)
@@ -36,14 +36,14 @@
 ### Downloading the SST-Elements Source Code

 ```sh
-wget  
https://github.com/sstsimulator/sst-elements/releases/download/v11.0.0_Final/sstelements-11.0.0.tar.gz

-tar xf sstelements-11.0.0.tar.gz
+wget  
https://github.com/sstsimulator/sst-elements/releases/download/v11.1.0_Final/sstelements-11.1.0.tar.gz

+tar xf sstelements-11.1.0.tar.gz
 ```

 ### Installing SST-Elements

-```shs
-cd sst-elements-library-11.0.0
+```sh
+cd sst-elements-library-11.1.0
 ./configure --prefix=$SST_CORE_HOME --with-python=/usr/bin/python3-config \
 --with-sst-core=$SST_CORE_HOME
 make all -j$(nproc)
@@ -75,20 +75,17 @@

 ### Running an example simulation

-Downloading the built bootloader containing a Linux Kernel and a workload,
-
-```sh
-wget http://dist.gem5.org/dist/develop/misc/riscv/bbl-busybox-boot-exit
-```
-
 Running the simulation

 ```sh
 sst --add-lib-path=./ sst/example.py
 ```

-`bbl-busybox-boot-exit` contains an m5 binary, and `m5 exit` will be called
-upon the booting process reaching the early userspace.
+The example SST system configuration will instantiate the gem5 system
+as specified in the gem5 system configuration located at
+`gem5/configs/example/sst/riscv_fs.py`. This configuration will download
+the `bbl-busybox-boot-exit` resource, which contains an m5 binary, and
+`m5 exit` will be called upon the booting process reaching the early  
userspace.
 More information about building a bootloader containing a Linux Kernel and  
a

 customized workload is available at
  
[https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-boot-exit-nodisk/].


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I616ca38316213dcbd71b6eab121b5ac89eed1962
Gerrit-Change-Number: 53463
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: ext: Update ext/sst/INSTALL.md

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53463 )



Change subject: ext: Update ext/sst/INSTALL.md
..

ext: Update ext/sst/INSTALL.md

Currently, the installation instructions are for installing
SST-core and SST-elements version 11.0.0. This change updates
instructions to the current SST-core and SST-element version,
11.1.0.

This change also reflects that manually downloading the
`bbl-busybox-boot-exit` is no longer necessary as the example
gem5 config will download automatically.

Change-Id: I616ca38316213dcbd71b6eab121b5ac89eed1962
Signed-off-by: Hoa Nguyen 
---
M ext/sst/INSTALL.md
1 file changed, 31 insertions(+), 15 deletions(-)



diff --git a/ext/sst/INSTALL.md b/ext/sst/INSTALL.md
index 4268724..46ff4f0 100644
--- a/ext/sst/INSTALL.md
+++ b/ext/sst/INSTALL.md
@@ -11,14 +11,14 @@
 ### Downloading the SST-Core Source Code

 ```sh
-wget  
https://github.com/sstsimulator/sst-core/releases/download/v11.0.0_Final/sstcore-11.0.0.tar.gz

-tar xf sstcore-11.0.0.tar.gz
+wget  
https://github.com/sstsimulator/sst-core/releases/download/v11.1.0_Final/sstcore-11.1.0.tar.gz

+tar xf sstcore-11.1.0.tar.gz
 ```

 ### Installing SST-Core

 ```sh
-cd sstcore-11.0.0
+cd sstcore-11.1.0
 ./configure --prefix=$SST_CORE_HOME --with-python=/usr/bin/python3-config \
 --disable-mpi # optional, used when MPI is not available.
 make all -j$(nproc)
@@ -36,14 +36,14 @@
 ### Downloading the SST-Elements Source Code

 ```sh
-wget  
https://github.com/sstsimulator/sst-elements/releases/download/v11.0.0_Final/sstelements-11.0.0.tar.gz

-tar xf sstelements-11.0.0.tar.gz
+wget  
https://github.com/sstsimulator/sst-elements/releases/download/v11.1.0_Final/sstelements-11.1.0.tar.gz

+tar xf sstelements-11.1.0.tar.gz
 ```

 ### Installing SST-Elements

-```shs
-cd sst-elements-library-11.0.0
+```sh
+cd sst-elements-library-11.1.0
 ./configure --prefix=$SST_CORE_HOME --with-python=/usr/bin/python3-config \
 --with-sst-core=$SST_CORE_HOME
 make all -j$(nproc)
@@ -75,20 +75,17 @@

 ### Running an example simulation

-Downloading the built bootloader containing a Linux Kernel and a workload,
-
-```sh
-wget http://dist.gem5.org/dist/develop/misc/riscv/bbl-busybox-boot-exit
-```
-
 Running the simulation

 ```sh
 sst --add-lib-path=./ sst/example.py
 ```

-`bbl-busybox-boot-exit` contains an m5 binary, and `m5 exit` will be called
-upon the booting process reaching the early userspace.
+The example SST system configuration will instantiate the gem5 system
+as specified in the gem5 system configuration located at
+`gem5/configs/example/sst/riscv_fs.py`. This configuration will download
+the `bbl-busybox-boot-exit` resource, which contains an m5 binary, and
+`m5 exit` will be called upon the booting process reaching the early  
userspace.
 More information about building a bootloader containing a Linux Kernel and  
a

 customized workload is available at
  
[https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-boot-exit-nodisk/].


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Gerrit-Branch: develop
Gerrit-Change-Id: I616ca38316213dcbd71b6eab121b5ac89eed1962
Gerrit-Change-Number: 53463
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add a weekly test for SST integration.

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52564 )



Change subject: tests: Add a weekly test for SST integration.
..

tests: Add a weekly test for SST integration.

This test includes,
- A dockerfile creating a Docker image containing SST-Core
and SST-Elements installed. The image also contains the
bbl-busybox-boot-exit binary from gem5-resources.
- A week test involving compiling gem5 as a library, and
booting a linux kernel without a disk image using SST where
gem5 TimingSimpleCPU is the CPU core.

Change-Id: I2bf90b4121ed0d38300451648f2e358a7c3fffe2
Signed-off-by: Hoa Nguyen 
---
M tests/weekly.sh
A util/dockerfiles/sst-11.1.0/Dockerfile
2 files changed, 108 insertions(+), 0 deletions(-)



diff --git a/tests/weekly.sh b/tests/weekly.sh
index 393c66f..882da7b 100755
--- a/tests/weekly.sh
+++ b/tests/weekly.sh
@@ -39,7 +39,26 @@
 threads=$1
 fi

+build_and_run_SST () {
+isa=$1
+variant=$2
+
+docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
+"${gem5_root}" --rm TODO? \
+bash -c "\
+scons build/${isa}/libgem5_${variant}.so -j${threads} --without-tcmalloc; \
+cd ext/sst; \
+make clean; make -j ${threads}; \
+ln -s /resources/bbl-busybox-boot-exit; \
+sst --add-lib-path=./ sst/example.py; \
+"
+}
+
 # Run the gem5 very-long tests.
 docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
 "${gem5_root}"/tests --rm  
gcr.io/gem5-test/ubuntu-20.04_all-dependencies \

 ./main.py run --length very-long -j${threads} -t${threads}
+
+# Run an SST test.
+build_and_run_SST RISCV opt
+
diff --git a/util/dockerfiles/sst-11.1.0/Dockerfile  
b/util/dockerfiles/sst-11.1.0/Dockerfile

new file mode 100644
index 000..e30cdea
--- /dev/null
+++ b/util/dockerfiles/sst-11.1.0/Dockerfile
@@ -0,0 +1,71 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+FROM ubuntu:20.04
+
+ENV DEBIAN_FRONTEND=noninteractive
+RUN apt -y update
+RUN apt -y upgrade
+RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \
+libprotobuf-dev protobuf-compiler libprotoc-dev  
libgoogle-perftools-dev \

+python3-dev python3-six python-is-python3 doxygen libboost-all-dev \
+libhdf5-serial-dev python3-pydot libpng-dev libelf-dev pkg-config pip \
+python3-venv wget
+
+ENV SST_CORE_HOME="/sst/"
+
+# SST Stuff
+RUN mkdir /sst
+
+# Download and build SST-Core without MPI support
+WORKDIR /sst/
+RUN wget  
https://github.com/sstsimulator/sst-core/releases/download/v11.1.0_Final/sstcore-11.1.0.tar.gz;  
\

+tar xf sstcore-11.1.0.tar.gz;
+WORKDIR /sst/sstcore-11.1.0/
+RUN ./configure --prefix=$SST_CORE_HOME  
--with-python=/usr/bin/python3-config \

+--disable-mpi; \
+make all -j $(nproc); \
+make install;
+
+# Download and build SST-Elements
+WORKDIR /sst
+RUN wget  
https://github.com/sstsimulator/sst-elements/releases/download/v11.1.0_Final/sstelements-11.1.0.tar.gz;  
\

+tar xf sstelements-11.1.0.tar.gz;
+WORKDIR /sst/sst-elements-library-11.1.0/
+RUN ./configure --prefix=$SST_CORE_HOME  
--with-python=/usr/bin/python3-config \

+--with-sst-core=$SST_CORE_HOME; \
+make all -j $(nproc); \
+make install;
+
+# Download the disk image
+RUN mkdir /resources/
+WORKDIR /resources/
+RUN wget  

[gem5-dev] Change in gem5/gem5[develop]: util: Make gerrit bot respect reviewer removal

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50187 )


Change subject: util: Make gerrit bot respect reviewer removal
..

util: Make gerrit bot respect reviewer removal

Currently, if a maintainer is removed from a change, the maintainer
will be added again. This change prevents the bot from adding the
removed maintainer again.

The bot will query all updates related to reviewer addition/removal
for each new change. If a reviewer has ever been added/removed
from a change, that reviewer won't be added to that change again.

Change-Id: Ifaab5ebd7ebf3e6453b2551d3e37c1b9e214c906
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50187
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Bobby R. Bruce 
---
M util/gerrit-bot/bot.py
M util/gerrit-bot/util.py
2 files changed, 36 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/util/gerrit-bot/bot.py b/util/gerrit-bot/bot.py
index 709279c..6f6b018 100755
--- a/util/gerrit-bot/bot.py
+++ b/util/gerrit-bot/bot.py
@@ -170,9 +170,10 @@
 def __query_new_changes(self, query_age):
 query = (f"projects:{self.config.projects_prefix} "
  f"status:open -is:wip -age:{query_age}")
-response = self.gerrit_api.query_changes(query,
- self.config.query_limit,
- "CURRENT_REVISION")
+response = self.gerrit_api.query_changes(
+query, self.config.query_limit,
+["CURRENT_REVISION", "REVIEWER_UPDATES", "DETAILED_ACCOUNTS"]
+)

 if response.status_code >= 300:
 print("Error: Couldn't query new Gerrit changes")
diff --git a/util/gerrit-bot/util.py b/util/gerrit-bot/util.py
index d836690..1d00372 100644
--- a/util/gerrit-bot/util.py
+++ b/util/gerrit-bot/util.py
@@ -60,6 +60,14 @@
 tags, message = parse_commit_subject(change["subject"])
 change_id = change["id"]
 maintainer_emails = set()
+
+# There are cases that a reviewer being removed from the reviewer list
+# by another reviewer. We want to respect this removal. To do this,
+# we can avoid adding reviewers that have been added/removed to the
+# reviewer list.
+avoid_emails = set()
+for update in change["reviewer_updates"]:
+avoid_emails.add(update["reviewer"]["email"])
 for tag in tags:
 try:
 for name, email in maintainers[tag].maintainers:
@@ -68,6 +76,8 @@
 print((f"warning: `change-{change_id}` has an unknown tag: "
f"`{tag}`"))
 for email in maintainer_emails:
+if email in avoid_emails:
+continue
 try:
 account_id = maintainers_account_ids[email]
 gerrit_api.add_reviewer(change_id, account_id)

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifaab5ebd7ebf3e6453b2551d3e37c1b9e214c906
Gerrit-Change-Number: 50187
Gerrit-PatchSet: 4
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Make disk image optional for riscv-board

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50754 )



Change subject: python: Make disk image optional for riscv-board
..

python: Make disk image optional for riscv-board

This resource allows booting Linux without using a disk image.
https://gem5-review.googlesource.com/c/public/gem5-resources/+/50547

Change-Id: I15723e3c22ce116660767068e75da7920c7b8be2
Signed-off-by: Hoa Nguyen 
---
M src/python/gem5/components/boards/riscv_board.py
1 file changed, 40 insertions(+), 26 deletions(-)



diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index 2cc151d..7b3c2af 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -84,6 +84,7 @@
 processor: AbstractProcessor,
 memory: AbstractMemorySystem,
 cache_hierarchy: AbstractCacheHierarchy,
+use_disk_image: bool = True
 ) -> None:
 super().__init__(clk_freq, processor, memory, cache_hierarchy)

@@ -110,17 +111,20 @@
 self.iobus = IOXBar()

 # The virtio disk
-self.disk = MmioVirtIO(
-vio=VirtIOBlock(),
-interrupt_id=0x8,
-pio_size=4096,
-pio_addr=0x10008000,
-)
+if use_disk_image:
+self.disk = MmioVirtIO(
+vio=VirtIOBlock(),
+interrupt_id=0x8,
+pio_size=4096,
+pio_addr=0x10008000,
+)

 # Note: This overrides the platform's code because the platform  
isn't

 # general enough.
 self._on_chip_devices = [self.platform.clint, self.platform.plic]
-self._off_chip_devices = [self.platform.uart, self.disk]
+self._off_chip_devices = [self.platform.uart]
+if use_disk_image:
+self._off_chip_devices.append(self.disk)

 def _setup_io_devices(self) -> None:
 """Connect the I/O devices to the I/O bus"""
@@ -175,7 +179,9 @@
 memory.set_memory_range(self.mem_ranges)

 def set_workload(
-self, bootloader: AbstractResource, disk_image: AbstractResource,
+self, bootloader: AbstractResource,
+disk_image: Optional[AbstractResource],
+kernel_boot_params: Optional[str] = "console=ttyS0 root=/dev/vda  
ro",

 command: Optional[str] = None
 ) -> None:
 """Setup the full system files
@@ -199,18 +205,24 @@
 with the kernel as a payload
 :param disk_image: The resource encapsulating the disk image  
containing

 the OS data. The first partition should be the root partition.
+:param kernel_boot_params: The options for booting a Linux kernel.
+More information about options is available at
+ 
www.kernel.org/doc/html/latest/admin-guide/kernel-parameters.html
 :param command: The command(s) to run with bash once the OS is  
booted

 """

 self.workload.object_file = bootloader.get_local_path()

-image = CowDiskImage(
-child=RawDiskImage(read_only=True), read_only=False
-)
-image.child.image_file = disk_image.get_local_path()
-self.disk.vio.image = image
+use_disk_image = not (disk_image == None)

-self.workload.command_line = "console=ttyS0 root=/dev/vda ro"
+if use_disk_image:
+image = CowDiskImage(
+child=RawDiskImage(read_only=True), read_only=False
+)
+image.child.image_file = disk_image.get_local_path()
+self.disk.vio.image = image
+
+self.workload.command_line = kernel_boot_params

 # Note: This must be called after set_workload because it looks  
for an

 # attribute named "disk" and connects
@@ -224,12 +236,12 @@
 # We need to wait to generate the device tree until after the disk  
is
 # set up. Now that the disk and workload are set, we can generate  
the

 # device tree file.
-self.generate_device_tree(m5.options.outdir)
+self.generate_device_tree(m5.options.outdir, use_disk_image)
 self.workload.dtb_filename = os.path.join(
 m5.options.outdir, "device.dtb"
 )

-def generate_device_tree(self, outdir: str) -> None:
+def generate_device_tree(self, outdir: str, use_disk_image: bool) ->  
None:

 """Creates the dtb and dts files.

 Creates two files in the outdir: 'device.dtb' and 'device.dts'
@@ -360,16 +372,18 @@
 soc_node.append(uart_node)

 # VirtIO MMIO disk node
-disk = self.disk
-disk_node = disk.generateBasicPioDeviceNode(
-soc_state, "virtio_mmio", disk.pio_addr, disk.pio_size
-)
-disk_node.append(FdtPropertyWords("interrupts",  
[disk.interrupt_id]))

-disk_node.append(
-  

[gem5-dev] Change in gem5/gem5[develop]: scons: Fix gem5 build fails when install-hooks is not set

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50627 )



Change subject: scons: Fix gem5 build fails when install-hooks is not set
..

scons: Fix gem5 build fails when install-hooks is not set

For interactive build, gem5 build fails when the git-hooks
is not available since scons would look for `install-hooks`
option, which is not necessarily set for interactive build.

JIRA: https://gem5.atlassian.net/browse/GEM5-1091

Signed-off-by: Hoa Nguyen 
Change-Id: Ife248117420eb470c02d6e7536c1065256ba71e0
---
M site_scons/site_tools/git.py
1 file changed, 4 insertions(+), 3 deletions(-)



diff --git a/site_scons/site_tools/git.py b/site_scons/site_tools/git.py
index e95c62f..3a23276 100644
--- a/site_scons/site_tools/git.py
+++ b/site_scons/site_tools/git.py
@@ -100,9 +100,10 @@
 return

 print(git_style_message, end=' ')
-if SCons.Script.GetOption('install-hooks'):
-print("Installing revision control hooks automatically.")
-else:
+try:
+if SCons.Script.GetOption('install-hooks'):
+print("Installing revision control hooks automatically.")
+except AttributeError:
 try:
 input()
 except:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ife248117420eb470c02d6e7536c1065256ba71e0
Gerrit-Change-Number: 50627
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: util: Make gerrit bot respect reviewer removal

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50187 )



Change subject: util: Make gerrit bot respect reviewer removal
..

util: Make gerrit bot respect reviewer removal

Currently, if a maintainer is removed from a change, the maintainer
will be added again. This change prevents the bot from adding the
removed maintainer again.

The bot will query all updates related to reviewer addition/removal
for each new change. If a reviewer has ever been added/removed
from a change, that reviewer won't be added to that change again.

Change-Id: Ifaab5ebd7ebf3e6453b2551d3e37c1b9e214c906
Signed-off-by: Hoa Nguyen 
---
M util/gerrit-bot/bot.py
M util/gerrit-bot/util.py
2 files changed, 14 insertions(+), 3 deletions(-)



diff --git a/util/gerrit-bot/bot.py b/util/gerrit-bot/bot.py
index 709279c..6f6b018 100755
--- a/util/gerrit-bot/bot.py
+++ b/util/gerrit-bot/bot.py
@@ -170,9 +170,10 @@
 def __query_new_changes(self, query_age):
 query = (f"projects:{self.config.projects_prefix} "
  f"status:open -is:wip -age:{query_age}")
-response = self.gerrit_api.query_changes(query,
- self.config.query_limit,
- "CURRENT_REVISION")
+response = self.gerrit_api.query_changes(
+query, self.config.query_limit,
+["CURRENT_REVISION", "REVIEWER_UPDATES", "DETAILED_ACCOUNTS"]
+)

 if response.status_code >= 300:
 print("Error: Couldn't query new Gerrit changes")
diff --git a/util/gerrit-bot/util.py b/util/gerrit-bot/util.py
index d836690..a5142e4 100644
--- a/util/gerrit-bot/util.py
+++ b/util/gerrit-bot/util.py
@@ -60,6 +60,14 @@
 tags, message = parse_commit_subject(change["subject"])
 change_id = change["id"]
 maintainer_emails = set()
+
+# There are cases that a reviewer being removed from the reviewer list
+# by another reviewer. We want to respect this removal. To do this,
+# we can avoid adding reviewers that have been added/removed to the
+# reviewer list.
+avoid_emails = set()
+for update in change["reviewer_updates"]:
+avoid_emails = update["reviewer"]["email"]
 for tag in tags:
 try:
 for name, email in maintainers[tag].maintainers:
@@ -68,6 +76,8 @@
 print((f"warning: `change-{change_id}` has an unknown tag: "
f"`{tag}`"))
 for email in maintainer_emails:
+if email in avoid_emails:
+continue
 try:
 account_id = maintainers_account_ids[email]
 gerrit_api.add_reviewer(change_id, account_id)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifaab5ebd7ebf3e6453b2551d3e37c1b9e214c906
Gerrit-Change-Number: 50187
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Make loading workloads to memory optional

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49283 )



Change subject: sim: Make loading workloads to memory optional
..

sim: Make loading workloads to memory optional

There are use cases of gem5 that memory being an external
component and does not exist until after gem5 being instantiated.

Change-Id: I2fefad67072d7bab37ff6f732a76a5ba507cd602
Signed-off-by: Hoa Nguyen 
---
M src/sim/Workload.py
M src/sim/kernel_workload.cc
2 files changed, 7 insertions(+), 2 deletions(-)



diff --git a/src/sim/Workload.py b/src/sim/Workload.py
index 62aa047..03238c0 100644
--- a/src/sim/Workload.py
+++ b/src/sim/Workload.py
@@ -54,6 +54,9 @@
 "auto-calculated to be the most restrictive.")
 load_addr_offset = Param.UInt64(0, "Address to offset the kernel with")

+load_workload_to_memory = Param.Bool(True,
+"whether to load the workload to memory")
+
 command_line = Param.String("a", "boot flags to pass to the kernel")

 class SEWorkloadMeta(type(Workload)):
diff --git a/src/sim/kernel_workload.cc b/src/sim/kernel_workload.cc
index c338b23..cdc081d 100644
--- a/src/sim/kernel_workload.cc
+++ b/src/sim/kernel_workload.cc
@@ -112,12 +112,14 @@
 _start, _end, mapper(_start), mapper(_end));
 }
 // Load program sections into memory
-image.write(phys_mem);
+if (params().load_workload_to_memory)
+image.write(phys_mem);

 DPRINTF(Loader, "Kernel start = %#x\n", _start);
 DPRINTF(Loader, "Kernel end   = %#x\n", _end);
 DPRINTF(Loader, "Kernel entry = %#x\n", kernelObj->entryPoint());
-DPRINTF(Loader, "Kernel loaded...\n");
+if (params().load_workload_to_memory)
+DPRINTF(Loader, "Kernel loaded...\n");
 }

 std::vector extras_addrs = params().extras_addrs;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2fefad67072d7bab37ff6f732a76a5ba507cd602
Gerrit-Change-Number: 49283
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix illegal instruction error message

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48923 )


Change subject: arch-riscv: Fix illegal instruction error message
..

arch-riscv: Fix illegal instruction error message

Previously, the reason for the fault was not printed to the output.

Change-Id: I931b0de96fbb241f24ba69ad7e84d5d1c9db9e60
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48923
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Ayaz Akram 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/faults.hh
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Ayaz Akram: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index 38c5638..a8df3f5 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -166,7 +166,8 @@

   public:
 IllegalInstFault(std::string r, const ExtMachInst inst)
-: InstFault("Illegal instruction", inst)
+: InstFault("Illegal instruction", inst),
+  reason(r)
 {}

 void invokeSE(ThreadContext *tc, const StaticInstPtr ) override;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I931b0de96fbb241f24ba69ad7e84d5d1c9db9e60
Gerrit-Change-Number: 48923
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch: Fix illegal instruction error message

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48923 )



Change subject: arch: Fix illegal instruction error message
..

arch: Fix illegal instruction error message

Previously, the reason for the fault was not printed to the output.

Change-Id: I931b0de96fbb241f24ba69ad7e84d5d1c9db9e60
Signed-off-by: Hoa Nguyen 
---
M src/arch/riscv/faults.hh
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index 38c5638..a8df3f5 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -166,7 +166,8 @@

   public:
 IllegalInstFault(std::string r, const ExtMachInst inst)
-: InstFault("Illegal instruction", inst)
+: InstFault("Illegal instruction", inst),
+  reason(r)
 {}

 void invokeSE(ThreadContext *tc, const StaticInstPtr ) override;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I931b0de96fbb241f24ba69ad7e84d5d1c9db9e60
Gerrit-Change-Number: 48923
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[develop]: util: Fix gerrit bot commit subject parser

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48586 )



Change subject: util: Fix gerrit bot commit subject parser
..

util: Fix gerrit bot commit subject parser

Currently, if the commit subject does have tags, the parser will
return the list of tags as a NoneType object, which will be
iterated later. This caused the gerrit bot to fail.

This change lets the parser return the list of tags as an empty
list rather than a NoneType object. Also, a commit subject without
a semicolon `:` will be assumed as having no tags and the whole
subject is the commit message.

Signed-off-by: Hoa Nguyen 
Change-Id: Ie8c90e14bb85c4ce1c583121d02e75aa87db7811
---
M util/gerrit-bot/util.py
1 file changed, 3 insertions(+), 2 deletions(-)



diff --git a/util/gerrit-bot/util.py b/util/gerrit-bot/util.py
index 31b9fcc..d836690 100644
--- a/util/gerrit-bot/util.py
+++ b/util/gerrit-bot/util.py
@@ -30,9 +30,10 @@
 parsed_subject = subject.split(":", maxsplit = 1)

 # If the subject does not have a colon, it either does not have tags
-# or does not have a message
+# or does not have a message. In this case, we assume that the subject
+# is the commit message.
 if len(parsed_subject) <= 1:
-return None, None
+return [], parsed_subject[0]

 tags = [ tag.strip() for tag in parsed_subject[0].split(",") ]
 message = parsed_subject[1]

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie8c90e14bb85c4ce1c583121d02e75aa87db7811
Gerrit-Change-Number: 48586
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[master]: misc: Test

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48223 )



Change subject: misc: Test
..

misc: Test

Change-Id: Ie28dd4b13ee36b5f4c0a27646645180dd211e90a
---
A hello
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/hello b/hello
new file mode 100644
index 000..9daeafb
--- /dev/null
+++ b/hello
@@ -0,0 +1 @@
+test

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie28dd4b13ee36b5f4c0a27646645180dd211e90a
Gerrit-Change-Number: 48223
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[stable]: misc: Test

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48222 )



Change subject: misc: Test
..

misc: Test

Change-Id: I99f6723061e3564c63b94fe5dd309cfdc32202f1
---
A hello
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/hello b/hello
new file mode 100644
index 000..9daeafb
--- /dev/null
+++ b/hello
@@ -0,0 +1 @@
+test

--
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Gerrit-Project: public/gem5
Gerrit-Branch: stable
Gerrit-Change-Id: I99f6723061e3564c63b94fe5dd309cfdc32202f1
Gerrit-Change-Number: 48222
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[release-staging-v21-1]: arch-riscv: Revert change-45522

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48099 )


Change subject: arch-riscv: Revert change-45522
..

arch-riscv: Revert change-45522

This reverts change:
https://gem5-review.googlesource.com/c/public/gem5/+/45522.

This reverts commit 1cf41d4c54c988ef4808d8efc1f6212e54a4c120.

Reason for revert:

The above commit caused booting Linux using RISCV either to
hang or to take significantly time more than to finish.

For the v21-1 release, the above commit will be reverted.

JIRA: https://gem5.atlassian.net/browse/GEM5-1043

Change-Id: I58fbe96d7ea50031eba40ff49dabdef971faf6ff
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48099
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 46 insertions(+), 94 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index edb2268..dad2c2b 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -274,7 +274,7 @@
 }
 }};

-def template CSRExecuteRo {{
+def template CSRExecute {{
 Fault
 %(class_name)s::execute(ExecContext *xc,
 Trace::InstRecord *traceData) const
@@ -287,6 +287,8 @@
 %(op_decl)s;
 %(op_rd)s;

+RegVal data, olddata;
+
 switch (csr) {
   case CSR_SATP: {
 auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
@@ -311,91 +313,55 @@
 break;
 }

-RegVal data;
 if (csr == CSR_FCSR) {
-data = xc->readMiscReg(MISCREG_FFLAGS) |
-   (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
-} else {
-data = xc->readMiscReg(midx);
-}
-
-DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data);
-
-%(code)s;
-%(op_wb)s;
-
-return NoFault;
-}
-}};
-
-def template CSRExecuteRw {{
-Fault
-%(class_name)s::execute(ExecContext *xc,
-Trace::InstRecord *traceData) const
-{
-if (!valid) {
-return std::make_shared(
-csprintf("Illegal CSR index %#x\n", csr), machInst);
-}
-if (bits(csr, 11, 10) == 0x3) {
-return std::make_shared(
-csprintf("CSR %s is read-only\n", csrName), machInst);
-}
-
-%(op_decl)s;
-%(op_rd)s;
-
-switch (csr) {
-  case CSR_SATP: {
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
-if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) {
-return std::make_shared(
-"SATP access in user mode or with TVM enabled\n",
-machInst);
-}
-break;
-  }
-  case CSR_MSTATUS: {
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-if (pm != PrivilegeMode::PRV_M) {
-return std::make_shared(
-"MSTATUS is only accessibly in machine mode\n",
-machInst);
-}
-break;
-  }
-  default:
-break;
-}
-
-RegVal data;
-if (csr == CSR_FCSR) {
-data = xc->readMiscReg(MISCREG_FFLAGS) |
+olddata = xc->readMiscReg(MISCREG_FFLAGS) |
   (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
 } else {
-data = xc->readMiscReg(midx);
+olddata = xc->readMiscReg(midx);
 }
+auto olddata_all = olddata;

-RegVal original = data;
-
-DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data &  
maskVal);

+olddata &= maskVal;
+DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, olddata);
+data = olddata;

 %(code)s;

-// We must keep those original bits not in the mask. Hidden bits  
should

-// keep their original value.
-data = (original & ~maskVal) | (data & maskVal);
-
-DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n", data, csrName);
-
-if (csr == CSR_FCSR) {
-xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
-xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
-} else {
-xc->setMiscReg(midx, data);
+data &= maskVal;
+if (data != olddata) {
+if (bits(csr, 11, 10) == 0x3) {
+return std::make_shared(
+csprintf("CSR %s is read-only\n", csrName),  
machInst);

+}
+auto newdata_all = data;
+// We must keep those original bits not in mask.
+// olddata and data only 

[gem5-dev] Change in gem5/gem5[release-staging-v21-1]: cpu: remove O3 dependency of CheckerCPU

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48079 )


Change subject: cpu: remove O3 dependency of CheckerCPU
..

cpu: remove O3 dependency of CheckerCPU

Currently, compiling CheckerCPU uses the dyn_inst.hh header from
O3CPU. However, including this header is not required and it
causes gem5 failed to build when O3CPU is not part of CPU_MODELS.

This change also involves moving the the dependency on
src/cpu/o3/dyn_inst.hh to src/cpu/o3/cpu.cc and src/cpu/lsq_unit.cc,
which previously includes src/cpu/o3/dyn_inst.hh implicitly through
src/cpu/checker/cpu.hh.

JIRA: https://gem5.atlassian.net/browse/GEM5-1025

Change-Id: I7664cd4b9591bf0a4635338fff576cb5f5cbfa10
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48079
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/checker/cpu.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/lsq_unit.cc
3 files changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index aebf522..a191ae4 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -51,7 +51,6 @@
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/inst_res.hh"
-#include "cpu/o3/dyn_inst.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index fbdfcbd..e352236 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -46,6 +46,7 @@
 #include "cpu/activity.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/checker/thread_context.hh"
+#include "cpu/o3/dyn_inst.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/thread_context.hh"
 #include "cpu/simple_thread.hh"
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 5394e4f..039184d 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -46,6 +46,7 @@
 #include "base/str.hh"
 #include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
+#include "cpu/o3/dyn_inst.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/lsq.hh"
 #include "debug/Activity.hh"

--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-1
Gerrit-Change-Id: I7664cd4b9591bf0a4635338fff576cb5f5cbfa10
Gerrit-Change-Number: 48079
Gerrit-PatchSet: 4
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Revert "Split up read/write and read only CSR instructions."

[Hoa Nguyen (Gerrit) via gem5-dev]

Attention is currently required from: Daniel Carvalho, Bobby R. Bruce, Gabe  
Black, Ayaz Akram.

Hello kokoro, Daniel Carvalho, Bobby R. Bruce, Gabe Black, Ayaz Akram,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/48099

to review the following change.


Change subject: arch-riscv: Revert "Split up read/write and read only CSR  
instructions."

..

arch-riscv: Revert "Split up read/write and read only CSR instructions."

This reverts commit 1cf41d4c54c988ef4808d8efc1f6212e54a4c120.

Reason for revert:

The above commit caused booting Linux using RISCV either to
hang or to take significantly time more than to finish.

For the v21-1 release, the above commit will be reverted.

Change-Id: I58fbe96d7ea50031eba40ff49dabdef971faf6ff
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 46 insertions(+), 94 deletions(-)



diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index dba460f..e0b270b 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -274,7 +274,7 @@
 }
 }};

-def template CSRExecuteRo {{
+def template CSRExecute {{
 Fault
 %(class_name)s::execute(ExecContext *xc,
 Trace::InstRecord *traceData) const
@@ -287,6 +287,8 @@
 %(op_decl)s;
 %(op_rd)s;

+RegVal data, olddata;
+
 switch (csr) {
   case CSR_SATP: {
 auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
@@ -311,91 +313,55 @@
 break;
 }

-RegVal data;
 if (csr == CSR_FCSR) {
-data = xc->readMiscReg(MISCREG_FFLAGS) |
-   (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
-} else {
-data = xc->readMiscReg(midx);
-}
-
-DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data);
-
-%(code)s;
-%(op_wb)s;
-
-return NoFault;
-}
-}};
-
-def template CSRExecuteRw {{
-Fault
-%(class_name)s::execute(ExecContext *xc,
-Trace::InstRecord *traceData) const
-{
-if (!valid) {
-return std::make_shared(
-csprintf("Illegal CSR index %#x\n", csr), machInst);
-}
-if (bits(csr, 11, 10) == 0x3) {
-return std::make_shared(
-csprintf("CSR %s is read-only\n", csrName), machInst);
-}
-
-%(op_decl)s;
-%(op_rd)s;
-
-switch (csr) {
-  case CSR_SATP: {
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
-if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) {
-return std::make_shared(
-"SATP access in user mode or with TVM enabled\n",
-machInst);
-}
-break;
-  }
-  case CSR_MSTATUS: {
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-if (pm != PrivilegeMode::PRV_M) {
-return std::make_shared(
-"MSTATUS is only accessibly in machine mode\n",
-machInst);
-}
-break;
-  }
-  default:
-break;
-}
-
-RegVal data;
-if (csr == CSR_FCSR) {
-data = xc->readMiscReg(MISCREG_FFLAGS) |
+olddata = xc->readMiscReg(MISCREG_FFLAGS) |
   (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
 } else {
-data = xc->readMiscReg(midx);
+olddata = xc->readMiscReg(midx);
 }
+auto olddata_all = olddata;

-RegVal original = data;
-
-DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data &  
maskVal);

+olddata &= maskVal;
+DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, olddata);
+data = olddata;

 %(code)s;

-// We must keep those original bits not in the mask. Hidden bits  
should

-// keep their original value.
-data = (original & ~maskVal) | (data & maskVal);
-
-DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n", data, csrName);
-
-if (csr == CSR_FCSR) {
-xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
-xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
-} else {
-xc->setMiscReg(midx, data);
+data &= maskVal;
+if (data != olddata) {
+if (bits(csr, 11, 10) == 0x3) {
+return std::make_shared(
+csprintf("CSR %s is read-only\n", csrName),  
machInst);

+}
+auto newdata_all = data;
+// We must keep those original bits not in mask.
+// olddata and data only contain the bits visable
+// in current privilige level.
+newdata_all = 

[gem5-dev] Change in gem5/gem5[develop]: cpu: remove O3 dependency of CheckerCPU

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48080 )



Change subject: cpu: remove O3 dependency of CheckerCPU
..

cpu: remove O3 dependency of CheckerCPU

Currently, compiling CheckerCPU uses the dyn_inst.hh header from
O3CPU. However, including this header is not required and it
causes gem5 failed to build when O3CPU is not part of CPU_MODELS.

This change also involves moving the the dependency on
src/cpu/o3/dyn_inst.hh to src/cpu/o3/cpu.cc and src/cpu/lsq_unit.cc,
which previously includes src/cpu/o3/dyn_inst.hh implicitly through
src/cpu/checker/cpu.hh.

JIRA: https://gem5.atlassian.net/browse/GEM5-1025

Change-Id: I7664cd4b9591bf0a4635338fff576cb5f5cbfa10
Signed-off-by: Hoa Nguyen 
---
M src/cpu/checker/cpu.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/lsq_unit.cc
3 files changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index aebf522..a191ae4 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -51,7 +51,6 @@
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/inst_res.hh"
-#include "cpu/o3/dyn_inst.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index fbdfcbd..e352236 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -46,6 +46,7 @@
 #include "cpu/activity.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/checker/thread_context.hh"
+#include "cpu/o3/dyn_inst.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/thread_context.hh"
 #include "cpu/simple_thread.hh"
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 5394e4f..039184d 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -46,6 +46,7 @@
 #include "base/str.hh"
 #include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
+#include "cpu/o3/dyn_inst.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/lsq.hh"
 #include "debug/Activity.hh"

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Gerrit-Branch: develop
Gerrit-Change-Id: I7664cd4b9591bf0a4635338fff576cb5f5cbfa10
Gerrit-Change-Number: 48080
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[develop]: cpu: remove O3 dependency of CheckerCPU

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48079 )



Change subject: cpu: remove O3 dependency of CheckerCPU
..

cpu: remove O3 dependency of CheckerCPU

Currently, compiling CheckerCPU uses the dyn_inst.hh header from
O3CPU. However, including this header is not required and it
causes gem5 failed to build when O3CPU is not part of CPU_MODELS.

JIRA: https://gem5.atlassian.net/browse/GEM5-1025

Change-Id: I7664cd4b9591bf0a4635338fff576cb5f5cbfa10
Signed-off-by: Hoa Nguyen 
---
M src/cpu/checker/cpu.hh
1 file changed, 0 insertions(+), 1 deletion(-)



diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index aebf522..a191ae4 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -51,7 +51,6 @@
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/inst_res.hh"
-#include "cpu/o3/dyn_inst.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"

--
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Gerrit-Change-Number: 48079
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Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Explicitly add librt to scons

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47659 )


Change subject: scons: Explicitly add librt to scons
..

scons: Explicitly add librt to scons

gem5 uses the `shm_open()` funciton from .
This function requires linking to librt.

JIRA: https://gem5.atlassian.net/browse/GEM5-1015

Change-Id: I461400e3cb7474a80a995b264af2e03b19fea29c
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47659
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
A src/mem/SConsopts
1 file changed, 38 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/SConsopts b/src/mem/SConsopts
new file mode 100644
index 000..7d6ef35
--- /dev/null
+++ b/src/mem/SConsopts
@@ -0,0 +1,38 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Import('*')
+
+from gem5_scons import warning
+
+import gem5_scons
+
+with gem5_scons.Configure(main) as conf:
+have_shm_open = \
+conf.CheckLibWithHeader([None, 'rt'], 'sys/mman.h', 'C',
+'shm_open("/test", 0, 0);')
+if not have_shm_open:
+warning("Can't find library for sys/mman.")

--
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Gerrit-Change-Id: I461400e3cb7474a80a995b264af2e03b19fea29c
Gerrit-Change-Number: 47659
Gerrit-PatchSet: 9
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Not compiling with systemc when host is RISCV

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47660 )


Change subject: scons: Not compiling with systemc when host is RISCV
..

scons: Not compiling with systemc when host is RISCV

Compiling gem5 with systemc enabled results in the errors
described in https://gem5.atlassian.net/browse/GEM5-1027.

This change tells scons not to compile gem5 with systemc
when the host ISA is RISC-V.

JIRA: https://gem5.atlassian.net/browse/GEM5-1027

Change-Id: I04e1bc722c9d702472152c9116d89938e8408047
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47660
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/systemc/SConsopts
1 file changed, 8 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/systemc/SConsopts b/src/systemc/SConsopts
index 4f2ae5c..891431c 100644
--- a/src/systemc/SConsopts
+++ b/src/systemc/SConsopts
@@ -28,6 +28,14 @@
 from gem5_scons import warning

 def use_systemc_check(env, warn=False):
+import platform
+host_isa = platform.machine()
+# Disallow compiling systemc if the host ISA is RISC-V.
+# The error is described here:  
https://gem5.atlassian.net/browse/GEM5-1027

+if host_isa.startswith("riscv"):
+if warn:
+warning('Warning: Systemc may not work on RISC-V.')
+return False
 if env['PLATFORM'] == 'darwin':
 if warn:
 warning('Warning: Systemc may not work on Mac OS.')

--
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Gerrit-Change-Number: 47660
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Not compiling with systemc when host is RISCV

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47660 )



Change subject: scons: Not compiling with systemc when host is RISCV
..

scons: Not compiling with systemc when host is RISCV

Compiling gem5 with systemc enabled results in the errors
described in https://gem5.atlassian.net/browse/GEM5-1027.

This change tells scons not to compile gem5 with systemc
when the host ISA is RISC-V.

JIRA: https://gem5.atlassian.net/browse/GEM5-1027

Change-Id: I04e1bc722c9d702472152c9116d89938e8408047
Signed-off-by: Hoa Nguyen 
---
M src/systemc/SConsopts
1 file changed, 6 insertions(+), 0 deletions(-)



diff --git a/src/systemc/SConsopts b/src/systemc/SConsopts
index 4f2ae5c..65451cf 100644
--- a/src/systemc/SConsopts
+++ b/src/systemc/SConsopts
@@ -28,6 +28,12 @@
 from gem5_scons import warning

 def use_systemc_check(env, warn=False):
+import platform
+host_isa = platform.machine()
+if host_isa.startswith("riscv"):
+if warn:
+warning('Warning: Systemc may not work on RISC-V.')
+return False
 if env['PLATFORM'] == 'darwin':
 if warn:
 warning('Warning: Systemc may not work on Mac OS.')

--
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[gem5-dev] Change in gem5/gem5[develop]: scons: Explicitly add librt to scons

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47659 )



Change subject: scons: Explicitly add librt to scons
..

scons: Explicitly add librt to scons

Building gem5 requires linking to librt. Prior to this change, the
SConscript files do not include the librt explicitly, and building
gem5 on the preformatted disk of Ubuntu 21.04 for RISC-V results
in the missing reference to `shm_open`, which is part of librt.

This change tells scons to add librt to all combinations of building
gem5.

JIRA: https://gem5.atlassian.net/browse/GEM5-1015

Change-Id: I461400e3cb7474a80a995b264af2e03b19fea29c
Signed-off-by: Hoa Nguyen 
---
M SConstruct
1 file changed, 3 insertions(+), 0 deletions(-)



diff --git a/SConstruct b/SConstruct
index f3af8ff..5593c17 100755
--- a/SConstruct
+++ b/SConstruct
@@ -698,6 +698,9 @@
 env.Append(CCFLAGS='$CCFLAGS_EXTRA')
 env.Append(LINKFLAGS='$LDFLAGS_EXTRA')

+# Add librt, which is required by gem5
+env.Append(LIBS=['rt'])
+
 exports=['env']
 if main['USE_PYTHON']:
 exports.append('marshal_env')

--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Improve error message of missing files

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45105 )


Change subject: configs: Improve error message of missing files
..

configs: Improve error message of missing files

In PathSearchFunc.__call__(), filename is the name of the file
while filepath contains the relative path to the missing file
relative to $M5_PATH.

Outputing the filepath in the error message makes the error
message more useful as it provides the expected location of
the file as well as the name of the file.

Change-Id: I5f1fdb9e48ac9ae59a26d1a4a40bc9ff9acd
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45105
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/common/SysPaths.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/common/SysPaths.py b/configs/common/SysPaths.py
index 2b2fca3..762efaf 100644
--- a/configs/common/SysPaths.py
+++ b/configs/common/SysPaths.py
@@ -70,7 +70,7 @@
 return next(p for p in paths if os.path.exists(p))
 except StopIteration:
 raise IOError("Can't find file '{}' on {}."
-.format(filename, self.environment_variable))
+.format(filepath, self.environment_variable))

 disk = PathSearchFunc('disks')
 binary = PathSearchFunc('binaries')



1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5f1fdb9e48ac9ae59a26d1a4a40bc9ff9acd
Gerrit-Change-Number: 45105
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: Make sorted includes verifier less confusing

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46580 )


Change subject: util: Make sorted includes verifier less confusing
..

util: Make sorted includes verifier less confusing

verifiers.py complains about unordered includes where there is
more than one empty line under the #include region, even if
the includes are sorted.

This change adds a note about the fact.

Change-Id: I7a8dbc12fd82db0f0cadcfec270e42f6e0de4aea
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46580
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M util/style/verifiers.py
1 file changed, 4 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/style/verifiers.py b/util/style/verifiers.py
index efc347e..7ab7344 100644
--- a/util/style/verifiers.py
+++ b/util/style/verifiers.py
@@ -361,8 +361,10 @@

 if modified:
 if not silent:
-self.ui.write("invalid sorting of includes in %s\n"
-% (filename))
+self.ui.write("invalid sorting of includes in %s. Note:  
If "
+  "there is more than one empty line under  
the "

+  "#include region, please reduce it to one.\n"
+  % (filename))
 if self.ui.verbose:
 for start, end in modified.regions:
 self.ui.write("bad region [%d, %d)\n" % (start,  
end))


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7a8dbc12fd82db0f0cadcfec270e42f6e0de4aea
Gerrit-Change-Number: 46580
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem,configs,ext,util: Replace ExternalMaster by ExternalRequestor

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46581 )



Change subject: mem,configs,ext,util: Replace ExternalMaster by  
ExternalRequestor

..

mem,configs,ext,util: Replace ExternalMaster by ExternalRequestor

Signed-off-by: Hoa Nguyen 
Change-Id: Icc404e23df1026ec84250520007ce6f4b8f1edd4
---
M configs/common/FSConfig.py
M ext/sst/ExtMaster.cc
M ext/sst/ExtMaster.hh
M ext/sst/README
M ext/sst/gem5.cc
M ext/sst/gem5.hh
R src/mem/ExternalRequestor.py
M src/mem/SConscript
R src/mem/external_requestor.cc
R src/mem/external_requestor.hh
M util/tlm/README
M util/tlm/conf/tlm_master.py
M util/tlm/src/sc_master_port.cc
M util/tlm/src/sc_master_port.hh
M util/tlm/src/sim_control.cc
15 files changed, 62 insertions(+), 60 deletions(-)



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 4c1afce..cc93322 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -299,8 +299,8 @@

 if external_memory:
 # I/O traffic enters iobus
-self.external_io = ExternalMaster(port_data="external_io",
-  port_type=external_memory)
+self.external_io = ExternalRequestor(port_data="external_io",
+ port_type=external_memory)
 self.external_io.port = self.iobus.slave

 # Ensure iocache only receives traffic destined for (actual)  
memory.

diff --git a/ext/sst/ExtMaster.cc b/ext/sst/ExtMaster.cc
index 3afd6b4..4d6b54f 100644
--- a/ext/sst/ExtMaster.cc
+++ b/ext/sst/ExtMaster.cc
@@ -56,7 +56,7 @@
 using namespace SST::gem5;
 using namespace SST::MemHierarchy;

-ExtMaster::ExtMaster(gem5Component *g, Output , ::ExternalMaster& p,
+ExtMaster::ExtMaster(gem5Component *g, Output , ::ExternalRequestor& p,
 std::string ) :
 Port(n, p), out(o), port(p), simPhase(CONSTRUCTION),
 gem5(g), name(n)
diff --git a/ext/sst/ExtMaster.hh b/ext/sst/ExtMaster.hh
index 04e98e5..ec73993 100644
--- a/ext/sst/ExtMaster.hh
+++ b/ext/sst/ExtMaster.hh
@@ -70,12 +70,12 @@

 class gem5Component;

-class ExtMaster : public ExternalMaster::Port {
+class ExtMaster : public ExternalRequestor::Port {

 enum Phase { CONSTRUCTION, INIT, RUN };

 Output& out;
-const ExternalMaster& port;
+const ExternalRequestor& port;
 Phase simPhase;

 gem5Component *const gem5;
@@ -97,7 +97,7 @@
 bool recvTimingResp(PacketPtr);
 void recvReqRetry();

-ExtMaster(gem5Component*, Output&, ExternalMaster&, std::string&);
+ExtMaster(gem5Component*, Output&, ExternalRequestor&, std::string&);
 void init(unsigned phase);
 void setup();
 void finish();
@@ -105,7 +105,8 @@
 void clock();

 // receive Requests from SST bound for a gem5 slave;
-// this module is "external" from gem5's perspective, thus  
ExternalMaster.

+// this module is "external" from gem5's perspective, thus
+// ExternalRequestor.
 void handleEvent(SST::Event*);

 protected:
diff --git a/ext/sst/README b/ext/sst/README
index 0dcc45e..834f46b 100644
--- a/ext/sst/README
+++ b/ext/sst/README
@@ -6,7 +6,7 @@
 a notion of master and slave. This distinction is important to gem5, so
 when connecting a gem5 CPU to an SST cache, an ExternalResponder must be  
used,

 and similarly when connecting the memory side of SST cache to a gem5 port
-(for memory <-> I/O), an ExternalMaster must be used.
+(for memory <-> I/O), an ExternalRequestor must be used.

 The connector handles the administrative aspects of gem5
 (initialization, simulation, shutdown) as well as translating
@@ -45,7 +45,7 @@

 This directory provides:
 1. an SST "Component" for gem5;
-2. a class that implements gem5's "ExternalMaster" interface to connect  
with
+2. a class that implements gem5's "ExternalRequestor" interface to connect  
with

SST "Link"s exchanging "memEvents"
(sst/elements/memHierarchy stuff - caches, memories, etc.)
This lets gem5 receive packets from SST, as in
@@ -60,6 +60,6 @@
v
SST cache hierarchy <-> SST memory
^
-   | [ExternalMaster]
+   | [ExternalRequestor]
v
gem5 I/O devices (terminal, disk, etc.)
diff --git a/ext/sst/gem5.cc b/ext/sst/gem5.cc
index b18eadc..e5c2a9f 100644
--- a/ext/sst/gem5.cc
+++ b/ext/sst/gem5.cc
@@ -111,7 +111,7 @@
 setDebugFlag(flag);
 }

-ExternalMaster::registerHandler("sst", this); // these are idempotent
+ExternalRequestor::registerHandler("sst", this); // these are  
idempotent

 ExternalResponder ::registerHandler("sst", this);

 // Initialize m5 special signal handling.
@@ -248,9 +248,9 @@
 }
 }

-ExternalMaster::Port*
+ExternalRequestor::Port*
 gem5Component::getExternalPort(const std::string ,
-ExternalMaster , const std::string _data)
+ExternalRequestor , const std::string _data)
 {
 std::string s(name); // bridges non-& result 

[gem5-dev] Change in gem5/gem5[develop]: util: Make sorted includes verifier less confusing

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46580 )



Change subject: util: Make sorted includes verifier less confusing
..

util: Make sorted includes verifier less confusing

verifiers.py complains about unordered includes where there is
more than one empty line under the #include region, even if
the includes are sorted.

This change adds a note about the fact.

Change-Id: I7a8dbc12fd82db0f0cadcfec270e42f6e0de4aea
Signed-off-by: Hoa Nguyen 
---
M util/style/verifiers.py
1 file changed, 4 insertions(+), 2 deletions(-)



diff --git a/util/style/verifiers.py b/util/style/verifiers.py
index efc347e..7ab7344 100644
--- a/util/style/verifiers.py
+++ b/util/style/verifiers.py
@@ -361,8 +361,10 @@

 if modified:
 if not silent:
-self.ui.write("invalid sorting of includes in %s\n"
-% (filename))
+self.ui.write("invalid sorting of includes in %s. Note:  
If "
+  "there is more than one empty line under  
the "

+  "#include region, please reduce it to one.\n"
+  % (filename))
 if self.ui.verbose:
 for start, end in modified.regions:
 self.ui.write("bad region [%d, %d)\n" % (start,  
end))


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7a8dbc12fd82db0f0cadcfec270e42f6e0de4aea
Gerrit-Change-Number: 46580
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: fix se.py error when using "--redirects"

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46099 )


Change subject: configs: fix se.py error when using "--redirects"
..

configs: fix se.py error when using "--redirects"

Currently, the workload is initialized before host filesystem
redirections take place (i.e. before --redirects is taken into
account).

This change moves the initialization of the workload to the place
where the redirections have taken place.

JIRA: https://gem5.atlassian.net/browse/GEM5-1001

Change-Id: Id8f4c8486b4e0adb19ccc25d02d0c28cbf671063
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46099
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/example/se.py
1 file changed, 3 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/se.py b/configs/example/se.py
index 891dd72..65acf6a 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -166,8 +166,7 @@
 system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)],
 mem_mode = test_mem_mode,
 mem_ranges = [AddrRange(args.mem_size)],
-cache_line_size = args.cacheline_size,
-workload = SEWorkload.init_compatible(mp0_path))
+cache_line_size = args.cacheline_size)

 if numThreads > 1:
 system.multi_thread = True
@@ -262,6 +261,8 @@
 MemConfig.config_mem(args, system)
 config_filesystem(system, args)

+system.workload = SEWorkload.init_compatible(mp0_path)
+
 if args.wait_gdb:
 for cpu in system.cpu:
 cpu.wait_for_remote_gdb = True

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id8f4c8486b4e0adb19ccc25d02d0c28cbf671063
Gerrit-Change-Number: 46099
Gerrit-PatchSet: 5
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bobby R. Bruce 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: replace desks, add desc where required

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46119 )


Change subject: mem-ruby: replace desks, add desc where required
..

mem-ruby: replace desks, add desc where required

Events in *.sm are required to have "desc" defined.

JIRA: https://gem5.atlassian.net/browse/GEM5-999

Change-Id: I95f59c422bdd264a9e1077b75bf7a0e9f39685aa
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46119
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/chi/CHI-cache.sm
M src/mem/ruby/protocol/chi/CHI-mem.sm
3 files changed, 114 insertions(+), 114 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm

index 03010d5..3b4a801 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -114,7 +114,7 @@
 DMA_WRITE_PARTIAL, desc="DMA Write partial line";
 DMA_ACK,   desc="DMA Ack";
 Data,  desc="Data to directory";
-All_Acks,  desk="All pending acks, unblocks, etc have been  
received";
+All_Acks,  desc="All pending acks, unblocks, etc have been  
received";

   }

   // TYPES
diff --git a/src/mem/ruby/protocol/chi/CHI-cache.sm  
b/src/mem/ruby/protocol/chi/CHI-cache.sm

index 160f674..a0d1888 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache.sm
@@ -206,7 +206,7 @@
   state_declaration(State, default="Cache_State_null") {
 // Stable states

-I, AccessPermission:Invalid,desk="Invalid / not present locally or  
upstream";
+I, AccessPermission:Invalid,desc="Invalid / not present locally or  
upstream";


 // States when block is present in local cache only
 SC, AccessPermission:Read_Only, desc="Shared Clean";
@@ -216,21 +216,21 @@
 UD_T, AccessPermission:Read_Write,  desc="UD with use timeout";

 // Invalid in local cache but present in upstream caches
-RU, AccessPermission:Invalid,   desk="Upstream requester has line in  
UD/UC";
-RSC, AccessPermission:Invalid,  desk="Upstream requester has line in  
SC";
-RSD, AccessPermission:Invalid,  desk="Upstream requester has line in  
SD and maybe SC";
-RUSC, AccessPermission:Invalid, desk="RSC + this node stills has  
exclusive access";
-RUSD, AccessPermission:Invalid, desk="RSD + this node stills has  
exclusive access";
+RU, AccessPermission:Invalid,   desc="Upstream requester has line in  
UD/UC";
+RSC, AccessPermission:Invalid,  desc="Upstream requester has line in  
SC";
+RSD, AccessPermission:Invalid,  desc="Upstream requester has line in  
SD and maybe SC";
+RUSC, AccessPermission:Invalid, desc="RSC + this node stills has  
exclusive access";
+RUSD, AccessPermission:Invalid, desc="RSD + this node stills has  
exclusive access";


 // Both in local and upstream caches. In some cases local maybe stale
-SC_RSC, AccessPermission:Read_Only,desk="SC + RSC";
-SD_RSC, AccessPermission:Read_Only,desk="SD + RSC";
-SD_RSD, AccessPermission:Read_Only,desk="SD + RSD";
-UC_RSC, AccessPermission:Read_Write,   desk="UC + RSC";
-UC_RU, AccessPermission:Invalid,   desk="UC + RU";
-UD_RU, AccessPermission:Invalid,   desk="UD + RU";
-UD_RSD, AccessPermission:Read_Write,   desk="UD + RSD";
-UD_RSC, AccessPermission:Read_Write,   desk="UD + RSC";
+SC_RSC, AccessPermission:Read_Only,desc="SC + RSC";
+SD_RSC, AccessPermission:Read_Only,desc="SD + RSC";
+SD_RSD, AccessPermission:Read_Only,desc="SD + RSD";
+UC_RSC, AccessPermission:Read_Write,   desc="UC + RSC";
+UC_RU, AccessPermission:Invalid,   desc="UC + RU";
+UD_RU, AccessPermission:Invalid,   desc="UD + RU";
+UD_RSD, AccessPermission:Read_Write,   desc="UD + RSD";
+UD_RSC, AccessPermission:Read_Write,   desc="UD + RSC";

 // Generic transient state
 // There is only a transient "BUSY" state. The actions taken at this  
state

@@ -261,90 +261,90 @@

 // Events triggered by sequencer requests or snoops in the rdy queue
 // See CHIRequestType in CHi-msg.sm for descriptions
-Load;
-Store;
-Prefetch;
-ReadShared;
-ReadNotSharedDirty;
-ReadUnique;
-ReadUnique_PoC;
-ReadOnce;
-CleanUnique;
-Evict;
-WriteBackFull;
-WriteEvictFull;
-WriteCleanFull;
-WriteUnique;
-WriteUniquePtl_PoC;
-WriteUniqueFull_PoC;
-WriteUniqueFull_PoC_Alloc;
-SnpCleanInvalid;
-SnpShared;
-SnpSharedFwd;
-SnpNotSharedDirtyFwd;
-SnpUnique;
-SnpUniqueFwd;
-SnpOnce;
-SnpOnceFwd;
-SnpStalled; // A 

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: replace desks, add desc where required

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46119 )



Change subject: mem-ruby: replace desks, add desc where required
..

mem-ruby: replace desks, add desc where required

Events in *.sm are required to have "desc" defined.

JIRA: https://gem5.atlassian.net/browse/GEM5-999

Change-Id: I95f59c422bdd264a9e1077b75bf7a0e9f39685aa
Signed-off-by: Hoa Nguyen 
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/chi/CHI-cache.sm
M src/mem/ruby/protocol/chi/CHI-mem.sm
3 files changed, 114 insertions(+), 114 deletions(-)



diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm

index 03010d5..3b4a801 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -114,7 +114,7 @@
 DMA_WRITE_PARTIAL, desc="DMA Write partial line";
 DMA_ACK,   desc="DMA Ack";
 Data,  desc="Data to directory";
-All_Acks,  desk="All pending acks, unblocks, etc have been  
received";
+All_Acks,  desc="All pending acks, unblocks, etc have been  
received";

   }

   // TYPES
diff --git a/src/mem/ruby/protocol/chi/CHI-cache.sm  
b/src/mem/ruby/protocol/chi/CHI-cache.sm

index 160f674..a0d1888 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache.sm
@@ -206,7 +206,7 @@
   state_declaration(State, default="Cache_State_null") {
 // Stable states

-I, AccessPermission:Invalid,desk="Invalid / not present locally or  
upstream";
+I, AccessPermission:Invalid,desc="Invalid / not present locally or  
upstream";


 // States when block is present in local cache only
 SC, AccessPermission:Read_Only, desc="Shared Clean";
@@ -216,21 +216,21 @@
 UD_T, AccessPermission:Read_Write,  desc="UD with use timeout";

 // Invalid in local cache but present in upstream caches
-RU, AccessPermission:Invalid,   desk="Upstream requester has line in  
UD/UC";
-RSC, AccessPermission:Invalid,  desk="Upstream requester has line in  
SC";
-RSD, AccessPermission:Invalid,  desk="Upstream requester has line in  
SD and maybe SC";
-RUSC, AccessPermission:Invalid, desk="RSC + this node stills has  
exclusive access";
-RUSD, AccessPermission:Invalid, desk="RSD + this node stills has  
exclusive access";
+RU, AccessPermission:Invalid,   desc="Upstream requester has line in  
UD/UC";
+RSC, AccessPermission:Invalid,  desc="Upstream requester has line in  
SC";
+RSD, AccessPermission:Invalid,  desc="Upstream requester has line in  
SD and maybe SC";
+RUSC, AccessPermission:Invalid, desc="RSC + this node stills has  
exclusive access";
+RUSD, AccessPermission:Invalid, desc="RSD + this node stills has  
exclusive access";


 // Both in local and upstream caches. In some cases local maybe stale
-SC_RSC, AccessPermission:Read_Only,desk="SC + RSC";
-SD_RSC, AccessPermission:Read_Only,desk="SD + RSC";
-SD_RSD, AccessPermission:Read_Only,desk="SD + RSD";
-UC_RSC, AccessPermission:Read_Write,   desk="UC + RSC";
-UC_RU, AccessPermission:Invalid,   desk="UC + RU";
-UD_RU, AccessPermission:Invalid,   desk="UD + RU";
-UD_RSD, AccessPermission:Read_Write,   desk="UD + RSD";
-UD_RSC, AccessPermission:Read_Write,   desk="UD + RSC";
+SC_RSC, AccessPermission:Read_Only,desc="SC + RSC";
+SD_RSC, AccessPermission:Read_Only,desc="SD + RSC";
+SD_RSD, AccessPermission:Read_Only,desc="SD + RSD";
+UC_RSC, AccessPermission:Read_Write,   desc="UC + RSC";
+UC_RU, AccessPermission:Invalid,   desc="UC + RU";
+UD_RU, AccessPermission:Invalid,   desc="UD + RU";
+UD_RSD, AccessPermission:Read_Write,   desc="UD + RSD";
+UD_RSC, AccessPermission:Read_Write,   desc="UD + RSC";

 // Generic transient state
 // There is only a transient "BUSY" state. The actions taken at this  
state

@@ -261,90 +261,90 @@

 // Events triggered by sequencer requests or snoops in the rdy queue
 // See CHIRequestType in CHi-msg.sm for descriptions
-Load;
-Store;
-Prefetch;
-ReadShared;
-ReadNotSharedDirty;
-ReadUnique;
-ReadUnique_PoC;
-ReadOnce;
-CleanUnique;
-Evict;
-WriteBackFull;
-WriteEvictFull;
-WriteCleanFull;
-WriteUnique;
-WriteUniquePtl_PoC;
-WriteUniqueFull_PoC;
-WriteUniqueFull_PoC_Alloc;
-SnpCleanInvalid;
-SnpShared;
-SnpSharedFwd;
-SnpNotSharedDirtyFwd;
-SnpUnique;
-SnpUniqueFwd;
-SnpOnce;
-SnpOnceFwd;
-SnpStalled; // A snoop stall triggered from the inport
+Load,desc="";
+Store,   desc="";
+Prefetch,desc="";
+ReadShared,  desc="";
+ReadNotSharedDirty,  desc="";
+

[gem5-dev] Change in gem5/gem5[develop]: configs: fix se.py error when using "--redirects"

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46099 )



Change subject: configs: fix se.py error when using "--redirects"
..

configs: fix se.py error when using "--redirects"

Currently, the workload is initialized before host filesystem
redirections take place (i.e. before --redirects is taken into
account).

This change moves the initialization of the workload to the place
when the redirections have taken place.

Change-Id: Id8f4c8486b4e0adb19ccc25d02d0c28cbf671063
Signed-off-by: Hoa Nguyen 
---
M configs/example/se.py
1 file changed, 3 insertions(+), 2 deletions(-)



diff --git a/configs/example/se.py b/configs/example/se.py
index 891dd72..d42d147 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -166,8 +166,7 @@
 system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)],
 mem_mode = test_mem_mode,
 mem_ranges = [AddrRange(args.mem_size)],
-cache_line_size = args.cacheline_size,
-workload = SEWorkload.init_compatible(mp0_path))
+cache_line_size = args.cacheline_size)

 if numThreads > 1:
 system.multi_thread = True
@@ -262,6 +261,8 @@
 MemConfig.config_mem(args, system)
 config_filesystem(system, args)

+system.workload = SEWorkload.init_compatible(mp0_path))
+
 if args.wait_gdb:
 for cpu in system.cpu:
 cpu.wait_for_remote_gdb = True

--
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[gem5-dev] Change in gem5/gem5[develop]: util-docker: Use python3 by default for Ubuntu 18.04 docker images

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45125 )


Change subject: util-docker: Use python3 by default for Ubuntu 18.04 docker  
images

..

util-docker: Use python3 by default for Ubuntu 18.04 docker images

gem5 dropped the support for python2. This change sets python3
to have a higher priority than python2 in the Ubuntu 18.04 docker
images. This is done so that gem5 will be compiled and tested
in the python3 environment by default.

JIRA: https://gem5.atlassian.net/browse/GEM5-958

Signed-off-by: Hoa Nguyen 
Change-Id: I11ffb06697ecf4cebf9f98b611641faa42805547
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45125
Maintainer: Bobby R. Bruce 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
M util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile
2 files changed, 6 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile  
b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile

index 2403a50..775e549 100644
--- a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
+++ b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
@@ -32,3 +32,6 @@
 libprotobuf-dev protobuf-compiler libprotoc-dev  
libgoogle-perftools-dev \

 python3-dev python3 python3-six doxygen libboost-all-dev \
 libhdf5-serial-dev python3-pydot libpng-dev libelf-dev pkg-config
+
+RUN update-alternatives --install /usr/bin/python python /usr/bin/python3  
10

+RUN update-alternatives --install /usr/bin/python python /usr/bin/python2 1
diff --git a/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile  
b/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile

index 5ec6784..53a7d92 100644
--- a/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile
+++ b/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile
@@ -30,3 +30,6 @@
 RUN apt -y upgrade
 RUN apt -y install build-essential scons zlib1g-dev m4 python3-dev python3  
\

 python3-six
+
+RUN update-alternatives --install /usr/bin/python python /usr/bin/python3  
10

+RUN update-alternatives --install /usr/bin/python python /usr/bin/python2 1

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I11ffb06697ecf4cebf9f98b611641faa42805547
Gerrit-Change-Number: 45125
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: Use python3 by default for Ubuntu 18.04 docker images

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45125 )



Change subject: util: Use python3 by default for Ubuntu 18.04 docker images
..

util: Use python3 by default for Ubuntu 18.04 docker images

gem5 dropped the support for python2. This change sets python3
to have a higher priority than python2 in the Ubuntu 18.04 docker
images. This is done so that gem5 will be compiled and tested
in the python3 environment by default.

JIRA: https://gem5.atlassian.net/browse/GEM5-958

Signed-off-by: Hoa Nguyen 
Change-Id: I11ffb06697ecf4cebf9f98b611641faa42805547
---
M util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
M util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile
2 files changed, 6 insertions(+), 0 deletions(-)



diff --git a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile  
b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile

index 2403a50..775e549 100644
--- a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
+++ b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
@@ -32,3 +32,6 @@
 libprotobuf-dev protobuf-compiler libprotoc-dev  
libgoogle-perftools-dev \

 python3-dev python3 python3-six doxygen libboost-all-dev \
 libhdf5-serial-dev python3-pydot libpng-dev libelf-dev pkg-config
+
+RUN update-alternatives --install /usr/bin/python python /usr/bin/python3  
10

+RUN update-alternatives --install /usr/bin/python python /usr/bin/python2 1
diff --git a/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile  
b/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile

index 5ec6784..53a7d92 100644
--- a/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile
+++ b/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile
@@ -30,3 +30,6 @@
 RUN apt -y upgrade
 RUN apt -y install build-essential scons zlib1g-dev m4 python3-dev python3  
\

 python3-six
+
+RUN update-alternatives --install /usr/bin/python python /usr/bin/python3  
10

+RUN update-alternatives --install /usr/bin/python python /usr/bin/python2 1

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I11ffb06697ecf4cebf9f98b611641faa42805547
Gerrit-Change-Number: 45125
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[develop]: base: Add warnings for legacy stats

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44706 )


Change subject: base: Add warnings for legacy stats
..

base: Add warnings for legacy stats

Legacy stat is defined as a stat that doesn't belong to any
Stats::Group.

JIRA: https://gem5.atlassian.net/browse/GEM5-645

Change-Id: I8d426882b6bf7600998e181f18d1339ce82d5917
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44706
Reviewed-by: Daniel Carvalho 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/statistics.hh
1 file changed, 9 insertions(+), 0 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 63bfb5b..9de975b 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -75,6 +75,7 @@
 #include "base/cast.hh"
 #include "base/cprintf.hh"
 #include "base/intmath.hh"
+#include "base/logging.hh"
 #include "base/stats/group.hh"
 #include "base/stats/info.hh"
 #include "base/stats/output.hh"
@@ -259,6 +260,14 @@

 if (desc)
 info->desc = desc;
+
+// Stat that does not belong to any Stats::Group is a legacy stat
+std::string common_message = "Legacy stat is a stat that does not "
+"belong to any Stats::Group. Legacy stat is deprecated.";
+if (parent == nullptr && name != nullptr)
+warn(csprintf("`%s` is a legacy stat. %s", name,  
common_message));

+else if (parent == nullptr)
+warn_once("One of the stats is a legacy stat. " +  
common_message);

 }

 /**

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I8d426882b6bf7600998e181f18d1339ce82d5917
Gerrit-Change-Number: 44706
Gerrit-PatchSet: 8
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Improve error message of missing files

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45105 )



Change subject: configs: Improve error message of missing files
..

configs: Improve error message of missing files

In PathSearchFunc.__call__(), filename is the name of the file
while filepath contains the relative path to the missing file
relative to $M5_PATH.

Outputing the filepath in the error message makes the error
message more useful as it provides the expected location of
the file as well as the name of the file.

Change-Id: I5f1fdb9e48ac9ae59a26d1a4a40bc9ff9acd
Signed-off-by: Hoa Nguyen 
---
M configs/common/SysPaths.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/configs/common/SysPaths.py b/configs/common/SysPaths.py
index 2b2fca3..762efaf 100644
--- a/configs/common/SysPaths.py
+++ b/configs/common/SysPaths.py
@@ -70,7 +70,7 @@
 return next(p for p in paths if os.path.exists(p))
 except StopIteration:
 raise IOError("Can't find file '{}' on {}."
-.format(filename, self.environment_variable))
+.format(filepath, self.environment_variable))

 disk = PathSearchFunc('disks')
 binary = PathSearchFunc('binaries')

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I5f1fdb9e48ac9ae59a26d1a4a40bc9ff9acd
Gerrit-Change-Number: 45105
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[develop]: util: Fix checkpoint-tester.py checkpoint parameter

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/9 )


Change subject: util: Fix checkpoint-tester.py checkpoint parameter
..

util: Fix checkpoint-tester.py checkpoint parameter

checkpoint-tester script tests gem5's checkpoints by
using gem5 to produce a series of checkpoints, each with
a specified interval. After that, for all K > 1,
each of K-th produced checkpoint is used by gem5 to produce
the {K+1}-th checkpoint. The newly produced checkpoint will
be compared against the {K+1}-th checkpoint that was
previously produced.

Previously, in the tester script, the inputs to
`--take-checkpoints X,Y` was `(interval, interval)`.
The intention was to restore the N-th checkpoint and to run
the simulation for `interval` ticks.

According to the current configs/common/Options.py file,
`--take-checkpoints X,Y` means `X` is the starting tick of
the simulation, while `Y` is the number of ticks to be simulated
after tick `X`.

Therefore, `X` should be the starting tick of the N-th checkpont,
and this change addresses this problem.

Change-Id: I1fd7c91c9454f42a4fb98aa878fb5e4ac7d238f3
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/9
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Daniel Carvalho 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M util/checkpoint-tester.py
1 file changed, 8 insertions(+), 7 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/checkpoint-tester.py b/util/checkpoint-tester.py
index 2600644..5817469 100755
--- a/util/checkpoint-tester.py
+++ b/util/checkpoint-tester.py
@@ -55,12 +55,12 @@
 #
 # Examples:
 #
-# util/checkpoint-tester.py -i 40 -- build//m5.opt \
-#  configs/example/se.py -c  
tests/test-progs/hello/bin//tru64/hello \

+# util/checkpoint-tester.py -i 40 -- build//gem5.opt \
+#  configs/example/se.py -c  
tests/test-progs/hello/bin//linux/hello \

 #  --output=progout --errout=progerr
 #
-# util/checkpoint-tester.py -i 2000 -- build//m5.opt \
-#  configs/example/fs.py --script tests/halt.sh
+# util/checkpoint-tester.py -i 2000 -- build//gem5.opt \
+#  configs/example/fs.py --script configs/boot/halt.sh
 #


@@ -94,12 +94,12 @@

 args = args.cmdline[1:]

-initial_args = ['--take-checkpoints', '%d,%d' % (interval, interval)]
+checkpoint_args = ['--take-checkpoints', '%d,%d' % (interval, interval)]

 cptdir = os.path.join(top_dir, 'm5out')

 print('===> Running initial simulation.')
-subprocess.call([m5_binary] + ['-red', cptdir] + args + initial_args)
+subprocess.call([m5_binary] + ['-red', cptdir] + args + checkpoint_args)

 dirs = os.listdir(cptdir)
 expr = re.compile('cpt\.([0-9]*)')
@@ -117,8 +117,9 @@
 # less than tha number of checkpoints.
 for i in range(1, len(cpts)):
 print('===> Running test %d of %d.' % (i, len(cpts)-1))
+checkpoint_args = ['--take-checkpoints', '%d,%d' % (cpts[i], interval)]
 mydir = os.path.join(top_dir, 'test.%d' % i)
-subprocess.call([m5_binary] + ['-red', mydir] + args + initial_args +
+subprocess.call([m5_binary] + ['-red', mydir] + args + checkpoint_args  
+

 ['--max-checkpoints' , '1', '--checkpoint-dir', cptdir,
  '--checkpoint-restore', str(i)])
 cpt_name = 'cpt.%d' % cpts[i]

--
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Gerrit-Change-Id: I1fd7c91c9454f42a4fb98aa878fb5e4ac7d238f3
Gerrit-Change-Number: 9
Gerrit-PatchSet: 4
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix stats name in arm/fs_power.py

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44626 )


Change subject: configs: Fix stats name in arm/fs_power.py
..

configs: Fix stats name in arm/fs_power.py

In the config, there are stats having name changed:
- overall_misses -> overallMisses
- sim_seconds -> simSeconds
- overall_accesses -> overallAccesses

JIRA: https://gem5.atlassian.net/browse/GEM5-957

Signed-off-by: Hoa Nguyen 
Change-Id: I35faa72b12320e6b41833f601eb23604358b3d42
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44626
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Giacomo Travaglini 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/example/arm/fs_power.py
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/arm/fs_power.py  
b/configs/example/arm/fs_power.py

index 1c7b6b7..7ae9cf8 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -51,8 +51,8 @@
 # 2A per IPC, 3pA per cache miss
 # and then convert to Watt
 self.dyn =  "voltage * (2 * {}.ipc + 3 * 0.1 * " \
-"{}.dcache.overall_misses /  
sim_seconds)".format(cpu_path,
-  
cpu_path)
+"{}.dcache.overallMisses /  
simSeconds)".format(cpu_path,
+
cpu_path)

 self.st = "4 * temp"

 class CpuPowerOff(MathExprPowerModel):
@@ -72,10 +72,10 @@
 class L2PowerOn(MathExprPowerModel):
 def __init__(self, l2_path, **kwargs):
 super(L2PowerOn, self).__init__(**kwargs)
-# Example to report l2 Cache overall_accesses
+# Example to report l2 Cache overallAccesses
 # The estimated power is converted to Watt and will vary based
 # on the size of the cache
-self.dyn = "{}.overall_accesses * 0.18000".format(l2_path)
+self.dyn = "{}.overallAccesses * 0.18000".format(l2_path)
 self.st = "(voltage * 3)/10"

 class L2PowerOff(MathExprPowerModel):

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I35faa72b12320e6b41833f601eb23604358b3d42
Gerrit-Change-Number: 44626
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Add warnings for legacy stats

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44706 )



Change subject: base: Add warnings for legacy stats
..

base: Add warnings for legacy stats

Legacy stat is defined as a stat that doesn't belong to any
Stats::Group.

Change-Id: I8d426882b6bf7600998e181f18d1339ce82d5917
Signed-off-by: Hoa Nguyen 
---
M src/base/statistics.hh
1 file changed, 34 insertions(+), 3 deletions(-)



diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 63bfb5b..548c351 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -546,6 +546,10 @@
 : DataWrap(parent, name, unit, desc)
 {
 this->doInit();
+if (parent == nullptr && name != nullptr)
+warn(csprintf("`%s` is a legacy stat", name));
+else if (parent == nullptr)
+warn_once("Legacy stat exists");
 }

   public:
@@ -704,6 +708,10 @@
 : DataWrap(parent, name, unit, desc),
   proxy(NULL)
 {
+if (parent == nullptr && name != nullptr)
+warn(csprintf("`%s` is a legacy stat", name));
+else if (parent == nullptr)
+warn_once("Legacy stat exists");
 }

 ~ValueBase() { if (proxy) delete proxy; }
@@ -1007,7 +1015,12 @@
const char *desc)
 : DataWrapVec(parent, name, unit, desc),
   storage(nullptr), _size(0)
-{}
+{
+if (parent == nullptr && name != nullptr)
+warn(csprintf("`%s` is a legacy stat", name));
+else if (parent == nullptr)
+warn_once("Legacy stat exists");
+}

 ~VectorBase()
 {
@@ -1150,7 +1163,12 @@
  const char *desc)
 : DataWrapVec2d(parent, name, unit,  
desc),

   x(0), y(0), _size(0), storage(nullptr)
-{}
+{
+if (parent == nullptr && name != nullptr)
+warn(csprintf("`%s` is a legacy stat", name));
+else if (parent == nullptr)
+warn_once("Legacy stat exists");
+}

 ~Vector2dBase()
 {
@@ -1311,6 +1329,10 @@
  const char *desc)
 : DataWrap(parent, name, unit, desc)
 {
+if (parent == nullptr && name != nullptr)
+warn(csprintf("`%s` is a legacy stat", name));
+else if (parent == nullptr)
+warn_once("Legacy stat exists");
 }

 /**
@@ -1409,7 +1431,12 @@
const char *desc)
 : DataWrapVec(parent, name, unit,  
desc),

   storage(NULL)
-{}
+{
+if (parent == nullptr && name != nullptr)
+warn(csprintf("`%s` is a legacy stat", name));
+else if (parent == nullptr)
+warn_once("Legacy stat exists");
+}

 ~VectorDistBase()
 {
@@ -2452,6 +2479,10 @@
const char *desc)
 : DataWrap(parent, name, unit, desc)
 {
+if (parent == nullptr && name != nullptr)
+warn(csprintf("`%s` is a legacy stat", name));
+else if (parent == nullptr)
+warn_once("Legacy stat exists");
 }

 /**

--
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Gerrit-Change-Number: 44706
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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix stats name in arm/fs_power.py

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44626 )



Change subject: configs: Fix stats name in arm/fs_power.py
..

configs: Fix stats name in arm/fs_power.py

In the config, there are stats having name changed:
- overall_misses -> overallMisses
- sim_seconds -> simSeconds
- overall_accesses -> overallAccesses

JIRA: https://gem5.atlassian.net/browse/GEM5-957

Signed-off-by: Hoa Nguyen 
Change-Id: I35faa72b12320e6b41833f601eb23604358b3d42
---
M configs/example/arm/fs_power.py
1 file changed, 4 insertions(+), 4 deletions(-)



diff --git a/configs/example/arm/fs_power.py  
b/configs/example/arm/fs_power.py

index 1c7b6b7..7ae9cf8 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -51,8 +51,8 @@
 # 2A per IPC, 3pA per cache miss
 # and then convert to Watt
 self.dyn =  "voltage * (2 * {}.ipc + 3 * 0.1 * " \
-"{}.dcache.overall_misses /  
sim_seconds)".format(cpu_path,
-  
cpu_path)
+"{}.dcache.overallMisses /  
simSeconds)".format(cpu_path,
+
cpu_path)

 self.st = "4 * temp"

 class CpuPowerOff(MathExprPowerModel):
@@ -72,10 +72,10 @@
 class L2PowerOn(MathExprPowerModel):
 def __init__(self, l2_path, **kwargs):
 super(L2PowerOn, self).__init__(**kwargs)
-# Example to report l2 Cache overall_accesses
+# Example to report l2 Cache overallAccesses
 # The estimated power is converted to Watt and will vary based
 # on the size of the cache
-self.dyn = "{}.overall_accesses * 0.18000".format(l2_path)
+self.dyn = "{}.overallAccesses * 0.18000".format(l2_path)
 self.st = "(voltage * 3)/10"

 class L2PowerOff(MathExprPowerModel):

--
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[gem5-dev] Change in gem5/gem5[develop]: util: Add missing parameter for print_insts

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/8 )


Change subject: util: Add missing parameter for print_insts
..

util: Add missing parameter for print_insts

JIRA: https://gem5.atlassian.net/browse/GEM5-949

Change-Id: I74fe7adc06124d193f17d682882766484ac18528
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/8
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M util/o3-pipeview.py
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/o3-pipeview.py b/util/o3-pipeview.py
index 11e86a7..630c536 100755
--- a/util/o3-pipeview.py
+++ b/util/o3-pipeview.py
@@ -129,7 +129,8 @@
 if fields[1] == 'fetch':
 if ((stop_tick > 0 and int(fields[2]) >  
stop_tick+insts['tick_drift']) or
 (stop_sn > 0 and int(fields[5]) >  
(stop_sn+insts['max_threshold']))):
-print_insts(outfile, cycle_time, width, color,  
timestamps, 0)
+print_insts(outfile, cycle_time, width, color,  
timestamps,

+store_completions, 0)
 return
 (curr_inst['pc'], curr_inst['upc']) = fields[3:5]
 curr_inst['sn'] = int(fields[5])

--
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Gerrit-Change-Number: 8
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: util: Make o3-pipeview Python3 compatible

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/7 )


Change subject: util: Make o3-pipeview Python3 compatible
..

util: Make o3-pipeview Python3 compatible

JIRA: https://gem5.atlassian.net/browse/GEM5-955

Change-Id: I48cb0bfb784eafe2057eb1095e6aad7abf9a1bc9
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/7
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M util/o3-pipeview.py
1 file changed, 6 insertions(+), 9 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/o3-pipeview.py b/util/o3-pipeview.py
index 2401e8f..11e86a7 100755
--- a/util/o3-pipeview.py
+++ b/util/o3-pipeview.py
@@ -148,10 +148,6 @@
 fields = line.split(':')


-#Sorts out instructions according to sequence number
-def compare_by_sn(a, b):
-return cmp(a['sn'], b['sn'])
-
 # Puts new instruction into the print queue.
 # Sorts out and prints instructions when their number reaches threshold  
value
 def queue_inst(outfile, inst, cycle_time, width, color, timestamps,  
store_completions):

@@ -164,7 +160,8 @@
 # Sorts out and prints instructions in print queue
 def print_insts(outfile, cycle_time, width, color, timestamps,  
store_completions, lower_threshold):

 global insts
-insts['queue'].sort(compare_by_sn)
+# sort the list of insts by sequence numbers
+insts['queue'].sort(key=lambda inst: inst['sn'])
 while len(insts['queue']) > lower_threshold:
 print_item=insts['queue'].pop(0)
 # As the instructions are processed out of order the main loop  
starts

@@ -223,7 +220,7 @@
 # Print

 time_width = width * cycle_time
-base_tick = (inst['fetch'] / time_width) * time_width
+base_tick = (inst['fetch'] // time_width) * time_width

 # Find out the time of the last event - it may not
 # be 'retire' if the instruction is not comlpeted.
@@ -237,7 +234,7 @@
 if ((last_event_time - inst['fetch']) < time_width):
 num_lines = 1 # compact form
 else:
-num_lines = ((last_event_time - base_tick) / time_width) + 1
+num_lines = ((last_event_time - base_tick) // time_width) + 1

 curr_color = termcap.Normal

@@ -267,7 +264,7 @@
 if (stages[event[2]]['name'] == 'dispatch' and
 inst['dispatch'] == inst['issue']):
 continue
-outfile.write(curr_color + dot * ((event[0] / cycle_time) -  
pos))
+outfile.write(curr_color + dot * ((event[0] // cycle_time) -  
pos))

 outfile.write(stages[event[2]]['color'] +
   stages[event[2]]['shorthand'])

@@ -276,7 +273,7 @@
 else:
 curr_color = termcap.Normal

-pos = (event[0] / cycle_time) + 1
+pos = (event[0] // cycle_time) + 1
 outfile.write(curr_color + dot * (width - pos) + termcap.Normal +
   ']-(' + str(base_tick + i * time_width).rjust(15)  
+ ') ')

 if i == 0:

--
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Gerrit-Change-Number: 7
Gerrit-PatchSet: 4
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: Fix checkpoint-tester.py checkpoint parameter

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/9 )



Change subject: util: Fix checkpoint-tester.py checkpoint parameter
..

util: Fix checkpoint-tester.py checkpoint parameter

Previously, the inputs to `--take-checkpoints X,Y` was
`(interval, interval)` with attention to restore the N^th checkpoint
and to run the simulation for `interval` ticks.

Currently, the parameter `X` is the starting tick of the simulation,
while `Y` is the number of ticks to be simulated after tick `X`.
Therefore, `X` should be the starting tick of the N^th checkpont.

Change-Id: I1fd7c91c9454f42a4fb98aa878fb5e4ac7d238f3
Signed-off-by: Hoa Nguyen 
---
M util/checkpoint-tester.py
1 file changed, 4 insertions(+), 3 deletions(-)



diff --git a/util/checkpoint-tester.py b/util/checkpoint-tester.py
index e2051cd..7b37c0d 100755
--- a/util/checkpoint-tester.py
+++ b/util/checkpoint-tester.py
@@ -93,12 +93,12 @@

 options = args[1:]

-initial_args = ['--take-checkpoints', '%d,%d' % (interval, interval)]
+checkpoint_args = ['--take-checkpoints', '%d,%d' % (interval, interval)]

 cptdir = os.path.join(top_dir, 'm5out')

 print('===> Running initial simulation.')
-subprocess.call([m5_binary] + ['-red', cptdir] + options + initial_args)
+subprocess.call([m5_binary] + ['-red', cptdir] + options + checkpoint_args)

 dirs = os.listdir(cptdir)
 expr = re.compile('cpt\.([0-9]*)')
@@ -116,8 +116,9 @@
 # less than tha number of checkpoints.
 for i in range(1, len(cpts)):
 print('===> Running test %d of %d.' % (i, len(cpts)-1))
+checkpoint_args = ['--take-checkpoints', '%d,%d' % (cpts[i], interval)]
 mydir = os.path.join(top_dir, 'test.%d' % i)
-subprocess.call([m5_binary] + ['-red', mydir] + options + initial_args  
+
+subprocess.call([m5_binary] + ['-red', mydir] + options +  
checkpoint_args +

 ['--max-checkpoints' , '1', '--checkpoint-dir', cptdir,
  '--checkpoint-restore', str(i)])
 cpt_name = 'cpt.%d' % cpts[i]

--
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[gem5-dev] Change in gem5/gem5[develop]: util: Add missing parameter for print_insts

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/8 )



Change subject: util: Add missing parameter for print_insts
..

util: Add missing parameter for print_insts

JIRA: https://gem5.atlassian.net/browse/GEM5-949

Change-Id: I74fe7adc06124d193f17d682882766484ac18528
Signed-off-by: Hoa Nguyen 
---
M util/o3-pipeview.py
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/util/o3-pipeview.py b/util/o3-pipeview.py
index 11e86a7..630c536 100755
--- a/util/o3-pipeview.py
+++ b/util/o3-pipeview.py
@@ -129,7 +129,8 @@
 if fields[1] == 'fetch':
 if ((stop_tick > 0 and int(fields[2]) >  
stop_tick+insts['tick_drift']) or
 (stop_sn > 0 and int(fields[5]) >  
(stop_sn+insts['max_threshold']))):
-print_insts(outfile, cycle_time, width, color,  
timestamps, 0)
+print_insts(outfile, cycle_time, width, color,  
timestamps,

+store_completions, 0)
 return
 (curr_inst['pc'], curr_inst['upc']) = fields[3:5]
 curr_inst['sn'] = int(fields[5])

--
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[gem5-dev] Change in gem5/gem5[develop]: util: Make o3-pipeview Python3 compatible

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/7 )



Change subject: util: Make o3-pipeview Python3 compatible
..

util: Make o3-pipeview Python3 compatible

Change-Id: I48cb0bfb784eafe2057eb1095e6aad7abf9a1bc9
Signed-off-by: Hoa Nguyen 
---
M util/o3-pipeview.py
1 file changed, 6 insertions(+), 9 deletions(-)



diff --git a/util/o3-pipeview.py b/util/o3-pipeview.py
index 2401e8f..11e86a7 100755
--- a/util/o3-pipeview.py
+++ b/util/o3-pipeview.py
@@ -148,10 +148,6 @@
 fields = line.split(':')


-#Sorts out instructions according to sequence number
-def compare_by_sn(a, b):
-return cmp(a['sn'], b['sn'])
-
 # Puts new instruction into the print queue.
 # Sorts out and prints instructions when their number reaches threshold  
value
 def queue_inst(outfile, inst, cycle_time, width, color, timestamps,  
store_completions):

@@ -164,7 +160,8 @@
 # Sorts out and prints instructions in print queue
 def print_insts(outfile, cycle_time, width, color, timestamps,  
store_completions, lower_threshold):

 global insts
-insts['queue'].sort(compare_by_sn)
+# sort the list of insts by sequence numbers
+insts['queue'].sort(key=lambda inst: inst['sn'])
 while len(insts['queue']) > lower_threshold:
 print_item=insts['queue'].pop(0)
 # As the instructions are processed out of order the main loop  
starts

@@ -223,7 +220,7 @@
 # Print

 time_width = width * cycle_time
-base_tick = (inst['fetch'] / time_width) * time_width
+base_tick = (inst['fetch'] // time_width) * time_width

 # Find out the time of the last event - it may not
 # be 'retire' if the instruction is not comlpeted.
@@ -237,7 +234,7 @@
 if ((last_event_time - inst['fetch']) < time_width):
 num_lines = 1 # compact form
 else:
-num_lines = ((last_event_time - base_tick) / time_width) + 1
+num_lines = ((last_event_time - base_tick) // time_width) + 1

 curr_color = termcap.Normal

@@ -267,7 +264,7 @@
 if (stages[event[2]]['name'] == 'dispatch' and
 inst['dispatch'] == inst['issue']):
 continue
-outfile.write(curr_color + dot * ((event[0] / cycle_time) -  
pos))
+outfile.write(curr_color + dot * ((event[0] // cycle_time) -  
pos))

 outfile.write(stages[event[2]]['color'] +
   stages[event[2]]['shorthand'])

@@ -276,7 +273,7 @@
 else:
 curr_color = termcap.Normal

-pos = (event[0] / cycle_time) + 1
+pos = (event[0] // cycle_time) + 1
 outfile.write(curr_color + dot * (width - pos) + termcap.Normal +
   ']-(' + str(base_tick + i * time_width).rjust(15)  
+ ') ')

 if i == 0:

--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Make MemConfig.py compatible with Python3

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44047 )


Change subject: configs: Make MemConfig.py compatible with Python3
..

configs: Make MemConfig.py compatible with Python3

Change-Id: I0c180fca18a19412348cbb90837825e7b6b544c6
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44047
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/common/MemConfig.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index b38d3c9..fa1f084 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -249,7 +249,7 @@
 for i in range(len(mem_ctrls)):
 if opt_mem_type == "HMC_2500_1x32":
 # Connect the controllers to the membus
-mem_ctrls[i].port = xbar[i/4].mem_side_ports
+mem_ctrls[i].port = xbar[i//4].mem_side_ports
 # Set memory device size. There is an independent controller
 # for each vault. All vaults are same size.
 mem_ctrls[i].dram.device_size = options.hmc_dev_vault_size

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I0c180fca18a19412348cbb90837825e7b6b544c6
Gerrit-Change-Number: 44047
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Make MemConfig.py compatible with Python3

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44047 )



Change subject: configs: Make MemConfig.py compatible with Python3
..

configs: Make MemConfig.py compatible with Python3

Change-Id: I0c180fca18a19412348cbb90837825e7b6b544c6
Signed-off-by: Hoa Nguyen 
---
M configs/common/MemConfig.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index b38d3c9..fa1f084 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -249,7 +249,7 @@
 for i in range(len(mem_ctrls)):
 if opt_mem_type == "HMC_2500_1x32":
 # Connect the controllers to the membus
-mem_ctrls[i].port = xbar[i/4].mem_side_ports
+mem_ctrls[i].port = xbar[i//4].mem_side_ports
 # Set memory device size. There is an independent controller
 # for each vault. All vaults are same size.
 mem_ctrls[i].dram.device_size = options.hmc_dev_vault_size

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0c180fca18a19412348cbb90837825e7b6b544c6
Gerrit-Change-Number: 44047
Gerrit-PatchSet: 1
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[gem5-dev] Change in gem5/gem5[develop]: scons: Fix gem5 failed to build with scons 4.0.1 and 4.1.0

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41601 )



Change subject: scons: Fix gem5 failed to build with scons 4.0.1 and 4.1.0
..

scons: Fix gem5 failed to build with scons 4.0.1 and 4.1.0

SCons failed to find m5 module while loading m5.util.terminal
from site_scons/gem5_scons/util.py.

This results in the current version of gem5 stable failed to
build with scons 4.0.1 and 4.1.0.

The nature of the bug and the explaination for the fix can be
found here,
https://gem5-review.googlesource.com/c/public/gem5/+/38616

Jira: https://gem5.atlassian.net/browse/GEM5-916

Change-Id: I3817f39ebc3021fb6fc89bcd09a96999f8ca2841
Signed-off-by: Hoa Nguyen 
---
M SConstruct
M site_scons/site_tools/default.py
2 files changed, 1 insertion(+), 7 deletions(-)



diff --git a/SConstruct b/SConstruct
index 0d8159b..bb038b8 100755
--- a/SConstruct
+++ b/SConstruct
@@ -139,7 +139,7 @@
 #
 

-main = Environment()
+main = Environment(tools=['default', 'git'])

 from gem5_scons.util import get_termcap
 termcap = get_termcap()
diff --git a/site_scons/site_tools/default.py  
b/site_scons/site_tools/default.py

index 1965a20..88a6932 100644
--- a/site_scons/site_tools/default.py
+++ b/site_scons/site_tools/default.py
@@ -78,15 +78,9 @@
 # as well
 env.AppendENVPath('PYTHONPATH', extra_python_paths)

-gem5_tool_list = [
-'git',
-]
-
 def generate(env):
 common_config(env)
 SCons.Tool.default.generate(env)
-for tool in gem5_tool_list:
-SCons.Tool.Tool(tool)(env)

 def exists(env):
 return 1

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I3817f39ebc3021fb6fc89bcd09a96999f8ca2841
Gerrit-Change-Number: 41601
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[stable]: scons: Fix gem5 v20.1.0.3 failed to build with scons 4.1.0

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41594 )



Change subject: scons: Fix gem5 v20.1.0.3 failed to build with scons 4.1.0
..

scons: Fix gem5 v20.1.0.3 failed to build with scons 4.1.0

SCons failed to find m5 module while loading m5.util.terminal
from site_scons/gem5_scons/util.py.

Change-Id: I3817f39ebc3021fb6fc89bcd09a96999f8ca2841
Signed-off-by: Hoa Nguyen 
---
M SConstruct
M site_scons/site_tools/default.py
2 files changed, 1 insertion(+), 7 deletions(-)



diff --git a/SConstruct b/SConstruct
index 0d8159b..bb038b8 100755
--- a/SConstruct
+++ b/SConstruct
@@ -139,7 +139,7 @@
 #
 

-main = Environment()
+main = Environment(tools=['default', 'git'])

 from gem5_scons.util import get_termcap
 termcap = get_termcap()
diff --git a/site_scons/site_tools/default.py  
b/site_scons/site_tools/default.py

index 1965a20..88a6932 100644
--- a/site_scons/site_tools/default.py
+++ b/site_scons/site_tools/default.py
@@ -78,15 +78,9 @@
 # as well
 env.AppendENVPath('PYTHONPATH', extra_python_paths)

-gem5_tool_list = [
-'git',
-]
-
 def generate(env):
 common_config(env)
 SCons.Tool.default.generate(env)
-for tool in gem5_tool_list:
-SCons.Tool.Tool(tool)(env)

 def exists(env):
 return 1

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41594
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Gerrit-Project: public/gem5
Gerrit-Branch: stable
Gerrit-Change-Id: I3817f39ebc3021fb6fc89bcd09a96999f8ca2841
Gerrit-Change-Number: 41594
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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