Re: [PULL v5 06/11] hw/xen/xen-hvm-common: skip ioreq creation on ioreq registration failure
On Fri, 16 Jun 2023 at 00:53, Stefano Stabellini wrote: > > From: Stefano Stabellini > > On ARM it is possible to have a functioning xenpv machine with only the > PV backends and no IOREQ server. If the IOREQ server creation fails continue > to the PV backends initialization. > > Also, moved the IOREQ registration and mapping subroutine to new function > xen_do_ioreq_register(). Hi. This refactoring has prompted Coverity to notice that we're passing around a large structure by value here: MemoryListener is 192 bytes in size, and we pass it by value into xen_register_ioreq() and now through into xen_do_ioreq_register(). Does this really need to be pass by value? Could we pass a pointer instead? (CID 1513106, 1513107). I suspect also that the argument should be a const pointer, and the callsites should mark the structs they're passing as const. > -void xen_register_ioreq(XenIOState *state, unsigned int max_cpus, > -MemoryListener xen_memory_listener) > +static void xen_do_ioreq_register(XenIOState *state, > + unsigned int max_cpus, > + MemoryListener > xen_memory_listener) thanks -- PMM
Re: [PATCH v3 25/34] target/arm/tcg: Extract PAuth definitions to 'helper-pauth.h.inc'
On 6/19/23 17:55, Philippe Mathieu-Daudé wrote: helper.h is used by all units, but not all require the crypto definitions. Move them to a new header, which we only include where necessary, removing the need for "exec/helper-proto.h". Signed-off-by: Philippe Mathieu-Daudé --- target/arm/tcg/helper-a64.h.inc | 12 target/arm/tcg/helper-pauth.h.inc | 19 +++ target/arm/tcg/pauth_helper.c | 4 +++- target/arm/tcg/translate-a64.c| 6 ++ 4 files changed, 28 insertions(+), 13 deletions(-) create mode 100644 target/arm/tcg/helper-pauth.h.inc Reviewed-by: Richard Henderson r~
Re: [PATCH v3 24/34] target/arm/tcg: Reduce 'helper-sme.h.inc' inclusion
On 6/19/23 17:55, Philippe Mathieu-Daudé wrote: Instead of including helper-sme.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.h| 1 - target/arm/tcg/sme_helper.c| 5 - target/arm/tcg/translate-a64.c | 4 target/arm/tcg/translate-sme.c | 6 ++ 4 files changed, 14 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v3 23/34] target/arm/tcg: Reduce 'helper-mve.h.inc' inclusion
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote: Instead of including helper-mve.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.h| 2 -- target/arm/tcg/mve_helper.c| 5 - target/arm/tcg/translate-mve.c | 6 ++ target/arm/tcg/translate.c | 4 4 files changed, 14 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v3 22/34] target/arm/tcg: Reduce 'helper-crypto.h.inc' inclusion
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote: +++ b/target/arm/tcg/crypto_helper.c @@ -12,12 +12,17 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "crypto/aes.h" #include "crypto/sm4.h" #include "vec_internal.h" +#define HELPER_H "tcg/helper-crypto.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + foo_helper.c does not require helper-gen.h.inc. Usually we put helper-info.c.inc into one of the translate*.c files; probably translate-neon.c in this case. r~
Re: [PATCH v3 21/34] target/arm/tcg: Extract crypto definitions to 'helper-crypto.h.inc'
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote: helper.h is used by all units, but not all require the crypto definitions. Move them to a new header; the next commit will remove it from the common helper.h. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.h| 37 ++ target/arm/tcg/helper-crypto.h.inc | 42 ++ 2 files changed, 44 insertions(+), 35 deletions(-) create mode 100644 target/arm/tcg/helper-crypto.h.inc Reviewed-by: Richard Henderson r~
[PATCH v3 0/4] hw/smbios: Cleanup topology related variables
From: Zhao Liu
Hi all,
This is my v3 patch series based on 48ab886d3da4f ("Merge tag 'pull-
target-arm-20230619' of https://git.linaro.org/people/pmaydell/qemu-arm
into staging").
Compared with v2 [1], v3 introduces 2 helpers to wrap the calculation of
threads/cores per socket so that smbios can use these 2 helpers directly
to avoid calculation error caused by missing topology changes.
Also due to the introduction of these two helpers, I involve more people
for review of this v3.
Introduction
This patchset is split from my previous hybrid topology RFC [2].
There are three places for topology-related cleanup:
1. Fix the calculation of the number of sockets.
Due to the misuse of the smp.cpus variable and the change in the
meaning of smp.cores, the calculation of socket number in smbios is
incorrect. This can be fixed by using smp.sockets directly.
2. Fix core count in type4.
The meaning of smp.cores changed so that the calculation of cores
per socket became wrong.
v3 introduces the helper "machine_topo_get_cores_per_socket()" to
wrap the calculation of cores per socket. This can help other modules
avoid calculation error caused by missing topology changes.
3. Fix thread count in type4.
I also found that the definition of thread count in type4 doesn't
match the spec (smbios 3.0.0) and cleaned it up as well.
Similar to core count, v3 uses a new helper to fix this.
[1]: https://lists.gnu.org/archive/html/qemu-devel/2023-06/msg00072.html
[2]: https://mail.gnu.org/archive/html/qemu-devel/2023-02/msg03205.html
Regards,
Zhao
---
Zhao Liu (4):
machine: Add helpers to get cores/threads per socket
hw/smbios: Fix smbios_smp_sockets caculation
hw/smbios: Fix thread count in type4
hw/smbios: Fix core count in type4
hw/smbios/smbios.c | 16 ++--
include/hw/boards.h | 12
2 files changed, 22 insertions(+), 6 deletions(-)
--
2.34.1
[PATCH v3 2/4] hw/smbios: Fix smbios_smp_sockets caculation
From: Zhao Liu
smp.sockets is the number of sockets which is configured by "-smp" (
otherwise, the default is 1). Trying to recalculate it here with another
rules leads to errors, such as:
1. 003f230e37d7 ("machine: Tweak the order of topology members in struct
CpuTopology") changes the meaning of smp.cores but doesn't fix
original smp.cores uses.
With the introduction of cluster, now smp.cores means the number of
cores in one cluster. So smp.cores * smp.threads just means the
threads in a cluster not in a socket.
2. On the other hand, we shouldn't use smp.cpus here because it
indicates the initial number of online CPUs at the boot time, and is
not mathematically related to smp.sockets.
So stop reinventing the another wheel and use the topo values that
has been calculated.
Fixes: 003f230e37d7 ("machine: Tweak the order of topology members in struct
CpuTopology")
Signed-off-by: Zhao Liu
---
v3:
* Reorganized changlog. (Igor)
v2:
* None.
---
hw/smbios/smbios.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
index d2007e70fb05..d67415d44dd8 100644
--- a/hw/smbios/smbios.c
+++ b/hw/smbios/smbios.c
@@ -1088,8 +1088,7 @@ void smbios_get_tables(MachineState *ms,
smbios_build_type_2_table();
smbios_build_type_3_table();
-smbios_smp_sockets = DIV_ROUND_UP(ms->smp.cpus,
- ms->smp.cores * ms->smp.threads);
+smbios_smp_sockets = ms->smp.sockets;
assert(smbios_smp_sockets >= 1);
for (i = 0; i < smbios_smp_sockets; i++) {
--
2.34.1
[PATCH v3 4/4] hw/smbios: Fix core count in type4
From: Zhao Liu
>From SMBIOS 3.0 specification, core count field means:
Core Count is the number of cores detected by the BIOS for this
processor socket. [1]
Before 003f230e37d7 ("machine: Tweak the order of topology members in
struct CpuTopology"), MachineState.smp.cores means "the number of cores
in one package", and it's correct to use smp.cores for core count.
But 003f230e37d7 changes the smp.cores' meaning to "the number of cores
in one die" and doesn't change the original smp.cores' use in smbios as
well, which makes core count in type4 go wrong.
Fix this issue with the correct "cores per socket" caculation.
[1] SMBIOS 3.0.0, section 7.5.6, Processor Information - Core Count
Fixes: 003f230e37d7 ("machine: Tweak the order of topology members in struct
CpuTopology")
Signed-off-by: Zhao Liu
---
v3:
* Use the wrapped helper to get cores per socket.
v2:
* Calculate cores_per_socket in a different way from
threads_per_socket.
* Add the sanity check to ensure consistency of results between these 2
ways. This can help not miss any future change of cpu topology.
---
hw/smbios/smbios.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
index 3aae9328c014..10cd22f610ef 100644
--- a/hw/smbios/smbios.c
+++ b/hw/smbios/smbios.c
@@ -714,6 +714,7 @@ static void smbios_build_type_4_table(MachineState *ms,
unsigned instance)
char sock_str[128];
size_t tbl_len = SMBIOS_TYPE_4_LEN_V28;
unsigned threads_per_socket;
+unsigned cores_per_socket;
if (smbios_ep_type == SMBIOS_ENTRY_POINT_TYPE_64) {
tbl_len = SMBIOS_TYPE_4_LEN_V30;
@@ -749,8 +750,9 @@ static void smbios_build_type_4_table(MachineState *ms,
unsigned instance)
SMBIOS_TABLE_SET_STR(4, part_number_str, type4.part);
threads_per_socket = machine_topo_get_threads_per_socket(ms);
+cores_per_socket = machine_topo_get_cores_per_socket(ms);
-t->core_count = (ms->smp.cores > 255) ? 0xFF : ms->smp.cores;
+t->core_count = (cores_per_socket > 255) ? 0xFF : cores_per_socket;
t->core_enabled = t->core_count;
t->thread_count = (threads_per_socket > 255) ? 0xFF : threads_per_socket;
@@ -759,7 +761,7 @@ static void smbios_build_type_4_table(MachineState *ms,
unsigned instance)
t->processor_family2 = cpu_to_le16(0x01); /* Other */
if (tbl_len == SMBIOS_TYPE_4_LEN_V30) {
-t->core_count2 = t->core_enabled2 = cpu_to_le16(ms->smp.cores);
+t->core_count2 = t->core_enabled2 = cpu_to_le16(cores_per_socket);
t->thread_count2 = cpu_to_le16(threads_per_socket);
}
--
2.34.1
[PATCH v3 1/4] machine: Add helpers to get cores/threads per socket
From: Zhao Liu
The number of cores/threads per socket are needed for smbios, and are
also useful for other modules.
Provide the helpers to wrap the calculation of cores/threads per socket
so that we can avoid calculation errors caused by other modules miss
topology changes.
Suggested-by: Igor Mammedov
Signed-off-by: Zhao Liu
---
v3:
* The new patch to wrap the calculation of cores/threads per socket.
---
include/hw/boards.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index a385010909d5..40ee22fd93e3 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -384,6 +384,18 @@ struct MachineState {
} \
type_init(machine_initfn##_register_types)
+static inline
+unsigned int machine_topo_get_cores_per_socket(const MachineState *ms)
+{
+return ms->smp.cores * ms->smp.clusters * ms->smp.dies;
+}
+
+static inline
+unsigned int machine_topo_get_threads_per_socket(const MachineState *ms)
+{
+return ms->smp.threads * machine_topo_get_cores_per_socket(ms);
+}
+
extern GlobalProperty hw_compat_8_0[];
extern const size_t hw_compat_8_0_len;
--
2.34.1
Re: [PATCH v3 20/34] target/arm/tcg: Reduce 'helper-sve.h.inc' inclusion
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote: Instead of including helper-sve.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.h| 1 - target/arm/tcg/sve_helper.c| 4 target/arm/tcg/translate-sme.c | 4 target/arm/tcg/translate-sve.c | 6 ++ target/arm/tcg/vec_helper.c| 4 5 files changed, 18 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~
[PATCH v3 3/4] hw/smbios: Fix thread count in type4
From: Zhao Liu
>From SMBIOS 3.0 specification, thread count field means:
Thread Count is the total number of threads detected by the BIOS for
this processor socket. It is a processor-wide count, not a
thread-per-core count. [1]
So here we should use threads per socket other than threads per core.
[1] SMBIOS 3.0.0, section 7.5.8, Processor Information - Thread Count
Fixes: c97294ec1b9e ("SMBIOS: Build aggregate smbios tables and entry point")
Signed-off-by: Zhao Liu
---
v3:
* Use the wrapped hepler to get threads per socket.
v2:
* Rename cpus_per_socket to threads_per_socket.
* Add the comment about smp.max_cpus. Thread count and core count will
be calculated in 2 ways and will add a sanity check to ensure we
don't miss any topology level.
---
hw/smbios/smbios.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
index d67415d44dd8..3aae9328c014 100644
--- a/hw/smbios/smbios.c
+++ b/hw/smbios/smbios.c
@@ -713,6 +713,7 @@ static void smbios_build_type_4_table(MachineState *ms,
unsigned instance)
{
char sock_str[128];
size_t tbl_len = SMBIOS_TYPE_4_LEN_V28;
+unsigned threads_per_socket;
if (smbios_ep_type == SMBIOS_ENTRY_POINT_TYPE_64) {
tbl_len = SMBIOS_TYPE_4_LEN_V30;
@@ -747,17 +748,19 @@ static void smbios_build_type_4_table(MachineState *ms,
unsigned instance)
SMBIOS_TABLE_SET_STR(4, asset_tag_number_str, type4.asset);
SMBIOS_TABLE_SET_STR(4, part_number_str, type4.part);
+threads_per_socket = machine_topo_get_threads_per_socket(ms);
+
t->core_count = (ms->smp.cores > 255) ? 0xFF : ms->smp.cores;
t->core_enabled = t->core_count;
-t->thread_count = (ms->smp.threads > 255) ? 0xFF : ms->smp.threads;
+t->thread_count = (threads_per_socket > 255) ? 0xFF : threads_per_socket;
t->processor_characteristics = cpu_to_le16(0x02); /* Unknown */
t->processor_family2 = cpu_to_le16(0x01); /* Other */
if (tbl_len == SMBIOS_TYPE_4_LEN_V30) {
t->core_count2 = t->core_enabled2 = cpu_to_le16(ms->smp.cores);
-t->thread_count2 = cpu_to_le16(ms->smp.threads);
+t->thread_count2 = cpu_to_le16(threads_per_socket);
}
SMBIOS_BUILD_TABLE_POST;
--
2.34.1
Re: [PATCH v3 18/34] target/arm/tcg: Reduce 'helper-gvec.h.inc' inclusion
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote: Instead of including helper-gvec.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.h | 1 - target/arm/tcg/translate-a64.c | 4 target/arm/tcg/translate-gvec.c | 6 ++ target/arm/tcg/translate-neon.c | 4 target/arm/tcg/translate-sve.c | 3 +++ target/arm/tcg/vec_helper.c | 4 6 files changed, 21 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 0/4] target/ppc: TCG SMT support for spapr
On 6/20/23 12:12, Nicholas Piggin wrote: On Wed Jun 7, 2023 at 12:09 AM AEST, Cédric Le Goater wrote: On 6/5/23 13:23, Nicholas Piggin wrote: Previous RFC here https://lists.gnu.org/archive/html/qemu-ppc/2023-05/msg00453.html This series drops patch 1 from the previous, which is more of a standalone bugfix. Also accounted for Cedric's comments, except a nicer way to set cpu_index vs PIR/TIR SPRs, which is not quite trivial. This limits support for SMT to POWER8 and newer. It is also incompatible with nested-HV so that is checked for too. Iterating CPUs to find siblings for now I kept because similar loops exist in a few places, and it is not conceptually difficult for SMT, just fiddly code to improve. For now it should not be much performane concern. I removed hypervisor msgsnd support from patch 3, which is not required for spapr and added significantly to the patch. For now nobody has objected to the way shared SPR access is handled (serialised with TCG atomics support) so we'll keep going with it. Cc:ing more people for possible feedback. Not much feedback so I'll plan to go with this. A more performant implementation might try to synchronize threads at the register level rather than serialize everything, but SMT shared registers are not too performance critical so this should do for now. yes. Could you please rebase this series on upstream ? It would be good to add tests for SMT. May be we could extend : tests/avocado/ppc_pseries.py with a couple of extra QEMU configs adding 'threads=' (if possible) and check : "CPU maps initialized for Y threads per core" and "smp: Brought up 1 node, X*Y CPUs" ? Thanks, C.
Re: [PATCH v3 17/34] target/arm/tcg: Extract gvec definitions to 'helper-gvec.h.inc'
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote: helper.h is used by all units, but not all require the generic vector definitions. Move them to a new header; the next commit will remove it from the common helper.h. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.h | 380 +-- target/arm/tcg/helper-gvec.h.inc | 378 ++ 2 files changed, 379 insertions(+), 379 deletions(-) create mode 100644 target/arm/tcg/helper-gvec.h.inc Reviewed-by: Richard Henderson r~
Re: [PATCH v3 16/34] target/arm/tcg: Extract generic vector helpers to translate-gvec.c
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote: Extract 1600 lines from the big enough translate.c. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/tcg/translate-gvec.c | 1644 +++ target/arm/tcg/translate.c | 1630 -- target/arm/tcg/meson.build |1 + 3 files changed, 1645 insertions(+), 1630 deletions(-) create mode 100644 target/arm/tcg/translate-gvec.c Reviewed-by: Richard Henderson r~
Re: [PATCH v3 15/34] target/arm/tcg: Export some generic vector helpers
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote: We want to extract gvec helpers to a new translate-gvec.c file. Some helpers will still be accessed out of it, from the current translate.c. Expose their prototype. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/tcg/translate.h | 5 + target/arm/tcg/translate.c | 8 2 files changed, 9 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v3 14/34] target/arm/tcg: Reduce 'helper-neon.h.inc' inclusion
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote: Instead of including helper-neon.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.h | 1 - target/arm/tcg/neon_helper.c| 5 - target/arm/tcg/translate-a64.c | 4 target/arm/tcg/translate-neon.c | 6 ++ target/arm/tcg/translate-sme.c | 4 target/arm/tcg/translate.c | 4 target/arm/tcg/vec_helper.c | 4 7 files changed, 26 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 4/5] docs/devel: split qom-api reference into new file
On 20/6/23 12:03, Richard Henderson wrote: On 6/19/23 19:14, Alex Bennée wrote: +We don't currently generate the API documentation for QDEV due to QEMU +macros confusing the kerneldoc tool. For now see the headers in +``include/hw/qdev-core.h`` + +.. + kernel-doc:: include/hw/qdev-core.h I'm confused. Isn't that exactly what you're doing here? IIUC the kernel-doc style comments from "hw/qdev-core.h" are embedded as rST doc, see: https://kernel.readthedocs.io/en/sphinx-samples/kernel-documentation.html#including-kernel-doc-comments
Re: [PATCH v3 11/34] target/arm/tcg: Reduce 'helper-vfp.h.inc' inclusion
On 6/19/23 17:42, Philippe Mathieu-Daudé wrote: Instead of including helper-vfp.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.h | 1 - target/arm/tcg/mve_helper.c | 4 target/arm/tcg/sve_helper.c | 3 +++ target/arm/tcg/translate-a64.c| 4 target/arm/tcg/translate-m-nocp.c | 5 + target/arm/tcg/translate-neon.c | 4 target/arm/tcg/translate-vfp.c| 6 ++ target/arm/tcg/vec_helper.c | 4 target/arm/vfp_helper.c | 5 - 9 files changed, 34 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v3 09/34] target/arm/tcg: Move VFP helpers from helper-a64.c to vfp_helper.c
On 6/19/23 17:42, Philippe Mathieu-Daudé wrote: Keep the VFP helpers in the same file, guarding them with #ifdef'ry. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/tcg/helper-a64.c | 87 -- target/arm/vfp_helper.c | 93 - 2 files changed, 92 insertions(+), 88 deletions(-) I'm not keen on this. First, because we have not yet disentangled vfp_helper.c from the bits required by KVM, so to move the rest into tcg/. Second because large ifdef blocks are a sign that something wants splitting anyway. Perhaps tcg/vfp_a64_helper.c? There's probably a better name we could use... r~
Re: [PATCH] x86_64/atomic128-ldst.h: fix arch include guard
On 20/6/23 10:39, Frédéric Pétrot wrote: Fix arch name in the define that prevents multiple inclusions. Signed-off-by: Frédéric Pétrot --- host/include/x86_64/host/atomic128-ldst.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 2/9] MAINTAINERS: Add reviewer for PowerPC TCG CPUs
On 20/6/23 07:59, Cédric Le Goater wrote: Nick has great knowledge of the PowerPC CPUs, software and hardware. Add him as a reviewer on CPU TCG modeling. Cc: Nicholas Piggin Signed-off-by: Cédric Le Goater --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 0/4] target/ppc: TCG SMT support for spapr
On Wed Jun 7, 2023 at 12:09 AM AEST, Cédric Le Goater wrote: > On 6/5/23 13:23, Nicholas Piggin wrote: > > Previous RFC here > > > > https://lists.gnu.org/archive/html/qemu-ppc/2023-05/msg00453.html > > > > This series drops patch 1 from the previous, which is more of > > a standalone bugfix. > > > > Also accounted for Cedric's comments, except a nicer way to > > set cpu_index vs PIR/TIR SPRs, which is not quite trivial. > > > > This limits support for SMT to POWER8 and newer. It is also > > incompatible with nested-HV so that is checked for too. > > > > Iterating CPUs to find siblings for now I kept because similar > > loops exist in a few places, and it is not conceptually > > difficult for SMT, just fiddly code to improve. For now it > > should not be much performane concern. > > > > I removed hypervisor msgsnd support from patch 3, which is not > > required for spapr and added significantly to the patch. > > > > For now nobody has objected to the way shared SPR access is > > handled (serialised with TCG atomics support) so we'll keep > > going with it. > > Cc:ing more people for possible feedback. Not much feedback so I'll plan to go with this. A more performant implementation might try to synchronize threads at the register level rather than serialize everything, but SMT shared registers are not too performance critical so this should do for now. Thanks, Nick
Re: [PATCH 5/5] docs/devel: introduce some key concepts for QOM development
On 6/19/23 19:14, Alex Bennée wrote: +As class initialisation cannot fail devices have an two additional +methods to handle the creation of dynamic devices. The ``realize`` Beginning with "as" feels like a continuation from something that has been omitted. You've skipped over describing ``init`` entirely, and then assumed it. +The reverse function is ``unrealize`` and should be were clean-up "and is where clean-up" r~
Re: [PATCH 4/5] docs/devel: split qom-api reference into new file
On 6/19/23 19:14, Alex Bennée wrote: +We don't currently generate the API documentation for QDEV due to QEMU +macros confusing the kerneldoc tool. For now see the headers in +``include/hw/qdev-core.h`` + +.. + kernel-doc:: include/hw/qdev-core.h I'm confused. Isn't that exactly what you're doing here? r~
Re: [PATCH 3/5] include/hw/qdev-core: fixup kerneldoc annotations (!COMPLETE)
On 6/19/23 19:14, Alex Bennée wrote: Fix up the kerneldoc markup and start documenting the various fields in QDEV related structures. Unfortunately this is not enough include the documentation because kerneldoc currently chokes on some of our macros such as: /** * @gpios: list of named GPIOs the device provides. */ QLIST_HEAD(, NamedGPIOList) gpios; where it demands we document QLIST_HEAD and NamedGPIOList despite them not technically being fields in the structure. Signed-off-by: Alex Bennée --- include/hw/qdev-core.h | 123 ++--- 1 file changed, 102 insertions(+), 21 deletions(-) I wonder if e.g. typedef QLIST_HEAD(, NamedGPIOList) NamedGPIOListHead; outside of struct DeviceClass would help with those. Anyway, for this patch, Reviewed-by: Richard Henderson r~
Re: [PATCH 2/5] include/migration: mark vmstate_register() as a legacy function
On 6/19/23 19:14, Alex Bennée wrote: Mention that QOM-ified devices already have support for registering the description. Signed-off-by: Alex Bennée --- include/migration/vmstate.h | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 1/5] docs/devel: add some front matter to the devel index
On 6/19/23 19:14, Alex Bennée wrote: +QEMU is a large and mature project with a number of complex subsystems +that can be overwhelming to understand. The development documentation +is not comprehensive but hopefully presents enough of a starting point +to get you started. If there are areas that are unclear please reach "start" used twice -- "presents enough to get you started"? Otherwise, Reviewed-by: Richard Henderson r~
Re: [PULL 00/16] tcg patch queue
On 6/20/23 10:25, Richard Henderson wrote: The following changes since commit 48ab886d3da4f3ab94f79f6c0f8b4535b446bbfd: Merge tag 'pull-target-arm-20230619' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-06-19 16:32:25 +0200) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230620 for you to fetch changes up to d7ee93e24359703debf4137f4cc632563aa4e8d1: cputlb: Restrict SavedIOTLB to system emulation (2023-06-20 10:02:14 +0200) tcg: Define _CALL_AIX for clang on ppc64 accel/tcg: Build fix for macos catalina accel/tcg: Handle MO_ATOM_WITHIN16 in do_st16_leN accel/tcg: Restrict SavedIOTLB to system emulation accel/tcg: Use generic 'helper-proto-common.h' header plugins: Remove unused 'exec/helper-proto.h' header *: Check for CONFIG_USER_ONLY instead of CONFIG_SOFTMMU Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate. r~
[PATCH v1 18/46] target/loongarch: Implement xvsat
This patch includes:
- XVSAT.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 ++
target/loongarch/helper.h| 9 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 86
target/loongarch/insns.decode| 13 +++
target/loongarch/lasx_helper.c | 37 +
5 files changed, 154 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 83efde440f..18fa454be8 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1978,6 +1978,15 @@ INSN_LASX(xvmod_hu, xxx)
INSN_LASX(xvmod_wu, xxx)
INSN_LASX(xvmod_du, xxx)
+INSN_LASX(xvsat_b, xx_i)
+INSN_LASX(xvsat_h, xx_i)
+INSN_LASX(xvsat_w, xx_i)
+INSN_LASX(xvsat_d, xx_i)
+INSN_LASX(xvsat_bu, xx_i)
+INSN_LASX(xvsat_hu, xx_i)
+INSN_LASX(xvsat_wu, xx_i)
+INSN_LASX(xvsat_du, xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 95c7ecba3b..741872a24d 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -886,3 +886,12 @@ DEF_HELPER_4(xvmod_bu, void, env, i32, i32, i32)
DEF_HELPER_4(xvmod_hu, void, env, i32, i32, i32)
DEF_HELPER_4(xvmod_wu, void, env, i32, i32, i32)
DEF_HELPER_4(xvmod_du, void, env, i32, i32, i32)
+
+DEF_HELPER_FLAGS_4(xvsat_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvsat_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvsat_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvsat_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvsat_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvsat_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvsat_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvsat_du, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 930872c939..350d575a6a 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -1747,6 +1747,92 @@ TRANS(xvmod_hu, gen_xxx, gen_helper_xvmod_hu)
TRANS(xvmod_wu, gen_xxx, gen_helper_xvmod_wu)
TRANS(xvmod_du, gen_xxx, gen_helper_xvmod_du)
+static void do_xvsat_s(unsigned vece, uint32_t xd_ofs, uint32_t xj_ofs,
+ int64_t imm, uint32_t oprsz, uint32_t maxsz)
+{
+static const TCGOpcode vecop_list[] = {
+INDEX_op_smax_vec, INDEX_op_smin_vec, 0
+};
+static const GVecGen2s op[4] = {
+{
+.fniv = gen_vsat_s,
+.fno = gen_helper_xvsat_b,
+.opt_opc = vecop_list,
+.vece = MO_8
+},
+{
+.fniv = gen_vsat_s,
+.fno = gen_helper_xvsat_h,
+.opt_opc = vecop_list,
+.vece = MO_16
+},
+{
+.fniv = gen_vsat_s,
+.fno = gen_helper_xvsat_w,
+.opt_opc = vecop_list,
+.vece = MO_32
+},
+{
+.fniv = gen_vsat_s,
+.fno = gen_helper_xvsat_d,
+.opt_opc = vecop_list,
+.vece = MO_64
+},
+};
+
+tcg_gen_gvec_2s(xd_ofs, xj_ofs, oprsz, maxsz,
+tcg_constant_i64((1ll << imm) - 1), &op[vece]);
+}
+
+TRANS(xvsat_b, gvec_xx_i, MO_8, do_xvsat_s)
+TRANS(xvsat_h, gvec_xx_i, MO_16, do_xvsat_s)
+TRANS(xvsat_w, gvec_xx_i, MO_32, do_xvsat_s)
+TRANS(xvsat_d, gvec_xx_i, MO_64, do_xvsat_s)
+
+static void do_xvsat_u(unsigned vece, uint32_t xd_ofs, uint32_t xj_ofs,
+ int64_t imm, uint32_t oprsz, uint32_t maxsz)
+{
+uint64_t max;
+static const TCGOpcode vecop_list[] = {
+INDEX_op_umin_vec, 0
+};
+static const GVecGen2s op[4] = {
+{
+.fniv = gen_vsat_u,
+.fno = gen_helper_xvsat_bu,
+.opt_opc = vecop_list,
+.vece = MO_8
+},
+{
+.fniv = gen_vsat_u,
+.fno = gen_helper_xvsat_hu,
+.opt_opc = vecop_list,
+.vece = MO_16
+},
+{
+.fniv = gen_vsat_u,
+.fno = gen_helper_xvsat_wu,
+.opt_opc = vecop_list,
+.vece = MO_32
+},
+{
+.fniv = gen_vsat_u,
+.fno = gen_helper_xvsat_du,
+.opt_opc = vecop_list,
+.vece = MO_64
+},
+};
+
+max = (imm == 0x3f) ? UINT64_MAX : (1ull << (imm + 1)) - 1;
+tcg_gen_gvec_2s(xd_ofs, xj_ofs, oprsz, maxsz,
+tcg_constant_i64(max), &op[vece]);
+}
+
+TRANS(xvsat_bu, gvec_xx_i, MO_8, do_xvsat_u)
+TRANS(xvsat_hu, gvec_xx_i, MO_16, do_xvsat_u)
+TRANS(xvsat_wu, gvec_xx_i, MO_32, do_xvsat_u)
+TRANS(xvsat_du, gvec_xx_i, MO_6
[PATCH v1 44/46] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i xvextrins
This patch includes:
- XVSHUF.{B/H/W/D};
- XVPERM.W;
- XVSHUF4i.{B/H/W/D};
- XVPERMI.{W/D/Q};
- XVEXTRINS.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 21 +++
target/loongarch/helper.h| 21 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 21 +++
target/loongarch/insns.decode| 21 +++
target/loongarch/lasx_helper.c | 168 +++
target/loongarch/lsx_helper.c| 3 +-
target/loongarch/vec.h | 2 +
7 files changed, 255 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 4b815c86b8..9af1c95641 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2574,3 +2574,24 @@ INSN_LASX(xvilvh_b, xxx)
INSN_LASX(xvilvh_h, xxx)
INSN_LASX(xvilvh_w, xxx)
INSN_LASX(xvilvh_d, xxx)
+
+INSN_LASX(xvshuf_b, )
+INSN_LASX(xvshuf_h, xxx)
+INSN_LASX(xvshuf_w, xxx)
+INSN_LASX(xvshuf_d, xxx)
+
+INSN_LASX(xvperm_w, xxx)
+
+INSN_LASX(xvshuf4i_b,xx_i)
+INSN_LASX(xvshuf4i_h,xx_i)
+INSN_LASX(xvshuf4i_w,xx_i)
+INSN_LASX(xvshuf4i_d,xx_i)
+
+INSN_LASX(xvpermi_w, xx_i)
+INSN_LASX(xvpermi_d, xx_i)
+INSN_LASX(xvpermi_q, xx_i)
+
+INSN_LASX(xvextrins_d, xx_i)
+INSN_LASX(xvextrins_w, xx_i)
+INSN_LASX(xvextrins_h, xx_i)
+INSN_LASX(xvextrins_b, xx_i)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index dc5ab59f8e..1058a7de75 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1264,3 +1264,24 @@ DEF_HELPER_4(xvilvh_b, void, env, i32, i32, i32)
DEF_HELPER_4(xvilvh_h, void, env, i32, i32, i32)
DEF_HELPER_4(xvilvh_w, void, env, i32, i32, i32)
DEF_HELPER_4(xvilvh_d, void, env, i32, i32, i32)
+
+DEF_HELPER_5(xvshuf_b, void, env, i32, i32, i32, i32)
+DEF_HELPER_4(xvshuf_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvshuf_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvshuf_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvperm_w, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvshuf4i_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvshuf4i_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvshuf4i_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvshuf4i_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvpermi_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpermi_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpermi_q, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvextrins_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvextrins_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvextrins_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvextrins_b, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 75ac0ae1f1..1344f75113 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -3083,3 +3083,24 @@ TRANS(xvilvh_b, gen_xxx, gen_helper_xvilvh_b)
TRANS(xvilvh_h, gen_xxx, gen_helper_xvilvh_h)
TRANS(xvilvh_w, gen_xxx, gen_helper_xvilvh_w)
TRANS(xvilvh_d, gen_xxx, gen_helper_xvilvh_d)
+
+TRANS(xvshuf_b, gen_, gen_helper_xvshuf_b)
+TRANS(xvshuf_h, gen_xxx, gen_helper_xvshuf_h)
+TRANS(xvshuf_w, gen_xxx, gen_helper_xvshuf_w)
+TRANS(xvshuf_d, gen_xxx, gen_helper_xvshuf_d)
+
+TRANS(xvperm_w, gen_xxx, gen_helper_xvperm_w)
+
+TRANS(xvshuf4i_b, gen_xx_i, gen_helper_xvshuf4i_b)
+TRANS(xvshuf4i_h, gen_xx_i, gen_helper_xvshuf4i_h)
+TRANS(xvshuf4i_w, gen_xx_i, gen_helper_xvshuf4i_w)
+TRANS(xvshuf4i_d, gen_xx_i, gen_helper_xvshuf4i_d)
+
+TRANS(xvpermi_w, gen_xx_i, gen_helper_xvpermi_w)
+TRANS(xvpermi_d, gen_xx_i, gen_helper_xvpermi_d)
+TRANS(xvpermi_q, gen_xx_i, gen_helper_xvpermi_q)
+
+TRANS(xvextrins_b, gen_xx_i, gen_helper_xvextrins_b)
+TRANS(xvextrins_h, gen_xx_i, gen_helper_xvextrins_h)
+TRANS(xvextrins_w, gen_xx_i, gen_helper_xvextrins_w)
+TRANS(xvextrins_d, gen_xx_i, gen_helper_xvextrins_d)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 5c3a18fbe2..9c6a6037e9 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -2078,3 +2078,24 @@ xvilvh_b 0111 01010001 11000 . . .
@xxx
xvilvh_h 0111 01010001 11001 . . .@xxx
xvilvh_w 0111 01010001 11010 . . .@xxx
xvilvh_d 0111 01010001 11011 . . .@xxx
+
+xvshuf_b 11010110 . . . .@
+xvshuf_h 0111 01010111 10101 . . .@xxx
+xvshuf_w 0111 01010111 10110 . . .@xxx
+xvshuf_d 0111 01010111 10111 . . .@xxx
+
+xvperm_w 0111 01010111 11010 . . .@xxx
+
+xvshuf4i_b 0111 0001 00 . .@xx_ui8
+xvshuf4i_h 0111 0001 01 . .@xx_ui8
+xvshuf4i_w 0111 0001 10 . .@xx_
[PATCH v1 33/46] target/loongarch: Implement xvpcnt
This patch includes:
- VPCNT.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 +
target/loongarch/helper.h| 5 +
target/loongarch/insn_trans/trans_lasx.c.inc | 5 +
target/loongarch/insns.decode| 5 +
target/loongarch/lasx_helper.c | 17 +
5 files changed, 37 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 99636ca56c..b7a322651f 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2204,6 +2204,11 @@ INSN_LASX(xvclz_h, xx)
INSN_LASX(xvclz_w, xx)
INSN_LASX(xvclz_d, xx)
+INSN_LASX(xvpcnt_b, xx)
+INSN_LASX(xvpcnt_h, xx)
+INSN_LASX(xvpcnt_w, xx)
+INSN_LASX(xvpcnt_d, xx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 950a73ec6f..a434443819 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1059,3 +1059,8 @@ DEF_HELPER_3(xvclz_b, void, env, i32, i32)
DEF_HELPER_3(xvclz_h, void, env, i32, i32)
DEF_HELPER_3(xvclz_w, void, env, i32, i32)
DEF_HELPER_3(xvclz_d, void, env, i32, i32)
+
+DEF_HELPER_3(xvpcnt_b, void, env, i32, i32)
+DEF_HELPER_3(xvpcnt_h, void, env, i32, i32)
+DEF_HELPER_3(xvpcnt_w, void, env, i32, i32)
+DEF_HELPER_3(xvpcnt_d, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index fa7dafa7f9..616d296432 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2153,6 +2153,11 @@ TRANS(xvclz_h, gen_xx, gen_helper_xvclz_h)
TRANS(xvclz_w, gen_xx, gen_helper_xvclz_w)
TRANS(xvclz_d, gen_xx, gen_helper_xvclz_d)
+TRANS(xvpcnt_b, gen_xx, gen_helper_xvpcnt_b)
+TRANS(xvpcnt_h, gen_xx, gen_helper_xvpcnt_h)
+TRANS(xvpcnt_w, gen_xx, gen_helper_xvpcnt_w)
+TRANS(xvpcnt_d, gen_xx, gen_helper_xvpcnt_d)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 91de5a3815..7d49ddb0ea 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1802,6 +1802,11 @@ xvclz_h 0111 01101001 11000 00101 . .
@xx
xvclz_w 0111 01101001 11000 00110 . .@xx
xvclz_d 0111 01101001 11000 00111 . .@xx
+xvpcnt_b 0111 01101001 11000 01000 . .@xx
+xvpcnt_h 0111 01101001 11000 01001 . .@xx
+xvpcnt_w 0111 01101001 11000 01010 . .@xx
+xvpcnt_d 0111 01101001 11000 01011 . .@xx
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010 . .@xr
diff --git a/target/loongarch/lasx_helper.c b/target/loongarch/lasx_helper.c
index 122c460fb5..f04817984b 100644
--- a/target/loongarch/lasx_helper.c
+++ b/target/loongarch/lasx_helper.c
@@ -2102,3 +2102,20 @@ XDO_2OP(xvclz_b, 8, UXB, DO_CLZ_B)
XDO_2OP(xvclz_h, 16, UXH, DO_CLZ_H)
XDO_2OP(xvclz_w, 32, UXW, DO_CLZ_W)
XDO_2OP(xvclz_d, 64, UXD, DO_CLZ_D)
+
+#define XVPCNT(NAME, BIT, E, FN)\
+void HELPER(NAME)(CPULoongArchState *env, uint32_t xd, uint32_t xj) \
+{ \
+int i; \
+XReg *Xd = &(env->fpr[xd].xreg);\
+XReg *Xj = &(env->fpr[xj].xreg);\
+\
+for (i = 0; i < LASX_LEN / BIT; i++) { \
+Xd->E(i) = FN(Xj->E(i));\
+} \
+}
+
+XVPCNT(xvpcnt_b, 8, UXB, ctpop8)
+XVPCNT(xvpcnt_h, 16, UXH, ctpop16)
+XVPCNT(xvpcnt_w, 32, UXW, ctpop32)
+XVPCNT(xvpcnt_d, 64, UXD, ctpop64)
--
2.39.1
[PATCH v1 15/46] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}
This patch includes:
- XVMUL.{B/H/W/D};
- XVMUH.{B/H/W/D}[U];
- XVMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 38 +++
target/loongarch/helper.h| 30 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 311 +++
target/loongarch/insns.decode| 38 +++
target/loongarch/lasx_helper.c | 74 +
target/loongarch/lsx_helper.c| 2 -
target/loongarch/vec.h | 2 +
7 files changed, 493 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index ff22fcb90e..e7c46bc3a2 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1889,6 +1889,44 @@ INSN_LASX(xvmini_hu, xx_i)
INSN_LASX(xvmini_wu, xx_i)
INSN_LASX(xvmini_du, xx_i)
+INSN_LASX(xvmul_b, xxx)
+INSN_LASX(xvmul_h, xxx)
+INSN_LASX(xvmul_w, xxx)
+INSN_LASX(xvmul_d, xxx)
+INSN_LASX(xvmuh_b, xxx)
+INSN_LASX(xvmuh_h, xxx)
+INSN_LASX(xvmuh_w, xxx)
+INSN_LASX(xvmuh_d, xxx)
+INSN_LASX(xvmuh_bu, xxx)
+INSN_LASX(xvmuh_hu, xxx)
+INSN_LASX(xvmuh_wu, xxx)
+INSN_LASX(xvmuh_du, xxx)
+
+INSN_LASX(xvmulwev_h_b, xxx)
+INSN_LASX(xvmulwev_w_h, xxx)
+INSN_LASX(xvmulwev_d_w, xxx)
+INSN_LASX(xvmulwev_q_d, xxx)
+INSN_LASX(xvmulwod_h_b, xxx)
+INSN_LASX(xvmulwod_w_h, xxx)
+INSN_LASX(xvmulwod_d_w, xxx)
+INSN_LASX(xvmulwod_q_d, xxx)
+INSN_LASX(xvmulwev_h_bu, xxx)
+INSN_LASX(xvmulwev_w_hu, xxx)
+INSN_LASX(xvmulwev_d_wu, xxx)
+INSN_LASX(xvmulwev_q_du, xxx)
+INSN_LASX(xvmulwod_h_bu, xxx)
+INSN_LASX(xvmulwod_w_hu, xxx)
+INSN_LASX(xvmulwod_d_wu, xxx)
+INSN_LASX(xvmulwod_q_du, xxx)
+INSN_LASX(xvmulwev_h_bu_b, xxx)
+INSN_LASX(xvmulwev_w_hu_h, xxx)
+INSN_LASX(xvmulwev_d_wu_w, xxx)
+INSN_LASX(xvmulwev_q_du_d, xxx)
+INSN_LASX(xvmulwod_h_bu_b, xxx)
+INSN_LASX(xvmulwod_w_hu_h, xxx)
+INSN_LASX(xvmulwod_d_wu_w, xxx)
+INSN_LASX(xvmulwod_q_du_d, xxx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index d5ebc0b963..88ae707027 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -809,3 +809,33 @@ DEF_HELPER_FLAGS_4(xvmaxi_bu, TCG_CALL_NO_RWG, void, ptr,
ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvmaxi_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvmaxi_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvmaxi_du, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
+DEF_HELPER_FLAGS_4(xvmuh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmuh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmuh_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmuh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmuh_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmuh_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmuh_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmuh_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvmulwev_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwev_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwev_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwod_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwod_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwod_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvmulwev_h_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwev_w_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwev_d_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwod_h_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwod_w_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwod_d_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvmulwev_h_bu_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwev_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwev_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwod_h_bu_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwod_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmulwod_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index cdf3dcc161..d57d867f17 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_
[PATCH v1 45/46] target/loongarch: Implement xvld xvst
This patch includes:
- XVLD[X], XVST[X];
- XVLDREPL.{B/H/W/D};
- XVSTELM.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 24 +
target/loongarch/helper.h| 3 +
target/loongarch/insn_trans/trans_lasx.c.inc | 97
target/loongarch/insns.decode| 25 +
target/loongarch/lasx_helper.c | 59
5 files changed, 208 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 9af1c95641..4403669047 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1753,6 +1753,16 @@ static void output_xxr(DisasContext *ctx, arg_xxr *a,
const char *mnemonic)
output(ctx, mnemonic, "x%d, x%d, r%d", a->xd, a->xj, a->rk);
}
+static void output_xrr(DisasContext *ctx, arg_xrr *a, const char *mnemonic)
+{
+output(ctx, mnemonic, "x%d, r%d, r%d", a->xd, a->rj, a->rk);
+}
+
+static void output_xr_ii(DisasContext *ctx, arg_xr_ii *a, const char *mnemonic)
+{
+output(ctx, mnemonic, "x%d, r%d, 0x%x, 0x%x", a->xd, a->rj, a->imm,
a->imm2);
+}
+
INSN_LASX(xvadd_b, xxx)
INSN_LASX(xvadd_h, xxx)
INSN_LASX(xvadd_w, xxx)
@@ -2595,3 +2605,17 @@ INSN_LASX(xvextrins_d, xx_i)
INSN_LASX(xvextrins_w, xx_i)
INSN_LASX(xvextrins_h, xx_i)
INSN_LASX(xvextrins_b, xx_i)
+
+INSN_LASX(xvld, xr_i)
+INSN_LASX(xvst, xr_i)
+INSN_LASX(xvldx, xrr)
+INSN_LASX(xvstx, xrr)
+
+INSN_LASX(xvldrepl_d,xr_i)
+INSN_LASX(xvldrepl_w,xr_i)
+INSN_LASX(xvldrepl_h,xr_i)
+INSN_LASX(xvldrepl_b,xr_i)
+INSN_LASX(xvstelm_d, xr_ii)
+INSN_LASX(xvstelm_w, xr_ii)
+INSN_LASX(xvstelm_h, xr_ii)
+INSN_LASX(xvstelm_b, xr_ii)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 1058a7de75..adeb181407 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1285,3 +1285,6 @@ DEF_HELPER_4(xvextrins_d, void, env, i32, i32, i32)
DEF_HELPER_4(xvextrins_w, void, env, i32, i32, i32)
DEF_HELPER_4(xvextrins_h, void, env, i32, i32, i32)
DEF_HELPER_4(xvextrins_b, void, env, i32, i32, i32)
+
+DEF_HELPER_3(xvld_b, void, env, i32, tl)
+DEF_HELPER_3(xvst_b, void, env, i32, tl)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 1344f75113..761f227c76 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -3104,3 +3104,100 @@ TRANS(xvextrins_b, gen_xx_i, gen_helper_xvextrins_b)
TRANS(xvextrins_h, gen_xx_i, gen_helper_xvextrins_h)
TRANS(xvextrins_w, gen_xx_i, gen_helper_xvextrins_w)
TRANS(xvextrins_d, gen_xx_i, gen_helper_xvextrins_d)
+
+static bool gen_lasx_memory(DisasContext *ctx, arg_xr_i * a,
+void (*func)(TCGv_ptr, TCGv_i32, TCGv))
+{
+TCGv_i32 xd = tcg_constant_i32(a->xd);
+TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+TCGv temp = NULL;
+
+CHECK_ASXE;
+
+if (a->imm) {
+temp = tcg_temp_new();
+tcg_gen_addi_tl(temp, addr, a->imm);
+addr = temp;
+}
+
+func(cpu_env, xd, addr);
+return true;
+}
+
+TRANS(xvld, gen_lasx_memory, gen_helper_xvld_b)
+TRANS(xvst, gen_lasx_memory, gen_helper_xvst_b)
+
+static bool gen_lasx_memoryx(DisasContext *ctx, arg_xrr *a,
+ void (*func)(TCGv_ptr, TCGv_i32, TCGv))
+{
+TCGv_i32 xd = tcg_constant_i32(a->xd);
+TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+TCGv addr = tcg_temp_new();
+
+CHECK_ASXE;
+
+tcg_gen_add_tl(addr, src1, src2);
+func(cpu_env, xd, addr);
+return true;
+}
+
+TRANS(xvldx, gen_lasx_memoryx, gen_helper_xvld_b)
+TRANS(xvstx, gen_lasx_memoryx, gen_helper_xvst_b)
+
+#define XVLDREPL(NAME, MO) \
+static bool trans_## NAME(DisasContext *ctx, arg_xr_i * a) \
+{ \
+TCGv addr, temp;\
+TCGv_i64 val; \
+\
+CHECK_ASXE; \
+\
+addr = gpr_src(ctx, a->rj, EXT_NONE); \
+val = tcg_temp_new_i64(); \
+\
+if (a->imm) { \
+temp = tcg_temp_new(); \
+tcg_gen_addi_tl(temp, addr, a->imm);\
+addr = temp;
[PATCH v1 46/46] target/loongarch: CPUCFG support LASX
Signed-off-by: Song Gao --- target/loongarch/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index c9f9cbb19d..aeccbb42e6 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -392,6 +392,7 @@ static void loongarch_la464_initfn(Object *obj) data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); data = FIELD_DP32(data, CPUCFG2, LSX, 1), +data = FIELD_DP32(data, CPUCFG2, LASX, 1), data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); data = FIELD_DP32(data, CPUCFG2, LAM, 1); -- 2.39.1
Re: [PATCH 4/4] spapr: Allow up to 8 threads SMT on POWER8 and newer
On Tue Jun 20, 2023 at 7:27 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 6/5/23 16:53, Nicholas Piggin wrote:
> > PPC TCG now supports multi-threaded CPU configuration for non-hypervisor
> > state. This requires PIR and TIR be set, because that's how sibling thread
> > matching is done.
> >
> > spapr's nested-HV capability does not currently coexist with SMT. This
> > is quite analogous to LPAR-per-core mode on real hardware which also
> > does not support KVM.
> >
> > Signed-off-by: Nicholas Piggin
> > ---
> > hw/ppc/spapr.c | 16
> > hw/ppc/spapr_caps.c | 14 ++
> > hw/ppc/spapr_cpu_core.c | 7 +--
> > 3 files changed, 31 insertions(+), 6 deletions(-)
> >
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index dcb7f1c70a..deb8b507e3 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -2524,10 +2524,18 @@ static void spapr_set_vsmt_mode(SpaprMachineState
> > *spapr, Error **errp)
> > int ret;
> > unsigned int smp_threads = ms->smp.threads;
> >
> > -if (!kvm_enabled() && (smp_threads > 1)) {
> > -error_setg(errp, "TCG cannot support more than 1 thread/core "
> > - "on a pseries machine");
> > -return;
> > +if (!kvm_enabled()) {
>
> Can we make it a check for tcg_enabled() which would be more appropriate
> or as Cedric suggested, may be include this one along with your series:
>
> https://lore.kernel.org/qemu-devel/20230620074802.86898-1-phi...@linaro.org/
Good point, I'll keep it in mind.
Thanks,
Nick
Re: [PATCH 2/9] MAINTAINERS: Add reviewer for PowerPC TCG CPUs
On Tue Jun 20, 2023 at 3:59 PM AEST, Cédric Le Goater wrote: > Nick has great knowledge of the PowerPC CPUs, software and hardware. > Add him as a reviewer on CPU TCG modeling. Reviewed-by: Nicholas Piggin > > Cc: Nicholas Piggin > Signed-off-by: Cédric Le Goater > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index e6f3dade2230..90fb83c4cb58 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -302,6 +302,7 @@ M: Daniel Henrique Barboza > R: Cédric Le Goater > R: David Gibson > R: Greg Kurz > +R: Nicholas Piggin > L: qemu-...@nongnu.org > S: Odd Fixes > F: target/ppc/ > -- > 2.41.0
Re: [QEMU PATCH 1/1] virtgpu: do not destroy resources when guest suspend
Hi, > > The guest driver should be able to restore resources after resume. > > Thank you for your suggestion! > As far as I know, resources are created on host side and guest has no backup, > if resources are destroyed, guest can't restore them. > Or do you mean guest driver need to send commands to re-create resources > after resume? The later. The guest driver knows which resources it has created, it can restore them after suspend. > If so, I have some questions. Can guest re-create resources by using > object(virtio_vpu_object) or others? Can the new resources replace the > destroyed resources to continue the suspended display tasks after > resume? Any display scanout information will be gone too, the guest driver needs re-create this too (after re-creating the resources). take care, Gerd
[PATCH v1 41/46] target/loongarch: Implement xvinsgr2vr xvpickve2gr
This patch includes:
- XVINSGR2VR.{W/D};
- XVPICKVE2GR.{W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 54
target/loongarch/insns.decode| 13 +
3 files changed, 84 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 5c2a81ee80..fd7d459921 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1738,6 +1738,16 @@ static void output_xr(DisasContext *ctx, arg_xr *a,
const char *mnemonic)
output(ctx, mnemonic, "x%d, r%d", a->xd, a->rj);
}
+static void output_xr_i(DisasContext *ctx, arg_xr_i *a, const char *mnemonic)
+{
+output(ctx, mnemonic, "x%d, r%d, 0x%x", a->xd, a->rj, a->imm);
+}
+
+static void output_rx_i(DisasContext *ctx, arg_rx_i *a, const char *mnemonic)
+{
+output(ctx, mnemonic, "r%d, x%d, 0x%x", a->rd, a->xj, a->imm);
+}
+
INSN_LASX(xvadd_b, xxx)
INSN_LASX(xvadd_h, xxx)
INSN_LASX(xvadd_w, xxx)
@@ -2497,6 +2507,13 @@ INSN_LASX(xvsetallnez_h, cx)
INSN_LASX(xvsetallnez_w, cx)
INSN_LASX(xvsetallnez_d, cx)
+INSN_LASX(xvinsgr2vr_w, xr_i)
+INSN_LASX(xvinsgr2vr_d, xr_i)
+INSN_LASX(xvpickve2gr_w, rx_i)
+INSN_LASX(xvpickve2gr_d, rx_i)
+INSN_LASX(xvpickve2gr_wu,rx_i)
+INSN_LASX(xvpickve2gr_du,rx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index cefb6a4973..0fc26023d1 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2782,6 +2782,60 @@ TRANS(xvsetallnez_h, gen_cx, gen_helper_xvsetallnez_h)
TRANS(xvsetallnez_w, gen_cx, gen_helper_xvsetallnez_w)
TRANS(xvsetallnez_d, gen_cx, gen_helper_xvsetallnez_d)
+static bool trans_xvinsgr2vr_w(DisasContext *ctx, arg_xr_i *a)
+{
+TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
+CHECK_ASXE;
+tcg_gen_st32_i64(src, cpu_env,
+ offsetof(CPULoongArchState, fpr[a->xd].xreg.XW(a->imm)));
+return true;
+}
+
+static bool trans_xvinsgr2vr_d(DisasContext *ctx, arg_xr_i *a)
+{
+TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
+CHECK_ASXE;
+tcg_gen_st_i64(src, cpu_env,
+ offsetof(CPULoongArchState, fpr[a->xd].xreg.XD(a->imm)));
+return true;
+}
+
+static bool trans_xvpickve2gr_w(DisasContext *ctx, arg_rx_i *a)
+{
+TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
+CHECK_ASXE;
+tcg_gen_ld32s_i64(dst, cpu_env,
+ offsetof(CPULoongArchState, fpr[a->xj].xreg.XW(a->imm)));
+return true;
+}
+
+static bool trans_xvpickve2gr_d(DisasContext *ctx, arg_rx_i *a)
+{
+TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
+CHECK_ASXE;
+tcg_gen_ld_i64(dst, cpu_env,
+ offsetof(CPULoongArchState, fpr[a->xj].xreg.XD(a->imm)));
+return true;
+}
+
+static bool trans_xvpickve2gr_wu(DisasContext *ctx, arg_rx_i *a)
+{
+TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
+CHECK_ASXE;
+tcg_gen_ld32u_i64(dst, cpu_env,
+ offsetof(CPULoongArchState, fpr[a->xj].xreg.XW(a->imm)));
+return true;
+}
+
+static bool trans_xvpickve2gr_du(DisasContext *ctx, arg_rx_i *a)
+{
+TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
+CHECK_ASXE;
+tcg_gen_ld_i64(dst, cpu_env,
+ offsetof(CPULoongArchState, fpr[a->xj].xreg.XD(a->imm)));
+return true;
+}
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index b696d99577..8c87b3f840 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1309,6 +1309,8 @@ vstelm_b 0011 000110 . .
@vr_i8i4
& xd xj xk xa
&xxx_fcondxd xj xk fcond
&cx cd xj
+&xr_i xd rj imm
+&rx_i rd xj imm
#
# LASX Formats
@@ -1328,6 +1330,10 @@ vstelm_b 0011 000110 . .
@vr_i8i4
@ xa:5 xk:5 xj:5 xd:5&
@xxx_fcond fcond:5 xk:5 xj:5 xd:5&xxx_fcond
@cx . . xj:5 .. cd:3&cx
+@xr_ui3 . .. imm:3 rj:5 xd:5&xr_i
+@xr_ui2 . ... imm:2 rj:5 xd:5&xr_i
+@rx_ui3 . .. imm:3 xj:5 rd:5&rx_i
+@rx_ui2 . ... imm:2 xj:5 rd:5&rx_i
xvadd_b 0111 0100 10100 . . .@xxx
xvadd_h 0111 0100 10101 . . .@xxx
@@ -2005,6 +2011,13 @@ xvsetallnez_h0111 01101001 11001 01101 . 00 ...
@cx
xvsetallnez_w0111 01101001 11001 01110 . 00 ... @cx
xvsetallnez_d0111 01101001 11001 0 . 00 ... @cx
+xvinsgr2vr_w
[PATCH v1 28/46] target/loongarch: Implement xvsrln xvsran
This patch includes:
- XVSRLN.{B.H/H.W/W.D};
- XVSRAN.{B.H/H.W/W.D};
- XVSRLNI.{B.H/H.W/W.D/D.Q};
- XVSRANI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 16 +++
target/loongarch/helper.h| 16 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 16 +++
target/loongarch/insns.decode| 17 +++
target/loongarch/lasx_helper.c | 128 +++
target/loongarch/lsx_helper.c| 2 -
target/loongarch/vec.h | 2 +
7 files changed, 195 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index a63ba6d6ee..5ea713075f 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2103,6 +2103,22 @@ INSN_LASX(xvsrari_h, xx_i)
INSN_LASX(xvsrari_w, xx_i)
INSN_LASX(xvsrari_d, xx_i)
+INSN_LASX(xvsrln_b_h,xxx)
+INSN_LASX(xvsrln_h_w,xxx)
+INSN_LASX(xvsrln_w_d,xxx)
+INSN_LASX(xvsran_b_h,xxx)
+INSN_LASX(xvsran_h_w,xxx)
+INSN_LASX(xvsran_w_d,xxx)
+
+INSN_LASX(xvsrlni_b_h, xx_i)
+INSN_LASX(xvsrlni_h_w, xx_i)
+INSN_LASX(xvsrlni_w_d, xx_i)
+INSN_LASX(xvsrlni_d_q, xx_i)
+INSN_LASX(xvsrani_b_h, xx_i)
+INSN_LASX(xvsrani_h_w, xx_i)
+INSN_LASX(xvsrani_w_d, xx_i)
+INSN_LASX(xvsrani_d_q, xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 6bb30ddd31..c41f8e2bc9 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -958,3 +958,19 @@ DEF_HELPER_4(xvsrari_b, void, env, i32, i32, i32)
DEF_HELPER_4(xvsrari_h, void, env, i32, i32, i32)
DEF_HELPER_4(xvsrari_w, void, env, i32, i32, i32)
DEF_HELPER_4(xvsrari_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvsrln_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrln_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrln_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsran_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsran_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsran_w_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvsrlni_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlni_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlni_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlni_d_q, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrani_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrani_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrani_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrani_d_q, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 602ba0c800..9a3c2114eb 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2052,6 +2052,22 @@ TRANS(xvsrari_h, gen_xx_i, gen_helper_xvsrari_h)
TRANS(xvsrari_w, gen_xx_i, gen_helper_xvsrari_w)
TRANS(xvsrari_d, gen_xx_i, gen_helper_xvsrari_d)
+TRANS(xvsrln_b_h, gen_xxx, gen_helper_xvsrln_b_h)
+TRANS(xvsrln_h_w, gen_xxx, gen_helper_xvsrln_h_w)
+TRANS(xvsrln_w_d, gen_xxx, gen_helper_xvsrln_w_d)
+TRANS(xvsran_b_h, gen_xxx, gen_helper_xvsran_b_h)
+TRANS(xvsran_h_w, gen_xxx, gen_helper_xvsran_h_w)
+TRANS(xvsran_w_d, gen_xxx, gen_helper_xvsran_w_d)
+
+TRANS(xvsrlni_b_h, gen_xx_i, gen_helper_xvsrlni_b_h)
+TRANS(xvsrlni_h_w, gen_xx_i, gen_helper_xvsrlni_h_w)
+TRANS(xvsrlni_w_d, gen_xx_i, gen_helper_xvsrlni_w_d)
+TRANS(xvsrlni_d_q, gen_xx_i, gen_helper_xvsrlni_d_q)
+TRANS(xvsrani_b_h, gen_xx_i, gen_helper_xvsrani_b_h)
+TRANS(xvsrani_h_w, gen_xx_i, gen_helper_xvsrani_h_w)
+TRANS(xvsrani_w_d, gen_xx_i, gen_helper_xvsrani_w_d)
+TRANS(xvsrani_d_q, gen_xx_i, gen_helper_xvsrani_d_q)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index d901ddf063..45f15e3be2 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1320,6 +1320,7 @@ vstelm_b 0011 000110 . .
@vr_i8i4
@xx_ui4 . . imm:4 xj:5 xd:5&xx_i
@xx_ui5 . imm:5 xj:5 xd:5&xx_i
@xx_ui6 imm:6 xj:5 xd:5&xx_i
+@xx_ui7 ... imm:7 xj:5 xd:5&xx_i
@xx_ui8 .. imm:8 xj:5 xd:5&xx_i
xvadd_b 0111 0100 10100 . . .@xxx
@@ -1700,6 +1701,22 @@ xvsrari_h0111 01101010 1 1 . .
@xx_ui4
xvsrari_w0111 01101010 10001 . . .@xx_ui5
xvsrari_d0111 01101010 1001 .. . .@xx_ui6
+xvsrln_b_h 0111 0100 01001 . . .@xxx
+xvsrln_h_w 0111 0100 01010 . . .@xxx
+xvsrln_w_d 0111 0100 01011 . . .@xxx
[PATCH v1 23/46] target/loognarch: Implement xvldi
This patch includes:
- XVLDI.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 7 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 21
target/loongarch/insns.decode| 5 -
3 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 5a3c14f33d..82a9826eb7 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1703,6 +1703,11 @@ static bool trans_##insn(DisasContext *ctx, arg_##type *
a) \
return true;\
}
+static void output_x_i(DisasContext *ctx, arg_x_i *a, const char *mnemonic)
+{
+output(ctx, mnemonic, "x%d, 0x%x", a->xd, a->imm);
+}
+
static void output_xxx(DisasContext *ctx, arg_xxx * a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, x%d, x%d", a->xd, a->xj, a->xk);
@@ -2021,6 +2026,8 @@ INSN_LASX(xvmskltz_d,xx)
INSN_LASX(xvmskgez_b,xx)
INSN_LASX(xvmsknz_b, xx)
+INSN_LASX(xvldi, x_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index b0aad21a9d..bf277e1fd9 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -1914,6 +1914,27 @@ TRANS(xvmskltz_d, gen_xx, gen_helper_xvmskltz_d)
TRANS(xvmskgez_b, gen_xx, gen_helper_xvmskgez_b)
TRANS(xvmsknz_b, gen_xx, gen_helper_xvmsknz_b)
+static bool trans_xvldi(DisasContext *ctx, arg_xvldi * a)
+{
+int sel, vece;
+uint64_t value;
+CHECK_ASXE;
+
+sel = (a->imm >> 12) & 0x1;
+
+if (sel) {
+value = vldi_get_value(ctx, a->imm);
+vece = MO_64;
+} else {
+value = ((int32_t)(a->imm << 22)) >> 22;
+vece = (a->imm >> 10) & 0x3;
+}
+
+tcg_gen_gvec_dup_i64(vece, vec_full_offset(a->xd), 32, ctx->vl / 8,
+ tcg_constant_i64(value));
+return true;
+}
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index b792a68fdf..fbd0dd229a 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1305,11 +1305,13 @@ vstelm_b 0011 000110 . .
@vr_i8i4
&xxx xd xj xk
&xr xd rj
&xx_i xd xj imm
+&x_i xd imm
#
# LASX Formats
#
+@x_i13 .. imm:13 xd:5&x_i
@xx . . xj:5 xd:5&xx
@xxx . xk:5 xj:5 xd:5&xxx
@xr . . rj:5 xd:5&xr
@@ -1319,7 +1321,6 @@ vstelm_b 0011 000110 . .
@vr_i8i4
@xx_ui5 . imm:5 xj:5 xd:5&xx_i
@xx_ui6 imm:6 xj:5 xd:5&xx_i
-
xvadd_b 0111 0100 10100 . . .@xxx
xvadd_h 0111 0100 10101 . . .@xxx
xvadd_w 0111 0100 10110 . . .@xxx
@@ -1625,6 +1626,8 @@ xvmskltz_d 0111 01101001 11000 10011 . .
@xx
xvmskgez_b 0111 01101001 11000 10100 . .@xx
xvmsknz_b0111 01101001 11000 11000 . .@xx
+xvldi0111 0110 00 . . @x_i13
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010 . .@xr
--
2.39.1
[PATCH v1 12/46] target/loongarch: Implement xvabsd
This patch includes:
- XVABSD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 +++
target/loongarch/helper.h| 9 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 81
target/loongarch/insns.decode| 9 +++
target/loongarch/lasx_helper.c | 9 +++
target/loongarch/lsx_helper.c| 2 -
target/loongarch/vec.h | 2 +
7 files changed, 119 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index d804caaee0..d6b6b8ddd6 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1842,6 +1842,15 @@ INSN_LASX(xvavgr_hu, xxx)
INSN_LASX(xvavgr_wu, xxx)
INSN_LASX(xvavgr_du, xxx)
+INSN_LASX(xvabsd_b, xxx)
+INSN_LASX(xvabsd_h, xxx)
+INSN_LASX(xvabsd_w, xxx)
+INSN_LASX(xvabsd_d, xxx)
+INSN_LASX(xvabsd_bu, xxx)
+INSN_LASX(xvabsd_hu, xxx)
+INSN_LASX(xvabsd_wu, xxx)
+INSN_LASX(xvabsd_du, xxx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index feeaa92447..3ec7717c88 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -777,3 +777,12 @@ DEF_HELPER_FLAGS_4(xvavgr_bu, TCG_CALL_NO_RWG, void, ptr,
ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvavgr_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvavgr_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvavgr_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvabsd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvabsd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvabsd_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvabsd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvabsd_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvabsd_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvabsd_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvabsd_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 4a8bcf618f..8f7ff2cba6 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -750,6 +750,87 @@ TRANS(xvavgr_hu, gvec_xxx, MO_16, do_xvavgr_u)
TRANS(xvavgr_wu, gvec_xxx, MO_32, do_xvavgr_u)
TRANS(xvavgr_du, gvec_xxx, MO_64, do_xvavgr_u)
+static void do_xvabsd_s(unsigned vece, uint32_t xd_ofs, uint32_t xj_ofs,
+uint32_t xk_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+static const TCGOpcode vecop_list[] = {
+INDEX_op_smax_vec, INDEX_op_smin_vec, INDEX_op_sub_vec, 0
+};
+static const GVecGen3 op[4] = {
+{
+.fniv = gen_vabsd_s,
+.fno = gen_helper_xvabsd_b,
+.opt_opc = vecop_list,
+.vece = MO_8
+},
+{
+.fniv = gen_vabsd_s,
+.fno = gen_helper_xvabsd_h,
+.opt_opc = vecop_list,
+.vece = MO_16
+},
+{
+.fniv = gen_vabsd_s,
+.fno = gen_helper_xvabsd_w,
+.opt_opc = vecop_list,
+.vece = MO_32
+},
+{
+.fniv = gen_vabsd_s,
+.fno = gen_helper_xvabsd_d,
+.opt_opc = vecop_list,
+.vece = MO_64
+},
+};
+
+tcg_gen_gvec_3(xd_ofs, xj_ofs, xk_ofs, oprsz, maxsz, &op[vece]);
+}
+
+static void do_xvabsd_u(unsigned vece, uint32_t xd_ofs, uint32_t xj_ofs,
+uint32_t xk_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+static const TCGOpcode vecop_list[] = {
+INDEX_op_umax_vec, INDEX_op_umin_vec, INDEX_op_sub_vec, 0
+};
+static const GVecGen3 op[4] = {
+{
+.fniv = gen_vabsd_u,
+.fno = gen_helper_xvabsd_bu,
+.opt_opc = vecop_list,
+.vece = MO_8
+},
+{
+.fniv = gen_vabsd_u,
+.fno = gen_helper_xvabsd_hu,
+.opt_opc = vecop_list,
+.vece = MO_16
+},
+{
+.fniv = gen_vabsd_u,
+.fno = gen_helper_xvabsd_wu,
+.opt_opc = vecop_list,
+.vece = MO_32
+},
+{
+.fniv = gen_vabsd_u,
+.fno = gen_helper_xvabsd_du,
+.opt_opc = vecop_list,
+.vece = MO_64
+},
+};
+
+tcg_gen_gvec_3(xd_ofs, xj_ofs, xk_ofs, oprsz, maxsz, &op[vece]);
+}
+
+TRANS(xvabsd_b, gvec_xxx, MO_8, do_xvabsd_s)
+TRANS(xvabsd_h, gvec_xxx, MO_16, do_xvabsd_s)
+TRANS(xvabsd_w, gvec_xxx, MO_32, do_xvabsd_s)
+TRANS(xvabsd_d, gvec_xxx, MO_64, do_xvabsd_s)
+TRANS(xvabsd_bu, gvec_xxx, MO_8, do_xvabsd
[PATCH v1 30/46] target/loongarch: Implement xvssrln xvssran
This patch includes:
- XVSSRLN.{B.H/H.W/W.D};
- XVSSRAN.{B.H/H.W/W.D};
- XVSSRLN.{BU.H/HU.W/WU.D};
- XVSSRAN.{BU.H/HU.W/WU.D};
- XVSSRLNI.{B.H/H.W/W.D/D.Q};
- XVSSRANI.{B.H/H.W/W.D/D.Q};
- XVSSRLNI.{BU.H/HU.W/WU.D/DU.Q};
- XVSSRANI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 30 ++
target/loongarch/helper.h| 30 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 30 ++
target/loongarch/insns.decode| 30 ++
target/loongarch/lasx_helper.c | 428 +++
5 files changed, 548 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 515d99aa1f..1f40f3aaca 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2135,6 +2135,36 @@ INSN_LASX(xvsrarni_h_w, xx_i)
INSN_LASX(xvsrarni_w_d, xx_i)
INSN_LASX(xvsrarni_d_q, xx_i)
+INSN_LASX(xvssrln_b_h, xxx)
+INSN_LASX(xvssrln_h_w, xxx)
+INSN_LASX(xvssrln_w_d, xxx)
+INSN_LASX(xvssran_b_h, xxx)
+INSN_LASX(xvssran_h_w, xxx)
+INSN_LASX(xvssran_w_d, xxx)
+INSN_LASX(xvssrln_bu_h, xxx)
+INSN_LASX(xvssrln_hu_w, xxx)
+INSN_LASX(xvssrln_wu_d, xxx)
+INSN_LASX(xvssran_bu_h, xxx)
+INSN_LASX(xvssran_hu_w, xxx)
+INSN_LASX(xvssran_wu_d, xxx)
+
+INSN_LASX(xvssrlni_b_h, xx_i)
+INSN_LASX(xvssrlni_h_w, xx_i)
+INSN_LASX(xvssrlni_w_d, xx_i)
+INSN_LASX(xvssrlni_d_q, xx_i)
+INSN_LASX(xvssrani_b_h, xx_i)
+INSN_LASX(xvssrani_h_w, xx_i)
+INSN_LASX(xvssrani_w_d, xx_i)
+INSN_LASX(xvssrani_d_q, xx_i)
+INSN_LASX(xvssrlni_bu_h, xx_i)
+INSN_LASX(xvssrlni_hu_w, xx_i)
+INSN_LASX(xvssrlni_wu_d, xx_i)
+INSN_LASX(xvssrlni_du_q, xx_i)
+INSN_LASX(xvssrani_bu_h, xx_i)
+INSN_LASX(xvssrani_hu_w, xx_i)
+INSN_LASX(xvssrani_wu_d, xx_i)
+INSN_LASX(xvssrani_du_q, xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 09ae21edd6..2d76916049 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -990,3 +990,33 @@ DEF_HELPER_4(xvsrarni_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(xvsrarni_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(xvsrarni_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(xvsrarni_d_q, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvssrln_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrln_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrln_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssran_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssran_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssran_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrln_bu_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrln_hu_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrln_wu_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssran_bu_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssran_hu_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssran_wu_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvssrlni_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlni_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlni_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlni_d_q, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrani_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrani_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrani_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrani_d_q, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlni_bu_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlni_hu_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlni_wu_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlni_du_q, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrani_bu_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrani_hu_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrani_wu_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrani_du_q, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 5cd241bafa..b6c2ced30c 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2084,6 +2084,36 @@ TRANS(xvsrarni_h_w, gen_xx_i, gen_helper_xvsrarni_h_w)
TRANS(xvsrarni_w_d, gen_xx_i, gen_helper_xvsrarni_w_d)
TRANS(xvsrarni_d_q, gen_xx_i, gen_helper_xvsrarni_d_q)
+TRANS(xvssrln_b_h, gen_xxx, gen_helper_xvssrln_b_h)
+TRANS(xvssrln_h_w, gen_xxx, gen_helper_xvssrln_h_w)
+TRANS(xvssrln_w_d, gen_xxx, gen_helper_xvssrln_w_d)
+TRANS(xvssran_b_h, gen_xxx, gen_helper_xvssran_b_h)
+TRANS(xvssran_h_w, gen_xxx, gen_helper_xvssran_h_w)
+TRANS(xvssran_w_d, gen_xxx, gen_helper_xvssran_w_d)
+TRANS(xvssrln_bu_h, gen_xxx, gen_helper_xvssrln_bu_h)
+TRANS(xvssrln_hu_w, gen_xxx, gen_helper_xvssrln_hu_w)
+TRANS(xvssrln_wu_d, gen_xxx, gen_helper_xvssrln_wu_d)
+TRANS(xvssran_bu_h, gen_xxx, gen_helper_xvssran_bu_h)
+TRANS(xvssran_hu_w, gen_xxx, gen_helper_xvssran_hu_w)
+TRANS(xvssran_wu_d, gen_xxx, gen_help
[PATCH v1 09/46] target/loongarch: Implement xvhaddw/xvhsubw
This patch includes:
- XVHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU};
- XVHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17
target/loongarch/helper.h| 18
target/loongarch/insn_trans/trans_lasx.c.inc | 30 +++
target/loongarch/insns.decode| 18
target/loongarch/lasx_helper.c | 90
target/loongarch/lsx_helper.c| 3 -
target/loongarch/vec.h | 3 +
7 files changed, 176 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 2a2993cb95..770359524e 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1765,6 +1765,23 @@ INSN_LASX(xvssub_hu, xxx)
INSN_LASX(xvssub_wu, xxx)
INSN_LASX(xvssub_du, xxx)
+INSN_LASX(xvhaddw_h_b, xxx)
+INSN_LASX(xvhaddw_w_h, xxx)
+INSN_LASX(xvhaddw_d_w, xxx)
+INSN_LASX(xvhaddw_q_d, xxx)
+INSN_LASX(xvhaddw_hu_bu, xxx)
+INSN_LASX(xvhaddw_wu_hu, xxx)
+INSN_LASX(xvhaddw_du_wu, xxx)
+INSN_LASX(xvhaddw_qu_du, xxx)
+INSN_LASX(xvhsubw_h_b, xxx)
+INSN_LASX(xvhsubw_w_h, xxx)
+INSN_LASX(xvhsubw_d_w, xxx)
+INSN_LASX(xvhsubw_q_d, xxx)
+INSN_LASX(xvhsubw_hu_bu, xxx)
+INSN_LASX(xvhsubw_wu_hu, xxx)
+INSN_LASX(xvhsubw_du_wu, xxx)
+INSN_LASX(xvhsubw_qu_du, xxx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index b9de77d926..db2deaff79 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -696,3 +696,21 @@ DEF_HELPER_4(vextrins_b, void, env, i32, i32, i32)
DEF_HELPER_4(vextrins_h, void, env, i32, i32, i32)
DEF_HELPER_4(vextrins_w, void, env, i32, i32, i32)
DEF_HELPER_4(vextrins_d, void, env, i32, i32, i32)
+
+/* LoongArch LASX */
+DEF_HELPER_4(xvhaddw_h_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhaddw_w_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhaddw_d_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhaddw_q_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhaddw_hu_bu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhaddw_wu_hu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhaddw_du_wu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhaddw_qu_du, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhsubw_h_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhsubw_w_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhsubw_d_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhsubw_q_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhsubw_hu_bu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhsubw_wu_hu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhsubw_du_wu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvhsubw_qu_du, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index ec68193686..aa0e35b228 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -15,6 +15,19 @@
#define CHECK_ASXE
#endif
+static bool gen_xxx(DisasContext *ctx, arg_xxx *a,
+void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32))
+{
+TCGv_i32 xd = tcg_constant_i32(a->xd);
+TCGv_i32 xj = tcg_constant_i32(a->xj);
+TCGv_i32 xk = tcg_constant_i32(a->xk);
+
+CHECK_ASXE;
+
+func(cpu_env, xd, xj, xk);
+return true;
+}
+
static bool gvec_xxx(DisasContext *ctx, arg_xxx *a, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t))
@@ -148,6 +161,23 @@ TRANS(xvssub_hu, gvec_xxx, MO_16, tcg_gen_gvec_ussub)
TRANS(xvssub_wu, gvec_xxx, MO_32, tcg_gen_gvec_ussub)
TRANS(xvssub_du, gvec_xxx, MO_64, tcg_gen_gvec_ussub)
+TRANS(xvhaddw_h_b, gen_xxx, gen_helper_xvhaddw_h_b)
+TRANS(xvhaddw_w_h, gen_xxx, gen_helper_xvhaddw_w_h)
+TRANS(xvhaddw_d_w, gen_xxx, gen_helper_xvhaddw_d_w)
+TRANS(xvhaddw_q_d, gen_xxx, gen_helper_xvhaddw_q_d)
+TRANS(xvhaddw_hu_bu, gen_xxx, gen_helper_xvhaddw_hu_bu)
+TRANS(xvhaddw_wu_hu, gen_xxx, gen_helper_xvhaddw_wu_hu)
+TRANS(xvhaddw_du_wu, gen_xxx, gen_helper_xvhaddw_du_wu)
+TRANS(xvhaddw_qu_du, gen_xxx, gen_helper_xvhaddw_qu_du)
+TRANS(xvhsubw_h_b, gen_xxx, gen_helper_xvhsubw_h_b)
+TRANS(xvhsubw_w_h, gen_xxx, gen_helper_xvhsubw_w_h)
+TRANS(xvhsubw_d_w, gen_xxx, gen_helper_xvhsubw_d_w)
+TRANS(xvhsubw_q_d, gen_xxx, gen_helper_xvhsubw_q_d)
+TRANS(xvhsubw_hu_bu, gen_xxx, gen_helper_xvhsubw_hu_bu)
+TRANS(xvhsubw_wu_hu, gen_xxx, gen_helper_xvhsubw_wu_hu)
+TRANS(xvhsubw_du_wu, gen_xxx, gen_helper_xvhsubw_du_wu)
+TRANS(xvhsubw_qu_du, gen_xxx, gen_helper_xvhsubw_qu_du)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index be706fe0f7..48556b2267 100644
--- a/target/loongarch/in
[PATCH v1 25/46] target/loongarch: Implement xvsll xvsrl xvsra xvrotr
This patch includes:
- XVSLL[I].{B/H/W/D};
- XVSRL[I].{B/H/W/D};
- XVSRA[I].{B/H/W/D};
- XVROTR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 36
target/loongarch/insn_trans/trans_lasx.c.inc | 36
target/loongarch/insns.decode| 33 ++
3 files changed, 105 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 2f1da9db80..0c1c7a7e6e 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2040,6 +2040,42 @@ INSN_LASX(xvori_b, xx_i)
INSN_LASX(xvxori_b, xx_i)
INSN_LASX(xvnori_b, xx_i)
+INSN_LASX(xvsll_b, xxx)
+INSN_LASX(xvsll_h, xxx)
+INSN_LASX(xvsll_w, xxx)
+INSN_LASX(xvsll_d, xxx)
+INSN_LASX(xvslli_b, xx_i)
+INSN_LASX(xvslli_h, xx_i)
+INSN_LASX(xvslli_w, xx_i)
+INSN_LASX(xvslli_d, xx_i)
+
+INSN_LASX(xvsrl_b, xxx)
+INSN_LASX(xvsrl_h, xxx)
+INSN_LASX(xvsrl_w, xxx)
+INSN_LASX(xvsrl_d, xxx)
+INSN_LASX(xvsrli_b, xx_i)
+INSN_LASX(xvsrli_h, xx_i)
+INSN_LASX(xvsrli_w, xx_i)
+INSN_LASX(xvsrli_d, xx_i)
+
+INSN_LASX(xvsra_b, xxx)
+INSN_LASX(xvsra_h, xxx)
+INSN_LASX(xvsra_w, xxx)
+INSN_LASX(xvsra_d, xxx)
+INSN_LASX(xvsrai_b, xx_i)
+INSN_LASX(xvsrai_h, xx_i)
+INSN_LASX(xvsrai_w, xx_i)
+INSN_LASX(xvsrai_d, xx_i)
+
+INSN_LASX(xvrotr_b, xxx)
+INSN_LASX(xvrotr_h, xxx)
+INSN_LASX(xvrotr_w, xxx)
+INSN_LASX(xvrotr_d, xxx)
+INSN_LASX(xvrotri_b, xx_i)
+INSN_LASX(xvrotri_h, xx_i)
+INSN_LASX(xvrotri_w, xx_i)
+INSN_LASX(xvrotri_d, xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index d48f76f118..5d7deb312e 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -1977,6 +1977,42 @@ static void do_xvnori_b(unsigned vece, uint32_t xd_ofs,
uint32_t xj_ofs,
TRANS(xvnori_b, gvec_xx_i, MO_8, do_xvnori_b)
+TRANS(xvsll_b, gvec_xxx, MO_8, tcg_gen_gvec_shlv)
+TRANS(xvsll_h, gvec_xxx, MO_16, tcg_gen_gvec_shlv)
+TRANS(xvsll_w, gvec_xxx, MO_32, tcg_gen_gvec_shlv)
+TRANS(xvsll_d, gvec_xxx, MO_64, tcg_gen_gvec_shlv)
+TRANS(xvslli_b, gvec_xx_i, MO_8, tcg_gen_gvec_shli)
+TRANS(xvslli_h, gvec_xx_i, MO_16, tcg_gen_gvec_shli)
+TRANS(xvslli_w, gvec_xx_i, MO_32, tcg_gen_gvec_shli)
+TRANS(xvslli_d, gvec_xx_i, MO_64, tcg_gen_gvec_shli)
+
+TRANS(xvsrl_b, gvec_xxx, MO_8, tcg_gen_gvec_shrv)
+TRANS(xvsrl_h, gvec_xxx, MO_16, tcg_gen_gvec_shrv)
+TRANS(xvsrl_w, gvec_xxx, MO_32, tcg_gen_gvec_shrv)
+TRANS(xvsrl_d, gvec_xxx, MO_64, tcg_gen_gvec_shrv)
+TRANS(xvsrli_b, gvec_xx_i, MO_8, tcg_gen_gvec_shri)
+TRANS(xvsrli_h, gvec_xx_i, MO_16, tcg_gen_gvec_shri)
+TRANS(xvsrli_w, gvec_xx_i, MO_32, tcg_gen_gvec_shri)
+TRANS(xvsrli_d, gvec_xx_i, MO_64, tcg_gen_gvec_shri)
+
+TRANS(xvsra_b, gvec_xxx, MO_8, tcg_gen_gvec_sarv)
+TRANS(xvsra_h, gvec_xxx, MO_16, tcg_gen_gvec_sarv)
+TRANS(xvsra_w, gvec_xxx, MO_32, tcg_gen_gvec_sarv)
+TRANS(xvsra_d, gvec_xxx, MO_64, tcg_gen_gvec_sarv)
+TRANS(xvsrai_b, gvec_xx_i, MO_8, tcg_gen_gvec_sari)
+TRANS(xvsrai_h, gvec_xx_i, MO_16, tcg_gen_gvec_sari)
+TRANS(xvsrai_w, gvec_xx_i, MO_32, tcg_gen_gvec_sari)
+TRANS(xvsrai_d, gvec_xx_i, MO_64, tcg_gen_gvec_sari)
+
+TRANS(xvrotr_b, gvec_xxx, MO_8, tcg_gen_gvec_rotrv)
+TRANS(xvrotr_h, gvec_xxx, MO_16, tcg_gen_gvec_rotrv)
+TRANS(xvrotr_w, gvec_xxx, MO_32, tcg_gen_gvec_rotrv)
+TRANS(xvrotr_d, gvec_xxx, MO_64, tcg_gen_gvec_rotrv)
+TRANS(xvrotri_b, gvec_xx_i, MO_8, tcg_gen_gvec_rotri)
+TRANS(xvrotri_h, gvec_xx_i, MO_16, tcg_gen_gvec_rotri)
+TRANS(xvrotri_w, gvec_xx_i, MO_32, tcg_gen_gvec_rotri)
+TRANS(xvrotri_d, gvec_xx_i, MO_64, tcg_gen_gvec_rotri)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index ce2ad47b88..03c3aa0019 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1641,6 +1641,39 @@ xvori_b 0111 0101 01 . .
@xx_ui8
xvxori_b 0111 0101 10 . .@xx_ui8
xvnori_b 0111 0101 11 . .@xx_ui8
+xvsll_b 0111 01001110 1 . . .@xxx
+xvsll_h 0111 01001110 10001 . . .@xxx
+xvsll_w 0111 01001110 10010 . . .@xxx
+xvsll_d 0111 01001110 10011 . . .@xxx
+xvslli_b 0111 01110010 11000 01 ... . . @xx_ui3
+xvslli_h 0111 01110010 11000 1 . . @xx_ui4
+xvslli_w 0111 01110010 11001 . .
[PATCH v1 27/46] target/loongarch: Implement xvsrlr xvsrar
This patch includes:
- XVSRLR[I].{B/H/W/D};
- XVSRAR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 18
target/loongarch/helper.h| 18
target/loongarch/insn_trans/trans_lasx.c.inc | 18
target/loongarch/insns.decode| 17 +++
target/loongarch/lasx_helper.c | 104 +++
5 files changed, 175 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index b6940e6389..a63ba6d6ee 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2085,6 +2085,24 @@ INSN_LASX(xvsllwil_wu_hu,xx_i)
INSN_LASX(xvsllwil_du_wu,xx_i)
INSN_LASX(xvextl_qu_du, xx)
+INSN_LASX(xvsrlr_b, xxx)
+INSN_LASX(xvsrlr_h, xxx)
+INSN_LASX(xvsrlr_w, xxx)
+INSN_LASX(xvsrlr_d, xxx)
+INSN_LASX(xvsrlri_b, xx_i)
+INSN_LASX(xvsrlri_h, xx_i)
+INSN_LASX(xvsrlri_w, xx_i)
+INSN_LASX(xvsrlri_d, xx_i)
+
+INSN_LASX(xvsrar_b, xxx)
+INSN_LASX(xvsrar_h, xxx)
+INSN_LASX(xvsrar_w, xxx)
+INSN_LASX(xvsrar_d, xxx)
+INSN_LASX(xvsrari_b, xx_i)
+INSN_LASX(xvsrari_h, xx_i)
+INSN_LASX(xvsrari_w, xx_i)
+INSN_LASX(xvsrari_d, xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 672a5f8988..6bb30ddd31 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -940,3 +940,21 @@ DEF_HELPER_4(xvsllwil_hu_bu, void, env, i32, i32, i32)
DEF_HELPER_4(xvsllwil_wu_hu, void, env, i32, i32, i32)
DEF_HELPER_4(xvsllwil_du_wu, void, env, i32, i32, i32)
DEF_HELPER_3(xvextl_qu_du, void, env, i32, i32)
+
+DEF_HELPER_4(xvsrlr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlr_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlri_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlri_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlri_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlri_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvsrar_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrar_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrar_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrar_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrari_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrari_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrari_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrari_d, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 53631cea63..602ba0c800 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2034,6 +2034,24 @@ TRANS(xvsllwil_wu_hu, gen_xx_i,
gen_helper_xvsllwil_wu_hu)
TRANS(xvsllwil_du_wu, gen_xx_i, gen_helper_xvsllwil_du_wu)
TRANS(xvextl_qu_du, gen_xx, gen_helper_xvextl_qu_du)
+TRANS(xvsrlr_b, gen_xxx, gen_helper_xvsrlr_b)
+TRANS(xvsrlr_h, gen_xxx, gen_helper_xvsrlr_h)
+TRANS(xvsrlr_w, gen_xxx, gen_helper_xvsrlr_w)
+TRANS(xvsrlr_d, gen_xxx, gen_helper_xvsrlr_d)
+TRANS(xvsrlri_b, gen_xx_i, gen_helper_xvsrlri_b)
+TRANS(xvsrlri_h, gen_xx_i, gen_helper_xvsrlri_h)
+TRANS(xvsrlri_w, gen_xx_i, gen_helper_xvsrlri_w)
+TRANS(xvsrlri_d, gen_xx_i, gen_helper_xvsrlri_d)
+
+TRANS(xvsrar_b, gen_xxx, gen_helper_xvsrar_b)
+TRANS(xvsrar_h, gen_xxx, gen_helper_xvsrar_h)
+TRANS(xvsrar_w, gen_xxx, gen_helper_xvsrar_w)
+TRANS(xvsrar_d, gen_xxx, gen_helper_xvsrar_d)
+TRANS(xvsrari_b, gen_xx_i, gen_helper_xvsrari_b)
+TRANS(xvsrari_h, gen_xx_i, gen_helper_xvsrari_h)
+TRANS(xvsrari_w, gen_xx_i, gen_helper_xvsrari_w)
+TRANS(xvsrari_d, gen_xx_i, gen_helper_xvsrari_d)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index ebaddb94ea..d901ddf063 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1683,6 +1683,23 @@ xvsllwil_wu_hu 0111 0111 11000 1 . .
@xx_ui4
xvsllwil_du_wu 0111 0111 11001 . . .@xx_ui5
xvextl_qu_du 0111 0111 11010 0 . .@xx
+xvsrlr_b 0111 0100 0 . . .@xxx
+xvsrlr_h 0111 0100 1 . . .@xxx
+xvsrlr_w 0111 0100 00010 . . .@xxx
+xvsrlr_d 0111 0100 00011 . . .@xxx
+xvsrlri_b0111 01101010 01000 01 ... . . @xx_ui3
+xvsrlri_h0111 01101010 01000 1 . . @xx_ui4
+xvsrlri_w0111 01101010 01001 . . .@xx_ui5
+xvsrlri_d0111 01101010 0101 .. . .@xx_ui6
+xvsrar_b 0111 0100 00100 . . .@xxx
+xvsrar_h 0111 0100 00101 . . ...
[PATCH v1 40/46] target/loongarch: Implement xvbitsel xvset
This patch includes:
- XVBITSEL.V;
- XVBITSELI.B;
- XVSET{EQZ/NEZ}.V;
- XVSETANYEQZ.{B/H/W/D};
- XVSETALLNEZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 19 +
target/loongarch/helper.h| 11 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 76
target/loongarch/insns.decode| 17 +
target/loongarch/lasx_helper.c | 37 ++
target/loongarch/lsx_helper.c| 2 +-
target/loongarch/vec.h | 2 +
7 files changed, 163 insertions(+), 1 deletion(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index c3bcb9d84a..5c2a81ee80 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1703,6 +1703,11 @@ static bool trans_##insn(DisasContext *ctx, arg_##type *
a) \
return true;\
}
+static void output_cx(DisasContext *ctx, arg_cx *a, const char *mnemonic)
+{
+output(ctx, mnemonic, "fcc%d, x%d", a->cd, a->xj);
+}
+
static void output_x_i(DisasContext *ctx, arg_x_i *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, 0x%x", a->xd, a->imm);
@@ -2478,6 +2483,20 @@ static bool trans_xvfcmp_cond_##suffix(DisasContext
*ctx, \
LASX_FCMP_INSN(s)
LASX_FCMP_INSN(d)
+INSN_LASX(xvbitsel_v,)
+INSN_LASX(xvbitseli_b, xx_i)
+
+INSN_LASX(xvseteqz_v,cx)
+INSN_LASX(xvsetnez_v,cx)
+INSN_LASX(xvsetanyeqz_b, cx)
+INSN_LASX(xvsetanyeqz_h, cx)
+INSN_LASX(xvsetanyeqz_w, cx)
+INSN_LASX(xvsetanyeqz_d, cx)
+INSN_LASX(xvsetallnez_b, cx)
+INSN_LASX(xvsetallnez_h, cx)
+INSN_LASX(xvsetallnez_w, cx)
+INSN_LASX(xvsetallnez_d, cx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 665bcb812a..f6d64bfde5 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1221,3 +1221,14 @@ DEF_HELPER_5(xvfcmp_c_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(xvfcmp_s_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(xvfcmp_c_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(xvfcmp_s_d, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_FLAGS_4(xvbitseli_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
+DEF_HELPER_3(xvsetanyeqz_b, void, env, i32, i32)
+DEF_HELPER_3(xvsetanyeqz_h, void, env, i32, i32)
+DEF_HELPER_3(xvsetanyeqz_w, void, env, i32, i32)
+DEF_HELPER_3(xvsetanyeqz_d, void, env, i32, i32)
+DEF_HELPER_3(xvsetallnez_b, void, env, i32, i32)
+DEF_HELPER_3(xvsetallnez_h, void, env, i32, i32)
+DEF_HELPER_3(xvsetallnez_w, void, env, i32, i32)
+DEF_HELPER_3(xvsetallnez_d, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index cdcd4a279a..cefb6a4973 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -65,6 +65,17 @@ static bool gen_xx_i(DisasContext *ctx, arg_xx_i *a,
return true;
}
+static bool gen_cx(DisasContext *ctx, arg_cx *a,
+ void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32))
+{
+TCGv_i32 xj = tcg_constant_i32(a->xj);
+TCGv_i32 cd = tcg_constant_i32(a->cd);
+
+CHECK_ASXE;
+func(cpu_env, cd, xj);
+return true;
+}
+
static bool gvec_xxx(DisasContext *ctx, arg_xxx *a, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t))
@@ -2706,6 +2717,71 @@ static bool trans_xvfcmp_cond_d(DisasContext *ctx,
arg_xxx_fcond *a)
return true;
}
+static bool trans_xvbitsel_v(DisasContext *ctx, arg_ *a)
+{
+CHECK_ASXE;
+
+tcg_gen_gvec_bitsel(MO_64, vec_full_offset(a->xd), vec_full_offset(a->xa),
+vec_full_offset(a->xk), vec_full_offset(a->xj),
+32, ctx->vl / 8);
+return true;
+}
+
+static bool trans_xvbitseli_b(DisasContext *ctx, arg_xx_i *a)
+{
+static const GVecGen2i op = {
+ .fniv = gen_vbitseli,
+ .fnoi = gen_helper_xvbitseli_b,
+ .vece = MO_8,
+ .load_dest = true
+};
+
+CHECK_ASXE;
+
+tcg_gen_gvec_2i(vec_full_offset(a->xd), vec_full_offset(a->xj),
+32, ctx->vl / 8, a->imm, &op);
+return true;
+}
+
+#define XVSET(NAME, COND)
\
+static bool trans_## NAME(DisasContext *ctx, arg_cx * a)
\
+{
\
+TCGv_i64 t1, t2, d[4];
\
+
\
+d[0] = tcg_temp_new_i64();
\
+d[1] = tcg_temp_new_i64();
\
+d[2] = tcg_temp_new_i64();
[PATCH v1 14/46] target/loongarch: Implement xvmax/xvmin
This patch includes:
- XVMAX[I].{B/H/W/D}[U];
- XVMIN[I].{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 33
target/loongarch/helper.h| 18 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 180 +++
target/loongarch/insns.decode| 37
target/loongarch/lasx_helper.c | 30
target/loongarch/lsx_helper.c| 3 -
target/loongarch/vec.h | 3 +
7 files changed, 301 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index cc92f0e763..ff22fcb90e 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1856,6 +1856,39 @@ INSN_LASX(xvadda_h, xxx)
INSN_LASX(xvadda_w, xxx)
INSN_LASX(xvadda_d, xxx)
+INSN_LASX(xvmax_b, xxx)
+INSN_LASX(xvmax_h, xxx)
+INSN_LASX(xvmax_w, xxx)
+INSN_LASX(xvmax_d, xxx)
+INSN_LASX(xvmin_b, xxx)
+INSN_LASX(xvmin_h, xxx)
+INSN_LASX(xvmin_w, xxx)
+INSN_LASX(xvmin_d, xxx)
+INSN_LASX(xvmax_bu, xxx)
+INSN_LASX(xvmax_hu, xxx)
+INSN_LASX(xvmax_wu, xxx)
+INSN_LASX(xvmax_du, xxx)
+INSN_LASX(xvmin_bu, xxx)
+INSN_LASX(xvmin_hu, xxx)
+INSN_LASX(xvmin_wu, xxx)
+INSN_LASX(xvmin_du, xxx)
+INSN_LASX(xvmaxi_b, xx_i)
+INSN_LASX(xvmaxi_h, xx_i)
+INSN_LASX(xvmaxi_w, xx_i)
+INSN_LASX(xvmaxi_d, xx_i)
+INSN_LASX(xvmini_b, xx_i)
+INSN_LASX(xvmini_h, xx_i)
+INSN_LASX(xvmini_w, xx_i)
+INSN_LASX(xvmini_d, xx_i)
+INSN_LASX(xvmaxi_bu, xx_i)
+INSN_LASX(xvmaxi_hu, xx_i)
+INSN_LASX(xvmaxi_wu, xx_i)
+INSN_LASX(xvmaxi_du, xx_i)
+INSN_LASX(xvmini_bu, xx_i)
+INSN_LASX(xvmini_hu, xx_i)
+INSN_LASX(xvmini_wu, xx_i)
+INSN_LASX(xvmini_du, xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 67ef7491c4..d5ebc0b963 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -791,3 +791,21 @@ DEF_HELPER_FLAGS_4(xvadda_b, TCG_CALL_NO_RWG, void, ptr,
ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvadda_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvadda_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvadda_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvmini_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmini_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmini_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmini_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmini_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmini_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmini_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmini_du, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
+DEF_HELPER_FLAGS_4(xvmaxi_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmaxi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmaxi_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmaxi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmaxi_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmaxi_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmaxi_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvmaxi_du, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 4b2e50de68..cdf3dcc161 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -872,6 +872,186 @@ TRANS(xvadda_h, gvec_xxx, MO_16, do_xvadda)
TRANS(xvadda_w, gvec_xxx, MO_32, do_xvadda)
TRANS(xvadda_d, gvec_xxx, MO_64, do_xvadda)
+TRANS(xvmax_b, gvec_xxx, MO_8, tcg_gen_gvec_smax)
+TRANS(xvmax_h, gvec_xxx, MO_16, tcg_gen_gvec_smax)
+TRANS(xvmax_w, gvec_xxx, MO_32, tcg_gen_gvec_smax)
+TRANS(xvmax_d, gvec_xxx, MO_64, tcg_gen_gvec_smax)
+TRANS(xvmax_bu, gvec_xxx, MO_8, tcg_gen_gvec_umax)
+TRANS(xvmax_hu, gvec_xxx, MO_16, tcg_gen_gvec_umax)
+TRANS(xvmax_wu, gvec_xxx, MO_32, tcg_gen_gvec_umax)
+TRANS(xvmax_du, gvec_xxx, MO_64, tcg_gen_gvec_umax)
+
+TRANS(xvmin_b, gvec_xxx, MO_8, tcg_gen_gvec_smin)
+TRANS(xvmin_h, gvec_xxx, MO_16, tcg_gen_gvec_smin)
+TRANS(xvmin_w, gvec_xxx, MO_32, tcg_gen_gvec_smin)
+TRANS(xvmin_d, gvec_xxx, MO_64, tcg_gen_gvec_smin)
+TRANS(xvmin_bu, gvec_xxx, MO_8, tcg_gen_gvec_umin)
+TRANS(xvmin_hu, gvec_xxx, MO_16, tcg_gen_gvec_umin)
+TRANS(xvmin_wu, gvec_xxx, MO_32, tcg_gen_gvec_umin)
+TRANS(xvmin_du, gvec_xxx, MO_64, tcg_gen_gvec_umin)
+
+stat
[PATCH v1 38/46] target/loongarch: Implement xvseq xvsle xvslt
This patch includes:
- XVSEQ[I].{B/H/W/D};
- XVSLE[I].{B/H/W/D}[U];
- XVSLT[I].{B/H/W/D/}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 43 ++
target/loongarch/helper.h| 23 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 154 +++
target/loongarch/insns.decode| 43 ++
target/loongarch/lasx_helper.c | 34
target/loongarch/lsx_helper.c| 4 -
target/loongarch/vec.h | 4 +
7 files changed, 301 insertions(+), 4 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 65eccc8598..5d3904402d 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2341,6 +2341,49 @@ INSN_LASX(xvffintl_d_w, xx)
INSN_LASX(xvffinth_d_w, xx)
INSN_LASX(xvffint_s_l, xxx)
+INSN_LASX(xvseq_b, xxx)
+INSN_LASX(xvseq_h, xxx)
+INSN_LASX(xvseq_w, xxx)
+INSN_LASX(xvseq_d, xxx)
+INSN_LASX(xvseqi_b, xx_i)
+INSN_LASX(xvseqi_h, xx_i)
+INSN_LASX(xvseqi_w, xx_i)
+INSN_LASX(xvseqi_d, xx_i)
+
+INSN_LASX(xvsle_b, xxx)
+INSN_LASX(xvsle_h, xxx)
+INSN_LASX(xvsle_w, xxx)
+INSN_LASX(xvsle_d, xxx)
+INSN_LASX(xvslei_b, xx_i)
+INSN_LASX(xvslei_h, xx_i)
+INSN_LASX(xvslei_w, xx_i)
+INSN_LASX(xvslei_d, xx_i)
+INSN_LASX(xvsle_bu, xxx)
+INSN_LASX(xvsle_hu, xxx)
+INSN_LASX(xvsle_wu, xxx)
+INSN_LASX(xvsle_du, xxx)
+INSN_LASX(xvslei_bu, xx_i)
+INSN_LASX(xvslei_hu, xx_i)
+INSN_LASX(xvslei_wu, xx_i)
+INSN_LASX(xvslei_du, xx_i)
+
+INSN_LASX(xvslt_b, xxx)
+INSN_LASX(xvslt_h, xxx)
+INSN_LASX(xvslt_w, xxx)
+INSN_LASX(xvslt_d, xxx)
+INSN_LASX(xvslti_b, xx_i)
+INSN_LASX(xvslti_h, xx_i)
+INSN_LASX(xvslti_w, xx_i)
+INSN_LASX(xvslti_d, xx_i)
+INSN_LASX(xvslt_bu, xxx)
+INSN_LASX(xvslt_hu, xxx)
+INSN_LASX(xvslt_wu, xxx)
+INSN_LASX(xvslt_du, xxx)
+INSN_LASX(xvslti_bu, xx_i)
+INSN_LASX(xvslti_hu, xx_i)
+INSN_LASX(xvslti_wu, xx_i)
+INSN_LASX(xvslti_du, xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index d30ea7f6a4..fbfd15d711 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1193,3 +1193,26 @@ DEF_HELPER_3(xvffint_d_lu, void, env, i32, i32)
DEF_HELPER_3(xvffintl_d_w, void, env, i32, i32)
DEF_HELPER_3(xvffinth_d_w, void, env, i32, i32)
DEF_HELPER_4(xvffint_s_l, void, env, i32, i32, i32)
+
+DEF_HELPER_FLAGS_4(xvseqi_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvseqi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvseqi_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvseqi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
+DEF_HELPER_FLAGS_4(xvslei_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslei_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslei_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslei_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslei_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslei_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslei_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslei_du, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
+DEF_HELPER_FLAGS_4(xvslti_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslti_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslti_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslti_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslti_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslti_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslti_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvslti_du, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 998c07b358..cc1b4fd42a 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2520,6 +2520,160 @@ TRANS(xvffintl_d_w, gen_xx, gen_helper_xvffintl_d_w)
TRANS(xvffinth_d_w, gen_xx, gen_helper_xvffinth_d_w)
TRANS(xvffint_s_l, gen_xxx, gen_helper_xvffint_s_l)
+static bool do_xcmp(DisasContext *ctx, arg_xxx * a, MemOp mop, TCGCond cond)
+{
+uint32_t xd_ofs, xj_ofs, xk_ofs;
+
+CHECK_ASXE;
+
+xd_ofs = vec_full_offset(a->xd);
+xj_ofs = vec_full_offset(a->xj);
+xk_ofs = vec_full_offset(a->xk);
+
+tcg_gen_gvec_cmp(cond, mop, xd_ofs, xj_
[PATCH v1 24/46] target/loongarch: Implement LASX logic instructions
This patch includes:
- XV{AND/OR/XOR/NOR/ANDN/ORN}.V;
- XV{AND/OR/XOR/NOR}I.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 12 ++
target/loongarch/helper.h| 2 +
target/loongarch/insn_trans/trans_lasx.c.inc | 42
target/loongarch/insns.decode| 13 ++
target/loongarch/lasx_helper.c | 11 +
5 files changed, 80 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 82a9826eb7..2f1da9db80 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2028,6 +2028,18 @@ INSN_LASX(xvmsknz_b, xx)
INSN_LASX(xvldi, x_i)
+INSN_LASX(xvand_v, xxx)
+INSN_LASX(xvor_v,xxx)
+INSN_LASX(xvxor_v, xxx)
+INSN_LASX(xvnor_v, xxx)
+INSN_LASX(xvandn_v, xxx)
+INSN_LASX(xvorn_v, xxx)
+
+INSN_LASX(xvandi_b, xx_i)
+INSN_LASX(xvori_b, xx_i)
+INSN_LASX(xvxori_b, xx_i)
+INSN_LASX(xvnori_b, xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index b7ba78ee06..4e0a900318 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -929,3 +929,5 @@ DEF_HELPER_3(xvmskltz_w, void, env, i32, i32)
DEF_HELPER_3(xvmskltz_d, void, env, i32, i32)
DEF_HELPER_3(xvmskgez_b, void, env, i32, i32)
DEF_HELPER_3(xvmsknz_b, void, env, i32, i32)
+
+DEF_HELPER_FLAGS_4(xvnori_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index bf277e1fd9..d48f76f118 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -1935,6 +1935,48 @@ static bool trans_xvldi(DisasContext *ctx, arg_xvldi * a)
return true;
}
+TRANS(xvand_v, gvec_xxx, MO_64, tcg_gen_gvec_and)
+TRANS(xvor_v, gvec_xxx, MO_64, tcg_gen_gvec_or)
+TRANS(xvxor_v, gvec_xxx, MO_64, tcg_gen_gvec_xor)
+TRANS(xvnor_v, gvec_xxx, MO_64, tcg_gen_gvec_nor)
+
+static bool trans_xvandn_v(DisasContext *ctx, arg_xxx * a)
+{
+uint32_t xd_ofs, xj_ofs, xk_ofs;
+
+CHECK_ASXE;
+
+xd_ofs = vec_full_offset(a->xd);
+xj_ofs = vec_full_offset(a->xj);
+xk_ofs = vec_full_offset(a->xk);
+
+tcg_gen_gvec_andc(MO_64, xd_ofs, xk_ofs, xj_ofs, 32, ctx->vl / 8);
+return true;
+}
+TRANS(xvorn_v, gvec_xxx, MO_64, tcg_gen_gvec_orc)
+TRANS(xvandi_b, gvec_xx_i, MO_8, tcg_gen_gvec_andi)
+TRANS(xvori_b, gvec_xx_i, MO_8, tcg_gen_gvec_ori)
+TRANS(xvxori_b, gvec_xx_i, MO_8, tcg_gen_gvec_xori)
+
+static void do_xvnori_b(unsigned vece, uint32_t xd_ofs, uint32_t xj_ofs,
+int64_t imm, uint32_t oprsz, uint32_t maxsz)
+{
+static const TCGOpcode vecop_list[] = {
+INDEX_op_nor_vec, 0
+};
+static const GVecGen2i op = {
+ .fni8 = gen_vnori_b,
+ .fniv = gen_vnori,
+ .fnoi = gen_helper_xvnori_b,
+ .opt_opc = vecop_list,
+ .vece = MO_8
+};
+
+tcg_gen_gvec_2i(xd_ofs, xj_ofs, oprsz, maxsz, imm, &op);
+}
+
+TRANS(xvnori_b, gvec_xx_i, MO_8, do_xvnori_b)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index fbd0dd229a..ce2ad47b88 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1320,6 +1320,7 @@ vstelm_b 0011 000110 . .
@vr_i8i4
@xx_ui4 . . imm:4 xj:5 xd:5&xx_i
@xx_ui5 . imm:5 xj:5 xd:5&xx_i
@xx_ui6 imm:6 xj:5 xd:5&xx_i
+@xx_ui8 .. imm:8 xj:5 xd:5&xx_i
xvadd_b 0111 0100 10100 . . .@xxx
xvadd_h 0111 0100 10101 . . .@xxx
@@ -1628,6 +1629,18 @@ xvmsknz_b0111 01101001 11000 11000 . .
@xx
xvldi0111 0110 00 . . @x_i13
+xvand_v 0111 01010010 01100 . . .@xxx
+xvor_v 0111 01010010 01101 . . .@xxx
+xvxor_v 0111 01010010 01110 . . .@xxx
+xvnor_v 0111 01010010 0 . . .@xxx
+xvandn_v 0111 01010010 1 . . .@xxx
+xvorn_v 0111 01010010 10001 . . .@xxx
+
+xvandi_b 0111 0101 00 . .@xx_ui8
+xvori_b 0111 0101 01 . .@xx_ui8
+xvxori_b 0111 0101 10 . .@xx_ui8
+xvnori_b 0111 0101 11 . .@xx_ui8
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010
Re: [PATCH 1/9] MAINTAINERS: Add reviewers for PowerNV baremetal emulation
On Tue Jun 20, 2023 at 3:59 PM AEST, Cédric Le Goater wrote: > Fred and Nick have been hacking baremetal POWER systems (OPAL) for > many years. They use and modify the QEMU models regularly. Add them as > PowerNV reviewers. > Reviewed-by: Nicholas Piggin > Cc: Frédéric Barrat > Cc: Nicholas Piggin > Signed-off-by: Cédric Le Goater > --- > MAINTAINERS | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 88b5a7ee0a79..e6f3dade2230 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1448,6 +1448,8 @@ F: tests/avocado/ppc_pseries.py > > PowerNV (Non-Virtualized) > M: Cédric Le Goater > +R: Frédéric Barrat > +R: Nicholas Piggin > L: qemu-...@nongnu.org > S: Odd Fixes > F: docs/system/ppc/powernv.rst > -- > 2.41.0
[PATCH v1 26/46] target/loongarch: Implement xvsllwil xvextl
This patch includes:
- XVSLLWIL.{H.B/W.H/D.W};
- XVSLLWIL.{HU.BU/WU.HU/DU.WU};
- XVEXTL.Q.D, VEXTL.QU.DU.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9
target/loongarch/helper.h| 9
target/loongarch/insn_trans/trans_lasx.c.inc | 21 +
target/loongarch/insns.decode| 9
target/loongarch/lasx_helper.c | 45
5 files changed, 93 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 0c1c7a7e6e..b6940e6389 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2076,6 +2076,15 @@ INSN_LASX(xvrotri_h, xx_i)
INSN_LASX(xvrotri_w, xx_i)
INSN_LASX(xvrotri_d, xx_i)
+INSN_LASX(xvsllwil_h_b, xx_i)
+INSN_LASX(xvsllwil_w_h, xx_i)
+INSN_LASX(xvsllwil_d_w, xx_i)
+INSN_LASX(xvextl_q_d,xx)
+INSN_LASX(xvsllwil_hu_bu,xx_i)
+INSN_LASX(xvsllwil_wu_hu,xx_i)
+INSN_LASX(xvsllwil_du_wu,xx_i)
+INSN_LASX(xvextl_qu_du, xx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 4e0a900318..672a5f8988 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -931,3 +931,12 @@ DEF_HELPER_3(xvmskgez_b, void, env, i32, i32)
DEF_HELPER_3(xvmsknz_b, void, env, i32, i32)
DEF_HELPER_FLAGS_4(xvnori_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
+DEF_HELPER_4(xvsllwil_h_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsllwil_w_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsllwil_d_w, void, env, i32, i32, i32)
+DEF_HELPER_3(xvextl_q_d, void, env, i32, i32)
+DEF_HELPER_4(xvsllwil_hu_bu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsllwil_wu_hu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsllwil_du_wu, void, env, i32, i32, i32)
+DEF_HELPER_3(xvextl_qu_du, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 5d7deb312e..53631cea63 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -39,6 +39,18 @@ static bool gen_xx(DisasContext *ctx, arg_xx *a,
return true;
}
+static bool gen_xx_i(DisasContext *ctx, arg_xx_i *a,
+ void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32))
+{
+TCGv_i32 xd = tcg_constant_i32(a->xd);
+TCGv_i32 xj = tcg_constant_i32(a->xj);
+TCGv_i32 imm = tcg_constant_i32(a->imm);
+
+CHECK_SXE;
+func(cpu_env, xd, xj, imm);
+return true;
+}
+
static bool gvec_xxx(DisasContext *ctx, arg_xxx *a, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t))
@@ -2013,6 +2025,15 @@ TRANS(xvrotri_h, gvec_xx_i, MO_16, tcg_gen_gvec_rotri)
TRANS(xvrotri_w, gvec_xx_i, MO_32, tcg_gen_gvec_rotri)
TRANS(xvrotri_d, gvec_xx_i, MO_64, tcg_gen_gvec_rotri)
+TRANS(xvsllwil_h_b, gen_xx_i, gen_helper_xvsllwil_h_b)
+TRANS(xvsllwil_w_h, gen_xx_i, gen_helper_xvsllwil_w_h)
+TRANS(xvsllwil_d_w, gen_xx_i, gen_helper_xvsllwil_d_w)
+TRANS(xvextl_q_d, gen_xx, gen_helper_xvextl_q_d)
+TRANS(xvsllwil_hu_bu, gen_xx_i, gen_helper_xvsllwil_hu_bu)
+TRANS(xvsllwil_wu_hu, gen_xx_i, gen_helper_xvsllwil_wu_hu)
+TRANS(xvsllwil_du_wu, gen_xx_i, gen_helper_xvsllwil_du_wu)
+TRANS(xvextl_qu_du, gen_xx, gen_helper_xvextl_qu_du)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 03c3aa0019..ebaddb94ea 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1674,6 +1674,15 @@ xvrotri_h0111 01101010 0 1 . .
@xx_ui4
xvrotri_w0111 01101010 1 . . .@xx_ui5
xvrotri_d0111 01101010 0001 .. . .@xx_ui6
+xvsllwil_h_b 0111 0111 1 01 ... . . @xx_ui3
+xvsllwil_w_h 0111 0111 1 1 . . @xx_ui4
+xvsllwil_d_w 0111 0111 10001 . . .@xx_ui5
+xvextl_q_d 0111 0111 10010 0 . .@xx
+xvsllwil_hu_bu 0111 0111 11000 01 ... . . @xx_ui3
+xvsllwil_wu_hu 0111 0111 11000 1 . . @xx_ui4
+xvsllwil_du_wu 0111 0111 11001 . . .@xx_ui5
+xvextl_qu_du 0111 0111 11010 0 . .@xx
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010 . .@xr
diff --git a/target/loongarch/lasx_helper.c b/target/loongarch/lasx_helper.c
index 8e8860c1bb..cd0e18ac3c 100644
--- a/target/loongarch/lasx_helper.c
+++ b/target/loongarch/lasx_helper.c
@@ -815,3 +815,48 @@ void HELPER(xvnori_b)(void *xd, void *xj, uint64_t imm,
uint32_t v)
Xd->XB(i) = ~(X
[PATCH v1 43/46] target/loongarch: Implement xvpack xvpick xvilv{l/h}
This patch includes:
- XVPACK{EV/OD}.{B/H/W/D};
- XVPICK{EV/OD}.{B/H/W/D};
- XVILV{L/H}.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 27
target/loongarch/helper.h| 27
target/loongarch/insn_trans/trans_lasx.c.inc | 27
target/loongarch/insns.decode| 27
target/loongarch/lasx_helper.c | 144 +++
5 files changed, 252 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 3b89a5df87..4b815c86b8 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2547,3 +2547,30 @@ INSN_LASX(xvpickve_d,xx_i)
INSN_LASX(xvbsll_v, xx_i)
INSN_LASX(xvbsrl_v, xx_i)
+
+INSN_LASX(xvpackev_b,xxx)
+INSN_LASX(xvpackev_h,xxx)
+INSN_LASX(xvpackev_w,xxx)
+INSN_LASX(xvpackev_d,xxx)
+INSN_LASX(xvpackod_b,xxx)
+INSN_LASX(xvpackod_h,xxx)
+INSN_LASX(xvpackod_w,xxx)
+INSN_LASX(xvpackod_d,xxx)
+
+INSN_LASX(xvpickev_b,xxx)
+INSN_LASX(xvpickev_h,xxx)
+INSN_LASX(xvpickev_w,xxx)
+INSN_LASX(xvpickev_d,xxx)
+INSN_LASX(xvpickod_b,xxx)
+INSN_LASX(xvpickod_h,xxx)
+INSN_LASX(xvpickod_w,xxx)
+INSN_LASX(xvpickod_d,xxx)
+
+INSN_LASX(xvilvl_b, xxx)
+INSN_LASX(xvilvl_h, xxx)
+INSN_LASX(xvilvl_w, xxx)
+INSN_LASX(xvilvl_d, xxx)
+INSN_LASX(xvilvh_b, xxx)
+INSN_LASX(xvilvh_h, xxx)
+INSN_LASX(xvilvh_w, xxx)
+INSN_LASX(xvilvh_d, xxx)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 6c4525a413..dc5ab59f8e 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1237,3 +1237,30 @@ DEF_HELPER_4(xvinsve0_w, void, env, i32, i32, i32)
DEF_HELPER_4(xvinsve0_d, void, env, i32, i32, i32)
DEF_HELPER_4(xvpickve_w, void, env, i32, i32, i32)
DEF_HELPER_4(xvpickve_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvpackev_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpackev_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpackev_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpackev_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpackod_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpackod_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpackod_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpackod_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvpickev_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpickev_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpickev_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpickev_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpickod_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpickod_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpickod_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpickod_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvilvl_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvilvl_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvilvl_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvilvl_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvilvh_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvilvh_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvilvh_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvilvh_d, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index e63b1c67c9..75ac0ae1f1 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -3056,3 +3056,30 @@ static bool trans_xvbsrl_v(DisasContext *ctx, arg_xx_i
*a)
return true;
}
+
+TRANS(xvpackev_b, gen_xxx, gen_helper_xvpackev_b)
+TRANS(xvpackev_h, gen_xxx, gen_helper_xvpackev_h)
+TRANS(xvpackev_w, gen_xxx, gen_helper_xvpackev_w)
+TRANS(xvpackev_d, gen_xxx, gen_helper_xvpackev_d)
+TRANS(xvpackod_b, gen_xxx, gen_helper_xvpackod_b)
+TRANS(xvpackod_h, gen_xxx, gen_helper_xvpackod_h)
+TRANS(xvpackod_w, gen_xxx, gen_helper_xvpackod_w)
+TRANS(xvpackod_d, gen_xxx, gen_helper_xvpackod_d)
+
+TRANS(xvpickev_b, gen_xxx, gen_helper_xvpickev_b)
+TRANS(xvpickev_h, gen_xxx, gen_helper_xvpickev_h)
+TRANS(xvpickev_w, gen_xxx, gen_helper_xvpickev_w)
+TRANS(xvpickev_d, gen_xxx, gen_helper_xvpickev_d)
+TRANS(xvpickod_b, gen_xxx, gen_helper_xvpickod_b)
+TRANS(xvpickod_h, gen_xxx, gen_helper_xvpickod_h)
+TRANS(xvpickod_w, gen_xxx, gen_helper_xvpickod_w)
+TRANS(xvpickod_d, gen_xxx, gen_helper_xvpickod_d)
+
+TRANS(xvilvl_b, gen_xxx, gen_helper_xvilvl_b)
+TRANS(xvilvl_h, gen_xxx, gen_helper_xvilvl_h)
+TRANS(xvilvl_w, gen_xxx, gen_helper_xvilvl_w)
+TRANS(xvilvl_d, gen_xxx, gen_helper_xvilvl_d)
+TRANS(xvilvh_b, gen_xxx, gen_helper_xvilvh_b)
+TRANS(xvilvh_h, gen_xxx, gen_helper_xvilvh_h)
+TRANS(xvilvh_w, gen_xxx, gen_helper_xvilvh_w)
+TRANS(xvilvh_d, gen_xxx, gen_helper_xvilvh_d)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 697087e6ef..5c3a18fbe2 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -2051,3 +2051,30 @@ xvp
[PATCH v1 42/46] target/loongarch: Implement xvreplve xvinsve0 xvpickve xvb{sll/srl}v
This patch includes:
- XVREPLVE.{B/H/W/D};
- XVREPL128VEI.{B/H/W/D};
- XVREPLVE0.{B/H/W/D/Q};
- XVINSVE0.{W/D};
- XVPICKVE.{W/D};
- XVBSLL.V, XVBSRL.V.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 29 +++
target/loongarch/helper.h| 5 +
target/loongarch/insn_trans/trans_lasx.c.inc | 205 +++
target/loongarch/insns.decode| 29 +++
target/loongarch/lasx_helper.c | 29 +++
5 files changed, 297 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index fd7d459921..3b89a5df87 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1748,6 +1748,11 @@ static void output_rx_i(DisasContext *ctx, arg_rx_i *a,
const char *mnemonic)
output(ctx, mnemonic, "r%d, x%d, 0x%x", a->rd, a->xj, a->imm);
}
+static void output_xxr(DisasContext *ctx, arg_xxr *a, const char *mnemonic)
+{
+output(ctx, mnemonic, "x%d, x%d, r%d", a->xd, a->xj, a->rk);
+}
+
INSN_LASX(xvadd_b, xxx)
INSN_LASX(xvadd_h, xxx)
INSN_LASX(xvadd_w, xxx)
@@ -2518,3 +2523,27 @@ INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
INSN_LASX(xvreplgr2vr_d, xr)
+
+INSN_LASX(xvreplve_b,xxr)
+INSN_LASX(xvreplve_h,xxr)
+INSN_LASX(xvreplve_w,xxr)
+INSN_LASX(xvreplve_d,xxr)
+INSN_LASX(xvrepl128vei_b,xx_i)
+INSN_LASX(xvrepl128vei_h,xx_i)
+INSN_LASX(xvrepl128vei_w,xx_i)
+INSN_LASX(xvrepl128vei_d,xx_i)
+
+INSN_LASX(xvreplve0_b, xx)
+INSN_LASX(xvreplve0_h, xx)
+INSN_LASX(xvreplve0_w, xx)
+INSN_LASX(xvreplve0_d, xx)
+INSN_LASX(xvreplve0_q, xx)
+
+INSN_LASX(xvinsve0_w,xx_i)
+INSN_LASX(xvinsve0_d,xx_i)
+
+INSN_LASX(xvpickve_w,xx_i)
+INSN_LASX(xvpickve_d,xx_i)
+
+INSN_LASX(xvbsll_v, xx_i)
+INSN_LASX(xvbsrl_v, xx_i)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index f6d64bfde5..6c4525a413 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1232,3 +1232,8 @@ DEF_HELPER_3(xvsetallnez_b, void, env, i32, i32)
DEF_HELPER_3(xvsetallnez_h, void, env, i32, i32)
DEF_HELPER_3(xvsetallnez_w, void, env, i32, i32)
DEF_HELPER_3(xvsetallnez_d, void, env, i32, i32)
+
+DEF_HELPER_4(xvinsve0_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvinsve0_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpickve_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvpickve_d, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 0fc26023d1..e63b1c67c9 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2851,3 +2851,208 @@ TRANS(xvreplgr2vr_b, gvec_dupx, MO_8)
TRANS(xvreplgr2vr_h, gvec_dupx, MO_16)
TRANS(xvreplgr2vr_w, gvec_dupx, MO_32)
TRANS(xvreplgr2vr_d, gvec_dupx, MO_64)
+
+static bool gen_xvreplve(DisasContext *ctx, arg_xxr *a, int vece, int bit,
+ void (*func)(TCGv_i64, TCGv_ptr, tcg_target_long))
+{
+TCGv_i64 t0 = tcg_temp_new_i64();
+TCGv_ptr t1 = tcg_temp_new_ptr();
+TCGv_i64 t2 = tcg_temp_new_i64();
+
+CHECK_ASXE;
+
+tcg_gen_andi_i64(t0, gpr_src(ctx, a->rk, EXT_NONE), (LSX_LEN / bit) - 1);
+tcg_gen_shli_i64(t0, t0, vece);
+if (HOST_BIG_ENDIAN) {
+tcg_gen_xori_i64(t0, t0, vece << ((LSX_LEN / bit) - 1));
+}
+
+tcg_gen_trunc_i64_ptr(t1, t0);
+tcg_gen_add_ptr(t1, t1, cpu_env);
+func(t2, t1, vec_full_offset(a->xj));
+tcg_gen_gvec_dup_i64(vece, vec_full_offset(a->xd), 16, 16, t2);
+func(t2, t1, offsetof(CPULoongArchState, fpr[a->xj].xreg.XQ(1)));
+tcg_gen_gvec_dup_i64(vece,
+ offsetof(CPULoongArchState, fpr[a->xd].xreg.XQ(1)),
+ 16, 16, t2);
+return true;
+}
+
+TRANS(xvreplve_b, gen_xvreplve, MO_8, 8, tcg_gen_ld8u_i64)
+TRANS(xvreplve_h, gen_xvreplve, MO_16, 16, tcg_gen_ld16u_i64)
+TRANS(xvreplve_w, gen_xvreplve, MO_32, 32, tcg_gen_ld32u_i64)
+TRANS(xvreplve_d, gen_xvreplve, MO_64, 64, tcg_gen_ld_i64)
+
+static bool trans_xvrepl128vei_b(DisasContext *ctx, arg_xx_i * a)
+{
+CHECK_ASXE;
+
+tcg_gen_gvec_dup_mem(MO_8,
+ offsetof(CPULoongArchState, fpr[a->xd].xreg.XB(0)),
+ offsetof(CPULoongArchState,
+ fpr[a->xj].xreg.XB((a->imm))),
+ 16, 16);
+tcg_gen_gvec_dup_mem(MO_8,
+ offsetof(CPULoongArchState, fpr[a->xd].xreg.XB(16)),
+ offsetof(CPULoongArchState,
+ fpr[a->xj].xreg.XB((a->imm + 16))),
+ 16, 16);
+return true;
+}
+
+static bool trans_xvrepl128vei_h(DisasContext *ctx, arg_xx_i *a)
+{
+CHECK_ASXE;
+
+tcg_gen_gvec_dup_mem(MO_16,
+ offsetof(CPULoongArchState, fpr[a->xd].x
[PATCH v1 20/46] target/loongarch: Implement vext2xv
This patch includes:
- VEXT2XV.{H/W/D}.B, VEXT2XV.{HU/WU/DU}.BU;
- VEXT2XV.{W/D}.B, VEXT2XV.{WU/DU}.HU;
- VEXT2XV.D.W, VEXT2XV.DU.WU.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 13 ++
target/loongarch/helper.h| 13 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 13 ++
target/loongarch/insns.decode| 13 ++
target/loongarch/lasx_helper.c | 27
5 files changed, 79 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 5ac374bc63..1897aa7ba1 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1996,6 +1996,19 @@ INSN_LASX(xvexth_wu_hu, xx)
INSN_LASX(xvexth_du_wu, xx)
INSN_LASX(xvexth_qu_du, xx)
+INSN_LASX(vext2xv_h_b, xx)
+INSN_LASX(vext2xv_w_b, xx)
+INSN_LASX(vext2xv_d_b, xx)
+INSN_LASX(vext2xv_w_h, xx)
+INSN_LASX(vext2xv_d_h, xx)
+INSN_LASX(vext2xv_d_w, xx)
+INSN_LASX(vext2xv_hu_bu, xx)
+INSN_LASX(vext2xv_wu_bu, xx)
+INSN_LASX(vext2xv_du_bu, xx)
+INSN_LASX(vext2xv_wu_hu, xx)
+INSN_LASX(vext2xv_du_hu, xx)
+INSN_LASX(vext2xv_du_wu, xx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 17e54eb29a..7a303ee3f1 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -904,3 +904,16 @@ DEF_HELPER_3(xvexth_hu_bu, void, env, i32, i32)
DEF_HELPER_3(xvexth_wu_hu, void, env, i32, i32)
DEF_HELPER_3(xvexth_du_wu, void, env, i32, i32)
DEF_HELPER_3(xvexth_qu_du, void, env, i32, i32)
+
+DEF_HELPER_3(vext2xv_h_b, void, env, i32, i32)
+DEF_HELPER_3(vext2xv_w_b, void, env, i32, i32)
+DEF_HELPER_3(vext2xv_d_b, void, env, i32, i32)
+DEF_HELPER_3(vext2xv_w_h, void, env, i32, i32)
+DEF_HELPER_3(vext2xv_d_h, void, env, i32, i32)
+DEF_HELPER_3(vext2xv_d_w, void, env, i32, i32)
+DEF_HELPER_3(vext2xv_hu_bu, void, env, i32, i32)
+DEF_HELPER_3(vext2xv_wu_bu, void, env, i32, i32)
+DEF_HELPER_3(vext2xv_du_bu, void, env, i32, i32)
+DEF_HELPER_3(vext2xv_wu_hu, void, env, i32, i32)
+DEF_HELPER_3(vext2xv_du_hu, void, env, i32, i32)
+DEF_HELPER_3(vext2xv_du_wu, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 5110cf9a33..c04469af75 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -1853,6 +1853,19 @@ TRANS(xvexth_wu_hu, gen_xx, gen_helper_xvexth_wu_hu)
TRANS(xvexth_du_wu, gen_xx, gen_helper_xvexth_du_wu)
TRANS(xvexth_qu_du, gen_xx, gen_helper_xvexth_qu_du)
+TRANS(vext2xv_h_b, gen_xx, gen_helper_vext2xv_h_b)
+TRANS(vext2xv_w_b, gen_xx, gen_helper_vext2xv_w_b)
+TRANS(vext2xv_d_b, gen_xx, gen_helper_vext2xv_d_b)
+TRANS(vext2xv_w_h, gen_xx, gen_helper_vext2xv_w_h)
+TRANS(vext2xv_d_h, gen_xx, gen_helper_vext2xv_d_h)
+TRANS(vext2xv_d_w, gen_xx, gen_helper_vext2xv_d_w)
+TRANS(vext2xv_hu_bu, gen_xx, gen_helper_vext2xv_hu_bu)
+TRANS(vext2xv_wu_bu, gen_xx, gen_helper_vext2xv_wu_bu)
+TRANS(vext2xv_du_bu, gen_xx, gen_helper_vext2xv_du_bu)
+TRANS(vext2xv_wu_hu, gen_xx, gen_helper_vext2xv_wu_hu)
+TRANS(vext2xv_du_hu, gen_xx, gen_helper_vext2xv_du_hu)
+TRANS(vext2xv_du_wu, gen_xx, gen_helper_vext2xv_du_wu)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 98de616846..9f1cb04368 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1600,6 +1600,19 @@ xvexth_wu_hu 0111 01101001 11101 11101 . .
@xx
xvexth_du_wu 0111 01101001 11101 0 . .@xx
xvexth_qu_du 0111 01101001 11101 1 . .@xx
+vext2xv_h_b 0111 01101001 0 00100 . .@xx
+vext2xv_w_b 0111 01101001 0 00101 . .@xx
+vext2xv_d_b 0111 01101001 0 00110 . .@xx
+vext2xv_w_h 0111 01101001 0 00111 . .@xx
+vext2xv_d_h 0111 01101001 0 01000 . .@xx
+vext2xv_d_w 0111 01101001 0 01001 . .@xx
+vext2xv_hu_bu0111 01101001 0 01010 . .@xx
+vext2xv_wu_bu0111 01101001 0 01011 . .@xx
+vext2xv_du_bu0111 01101001 0 01100 . .@xx
+vext2xv_wu_hu0111 01101001 0 01101 . .@xx
+vext2xv_du_hu0111 01101001 0 01110 . .@xx
+vext2xv_du_wu0111 01101001 0 0 . .@xx
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010 . .@xr
diff --git a/target/loongarch/lasx_helper.c b/target/loongarch/lasx_helper.c
index ca74263c6e..ca82d03ff4 100644
--- a/target/loongarch/lasx_helper.c
+++ b/target/loon
[PATCH v1 16/46] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}
This patch includes:
- XVMADD.{B/H/W/D};
- XVMSUB.{B/H/W/D};
- XVMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 34 ++
target/loongarch/helper.h| 30 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 367 +++
target/loongarch/insns.decode| 34 ++
target/loongarch/lasx_helper.c | 104 ++
target/loongarch/vec.h | 3 +
6 files changed, 572 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index e7c46bc3a2..ddfc4921b9 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1927,6 +1927,40 @@ INSN_LASX(xvmulwod_w_hu_h, xxx)
INSN_LASX(xvmulwod_d_wu_w, xxx)
INSN_LASX(xvmulwod_q_du_d, xxx)
+INSN_LASX(xvmadd_b, xxx)
+INSN_LASX(xvmadd_h, xxx)
+INSN_LASX(xvmadd_w, xxx)
+INSN_LASX(xvmadd_d, xxx)
+INSN_LASX(xvmsub_b, xxx)
+INSN_LASX(xvmsub_h, xxx)
+INSN_LASX(xvmsub_w, xxx)
+INSN_LASX(xvmsub_d, xxx)
+
+INSN_LASX(xvmaddwev_h_b, xxx)
+INSN_LASX(xvmaddwev_w_h, xxx)
+INSN_LASX(xvmaddwev_d_w, xxx)
+INSN_LASX(xvmaddwev_q_d, xxx)
+INSN_LASX(xvmaddwod_h_b, xxx)
+INSN_LASX(xvmaddwod_w_h, xxx)
+INSN_LASX(xvmaddwod_d_w, xxx)
+INSN_LASX(xvmaddwod_q_d, xxx)
+INSN_LASX(xvmaddwev_h_bu,xxx)
+INSN_LASX(xvmaddwev_w_hu,xxx)
+INSN_LASX(xvmaddwev_d_wu,xxx)
+INSN_LASX(xvmaddwev_q_du,xxx)
+INSN_LASX(xvmaddwod_h_bu,xxx)
+INSN_LASX(xvmaddwod_w_hu,xxx)
+INSN_LASX(xvmaddwod_d_wu,xxx)
+INSN_LASX(xvmaddwod_q_du,xxx)
+INSN_LASX(xvmaddwev_h_bu_b, xxx)
+INSN_LASX(xvmaddwev_w_hu_h, xxx)
+INSN_LASX(xvmaddwev_d_wu_w, xxx)
+INSN_LASX(xvmaddwev_q_du_d, xxx)
+INSN_LASX(xvmaddwod_h_bu_b, xxx)
+INSN_LASX(xvmaddwod_w_hu_h, xxx)
+INSN_LASX(xvmaddwod_d_wu_w, xxx)
+INSN_LASX(xvmaddwod_q_du_d, xxx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 88ae707027..0dc4cc18da 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -839,3 +839,33 @@ DEF_HELPER_FLAGS_4(xvmulwev_d_wu_w, TCG_CALL_NO_RWG, void,
ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvmulwod_h_bu_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvmulwod_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvmulwod_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvmadd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmadd_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmsub_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmsub_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvmaddwev_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwev_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwev_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwod_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwod_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwod_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvmaddwev_h_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwev_w_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwev_d_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwod_h_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwod_w_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwod_d_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvmaddwev_h_bu_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwev_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwev_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwod_h_bu_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwod_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvmaddwod_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index d57d867f17..78ba31b8c2 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -1363,6 +1363,373 @@ TRANS(xvmulwod_h_bu_b, gvec_xxx, MO_8, do_xvmulwod_u_s)
TRANS(xvmulwod_w_hu_h, gvec_xxx, MO_16, do_xvmulwod_u_s)
TRANS
[PATCH v1 13/46] target/loongarch: Implement xvadda
This patch includes:
- XVADDA.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 +++
target/loongarch/helper.h| 5 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 41
target/loongarch/insns.decode| 5 +++
target/loongarch/lasx_helper.c | 17
target/loongarch/lsx_helper.c| 2 -
target/loongarch/vec.h | 2 +
7 files changed, 75 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index d6b6b8ddd6..cc92f0e763 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1851,6 +1851,11 @@ INSN_LASX(xvabsd_hu, xxx)
INSN_LASX(xvabsd_wu, xxx)
INSN_LASX(xvabsd_du, xxx)
+INSN_LASX(xvadda_b, xxx)
+INSN_LASX(xvadda_h, xxx)
+INSN_LASX(xvadda_w, xxx)
+INSN_LASX(xvadda_d, xxx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 3ec7717c88..67ef7491c4 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -786,3 +786,8 @@ DEF_HELPER_FLAGS_4(xvabsd_bu, TCG_CALL_NO_RWG, void, ptr,
ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvabsd_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvabsd_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvabsd_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvadda_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvadda_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvadda_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvadda_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 8f7ff2cba6..4b2e50de68 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -831,6 +831,47 @@ TRANS(xvabsd_hu, gvec_xxx, MO_16, do_xvabsd_u)
TRANS(xvabsd_wu, gvec_xxx, MO_32, do_xvabsd_u)
TRANS(xvabsd_du, gvec_xxx, MO_64, do_xvabsd_u)
+static void do_xvadda(unsigned vece, uint32_t xd_ofs, uint32_t xj_ofs,
+ uint32_t xk_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+static const TCGOpcode vecop_list[] = {
+INDEX_op_abs_vec, INDEX_op_add_vec, 0
+};
+static const GVecGen3 op[4] = {
+{
+.fniv = gen_vadda,
+.fno = gen_helper_xvadda_b,
+.opt_opc = vecop_list,
+.vece = MO_8
+},
+{
+.fniv = gen_vadda,
+.fno = gen_helper_xvadda_h,
+.opt_opc = vecop_list,
+.vece = MO_16
+},
+{
+.fniv = gen_vadda,
+.fno = gen_helper_xvadda_w,
+.opt_opc = vecop_list,
+.vece = MO_32
+},
+{
+.fniv = gen_vadda,
+.fno = gen_helper_xvadda_d,
+.opt_opc = vecop_list,
+.vece = MO_64
+},
+};
+
+tcg_gen_gvec_3(xd_ofs, xj_ofs, xk_ofs, oprsz, maxsz, &op[vece]);
+}
+
+TRANS(xvadda_b, gvec_xxx, MO_8, do_xvadda)
+TRANS(xvadda_h, gvec_xxx, MO_16, do_xvadda)
+TRANS(xvadda_w, gvec_xxx, MO_32, do_xvadda)
+TRANS(xvadda_d, gvec_xxx, MO_64, do_xvadda)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 8bd029a6e8..f8a17f262a 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1447,6 +1447,11 @@ xvabsd_hu0111 01000110 00101 . . .
@xxx
xvabsd_wu0111 01000110 00110 . . .@xxx
xvabsd_du0111 01000110 00111 . . .@xxx
+xvadda_b 0111 01000101 11000 . . .@xxx
+xvadda_h 0111 01000101 11001 . . .@xxx
+xvadda_w 0111 01000101 11010 . . .@xxx
+xvadda_d 0111 01000101 11011 . . .@xxx
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010 . .@xr
diff --git a/target/loongarch/lasx_helper.c b/target/loongarch/lasx_helper.c
index e9d38d83bc..52c230a681 100644
--- a/target/loongarch/lasx_helper.c
+++ b/target/loongarch/lasx_helper.c
@@ -346,3 +346,20 @@ XDO_3OP(xvabsd_bu, 8, UXB, DO_VABSD)
XDO_3OP(xvabsd_hu, 16, UXH, DO_VABSD)
XDO_3OP(xvabsd_wu, 32, UXW, DO_VABSD)
XDO_3OP(xvabsd_du, 64, UXD, DO_VABSD)
+
+#define XDO_VADDA(NAME, BIT, E, DO_OP) \
+void HELPER(NAME)(void *xd, void *xj, void *xk, uint32_t v) \
+{ \
+int i;
[PATCH v1 05/46] target/loongarch: Implement xvreplgr2vr
This patch includes:
- XVREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 10 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 16
target/loongarch/insns.decode| 8
3 files changed, 34 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 696f78c491..78e1fd19ac 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1708,6 +1708,11 @@ static void output_xxx(DisasContext *ctx, arg_xxx * a,
const char *mnemonic)
output(ctx, mnemonic, "x%d, x%d, x%d", a->xd, a->xj, a->xk);
}
+static void output_xr(DisasContext *ctx, arg_xr *a, const char *mnemonic)
+{
+output(ctx, mnemonic, "x%d, r%d", a->xd, a->rj);
+}
+
INSN_LASX(xvadd_b, xxx)
INSN_LASX(xvadd_h, xxx)
INSN_LASX(xvadd_w, xxx)
@@ -1718,3 +1723,8 @@ INSN_LASX(xvsub_h, xxx)
INSN_LASX(xvsub_w, xxx)
INSN_LASX(xvsub_d, xxx)
INSN_LASX(xvsub_q, xxx)
+
+INSN_LASX(xvreplgr2vr_b, xr)
+INSN_LASX(xvreplgr2vr_h, xr)
+INSN_LASX(xvreplgr2vr_w, xr)
+INSN_LASX(xvreplgr2vr_d, xr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index c918522f96..d394a4f40a 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -73,3 +73,19 @@ TRANS(xvsub_b, gvec_xxx, MO_8, tcg_gen_gvec_sub)
TRANS(xvsub_h, gvec_xxx, MO_16, tcg_gen_gvec_sub)
TRANS(xvsub_w, gvec_xxx, MO_32, tcg_gen_gvec_sub)
TRANS(xvsub_d, gvec_xxx, MO_64, tcg_gen_gvec_sub)
+
+static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
+{
+TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
+
+CHECK_ASXE;
+
+tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->xd),
+ 32, ctx->vl / 8, src);
+return true;
+}
+
+TRANS(xvreplgr2vr_b, gvec_dupx, MO_8)
+TRANS(xvreplgr2vr_h, gvec_dupx, MO_16)
+TRANS(xvreplgr2vr_w, gvec_dupx, MO_32)
+TRANS(xvreplgr2vr_d, gvec_dupx, MO_64)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index bac1903975..2eab7f6a98 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1302,12 +1302,15 @@ vstelm_b 0011 000110 . .
@vr_i8i4
#
&xxx xd xj xk
+&xr xd rj
+
#
# LASX Formats
#
@xxx . xk:5 xj:5 xd:5&xxx
+@xr . . rj:5 xd:5&xr
xvadd_b 0111 0100 10100 . . .@xxx
xvadd_h 0111 0100 10101 . . .@xxx
@@ -1319,3 +1322,8 @@ xvsub_h 0111 0100 11001 . . .
@xxx
xvsub_w 0111 0100 11010 . . .@xxx
xvsub_d 0111 0100 11011 . . .@xxx
xvsub_q 0111 01010010 11011 . . .@xxx
+
+xvreplgr2vr_b0111 01101001 0 0 . .@xr
+xvreplgr2vr_h0111 01101001 0 1 . .@xr
+xvreplgr2vr_w0111 01101001 0 00010 . .@xr
+xvreplgr2vr_d0111 01101001 0 00011 . .@xr
--
2.39.1
[PATCH v1 31/46] target/loongarch: Implement xvssrlrn xvssrarn
This patch includes:
- XVSSRLRN.{B.H/H.W/W.D};
- XVSSRARN.{B.H/H.W/W.D};
- XVSSRLRN.{BU.H/HU.W/WU.D};
- XVSSRARN.{BU.H/HU.W/WU.D};
- XVSSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSSRARNI.{B.H/H.W/W.D/D.Q};
- XVSSRLRNI.{BU.H/HU.W/WU.D/DU.Q};
- XVSSRARNI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 30 ++
target/loongarch/helper.h| 30 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 30 ++
target/loongarch/insns.decode| 30 ++
target/loongarch/lasx_helper.c | 411 +++
5 files changed, 531 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 1f40f3aaca..da07b56dee 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2165,6 +2165,36 @@ INSN_LASX(xvssrani_hu_w, xx_i)
INSN_LASX(xvssrani_wu_d, xx_i)
INSN_LASX(xvssrani_du_q, xx_i)
+INSN_LASX(xvssrlrn_b_h, xxx)
+INSN_LASX(xvssrlrn_h_w, xxx)
+INSN_LASX(xvssrlrn_w_d, xxx)
+INSN_LASX(xvssrarn_b_h, xxx)
+INSN_LASX(xvssrarn_h_w, xxx)
+INSN_LASX(xvssrarn_w_d, xxx)
+INSN_LASX(xvssrlrn_bu_h, xxx)
+INSN_LASX(xvssrlrn_hu_w, xxx)
+INSN_LASX(xvssrlrn_wu_d, xxx)
+INSN_LASX(xvssrarn_bu_h, xxx)
+INSN_LASX(xvssrarn_hu_w, xxx)
+INSN_LASX(xvssrarn_wu_d, xxx)
+
+INSN_LASX(xvssrlrni_b_h, xx_i)
+INSN_LASX(xvssrlrni_h_w, xx_i)
+INSN_LASX(xvssrlrni_w_d, xx_i)
+INSN_LASX(xvssrlrni_d_q, xx_i)
+INSN_LASX(xvssrlrni_bu_h,xx_i)
+INSN_LASX(xvssrlrni_hu_w,xx_i)
+INSN_LASX(xvssrlrni_wu_d,xx_i)
+INSN_LASX(xvssrlrni_du_q,xx_i)
+INSN_LASX(xvssrarni_b_h, xx_i)
+INSN_LASX(xvssrarni_h_w, xx_i)
+INSN_LASX(xvssrarni_w_d, xx_i)
+INSN_LASX(xvssrarni_d_q, xx_i)
+INSN_LASX(xvssrarni_bu_h,xx_i)
+INSN_LASX(xvssrarni_hu_w,xx_i)
+INSN_LASX(xvssrarni_wu_d,xx_i)
+INSN_LASX(xvssrarni_du_q,xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 2d76916049..b5d1cff1f0 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1020,3 +1020,33 @@ DEF_HELPER_4(xvssrani_bu_h, void, env, i32, i32, i32)
DEF_HELPER_4(xvssrani_hu_w, void, env, i32, i32, i32)
DEF_HELPER_4(xvssrani_wu_d, void, env, i32, i32, i32)
DEF_HELPER_4(xvssrani_du_q, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvssrlrn_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlrn_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlrn_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarn_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarn_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarn_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlrn_bu_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlrn_hu_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlrn_wu_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarn_bu_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarn_hu_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarn_wu_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvssrlrni_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlrni_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlrni_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlrni_d_q, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarni_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarni_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarni_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarni_d_q, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlrni_bu_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlrni_hu_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlrni_wu_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrlrni_du_q, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarni_bu_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarni_hu_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarni_wu_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvssrarni_du_q, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index b6c2ced30c..aa145c850b 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2114,6 +2114,36 @@ TRANS(xvssrani_hu_w, gen_xx_i, gen_helper_xvssrani_hu_w)
TRANS(xvssrani_wu_d, gen_xx_i, gen_helper_xvssrani_wu_d)
TRANS(xvssrani_du_q, gen_xx_i, gen_helper_xvssrani_du_q)
+TRANS(xvssrlrn_b_h, gen_xxx, gen_helper_xvssrlrn_b_h)
+TRANS(xvssrlrn_h_w, gen_xxx, gen_helper_xvssrlrn_h_w)
+TRANS(xvssrlrn_w_d, gen_xxx, gen_helper_xvssrlrn_w_d)
+TRANS(xvssrarn_b_h, gen_xxx, gen_helper_xvssrarn_b_h)
+TRANS(xvssrarn_h_w, gen_xxx, gen_helper_xvssrarn_h_w)
+TRANS(xvssrarn_w_d, gen_xxx, gen_helper_xvssrarn_w_d)
+TRANS(xvssrlrn_bu_h, gen_xxx, gen_helper_xvssrlrn_bu_h)
+TRANS(xvssrlrn_hu_w, gen_xxx, gen_helper_xvssrlrn_hu_w)
+TRANS(xvssrlrn_wu_d, gen_xxx, gen_helper_xvssrlrn_wu_d)
+TRANS(xvssrarn_bu_h, gen_xxx, gen_helper_xvssrarn_bu_h)
+TRANS(xvssrarn_hu_w, gen
[PATCH v1 01/46] target/loongarch: Add LASX data type XReg
Signed-off-by: Song Gao
---
linux-user/loongarch64/signal.c | 1 +
target/loongarch/cpu.c | 1 +
target/loongarch/cpu.h | 14 +
target/loongarch/gdbstub.c | 1 +
target/loongarch/internals.h| 22 --
target/loongarch/lsx_helper.c | 1 +
target/loongarch/machine.c | 40 --
target/loongarch/vec.h | 51 +
8 files changed, 106 insertions(+), 25 deletions(-)
create mode 100644 target/loongarch/vec.h
diff --git a/linux-user/loongarch64/signal.c b/linux-user/loongarch64/signal.c
index bb8efb1172..39572c1190 100644
--- a/linux-user/loongarch64/signal.c
+++ b/linux-user/loongarch64/signal.c
@@ -12,6 +12,7 @@
#include "linux-user/trace.h"
#include "target/loongarch/internals.h"
+#include "target/loongarch/vec.h"
/* FP context was used */
#define SC_USED_FP (1 << 0)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ad93ecac92..5037cfc02c 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -18,6 +18,7 @@
#include "cpu-csr.h"
#include "sysemu/reset.h"
#include "tcg/tcg.h"
+#include "vec.h"
const char * const regnames[32] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index b23f38c3d5..347950b4d0 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -259,9 +259,23 @@ typedef union VReg {
Int128 Q[LSX_LEN / 128];
}VReg;
+#define LASX_LEN (256)
+typedef union XReg {
+int8_t XB[LASX_LEN / 8];
+int16_t XH[LASX_LEN / 16];
+int32_t XW[LASX_LEN / 32];
+int64_t XD[LASX_LEN / 64];
+uint8_t UXB[LASX_LEN / 8];
+uint16_t UXH[LASX_LEN / 16];
+uint32_t UXW[LASX_LEN / 32];
+uint64_t UXD[LASX_LEN / 64];
+Int128 XQ[LASX_LEN / 128];
+} XReg;
+
typedef union fpr_t fpr_t;
union fpr_t {
VReg vreg;
+XReg xreg;
};
struct LoongArchTLB {
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
index 0752fff924..94c427f4da 100644
--- a/target/loongarch/gdbstub.c
+++ b/target/loongarch/gdbstub.c
@@ -11,6 +11,7 @@
#include "internals.h"
#include "exec/gdbstub.h"
#include "gdbstub/helpers.h"
+#include "vec.h"
uint64_t read_fcc(CPULoongArchState *env)
{
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 7b0f29c942..c492863cc5 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -21,28 +21,6 @@
/* Global bit for huge page */
#define LOONGARCH_HGLOBAL_SHIFT 12
-#if HOST_BIG_ENDIAN
-#define B(x) B[15 - (x)]
-#define H(x) H[7 - (x)]
-#define W(x) W[3 - (x)]
-#define D(x) D[1 - (x)]
-#define UB(x) UB[15 - (x)]
-#define UH(x) UH[7 - (x)]
-#define UW(x) UW[3 - (x)]
-#define UD(x) UD[1 -(x)]
-#define Q(x) Q[x]
-#else
-#define B(x) B[x]
-#define H(x) H[x]
-#define W(x) W[x]
-#define D(x) D[x]
-#define UB(x) UB[x]
-#define UH(x) UH[x]
-#define UW(x) UW[x]
-#define UD(x) UD[x]
-#define Q(x) Q[x]
-#endif
-
void loongarch_translate_init(void);
void loongarch_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index 9571f0aef0..b231a2798b 100644
--- a/target/loongarch/lsx_helper.c
+++ b/target/loongarch/lsx_helper.c
@@ -12,6 +12,7 @@
#include "fpu/softfloat.h"
#include "internals.h"
#include "tcg/tcg.h"
+#include "vec.h"
#define DO_ADD(a, b) (a + b)
#define DO_SUB(a, b) (a - b)
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
index d8ac99c9a4..3fbf68d7ff 100644
--- a/target/loongarch/machine.c
+++ b/target/loongarch/machine.c
@@ -8,7 +8,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "migration/cpu.h"
-#include "internals.h"
+#include "vec.h"
static const VMStateDescription vmstate_fpu_reg = {
.name = "fpu_reg",
@@ -76,6 +76,39 @@ static const VMStateDescription vmstate_lsx = {
},
};
+static const VMStateDescription vmstate_lasxh_reg = {
+.name = "lasxh_reg",
+.version_id = 1,
+.minimum_version_id = 1,
+.fields = (VMStateField[]) {
+VMSTATE_UINT64(UXD(2), XReg),
+VMSTATE_UINT64(UXD(3), XReg),
+VMSTATE_END_OF_LIST()
+}
+};
+
+#define VMSTATE_LASXH_REGS(_field, _state, _start) \
+VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, 32, 0, \
+ vmstate_lasxh_reg, fpr_t)
+
+static bool lasx_needed(void *opaque)
+{
+LoongArchCPU *cpu = opaque;
+
+return FIELD_EX64(cpu->env.cpucfg[2], CPUCFG2, LASX);
+}
+
+static const VMStateDescription vmstate_lasx = {
+.name = "cpu/lasx",
+.version_id = 1,
+.minimum_version_id = 1,
+.needed = lasx_needed,
+.fields = (VMStateField[]) {
+VMSTATE_LASXH_REGS(env.fpr, LoongArchCPU, 0),
+VMSTATE_END_OF_LIST()
+},
+};
+
/* TLB state */
const VMStateDescription vmstate_tlb = {
.name = "cpu/tlb",
@@ -92,8 +125,8 @@ const VMStateDescription vmstate_tl
[PATCH v1 32/46] target/loongarch: Implement xvclo xvclz
This patch includes:
- XVCLO.{B/H/W/D};
- XVCLZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 +
target/loongarch/helper.h| 9 +
target/loongarch/insn_trans/trans_lasx.c.inc | 9 +
target/loongarch/insns.decode| 9 +
target/loongarch/lasx_helper.c | 21
target/loongarch/lsx_helper.c| 9 -
target/loongarch/vec.h | 9 +
7 files changed, 66 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index da07b56dee..99636ca56c 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2195,6 +2195,15 @@ INSN_LASX(xvssrarni_hu_w,xx_i)
INSN_LASX(xvssrarni_wu_d,xx_i)
INSN_LASX(xvssrarni_du_q,xx_i)
+INSN_LASX(xvclo_b, xx)
+INSN_LASX(xvclo_h, xx)
+INSN_LASX(xvclo_w, xx)
+INSN_LASX(xvclo_d, xx)
+INSN_LASX(xvclz_b, xx)
+INSN_LASX(xvclz_h, xx)
+INSN_LASX(xvclz_w, xx)
+INSN_LASX(xvclz_d, xx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index b5d1cff1f0..950a73ec6f 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1050,3 +1050,12 @@ DEF_HELPER_4(xvssrarni_bu_h, void, env, i32, i32, i32)
DEF_HELPER_4(xvssrarni_hu_w, void, env, i32, i32, i32)
DEF_HELPER_4(xvssrarni_wu_d, void, env, i32, i32, i32)
DEF_HELPER_4(xvssrarni_du_q, void, env, i32, i32, i32)
+
+DEF_HELPER_3(xvclo_b, void, env, i32, i32)
+DEF_HELPER_3(xvclo_h, void, env, i32, i32)
+DEF_HELPER_3(xvclo_w, void, env, i32, i32)
+DEF_HELPER_3(xvclo_d, void, env, i32, i32)
+DEF_HELPER_3(xvclz_b, void, env, i32, i32)
+DEF_HELPER_3(xvclz_h, void, env, i32, i32)
+DEF_HELPER_3(xvclz_w, void, env, i32, i32)
+DEF_HELPER_3(xvclz_d, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index aa145c850b..fa7dafa7f9 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2144,6 +2144,15 @@ TRANS(xvssrarni_hu_w, gen_xx_i,
gen_helper_xvssrarni_hu_w)
TRANS(xvssrarni_wu_d, gen_xx_i, gen_helper_xvssrarni_wu_d)
TRANS(xvssrarni_du_q, gen_xx_i, gen_helper_xvssrarni_du_q)
+TRANS(xvclo_b, gen_xx, gen_helper_xvclo_b)
+TRANS(xvclo_h, gen_xx, gen_helper_xvclo_h)
+TRANS(xvclo_w, gen_xx, gen_helper_xvclo_w)
+TRANS(xvclo_d, gen_xx, gen_helper_xvclo_d)
+TRANS(xvclz_b, gen_xx, gen_helper_xvclz_b)
+TRANS(xvclz_h, gen_xx, gen_helper_xvclz_h)
+TRANS(xvclz_w, gen_xx, gen_helper_xvclz_w)
+TRANS(xvclz_d, gen_xx, gen_helper_xvclz_d)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 3aed69b766..91de5a3815 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1793,6 +1793,15 @@ xvssrarni_hu_w 0111 01110110 11001 . . .
@xx_ui5
xvssrarni_wu_d 0111 01110110 1101 .. . .@xx_ui6
xvssrarni_du_q 0111 01110110 111 ... . .@xx_ui7
+xvclo_b 0111 01101001 11000 0 . .@xx
+xvclo_h 0111 01101001 11000 1 . .@xx
+xvclo_w 0111 01101001 11000 00010 . .@xx
+xvclo_d 0111 01101001 11000 00011 . .@xx
+xvclz_b 0111 01101001 11000 00100 . .@xx
+xvclz_h 0111 01101001 11000 00101 . .@xx
+xvclz_w 0111 01101001 11000 00110 . .@xx
+xvclz_d 0111 01101001 11000 00111 . .@xx
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010 . .@xr
diff --git a/target/loongarch/lasx_helper.c b/target/loongarch/lasx_helper.c
index 0e223601de..122c460fb5 100644
--- a/target/loongarch/lasx_helper.c
+++ b/target/loongarch/lasx_helper.c
@@ -2081,3 +2081,24 @@ void HELPER(xvssrarni_du_q)(CPULoongArchState *env,
XVSSRARNUI(xvssrarni_bu_h, 16, XB, XH)
XVSSRARNUI(xvssrarni_hu_w, 32, XH, XW)
XVSSRARNUI(xvssrarni_wu_d, 64, XW, XD)
+
+#define XDO_2OP(NAME, BIT, E, DO_OP)\
+void HELPER(NAME)(CPULoongArchState *env, uint32_t xd, uint32_t xj) \
+{ \
+int i; \
+XReg *Xd = &(env->fpr[xd].xreg);\
+XReg *Xj = &(env->fpr[xj].xreg);\
+\
+for (i = 0; i < LASX_LEN / BIT; i++) { \
+
[PATCH v1 04/46] target/loongarch: Implement xvadd/xvsub
This patch includes:
- XVADD.{B/H/W/D/Q};
- XVSUB.{B/H/W/D/Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 23
target/loongarch/insn_trans/trans_lasx.c.inc | 59
target/loongarch/insns.decode| 23
target/loongarch/translate.c | 17 ++
4 files changed, 122 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 5c402d944d..696f78c491 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1695,3 +1695,26 @@ INSN_LSX(vstelm_d, vr_ii)
INSN_LSX(vstelm_w, vr_ii)
INSN_LSX(vstelm_h, vr_ii)
INSN_LSX(vstelm_b, vr_ii)
+
+#define INSN_LASX(insn, type) \
+static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
+{ \
+output_##type(ctx, a, #insn); \
+return true;\
+}
+
+static void output_xxx(DisasContext *ctx, arg_xxx * a, const char *mnemonic)
+{
+output(ctx, mnemonic, "x%d, x%d, x%d", a->xd, a->xj, a->xk);
+}
+
+INSN_LASX(xvadd_b, xxx)
+INSN_LASX(xvadd_h, xxx)
+INSN_LASX(xvadd_w, xxx)
+INSN_LASX(xvadd_d, xxx)
+INSN_LASX(xvadd_q, xxx)
+INSN_LASX(xvsub_b, xxx)
+INSN_LASX(xvsub_h, xxx)
+INSN_LASX(xvsub_w, xxx)
+INSN_LASX(xvsub_d, xxx)
+INSN_LASX(xvsub_q, xxx)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 75a77f5dce..c918522f96 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -14,3 +14,62 @@
#else
#define CHECK_ASXE
#endif
+
+static bool gvec_xxx(DisasContext *ctx, arg_xxx *a, MemOp mop,
+ void (*func)(unsigned, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t))
+{
+uint32_t xd_ofs, xj_ofs, xk_ofs;
+
+CHECK_ASXE;
+
+xd_ofs = vec_full_offset(a->xd);
+xj_ofs = vec_full_offset(a->xj);
+xk_ofs = vec_full_offset(a->xk);
+
+func(mop, xd_ofs, xj_ofs, xk_ofs, 32, ctx->vl / 8);
+return true;
+}
+
+TRANS(xvadd_b, gvec_xxx, MO_8, tcg_gen_gvec_add)
+TRANS(xvadd_h, gvec_xxx, MO_16, tcg_gen_gvec_add)
+TRANS(xvadd_w, gvec_xxx, MO_32, tcg_gen_gvec_add)
+TRANS(xvadd_d, gvec_xxx, MO_64, tcg_gen_gvec_add)
+
+#define XVADDSUB_Q(NAME)\
+static bool trans_xv## NAME ##_q(DisasContext *ctx, arg_xxx *a) \
+{ \
+TCGv_i64 rh, rl, ah, al, bh, bl;\
+int i; \
+\
+CHECK_ASXE; \
+\
+rh = tcg_temp_new_i64();\
+rl = tcg_temp_new_i64();\
+ah = tcg_temp_new_i64();\
+al = tcg_temp_new_i64();\
+bh = tcg_temp_new_i64();\
+bl = tcg_temp_new_i64();\
+\
+for (i = 0; i < 2; i++) { \
+get_xreg64(ah, a->xj, 1 + i * 2); \
+get_xreg64(al, a->xj, 0 + i * 2); \
+get_xreg64(bh, a->xk, 1 + i * 2); \
+get_xreg64(bl, a->xk, 0 + i * 2); \
+\
+tcg_gen_## NAME ##2_i64(rl, rh, al, ah, bl, bh);\
+\
+set_xreg64(rh, a->xd, 1 + i * 2); \
+set_xreg64(rl, a->xd, 0 + i * 2); \
+ }\
+\
+return true;\
+}
+
+XVADDSUB_Q(add)
+XVADDSUB_Q(sub)
+
+TRANS(xvsub_b, gvec_xxx, MO_8, tcg_gen_gvec_sub)
+TRANS(xvsub_h, gvec_xxx, MO_16, tcg_gen_gvec_sub)
+TRANS(xvsub_w, gvec_xxx, MO_32, tcg_gen_gvec_sub)
+TRANS(xvsub_d, gvec_xxx, MO_64, tcg_gen_gvec_sub)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index c9c3bc2c73..bac1903975 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1296,3 +1296,26 @@ vstelm_d 0011 00010001 0 . . .
@vr_i8i1
vstelm_w 0011 00010010 .. . .@vr_i8i2
vstelm_h 0011 0001010 ... .
[PATCH v1 39/46] target/loongarch: Implement xvfcmp
This patch includes:
- XVFCMP.cond.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 94
target/loongarch/helper.h| 5 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 32 +++
target/loongarch/insns.decode| 5 ++
target/loongarch/lasx_helper.c | 25 ++
target/loongarch/lsx_helper.c| 4 +-
target/loongarch/vec.h | 5 ++
7 files changed, 168 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 5d3904402d..c3bcb9d84a 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2384,6 +2384,100 @@ INSN_LASX(xvslti_hu, xx_i)
INSN_LASX(xvslti_wu, xx_i)
INSN_LASX(xvslti_du, xx_i)
+#define output_xvfcmp(C, PREFIX, SUFFIX)\
+{ \
+(C)->info->fprintf_func((C)->info->stream, "%08x %s%s\tx%d, x%d, x%d", \
+(C)->insn, PREFIX, SUFFIX, a->xd, \
+a->xj, a->xk); \
+}
+
+static bool output_xxx_fcond(DisasContext *ctx, arg_xxx_fcond * a,
+ const char *suffix)
+{
+bool ret = true;
+switch (a->fcond) {
+case 0x0:
+output_xvfcmp(ctx, "xvfcmp_caf_", suffix);
+break;
+case 0x1:
+output_xvfcmp(ctx, "xvfcmp_saf_", suffix);
+break;
+case 0x2:
+output_xvfcmp(ctx, "xvfcmp_clt_", suffix);
+break;
+case 0x3:
+output_xvfcmp(ctx, "xvfcmp_slt_", suffix);
+break;
+case 0x4:
+output_xvfcmp(ctx, "xvfcmp_ceq_", suffix);
+break;
+case 0x5:
+output_xvfcmp(ctx, "xvfcmp_seq_", suffix);
+break;
+case 0x6:
+output_xvfcmp(ctx, "xvfcmp_cle_", suffix);
+break;
+case 0x7:
+output_xvfcmp(ctx, "xvfcmp_sle_", suffix);
+break;
+case 0x8:
+output_xvfcmp(ctx, "xvfcmp_cun_", suffix);
+break;
+case 0x9:
+output_xvfcmp(ctx, "xvfcmp_sun_", suffix);
+break;
+case 0xA:
+output_xvfcmp(ctx, "xvfcmp_cult_", suffix);
+break;
+case 0xB:
+output_xvfcmp(ctx, "xvfcmp_sult_", suffix);
+break;
+case 0xC:
+output_xvfcmp(ctx, "xvfcmp_cueq_", suffix);
+break;
+case 0xD:
+output_xvfcmp(ctx, "xvfcmp_sueq_", suffix);
+break;
+case 0xE:
+output_xvfcmp(ctx, "xvfcmp_cule_", suffix);
+break;
+case 0xF:
+output_xvfcmp(ctx, "xvfcmp_sule_", suffix);
+break;
+case 0x10:
+output_xvfcmp(ctx, "xvfcmp_cne_", suffix);
+break;
+case 0x11:
+output_xvfcmp(ctx, "xvfcmp_sne_", suffix);
+break;
+case 0x14:
+output_xvfcmp(ctx, "xvfcmp_cor_", suffix);
+break;
+case 0x15:
+output_xvfcmp(ctx, "xvfcmp_sor_", suffix);
+break;
+case 0x18:
+output_xvfcmp(ctx, "xvfcmp_cune_", suffix);
+break;
+case 0x19:
+output_xvfcmp(ctx, "xvfcmp_sune_", suffix);
+break;
+default:
+ret = false;
+}
+return ret;
+}
+
+#define LASX_FCMP_INSN(suffix)\
+static bool trans_xvfcmp_cond_##suffix(DisasContext *ctx, \
+ arg_xxx_fcond * a) \
+{ \
+return output_xxx_fcond(ctx, a, #suffix); \
+}
+
+LASX_FCMP_INSN(s)
+LASX_FCMP_INSN(d)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index fbfd15d711..665bcb812a 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1216,3 +1216,8 @@ DEF_HELPER_FLAGS_4(xvslti_bu, TCG_CALL_NO_RWG, void, ptr,
ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvslti_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvslti_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvslti_du, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
+DEF_HELPER_5(xvfcmp_c_s, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(xvfcmp_s_s, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(xvfcmp_c_d, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(xvfcmp_s_d, void, env, i32, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index cc1b4fd42a..cdcd4a279a 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2674,6 +2674,38 @@ TRANS(xvslti_hu, do_xvslti_u, MO_16)
TRANS(xvslti_wu, do_xvslti_u, MO_32)
TRANS(xvslti_du, do_xvslti_u, MO_64)
+static bool trans_xvfcmp_cond_s(DisasContext *ctx, arg_xxx_fcond * a)
+{
+uint32_t flags;
+void (*fn)(TCGv_env, TCGv_i32, TCGv_i32, TCGv_i32,
[PATCH v1 36/46] target/loongarch: Implement LASX fpu arith instructions
This patch includes:
- XVF{ADD/SUB/MUL/DIV}.{S/D};
- XVF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- XVF{MAX/MIN}.{S/D};
- XVF{MAXA/MINA}.{S/D};
- XVFLOGB.{S/D};
- XVFCLASS.{S/D};
- XVF{SQRT/RECIP/RSQRT}.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 46 +
target/loongarch/helper.h| 41
target/loongarch/insn_trans/trans_lasx.c.inc | 55 +++
target/loongarch/insns.decode| 43 +
target/loongarch/lasx_helper.c | 99
target/loongarch/lsx_helper.c| 51 +-
target/loongarch/vec.h | 13 +++
7 files changed, 322 insertions(+), 26 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 5340609e6f..0e4ec2bd03 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1708,6 +1708,11 @@ static void output_x_i(DisasContext *ctx, arg_x_i *a,
const char *mnemonic)
output(ctx, mnemonic, "x%d, 0x%x", a->xd, a->imm);
}
+static void output_(DisasContext *ctx, arg_ *a, const char *mnemonic)
+{
+output(ctx, mnemonic, "x%d, x%d, x%d, x%d", a->xd, a->xj, a->xk, a->xa);
+}
+
static void output_xxx(DisasContext *ctx, arg_xxx * a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, x%d, x%d", a->xd, a->xj, a->xk);
@@ -2239,6 +2244,47 @@ INSN_LASX(xvfrstp_h, xxx)
INSN_LASX(xvfrstpi_b,xx_i)
INSN_LASX(xvfrstpi_h,xx_i)
+INSN_LASX(xvfadd_s, xxx)
+INSN_LASX(xvfadd_d, xxx)
+INSN_LASX(xvfsub_s, xxx)
+INSN_LASX(xvfsub_d, xxx)
+INSN_LASX(xvfmul_s, xxx)
+INSN_LASX(xvfmul_d, xxx)
+INSN_LASX(xvfdiv_s, xxx)
+INSN_LASX(xvfdiv_d, xxx)
+
+INSN_LASX(xvfmadd_s, )
+INSN_LASX(xvfmadd_d, )
+INSN_LASX(xvfmsub_s, )
+INSN_LASX(xvfmsub_d, )
+INSN_LASX(xvfnmadd_s,)
+INSN_LASX(xvfnmadd_d,)
+INSN_LASX(xvfnmsub_s,)
+INSN_LASX(xvfnmsub_d,)
+
+INSN_LASX(xvfmax_s, xxx)
+INSN_LASX(xvfmax_d, xxx)
+INSN_LASX(xvfmin_s, xxx)
+INSN_LASX(xvfmin_d, xxx)
+
+INSN_LASX(xvfmaxa_s, xxx)
+INSN_LASX(xvfmaxa_d, xxx)
+INSN_LASX(xvfmina_s, xxx)
+INSN_LASX(xvfmina_d, xxx)
+
+INSN_LASX(xvflogb_s, xx)
+INSN_LASX(xvflogb_d, xx)
+
+INSN_LASX(xvfclass_s,xx)
+INSN_LASX(xvfclass_d,xx)
+
+INSN_LASX(xvfsqrt_s, xx)
+INSN_LASX(xvfsqrt_d, xx)
+INSN_LASX(xvfrecip_s,xx)
+INSN_LASX(xvfrecip_d,xx)
+INSN_LASX(xvfrsqrt_s,xx)
+INSN_LASX(xvfrsqrt_d,xx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 4db0cd25d3..2e6e3f2fd3 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1096,3 +1096,44 @@ DEF_HELPER_4(xvfrstp_b, void, env, i32, i32, i32)
DEF_HELPER_4(xvfrstp_h, void, env, i32, i32, i32)
DEF_HELPER_4(xvfrstpi_b, void, env, i32, i32, i32)
DEF_HELPER_4(xvfrstpi_h, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvfadd_s, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfadd_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfsub_s, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfsub_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfmul_s, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfmul_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfdiv_s, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfdiv_d, void, env, i32, i32, i32)
+
+DEF_HELPER_5(xvfmadd_s, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(xvfmadd_d, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(xvfmsub_s, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(xvfmsub_d, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(xvfnmadd_s, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(xvfnmadd_d, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(xvfnmsub_s, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(xvfnmsub_d, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_4(xvfmax_s, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfmax_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfmin_s, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfmin_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvfmaxa_s, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfmaxa_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfmina_s, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfmina_d, void, env, i32, i32, i32)
+
+DEF_HELPER_3(xvflogb_s, void, env, i32, i32)
+DEF_HELPER_3(xvflogb_d, void, env, i32, i32)
+
+DEF_HELPER_3(xvfclass_s, void, env, i32, i32)
+DEF_HELPER_3(xvfclass_d, void, env, i32, i32)
+
+DEF_HELPER_3(xvfsqrt_s, void, env, i32, i32)
+DEF_HELPER_3(xvfsqrt_d, void, env, i32, i32)
+DEF_HELPER_3(xvfrecip_s, void, env, i32, i32)
+DEF_HELPER_3(xvfrecip_d, void, env, i32, i32)
+DEF_HELPER_3(xvfrsqrt_s, void, env, i32, i32)
+DEF_HELPER_3(xvfrsqrt_d, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/in
[PATCH v1 07/46] target/loongarch: Implement xvneg
This patch includes:
- XVNEG.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 10 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 20
target/loongarch/insns.decode| 7 +++
3 files changed, 37 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 7b84766fa8..eefd16e3f1 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1713,6 +1713,11 @@ static void output_xx_i(DisasContext *ctx, arg_xx_i *a,
const char *mnemonic)
output(ctx, mnemonic, "x%d, x%d, 0x%x", a->xd, a->xj, a->imm);
}
+static void output_xx(DisasContext *ctx, arg_xx *a, const char *mnemonic)
+{
+output(ctx, mnemonic, "x%d, x%d", a->xd, a->xj);
+}
+
static void output_xr(DisasContext *ctx, arg_xr *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, r%d", a->xd, a->rj);
@@ -1738,6 +1743,11 @@ INSN_LASX(xvsubi_hu, xx_i)
INSN_LASX(xvsubi_wu, xx_i)
INSN_LASX(xvsubi_du, xx_i)
+INSN_LASX(xvneg_b, xx)
+INSN_LASX(xvneg_h, xx)
+INSN_LASX(xvneg_w, xx)
+INSN_LASX(xvneg_d, xx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index a42e92f930..cea944c3ba 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -59,6 +59,21 @@ static bool gvec_xsubi(DisasContext *ctx, arg_xx_i *a, MemOp
mop)
return true;
}
+static bool gvec_xx(DisasContext *ctx, arg_xx *a, MemOp mop,
+void (*func)(unsigned, uint32_t, uint32_t,
+ uint32_t, uint32_t))
+{
+uint32_t xd_ofs, xj_ofs;
+
+CHECK_ASXE;
+
+xd_ofs = vec_full_offset(a->xd);
+xj_ofs = vec_full_offset(a->xj);
+
+func(mop, xd_ofs, xj_ofs, 32, ctx->vl / 8);
+return true;
+}
+
TRANS(xvadd_b, gvec_xxx, MO_8, tcg_gen_gvec_add)
TRANS(xvadd_h, gvec_xxx, MO_16, tcg_gen_gvec_add)
TRANS(xvadd_w, gvec_xxx, MO_32, tcg_gen_gvec_add)
@@ -111,6 +126,11 @@ TRANS(xvsubi_hu, gvec_xsubi, MO_16)
TRANS(xvsubi_wu, gvec_xsubi, MO_32)
TRANS(xvsubi_du, gvec_xsubi, MO_64)
+TRANS(xvneg_b, gvec_xx, MO_8, tcg_gen_gvec_neg)
+TRANS(xvneg_h, gvec_xx, MO_16, tcg_gen_gvec_neg)
+TRANS(xvneg_w, gvec_xx, MO_32, tcg_gen_gvec_neg)
+TRANS(xvneg_d, gvec_xx, MO_64, tcg_gen_gvec_neg)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 0bed748216..78452c622c 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1301,6 +1301,7 @@ vstelm_b 0011 000110 . .
@vr_i8i4
# LASX Argument sets
#
+&xx xd xj
&xxx xd xj xk
&xr xd rj
&xx_i xd xj imm
@@ -1309,6 +1310,7 @@ vstelm_b 0011 000110 . .
@vr_i8i4
# LASX Formats
#
+@xx . . xj:5 xd:5&xx
@xxx . xk:5 xj:5 xd:5&xxx
@xr . . rj:5 xd:5&xr
@xx_ui5 . imm:5 xj:5 xd:5&xx_i
@@ -1333,6 +1335,11 @@ xvsubi_hu0111 01101000 11001 . . .
@xx_ui5
xvsubi_wu0111 01101000 11010 . . .@xx_ui5
xvsubi_du0111 01101000 11011 . . .@xx_ui5
+xvneg_b 0111 01101001 11000 01100 . .@xx
+xvneg_h 0111 01101001 11000 01101 . .@xx
+xvneg_w 0111 01101001 11000 01110 . .@xx
+xvneg_d 0111 01101001 11000 0 . .@xx
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010 . .@xr
--
2.39.1
[PATCH v1 17/46] target/loongarch; Implement xvdiv/xvmod
This patch includes:
- XVDIV.{B/H/W/D}[U];
- XVMOD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 +++
target/loongarch/helper.h| 17 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 17 +++
target/loongarch/insns.decode| 17 +++
target/loongarch/lasx_helper.c | 30
target/loongarch/lsx_helper.c| 7 -
target/loongarch/vec.h | 7 +
7 files changed, 105 insertions(+), 7 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index ddfc4921b9..83efde440f 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1961,6 +1961,23 @@ INSN_LASX(xvmaddwod_w_hu_h, xxx)
INSN_LASX(xvmaddwod_d_wu_w, xxx)
INSN_LASX(xvmaddwod_q_du_d, xxx)
+INSN_LASX(xvdiv_b, xxx)
+INSN_LASX(xvdiv_h, xxx)
+INSN_LASX(xvdiv_w, xxx)
+INSN_LASX(xvdiv_d, xxx)
+INSN_LASX(xvdiv_bu, xxx)
+INSN_LASX(xvdiv_hu, xxx)
+INSN_LASX(xvdiv_wu, xxx)
+INSN_LASX(xvdiv_du, xxx)
+INSN_LASX(xvmod_b, xxx)
+INSN_LASX(xvmod_h, xxx)
+INSN_LASX(xvmod_w, xxx)
+INSN_LASX(xvmod_d, xxx)
+INSN_LASX(xvmod_bu, xxx)
+INSN_LASX(xvmod_hu, xxx)
+INSN_LASX(xvmod_wu, xxx)
+INSN_LASX(xvmod_du, xxx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 0dc4cc18da..95c7ecba3b 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -869,3 +869,20 @@ DEF_HELPER_FLAGS_4(xvmaddwev_d_wu_w, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvmaddwod_h_bu_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvmaddwod_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvmaddwod_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_4(xvdiv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvdiv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvdiv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvdiv_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvdiv_bu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvdiv_hu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvdiv_wu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvdiv_du, void, env, i32, i32, i32)
+DEF_HELPER_4(xvmod_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvmod_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvmod_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvmod_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvmod_bu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvmod_hu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvmod_wu, void, env, i32, i32, i32)
+DEF_HELPER_4(xvmod_du, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 78ba31b8c2..930872c939 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -1730,6 +1730,23 @@ TRANS(xvmaddwod_h_bu_b, gvec_xxx, MO_8, do_xvmaddwod_u_s)
TRANS(xvmaddwod_w_hu_h, gvec_xxx, MO_16, do_xvmaddwod_u_s)
TRANS(xvmaddwod_d_wu_w, gvec_xxx, MO_32, do_xvmaddwod_u_s)
+TRANS(xvdiv_b, gen_xxx, gen_helper_xvdiv_b)
+TRANS(xvdiv_h, gen_xxx, gen_helper_xvdiv_h)
+TRANS(xvdiv_w, gen_xxx, gen_helper_xvdiv_w)
+TRANS(xvdiv_d, gen_xxx, gen_helper_xvdiv_d)
+TRANS(xvdiv_bu, gen_xxx, gen_helper_xvdiv_bu)
+TRANS(xvdiv_hu, gen_xxx, gen_helper_xvdiv_hu)
+TRANS(xvdiv_wu, gen_xxx, gen_helper_xvdiv_wu)
+TRANS(xvdiv_du, gen_xxx, gen_helper_xvdiv_du)
+TRANS(xvmod_b, gen_xxx, gen_helper_xvmod_b)
+TRANS(xvmod_h, gen_xxx, gen_helper_xvmod_h)
+TRANS(xvmod_w, gen_xxx, gen_helper_xvmod_w)
+TRANS(xvmod_d, gen_xxx, gen_helper_xvmod_d)
+TRANS(xvmod_bu, gen_xxx, gen_helper_xvmod_bu)
+TRANS(xvmod_hu, gen_xxx, gen_helper_xvmod_hu)
+TRANS(xvmod_wu, gen_xxx, gen_helper_xvmod_wu)
+TRANS(xvmod_du, gen_xxx, gen_helper_xvmod_du)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index cc210314ff..0bd4e7709a 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1561,6 +1561,23 @@ xvmaddwod_w_hu_h 0111 01001011 11101 . . .
@xxx
xvmaddwod_d_wu_w 0111 01001011 0 . . .@xxx
xvmaddwod_q_du_d 0111 01001011 1 . . .@xxx
+xvdiv_b 0111 01001110 0 . . .@xxx
+xvdiv_h 0111 01001110 1 . . .@xxx
+xvdiv_w 0111 01001110 00010 . . .@xxx
+xvdiv_d 0111 01001110 00011 . . .@xxx
+xvmod_b 0111 01001110 00100 . . .@xxx
+xvmod_h 0111 01001110 00101 . . .@xxx
+xvmod_w 0111 01001110 00110 . . .@xxx
+xvm
[PATCH v1 29/46] target/loongarch: Implement xvsrlrn xvsrarn
This patch includes:
- XVSRLRN.{B.H/H.W/W.D};
- XVSRARN.{B.H/H.W/W.D};
- XVSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSRARNI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 16 ++
target/loongarch/helper.h| 16 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 16 ++
target/loongarch/insns.decode| 16 ++
target/loongarch/lasx_helper.c | 150 +++
5 files changed, 214 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 5ea713075f..515d99aa1f 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2119,6 +2119,22 @@ INSN_LASX(xvsrani_h_w, xx_i)
INSN_LASX(xvsrani_w_d, xx_i)
INSN_LASX(xvsrani_d_q, xx_i)
+INSN_LASX(xvsrlrn_b_h, xxx)
+INSN_LASX(xvsrlrn_h_w, xxx)
+INSN_LASX(xvsrlrn_w_d, xxx)
+INSN_LASX(xvsrarn_b_h, xxx)
+INSN_LASX(xvsrarn_h_w, xxx)
+INSN_LASX(xvsrarn_w_d, xxx)
+
+INSN_LASX(xvsrlrni_b_h, xx_i)
+INSN_LASX(xvsrlrni_h_w, xx_i)
+INSN_LASX(xvsrlrni_w_d, xx_i)
+INSN_LASX(xvsrlrni_d_q, xx_i)
+INSN_LASX(xvsrarni_b_h, xx_i)
+INSN_LASX(xvsrarni_h_w, xx_i)
+INSN_LASX(xvsrarni_w_d, xx_i)
+INSN_LASX(xvsrarni_d_q, xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index c41f8e2bc9..09ae21edd6 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -974,3 +974,19 @@ DEF_HELPER_4(xvsrani_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(xvsrani_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(xvsrani_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(xvsrani_d_q, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvsrlrn_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlrn_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlrn_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrarn_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrarn_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrarn_w_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(xvsrlrni_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlrni_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlrni_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrlrni_d_q, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrarni_b_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrarni_h_w, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrarni_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvsrarni_d_q, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 9a3c2114eb..5cd241bafa 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2068,6 +2068,22 @@ TRANS(xvsrani_h_w, gen_xx_i, gen_helper_xvsrani_h_w)
TRANS(xvsrani_w_d, gen_xx_i, gen_helper_xvsrani_w_d)
TRANS(xvsrani_d_q, gen_xx_i, gen_helper_xvsrani_d_q)
+TRANS(xvsrlrn_b_h, gen_xxx, gen_helper_xvsrlrn_b_h)
+TRANS(xvsrlrn_h_w, gen_xxx, gen_helper_xvsrlrn_h_w)
+TRANS(xvsrlrn_w_d, gen_xxx, gen_helper_xvsrlrn_w_d)
+TRANS(xvsrarn_b_h, gen_xxx, gen_helper_xvsrarn_b_h)
+TRANS(xvsrarn_h_w, gen_xxx, gen_helper_xvsrarn_h_w)
+TRANS(xvsrarn_w_d, gen_xxx, gen_helper_xvsrarn_w_d)
+
+TRANS(xvsrlrni_b_h, gen_xx_i, gen_helper_xvsrlrni_b_h)
+TRANS(xvsrlrni_h_w, gen_xx_i, gen_helper_xvsrlrni_h_w)
+TRANS(xvsrlrni_w_d, gen_xx_i, gen_helper_xvsrlrni_w_d)
+TRANS(xvsrlrni_d_q, gen_xx_i, gen_helper_xvsrlrni_d_q)
+TRANS(xvsrarni_b_h, gen_xx_i, gen_helper_xvsrarni_b_h)
+TRANS(xvsrarni_h_w, gen_xx_i, gen_helper_xvsrarni_h_w)
+TRANS(xvsrarni_w_d, gen_xx_i, gen_helper_xvsrarni_w_d)
+TRANS(xvsrarni_d_q, gen_xx_i, gen_helper_xvsrarni_d_q)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 45f15e3be2..0273576ada 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1717,6 +1717,22 @@ xvsrani_h_w 0111 01110101 10001 . . .
@xx_ui5
xvsrani_w_d 0111 01110101 1001 .. . .@xx_ui6
xvsrani_d_q 0111 01110101 101 ... . .@xx_ui7
+xvsrlrn_b_h 0111 0100 10001 . . .@xxx
+xvsrlrn_h_w 0111 0100 10010 . . .@xxx
+xvsrlrn_w_d 0111 0100 10011 . . .@xxx
+xvsrarn_b_h 0111 0100 10101 . . .@xxx
+xvsrarn_h_w 0111 0100 10110 . . .@xxx
+xvsrarn_w_d 0111 0100 10111 . . .@xxx
+
+xvsrlrni_b_h 0111 01110100 01000 1 . . @xx_ui4
+xvsrlrni_h_w 0111 01110100 01001 . . .@xx_ui5
+xvsrlrni_w_d 0111 01110100 0101 .. . .@xx_ui6
+xvsrlrni_d_q 0111 01110100 011 ... . .@xx_ui7
+xvsrarni_b_h 0111 01110101 11000 1 . . @xx_ui4
+xvsrarni_h_w
[PATCH v1 37/46] target/loongarch: Implement LASX fpu fcvt instructions
This patch includes:
- XVFCVT{L/H}.{S.H/D.S};
- XVFCVT.{H.S/S.D};
- XVFRINT[{RNE/RZ/RP/RM}].{S/D};
- XVFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- XVFTINT[RZ].{WU.S/LU.D};
- XVFTINT[{RNE/RZ/RP/RM}].W.D;
- XVFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- XVFFINT.{S.W/D.L}[U];
- X[CVFFINT.S.L, VFFINT{L/H}.D.W.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 56 +++
target/loongarch/helper.h| 56 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 56 +++
target/loongarch/insns.decode| 58 +++
target/loongarch/lasx_helper.c | 398 +++
5 files changed, 624 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 0e4ec2bd03..65eccc8598 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2285,6 +2285,62 @@ INSN_LASX(xvfrecip_d,xx)
INSN_LASX(xvfrsqrt_s,xx)
INSN_LASX(xvfrsqrt_d,xx)
+INSN_LASX(xvfcvtl_s_h, xx)
+INSN_LASX(xvfcvth_s_h, xx)
+INSN_LASX(xvfcvtl_d_s, xx)
+INSN_LASX(xvfcvth_d_s, xx)
+INSN_LASX(xvfcvt_h_s,xxx)
+INSN_LASX(xvfcvt_s_d,xxx)
+
+INSN_LASX(xvfrint_s, xx)
+INSN_LASX(xvfrint_d, xx)
+INSN_LASX(xvfrintrm_s, xx)
+INSN_LASX(xvfrintrm_d, xx)
+INSN_LASX(xvfrintrp_s, xx)
+INSN_LASX(xvfrintrp_d, xx)
+INSN_LASX(xvfrintrz_s, xx)
+INSN_LASX(xvfrintrz_d, xx)
+INSN_LASX(xvfrintrne_s, xx)
+INSN_LASX(xvfrintrne_d, xx)
+
+INSN_LASX(xvftint_w_s, xx)
+INSN_LASX(xvftint_l_d, xx)
+INSN_LASX(xvftintrm_w_s, xx)
+INSN_LASX(xvftintrm_l_d, xx)
+INSN_LASX(xvftintrp_w_s, xx)
+INSN_LASX(xvftintrp_l_d, xx)
+INSN_LASX(xvftintrz_w_s, xx)
+INSN_LASX(xvftintrz_l_d, xx)
+INSN_LASX(xvftintrne_w_s,xx)
+INSN_LASX(xvftintrne_l_d,xx)
+INSN_LASX(xvftint_wu_s, xx)
+INSN_LASX(xvftint_lu_d, xx)
+INSN_LASX(xvftintrz_wu_s,xx)
+INSN_LASX(xvftintrz_lu_d,xx)
+INSN_LASX(xvftint_w_d, xxx)
+INSN_LASX(xvftintrm_w_d, xxx)
+INSN_LASX(xvftintrp_w_d, xxx)
+INSN_LASX(xvftintrz_w_d, xxx)
+INSN_LASX(xvftintrne_w_d,xxx)
+INSN_LASX(xvftintl_l_s, xx)
+INSN_LASX(xvftinth_l_s, xx)
+INSN_LASX(xvftintrml_l_s,xx)
+INSN_LASX(xvftintrmh_l_s,xx)
+INSN_LASX(xvftintrpl_l_s,xx)
+INSN_LASX(xvftintrph_l_s,xx)
+INSN_LASX(xvftintrzl_l_s,xx)
+INSN_LASX(xvftintrzh_l_s,xx)
+INSN_LASX(xvftintrnel_l_s, xx)
+INSN_LASX(xvftintrneh_l_s, xx)
+
+INSN_LASX(xvffint_s_w, xx)
+INSN_LASX(xvffint_s_wu, xx)
+INSN_LASX(xvffint_d_l, xx)
+INSN_LASX(xvffint_d_lu, xx)
+INSN_LASX(xvffintl_d_w, xx)
+INSN_LASX(xvffinth_d_w, xx)
+INSN_LASX(xvffint_s_l, xxx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 2e6e3f2fd3..d30ea7f6a4 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1137,3 +1137,59 @@ DEF_HELPER_3(xvfrecip_s, void, env, i32, i32)
DEF_HELPER_3(xvfrecip_d, void, env, i32, i32)
DEF_HELPER_3(xvfrsqrt_s, void, env, i32, i32)
DEF_HELPER_3(xvfrsqrt_d, void, env, i32, i32)
+
+DEF_HELPER_3(xvfcvtl_s_h, void, env, i32, i32)
+DEF_HELPER_3(xvfcvth_s_h, void, env, i32, i32)
+DEF_HELPER_3(xvfcvtl_d_s, void, env, i32, i32)
+DEF_HELPER_3(xvfcvth_d_s, void, env, i32, i32)
+DEF_HELPER_4(xvfcvt_h_s, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfcvt_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_3(xvfrintrne_s, void, env, i32, i32)
+DEF_HELPER_3(xvfrintrne_d, void, env, i32, i32)
+DEF_HELPER_3(xvfrintrz_s, void, env, i32, i32)
+DEF_HELPER_3(xvfrintrz_d, void, env, i32, i32)
+DEF_HELPER_3(xvfrintrp_s, void, env, i32, i32)
+DEF_HELPER_3(xvfrintrp_d, void, env, i32, i32)
+DEF_HELPER_3(xvfrintrm_s, void, env, i32, i32)
+DEF_HELPER_3(xvfrintrm_d, void, env, i32, i32)
+DEF_HELPER_3(xvfrint_s, void, env, i32, i32)
+DEF_HELPER_3(xvfrint_d, void, env, i32, i32)
+
+DEF_HELPER_3(xvftintrne_w_s, void, env, i32, i32)
+DEF_HELPER_3(xvftintrne_l_d, void, env, i32, i32)
+DEF_HELPER_3(xvftintrz_w_s, void, env, i32, i32)
+DEF_HELPER_3(xvftintrz_l_d, void, env, i32, i32)
+DEF_HELPER_3(xvftintrp_w_s, void, env, i32, i32)
+DEF_HELPER_3(xvftintrp_l_d, void, env, i32, i32)
+DEF_HELPER_3(xvftintrm_w_s, void, env, i32, i32)
+DEF_HELPER_3(xvftintrm_l_d, void, env, i32, i32)
+DEF_HELPER_3(xvftint_w_s, void, env, i32, i32)
+DEF_HELPER_3(xvftint_l_d, void, env, i32, i32)
+DEF_HELPER_3(xvftintrz_wu_s, void, env, i32, i32)
+DEF_HELPER_3(xvftintrz_lu_d, void, env, i32, i32)
+DEF_HELPER_3(xvftint_wu_s, void, env, i32, i32)
+DEF_HELPER_3(xvftint_lu_d, void, env, i32, i32)
+DEF_HELPER_4(xvftintrne_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvftintrz_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvftintrp_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvftintrm_w_d, void, env, i32, i32, i32)
+DEF_HELPER_4(xvftint_w_d, void, env, i32, i32, i32)
+DEF_HELPER_3(xvftintrnel_l_s, void, env, i3
[PATCH v1 34/46] target/loongarch: Implement xvbitclr xvbitset xvbitrev
This patch includes:
- XVBITCLR[I].{B/H/W/D};
- XVBITSET[I].{B/H/W/D};
- XVBITREV[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 25 ++
target/loongarch/helper.h| 27 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 246 +++
target/loongarch/insns.decode| 27 ++
target/loongarch/lasx_helper.c | 51
target/loongarch/lsx_helper.c| 4 -
target/loongarch/vec.h | 4 +
7 files changed, 380 insertions(+), 4 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index b7a322651f..60d265a9f2 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2209,6 +2209,31 @@ INSN_LASX(xvpcnt_h, xx)
INSN_LASX(xvpcnt_w, xx)
INSN_LASX(xvpcnt_d, xx)
+INSN_LASX(xvbitclr_b,xxx)
+INSN_LASX(xvbitclr_h,xxx)
+INSN_LASX(xvbitclr_w,xxx)
+INSN_LASX(xvbitclr_d,xxx)
+INSN_LASX(xvbitclri_b, xx_i)
+INSN_LASX(xvbitclri_h, xx_i)
+INSN_LASX(xvbitclri_w, xx_i)
+INSN_LASX(xvbitclri_d, xx_i)
+INSN_LASX(xvbitset_b,xxx)
+INSN_LASX(xvbitset_h,xxx)
+INSN_LASX(xvbitset_w,xxx)
+INSN_LASX(xvbitset_d,xxx)
+INSN_LASX(xvbitseti_b, xx_i)
+INSN_LASX(xvbitseti_h, xx_i)
+INSN_LASX(xvbitseti_w, xx_i)
+INSN_LASX(xvbitseti_d, xx_i)
+INSN_LASX(xvbitrev_b,xxx)
+INSN_LASX(xvbitrev_h,xxx)
+INSN_LASX(xvbitrev_w,xxx)
+INSN_LASX(xvbitrev_d,xxx)
+INSN_LASX(xvbitrevi_b, xx_i)
+INSN_LASX(xvbitrevi_h, xx_i)
+INSN_LASX(xvbitrevi_w, xx_i)
+INSN_LASX(xvbitrevi_d, xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index a434443819..294ac477fc 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1064,3 +1064,30 @@ DEF_HELPER_3(xvpcnt_b, void, env, i32, i32)
DEF_HELPER_3(xvpcnt_h, void, env, i32, i32)
DEF_HELPER_3(xvpcnt_w, void, env, i32, i32)
DEF_HELPER_3(xvpcnt_d, void, env, i32, i32)
+
+DEF_HELPER_FLAGS_4(xvbitclr_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvbitclr_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvbitclr_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvbitclr_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvbitclri_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvbitclri_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvbitclri_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvbitclri_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
+DEF_HELPER_FLAGS_4(xvbitset_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvbitset_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvbitset_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvbitset_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvbitseti_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvbitseti_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvbitseti_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvbitseti_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
+DEF_HELPER_FLAGS_4(xvbitrev_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvbitrev_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvbitrev_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvbitrev_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvbitrevi_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvbitrevi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvbitrevi_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(xvbitrevi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 616d296432..e87e000478 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2158,6 +2158,252 @@ TRANS(xvpcnt_h, gen_xx, gen_helper_xvpcnt_h)
TRANS(xvpcnt_w, gen_xx, gen_helper_xvpcnt_w)
TRANS(xvpcnt_d, gen_xx, gen_helper_xvpcnt_d)
+static void do_xvbitclr(unsigned vece, uint32_t xd_ofs, uint32_t xj_ofs,
+uint32_t xk_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+static const TCGOpcode vecop_list[] = {
+INDEX_op_shlv_vec, INDEX_op_andc_vec, 0
+};
+static const GVecGen3 op[4] = {
+{
+.fniv = gen_vbitclr,
+.fno = gen_helper_xvbitclr_b,
+.opt_opc = vecop_list,
+.vece = MO_8
+},
+{
+.fniv = gen_vbitclr,
+.fno = gen_helper_xvbitclr_h,
+.opt_opc = vecop_list,
[PATCH v1 11/46] target/loongarch: Implement xavg/xvagr
This patch includes:
- XVAVG.{B/H/W/D/}[U];
- XVAVGR.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 ++
target/loongarch/helper.h| 18 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 162 +++
target/loongarch/insns.decode| 17 ++
target/loongarch/lasx_helper.c | 29
target/loongarch/vec.h | 3 +
6 files changed, 246 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 6e790f0959..d804caaee0 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1825,6 +1825,23 @@ INSN_LASX(xvaddwod_w_hu_h, xxx)
INSN_LASX(xvaddwod_d_wu_w, xxx)
INSN_LASX(xvaddwod_q_du_d, xxx)
+INSN_LASX(xvavg_b, xxx)
+INSN_LASX(xvavg_h, xxx)
+INSN_LASX(xvavg_w, xxx)
+INSN_LASX(xvavg_d, xxx)
+INSN_LASX(xvavg_bu, xxx)
+INSN_LASX(xvavg_hu, xxx)
+INSN_LASX(xvavg_wu, xxx)
+INSN_LASX(xvavg_du, xxx)
+INSN_LASX(xvavgr_b, xxx)
+INSN_LASX(xvavgr_h, xxx)
+INSN_LASX(xvavgr_w, xxx)
+INSN_LASX(xvavgr_d, xxx)
+INSN_LASX(xvavgr_bu, xxx)
+INSN_LASX(xvavgr_hu, xxx)
+INSN_LASX(xvavgr_wu, xxx)
+INSN_LASX(xvavgr_du, xxx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 2034576d87..feeaa92447 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -759,3 +759,21 @@ DEF_HELPER_FLAGS_4(xvaddwod_h_bu_b, TCG_CALL_NO_RWG, void,
ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvaddwod_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvaddwod_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvaddwod_q_du_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvavg_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavg_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavg_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavg_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavg_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavg_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavg_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavg_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvavgr_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavgr_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavgr_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavgr_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavgr_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavgr_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavgr_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvavgr_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 0a574182db..4a8bcf618f 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -588,6 +588,168 @@ TRANS(xvaddwod_w_hu_h, gvec_xxx, MO_16, do_xvaddwod_u_s)
TRANS(xvaddwod_d_wu_w, gvec_xxx, MO_32, do_xvaddwod_u_s)
TRANS(xvaddwod_q_du_d, gvec_xxx, MO_64, do_xvaddwod_u_s)
+static void do_xvavg_s(unsigned vece, uint32_t xd_ofs, uint32_t xj_ofs,
+ uint32_t xk_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+static const TCGOpcode vecop_list[] = {
+INDEX_op_sari_vec, INDEX_op_add_vec, 0
+};
+static const GVecGen3 op[4] = {
+{
+.fniv = gen_vavg_s,
+.fno = gen_helper_xvavg_b,
+.opt_opc = vecop_list,
+.vece = MO_8
+},
+{
+.fniv = gen_vavg_s,
+.fno = gen_helper_xvavg_h,
+.opt_opc = vecop_list,
+.vece = MO_16
+},
+{
+.fniv = gen_vavg_s,
+.fno = gen_helper_xvavg_w,
+.opt_opc = vecop_list,
+.vece = MO_32
+},
+{
+.fniv = gen_vavg_s,
+.fno = gen_helper_xvavg_d,
+.opt_opc = vecop_list,
+.vece = MO_64
+},
+};
+
+tcg_gen_gvec_3(xd_ofs, xj_ofs, xk_ofs, oprsz, maxsz, &op[vece]);
+}
+
+static void do_xvavg_u(unsigned vece, uint32_t xd_ofs, uint32_t xj_ofs,
+ uint32_t xk_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+static const TCGOpcode vecop_list[] = {
+INDEX_op_shri_vec, INDEX_op_add_vec, 0
+};
+static const GVecGen3 op[4] = {
+{
+.fniv = gen_vavg_u,
+.fno = gen_helper_xvavg_bu,
+.opt_opc = vecop_list,
+.ve
[PATCH v1 03/46] target/loongarch: Add CHECK_ASXE maccro for check LASX enable
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 2 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 10 ++
3 files changed, 14 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 5037cfc02c..c9f9cbb19d 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -54,6 +54,7 @@ static const char * const excp_names[] = {
[EXCCODE_DBP] = "Debug breakpoint",
[EXCCODE_BCE] = "Bound Check Exception",
[EXCCODE_SXD] = "128 bit vector instructions Disable exception",
+[EXCCODE_ASXD] = "256 bit vector instructions Disable exception",
};
const char *loongarch_exception_name(int32_t exception)
@@ -189,6 +190,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
case EXCCODE_FPD:
case EXCCODE_FPE:
case EXCCODE_SXD:
+case EXCCODE_ASXD:
env->CSR_BADV = env->pc;
QEMU_FALLTHROUGH;
case EXCCODE_BCE:
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 347950b4d0..6e8d247ae0 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -440,6 +440,7 @@ static inline int cpu_mmu_index(CPULoongArchState *env,
bool ifetch)
#define HW_FLAGS_CRMD_PGR_CSR_CRMD_PG_MASK /* 0x10 */
#define HW_FLAGS_EUEN_FPE 0x04
#define HW_FLAGS_EUEN_SXE 0x08
+#define HW_FLAGS_EUEN_ASXE 0x10
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
target_ulong *pc,
@@ -451,6 +452,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState
*env,
*flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
+*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE;
}
void loongarch_cpu_list(void);
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 56a9839255..75a77f5dce 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -4,3 +4,13 @@
* Copyright (c) 2023 Loongson Technology Corporation Limited
*/
+#ifndef CONFIG_USER_ONLY
+#define CHECK_ASXE do { \
+if ((ctx->base.tb->flags & HW_FLAGS_EUEN_ASXE) == 0) { \
+generate_exception(ctx, EXCCODE_ASXD); \
+return true; \
+} \
+} while (0)
+#else
+#define CHECK_ASXE
+#endif
--
2.39.1
[PATCH v1 35/46] target/loongarch: Implement xvfrstp
This patch includes:
- XVFRSTP[I].{B/H}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 ++
target/loongarch/helper.h| 5 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 5 ++
target/loongarch/insns.decode| 5 ++
target/loongarch/lasx_helper.c | 56
5 files changed, 76 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 60d265a9f2..5340609e6f 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2234,6 +2234,11 @@ INSN_LASX(xvbitrevi_h, xx_i)
INSN_LASX(xvbitrevi_w, xx_i)
INSN_LASX(xvbitrevi_d, xx_i)
+INSN_LASX(xvfrstp_b, xxx)
+INSN_LASX(xvfrstp_h, xxx)
+INSN_LASX(xvfrstpi_b,xx_i)
+INSN_LASX(xvfrstpi_h,xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 294ac477fc..4db0cd25d3 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -1091,3 +1091,8 @@ DEF_HELPER_FLAGS_4(xvbitrevi_b, TCG_CALL_NO_RWG, void,
ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvbitrevi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvbitrevi_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvbitrevi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
+DEF_HELPER_4(xvfrstp_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfrstp_h, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfrstpi_b, void, env, i32, i32, i32)
+DEF_HELPER_4(xvfrstpi_h, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index e87e000478..beeb9b3ff8 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2404,6 +2404,11 @@ TRANS(xvbitrevi_h, gvec_xx_i, MO_16, do_xvbitrevi)
TRANS(xvbitrevi_w, gvec_xx_i, MO_32, do_xvbitrevi)
TRANS(xvbitrevi_d, gvec_xx_i, MO_64, do_xvbitrevi)
+TRANS(xvfrstp_b, gen_xxx, gen_helper_xvfrstp_b)
+TRANS(xvfrstp_h, gen_xxx, gen_helper_xvfrstp_h)
+TRANS(xvfrstpi_b, gen_xx_i, gen_helper_xvfrstpi_b)
+TRANS(xvfrstpi_h, gen_xx_i, gen_helper_xvfrstpi_h)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 47374054c6..387c1e5776 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1834,6 +1834,11 @@ xvbitrevi_h 0111 01110001 1 1 . .
@xx_ui4
xvbitrevi_w 0111 01110001 10001 . . .@xx_ui5
xvbitrevi_d 0111 01110001 1001 .. . .@xx_ui6
+xvfrstp_b0111 01010010 10110 . . .@xxx
+xvfrstp_h0111 01010010 10111 . . .@xxx
+xvfrstpi_b 0111 01101001 10100 . . .@xx_ui5
+xvfrstpi_h 0111 01101001 10101 . . .@xx_ui5
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010 . .@xr
diff --git a/target/loongarch/lasx_helper.c b/target/loongarch/lasx_helper.c
index 7092835d30..011eab46fb 100644
--- a/target/loongarch/lasx_helper.c
+++ b/target/loongarch/lasx_helper.c
@@ -2170,3 +2170,59 @@ XDO_BITI(xvbitrevi_b, 8, UXB, DO_BITREV)
XDO_BITI(xvbitrevi_h, 16, UXH, DO_BITREV)
XDO_BITI(xvbitrevi_w, 32, UXW, DO_BITREV)
XDO_BITI(xvbitrevi_d, 64, UXD, DO_BITREV)
+
+#define XVFRSTP(NAME, BIT, MASK, E) \
+void HELPER(NAME)(CPULoongArchState *env,\
+ uint32_t xd, uint32_t xj, uint32_t xk) \
+{\
+int i, j, m1, m2, max; \
+XReg *Xd = &(env->fpr[xd].xreg); \
+XReg *Xj = &(env->fpr[xj].xreg); \
+XReg *Xk = &(env->fpr[xk].xreg); \
+ \
+max = LASX_LEN / (BIT * 2); \
+m1 = Xk->E(0) & MASK;\
+for (i = 0; i < max; i++) { \
+if (Xj->E(i) < 0) { \
+break; \
+}\
+}\
+Xd->E(m1) = i; \
+for (j = 0; j < max; j++) { \
+if (Xj->E(j + max) < 0) {\
+break; \
+}\
+}\
+m2 = Xk->E(max) & MASK;
[PATCH v1 22/46] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz
This patch includes:
- XVMSKLTZ.{B/H/W/D};
- XVMSKGEZ.B;
- XVMSKNZ.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 7 ++
target/loongarch/helper.h| 7 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 7 ++
target/loongarch/insns.decode| 7 ++
target/loongarch/lasx_helper.c | 95
target/loongarch/lsx_helper.c| 10 +--
target/loongarch/vec.h | 6 ++
7 files changed, 134 insertions(+), 5 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index d0ccf3e86c..5a3c14f33d 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2014,6 +2014,13 @@ INSN_LASX(xvsigncov_h, xxx)
INSN_LASX(xvsigncov_w, xxx)
INSN_LASX(xvsigncov_d, xxx)
+INSN_LASX(xvmskltz_b,xx)
+INSN_LASX(xvmskltz_h,xx)
+INSN_LASX(xvmskltz_w,xx)
+INSN_LASX(xvmskltz_d,xx)
+INSN_LASX(xvmskgez_b,xx)
+INSN_LASX(xvmsknz_b, xx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 53a33703b3..b7ba78ee06 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -922,3 +922,10 @@ DEF_HELPER_FLAGS_4(xvsigncov_b, TCG_CALL_NO_RWG, void,
ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvsigncov_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvsigncov_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(xvsigncov_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_3(xvmskltz_b, void, env, i32, i32)
+DEF_HELPER_3(xvmskltz_h, void, env, i32, i32)
+DEF_HELPER_3(xvmskltz_w, void, env, i32, i32)
+DEF_HELPER_3(xvmskltz_d, void, env, i32, i32)
+DEF_HELPER_3(xvmskgez_b, void, env, i32, i32)
+DEF_HELPER_3(xvmsknz_b, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 9c24e82ac0..b0aad21a9d 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -1907,6 +1907,13 @@ TRANS(xvsigncov_h, gvec_xxx, MO_16, do_xvsigncov)
TRANS(xvsigncov_w, gvec_xxx, MO_32, do_xvsigncov)
TRANS(xvsigncov_d, gvec_xxx, MO_64, do_xvsigncov)
+TRANS(xvmskltz_b, gen_xx, gen_helper_xvmskltz_b)
+TRANS(xvmskltz_h, gen_xx, gen_helper_xvmskltz_h)
+TRANS(xvmskltz_w, gen_xx, gen_helper_xvmskltz_w)
+TRANS(xvmskltz_d, gen_xx, gen_helper_xvmskltz_d)
+TRANS(xvmskgez_b, gen_xx, gen_helper_xvmskgez_b)
+TRANS(xvmsknz_b, gen_xx, gen_helper_xvmsknz_b)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 887d7f5a90..b792a68fdf 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1618,6 +1618,13 @@ xvsigncov_h 0111 01010010 11101 . . .
@xxx
xvsigncov_w 0111 01010010 0 . . .@xxx
xvsigncov_d 0111 01010010 1 . . .@xxx
+xvmskltz_b 0111 01101001 11000 1 . .@xx
+xvmskltz_h 0111 01101001 11000 10001 . .@xx
+xvmskltz_w 0111 01101001 11000 10010 . .@xx
+xvmskltz_d 0111 01101001 11000 10011 . .@xx
+xvmskgez_b 0111 01101001 11000 10100 . .@xx
+xvmsknz_b0111 01101001 11000 11000 . .@xx
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010 . .@xr
diff --git a/target/loongarch/lasx_helper.c b/target/loongarch/lasx_helper.c
index db7905fa4d..6aec554645 100644
--- a/target/loongarch/lasx_helper.c
+++ b/target/loongarch/lasx_helper.c
@@ -709,3 +709,98 @@ XDO_3OP(xvsigncov_b, 8, XB, DO_SIGNCOV)
XDO_3OP(xvsigncov_h, 16, XH, DO_SIGNCOV)
XDO_3OP(xvsigncov_w, 32, XW, DO_SIGNCOV)
XDO_3OP(xvsigncov_d, 64, XD, DO_SIGNCOV)
+
+void HELPER(xvmskltz_b)(CPULoongArchState *env, uint32_t xd, uint32_t xj)
+{
+uint16_t temp;
+int i;
+XReg *Xd = &(env->fpr[xd].xreg);
+XReg *Xj = &(env->fpr[xj].xreg);
+
+for (i = 0; i < 2; i++) {
+temp = 0;
+temp = do_vmskltz_b(Xj->XD(2 * i));
+temp |= (do_vmskltz_b(Xj->XD(2 * i + 1)) << 8);
+Xd->XD(2 * i) = temp;
+Xd->XD(2 * i + 1) = 0;
+}
+}
+
+void HELPER(xvmskltz_h)(CPULoongArchState *env, uint32_t xd, uint32_t xj)
+{
+uint16_t temp;
+int i;
+XReg *Xd = &(env->fpr[xd].xreg);
+XReg *Xj = &(env->fpr[xj].xreg);
+
+for (i = 0; i < 2; i++) {
+temp = 0;
+temp = do_vmskltz_h(Xj->XD(2 * i));
+temp |= (do_vmskltz_h(Xj->XD(2 * i + 1)) << 4);
+Xd->XD(2 * i) = temp;
+Xd->XD(2 * i + 1) = 0;
+}
+}
+
+void HELPER(xvmskltz_w)(CPULoongArchState *env, uint32_t xd, ui
[PATCH v1 21/46] target/loongarch: Implement xvsigncov
This patch includes:
- XVSIGNCOV.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 +++
target/loongarch/helper.h| 5 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 41
target/loongarch/insns.decode| 5 +++
target/loongarch/lasx_helper.c | 5 +++
target/loongarch/lsx_helper.c| 2 -
target/loongarch/vec.h | 2 +
7 files changed, 63 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 1897aa7ba1..d0ccf3e86c 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2009,6 +2009,11 @@ INSN_LASX(vext2xv_wu_hu, xx)
INSN_LASX(vext2xv_du_hu, xx)
INSN_LASX(vext2xv_du_wu, xx)
+INSN_LASX(xvsigncov_b, xxx)
+INSN_LASX(xvsigncov_h, xxx)
+INSN_LASX(xvsigncov_w, xxx)
+INSN_LASX(xvsigncov_d, xxx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 7a303ee3f1..53a33703b3 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -917,3 +917,8 @@ DEF_HELPER_3(vext2xv_du_bu, void, env, i32, i32)
DEF_HELPER_3(vext2xv_wu_hu, void, env, i32, i32)
DEF_HELPER_3(vext2xv_du_hu, void, env, i32, i32)
DEF_HELPER_3(vext2xv_du_wu, void, env, i32, i32)
+
+DEF_HELPER_FLAGS_4(xvsigncov_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsigncov_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsigncov_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsigncov_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index c04469af75..9c24e82ac0 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -1866,6 +1866,47 @@ TRANS(vext2xv_wu_hu, gen_xx, gen_helper_vext2xv_wu_hu)
TRANS(vext2xv_du_hu, gen_xx, gen_helper_vext2xv_du_hu)
TRANS(vext2xv_du_wu, gen_xx, gen_helper_vext2xv_du_wu)
+static void do_xvsigncov(unsigned vece, uint32_t xd_ofs, uint32_t xj_ofs,
+ uint32_t xk_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+static const TCGOpcode vecop_list[] = {
+INDEX_op_neg_vec, INDEX_op_cmpsel_vec, 0
+};
+static const GVecGen3 op[4] = {
+{
+.fniv = gen_vsigncov,
+.fno = gen_helper_xvsigncov_b,
+.opt_opc = vecop_list,
+.vece = MO_8
+},
+{
+.fniv = gen_vsigncov,
+.fno = gen_helper_xvsigncov_h,
+.opt_opc = vecop_list,
+.vece = MO_16
+},
+{
+.fniv = gen_vsigncov,
+.fno = gen_helper_xvsigncov_w,
+.opt_opc = vecop_list,
+.vece = MO_32
+},
+{
+.fniv = gen_vsigncov,
+.fno = gen_helper_xvsigncov_d,
+.opt_opc = vecop_list,
+.vece = MO_64
+},
+};
+
+tcg_gen_gvec_3(xd_ofs, xj_ofs, xk_ofs, oprsz, maxsz, &op[vece]);
+}
+
+TRANS(xvsigncov_b, gvec_xxx, MO_8, do_xvsigncov)
+TRANS(xvsigncov_h, gvec_xxx, MO_16, do_xvsigncov)
+TRANS(xvsigncov_w, gvec_xxx, MO_32, do_xvsigncov)
+TRANS(xvsigncov_d, gvec_xxx, MO_64, do_xvsigncov)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 9f1cb04368..887d7f5a90 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1613,6 +1613,11 @@ vext2xv_wu_hu0111 01101001 0 01101 . .
@xx
vext2xv_du_hu0111 01101001 0 01110 . .@xx
vext2xv_du_wu0111 01101001 0 0 . .@xx
+xvsigncov_b 0111 01010010 11100 . . .@xxx
+xvsigncov_h 0111 01010010 11101 . . .@xxx
+xvsigncov_w 0111 01010010 0 . . .@xxx
+xvsigncov_d 0111 01010010 1 . . .@xxx
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010 . .@xr
diff --git a/target/loongarch/lasx_helper.c b/target/loongarch/lasx_helper.c
index ca82d03ff4..db7905fa4d 100644
--- a/target/loongarch/lasx_helper.c
+++ b/target/loongarch/lasx_helper.c
@@ -704,3 +704,8 @@ VEXT2XV(vext2xv_du_bu, 64, UXD, UXB)
VEXT2XV(vext2xv_wu_hu, 32, UXW, UXH)
VEXT2XV(vext2xv_du_hu, 64, UXD, UXH)
VEXT2XV(vext2xv_du_wu, 64, UXD, UXW)
+
+XDO_3OP(xvsigncov_b, 8, XB, DO_SIGNCOV)
+XDO_3OP(xvsigncov_h, 16, XH, DO_SIGNCOV)
+XDO_3OP(xvsigncov_w, 32, XW, DO_SIGNCOV)
+XDO_3OP(xvsigncov_d, 64, XD, DO_SIGNCOV)
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index 5a
[PATCH v1 08/46] target/loongarch: Implement xvsadd/xvssub
This patch includes:
- XVSADD.{B/H/W/D}[U];
- XVSSUB.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 +
target/loongarch/insn_trans/trans_lasx.c.inc | 17 +
target/loongarch/insns.decode| 18 ++
3 files changed, 52 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index eefd16e3f1..2a2993cb95 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1748,6 +1748,23 @@ INSN_LASX(xvneg_h, xx)
INSN_LASX(xvneg_w, xx)
INSN_LASX(xvneg_d, xx)
+INSN_LASX(xvsadd_b, xxx)
+INSN_LASX(xvsadd_h, xxx)
+INSN_LASX(xvsadd_w, xxx)
+INSN_LASX(xvsadd_d, xxx)
+INSN_LASX(xvsadd_bu, xxx)
+INSN_LASX(xvsadd_hu, xxx)
+INSN_LASX(xvsadd_wu, xxx)
+INSN_LASX(xvsadd_du, xxx)
+INSN_LASX(xvssub_b, xxx)
+INSN_LASX(xvssub_h, xxx)
+INSN_LASX(xvssub_w, xxx)
+INSN_LASX(xvssub_d, xxx)
+INSN_LASX(xvssub_bu, xxx)
+INSN_LASX(xvssub_hu, xxx)
+INSN_LASX(xvssub_wu, xxx)
+INSN_LASX(xvssub_du, xxx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index cea944c3ba..ec68193686 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -131,6 +131,23 @@ TRANS(xvneg_h, gvec_xx, MO_16, tcg_gen_gvec_neg)
TRANS(xvneg_w, gvec_xx, MO_32, tcg_gen_gvec_neg)
TRANS(xvneg_d, gvec_xx, MO_64, tcg_gen_gvec_neg)
+TRANS(xvsadd_b, gvec_xxx, MO_8, tcg_gen_gvec_ssadd)
+TRANS(xvsadd_h, gvec_xxx, MO_16, tcg_gen_gvec_ssadd)
+TRANS(xvsadd_w, gvec_xxx, MO_32, tcg_gen_gvec_ssadd)
+TRANS(xvsadd_d, gvec_xxx, MO_64, tcg_gen_gvec_ssadd)
+TRANS(xvsadd_bu, gvec_xxx, MO_8, tcg_gen_gvec_usadd)
+TRANS(xvsadd_hu, gvec_xxx, MO_16, tcg_gen_gvec_usadd)
+TRANS(xvsadd_wu, gvec_xxx, MO_32, tcg_gen_gvec_usadd)
+TRANS(xvsadd_du, gvec_xxx, MO_64, tcg_gen_gvec_usadd)
+TRANS(xvssub_b, gvec_xxx, MO_8, tcg_gen_gvec_sssub)
+TRANS(xvssub_h, gvec_xxx, MO_16, tcg_gen_gvec_sssub)
+TRANS(xvssub_w, gvec_xxx, MO_32, tcg_gen_gvec_sssub)
+TRANS(xvssub_d, gvec_xxx, MO_64, tcg_gen_gvec_sssub)
+TRANS(xvssub_bu, gvec_xxx, MO_8, tcg_gen_gvec_ussub)
+TRANS(xvssub_hu, gvec_xxx, MO_16, tcg_gen_gvec_ussub)
+TRANS(xvssub_wu, gvec_xxx, MO_32, tcg_gen_gvec_ussub)
+TRANS(xvssub_du, gvec_xxx, MO_64, tcg_gen_gvec_ussub)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 78452c622c..be706fe0f7 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1340,6 +1340,24 @@ xvneg_h 0111 01101001 11000 01101 . .
@xx
xvneg_w 0111 01101001 11000 01110 . .@xx
xvneg_d 0111 01101001 11000 0 . .@xx
+xvsadd_b 0111 01000100 01100 . . .@xxx
+xvsadd_h 0111 01000100 01101 . . .@xxx
+xvsadd_w 0111 01000100 01110 . . .@xxx
+xvsadd_d 0111 01000100 0 . . .@xxx
+xvsadd_bu0111 01000100 10100 . . .@xxx
+xvsadd_hu0111 01000100 10101 . . .@xxx
+xvsadd_wu0111 01000100 10110 . . .@xxx
+xvsadd_du0111 01000100 10111 . . .@xxx
+
+xvssub_b 0111 01000100 1 . . .@xxx
+xvssub_h 0111 01000100 10001 . . .@xxx
+xvssub_w 0111 01000100 10010 . . .@xxx
+xvssub_d 0111 01000100 10011 . . .@xxx
+xvssub_bu0111 01000100 11000 . . .@xxx
+xvssub_hu0111 01000100 11001 . . .@xxx
+xvssub_wu0111 01000100 11010 . . .@xxx
+xvssub_du0111 01000100 11011 . . .@xxx
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010 . .@xr
--
2.39.1
[PATCH v1 00/46] Add LoongArch LASX instructions
Hi,
This series adds LoongArch LASX instructions.
About test:
We use RISU test the LoongArch LASX instructions.
QEMU:
https://github.com/loongson/qemu/tree/tcg-old-abi-support-lasx
RISU:
https://github.com/loongson/risu/tree/loongarch-suport-lasx
Please review, Thanks.
Song Gao (46):
target/loongarch: Add LASX data type XReg
target/loongarch: meson.build support build LASX
target/loongarch: Add CHECK_ASXE maccro for check LASX enable
target/loongarch: Implement xvadd/xvsub
target/loongarch: Implement xvreplgr2vr
target/loongarch: Implement xvaddi/xvsubi
target/loongarch: Implement xvneg
target/loongarch: Implement xvsadd/xvssub
target/loongarch: Implement xvhaddw/xvhsubw
target/loongarch: Implement xvaddw/xvsubw
target/loongarch: Implement xavg/xvagr
target/loongarch: Implement xvabsd
target/loongarch: Implement xvadda
target/loongarch: Implement xvmax/xvmin
target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}
target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}
target/loongarch; Implement xvdiv/xvmod
target/loongarch: Implement xvsat
target/loongarch: Implement xvexth
target/loongarch: Implement vext2xv
target/loongarch: Implement xvsigncov
target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz
target/loognarch: Implement xvldi
target/loongarch: Implement LASX logic instructions
target/loongarch: Implement xvsll xvsrl xvsra xvrotr
target/loongarch: Implement xvsllwil xvextl
target/loongarch: Implement xvsrlr xvsrar
target/loongarch: Implement xvsrln xvsran
target/loongarch: Implement xvsrlrn xvsrarn
target/loongarch: Implement xvssrln xvssran
target/loongarch: Implement xvssrlrn xvssrarn
target/loongarch: Implement xvclo xvclz
target/loongarch: Implement xvpcnt
target/loongarch: Implement xvbitclr xvbitset xvbitrev
target/loongarch: Implement xvfrstp
target/loongarch: Implement LASX fpu arith instructions
target/loongarch: Implement LASX fpu fcvt instructions
target/loongarch: Implement xvseq xvsle xvslt
target/loongarch: Implement xvfcmp
target/loongarch: Implement xvbitsel xvset
target/loongarch: Implement xvinsgr2vr xvpickve2gr
target/loongarch: Implement xvreplve xvinsve0 xvpickve xvb{sll/srl}v
target/loongarch: Implement xvpack xvpick xvilv{l/h}
target/loongarch: Implement xvshuf xvperm{i} xvshuf4i xvextrins
target/loongarch: Implement xvld xvst
target/loongarch: CPUCFG support LASX
linux-user/loongarch64/signal.c |1 +
target/loongarch/cpu.c |4 +
target/loongarch/cpu.h | 16 +
target/loongarch/disas.c | 924 +
target/loongarch/gdbstub.c |1 +
target/loongarch/helper.h| 592
target/loongarch/insn_trans/trans_lasx.c.inc | 3203 +
target/loongarch/insns.decode| 828 +
target/loongarch/internals.h | 22 -
target/loongarch/lasx_helper.c | 3221 ++
target/loongarch/lsx_helper.c| 111 +-
target/loongarch/machine.c | 40 +-
target/loongarch/meson.build |1 +
target/loongarch/translate.c | 18 +
target/loongarch/vec.h | 125 +
15 files changed, 9006 insertions(+), 101 deletions(-)
create mode 100644 target/loongarch/insn_trans/trans_lasx.c.inc
create mode 100644 target/loongarch/lasx_helper.c
create mode 100644 target/loongarch/vec.h
--
2.39.1
[PATCH v1 19/46] target/loongarch: Implement xvexth
This patch includes:
- XVEXTH.{H.B/W.H/D.W/Q.D};
- XVEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 +
target/loongarch/helper.h| 9 +
target/loongarch/insn_trans/trans_lasx.c.inc | 20 ++
target/loongarch/insns.decode| 9 +
target/loongarch/lasx_helper.c | 39
5 files changed, 86 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 18fa454be8..5ac374bc63 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1987,6 +1987,15 @@ INSN_LASX(xvsat_hu, xx_i)
INSN_LASX(xvsat_wu, xx_i)
INSN_LASX(xvsat_du, xx_i)
+INSN_LASX(xvexth_h_b,xx)
+INSN_LASX(xvexth_w_h,xx)
+INSN_LASX(xvexth_d_w,xx)
+INSN_LASX(xvexth_q_d,xx)
+INSN_LASX(xvexth_hu_bu, xx)
+INSN_LASX(xvexth_wu_hu, xx)
+INSN_LASX(xvexth_du_wu, xx)
+INSN_LASX(xvexth_qu_du, xx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 741872a24d..17e54eb29a 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -895,3 +895,12 @@ DEF_HELPER_FLAGS_4(xvsat_bu, TCG_CALL_NO_RWG, void, ptr,
ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvsat_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvsat_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvsat_du, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
+DEF_HELPER_3(xvexth_h_b, void, env, i32, i32)
+DEF_HELPER_3(xvexth_w_h, void, env, i32, i32)
+DEF_HELPER_3(xvexth_d_w, void, env, i32, i32)
+DEF_HELPER_3(xvexth_q_d, void, env, i32, i32)
+DEF_HELPER_3(xvexth_hu_bu, void, env, i32, i32)
+DEF_HELPER_3(xvexth_wu_hu, void, env, i32, i32)
+DEF_HELPER_3(xvexth_du_wu, void, env, i32, i32)
+DEF_HELPER_3(xvexth_qu_du, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 350d575a6a..5110cf9a33 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -28,6 +28,17 @@ static bool gen_xxx(DisasContext *ctx, arg_xxx *a,
return true;
}
+static bool gen_xx(DisasContext *ctx, arg_xx *a,
+ void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32))
+{
+TCGv_i32 xd = tcg_constant_i32(a->xd);
+TCGv_i32 xj = tcg_constant_i32(a->xj);
+
+CHECK_SXE;
+func(cpu_env, xd, xj);
+return true;
+}
+
static bool gvec_xxx(DisasContext *ctx, arg_xxx *a, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t))
@@ -1833,6 +1844,15 @@ TRANS(xvsat_hu, gvec_xx_i, MO_16, do_xvsat_u)
TRANS(xvsat_wu, gvec_xx_i, MO_32, do_xvsat_u)
TRANS(xvsat_du, gvec_xx_i, MO_64, do_xvsat_u)
+TRANS(xvexth_h_b, gen_xx, gen_helper_xvexth_h_b)
+TRANS(xvexth_w_h, gen_xx, gen_helper_xvexth_w_h)
+TRANS(xvexth_d_w, gen_xx, gen_helper_xvexth_d_w)
+TRANS(xvexth_q_d, gen_xx, gen_helper_xvexth_q_d)
+TRANS(xvexth_hu_bu, gen_xx, gen_helper_xvexth_hu_bu)
+TRANS(xvexth_wu_hu, gen_xx, gen_helper_xvexth_wu_hu)
+TRANS(xvexth_du_wu, gen_xx, gen_helper_xvexth_du_wu)
+TRANS(xvexth_qu_du, gen_xx, gen_helper_xvexth_qu_du)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 9efb5f2032..98de616846 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1591,6 +1591,15 @@ xvsat_hu 0111 01110010 1 1 . .
@xx_ui4
xvsat_wu 0111 01110010 10001 . . .@xx_ui5
xvsat_du 0111 01110010 1001 .. . .@xx_ui6
+xvexth_h_b 0111 01101001 11101 11000 . .@xx
+xvexth_w_h 0111 01101001 11101 11001 . .@xx
+xvexth_d_w 0111 01101001 11101 11010 . .@xx
+xvexth_q_d 0111 01101001 11101 11011 . .@xx
+xvexth_hu_bu 0111 01101001 11101 11100 . .@xx
+xvexth_wu_hu 0111 01101001 11101 11101 . .@xx
+xvexth_du_wu 0111 01101001 11101 0 . .@xx
+xvexth_qu_du 0111 01101001 11101 1 . .@xx
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .@xr
xvreplgr2vr_w0111 01101001 0 00010 . .@xr
diff --git a/target/loongarch/lasx_helper.c b/target/loongarch/lasx_helper.c
index 33da60f2d8..ca74263c6e 100644
--- a/target/loongarch/lasx_helper.c
+++ b/target/loongarch/lasx_helper.c
@@ -638,3 +638,42 @@ XVSAT_U(xvsat_bu, 8, UXB)
XVSAT_U(xvsat_hu, 16, UXH)
XVSAT_U(xvsat_wu, 32, UXW)
XVSAT_U(xvsat_du, 64, UXD)
+
+#define XVEXTH(NAME, BIT, E1, E2) \
+void HE
[PATCH v1 10/46] target/loongarch: Implement xvaddw/xvsubw
This patch includes:
- XVADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 43 ++
target/loongarch/helper.h| 45 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 410 +++
target/loongarch/insns.decode| 45 ++
target/loongarch/lasx_helper.c | 214 ++
5 files changed, 757 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 770359524e..6e790f0959 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1782,6 +1782,49 @@ INSN_LASX(xvhsubw_wu_hu, xxx)
INSN_LASX(xvhsubw_du_wu, xxx)
INSN_LASX(xvhsubw_qu_du, xxx)
+INSN_LASX(xvaddwev_h_b, xxx)
+INSN_LASX(xvaddwev_w_h, xxx)
+INSN_LASX(xvaddwev_d_w, xxx)
+INSN_LASX(xvaddwev_q_d, xxx)
+INSN_LASX(xvaddwod_h_b, xxx)
+INSN_LASX(xvaddwod_w_h, xxx)
+INSN_LASX(xvaddwod_d_w, xxx)
+INSN_LASX(xvaddwod_q_d, xxx)
+INSN_LASX(xvsubwev_h_b, xxx)
+INSN_LASX(xvsubwev_w_h, xxx)
+INSN_LASX(xvsubwev_d_w, xxx)
+INSN_LASX(xvsubwev_q_d, xxx)
+INSN_LASX(xvsubwod_h_b, xxx)
+INSN_LASX(xvsubwod_w_h, xxx)
+INSN_LASX(xvsubwod_d_w, xxx)
+INSN_LASX(xvsubwod_q_d, xxx)
+
+INSN_LASX(xvaddwev_h_bu, xxx)
+INSN_LASX(xvaddwev_w_hu, xxx)
+INSN_LASX(xvaddwev_d_wu, xxx)
+INSN_LASX(xvaddwev_q_du, xxx)
+INSN_LASX(xvaddwod_h_bu, xxx)
+INSN_LASX(xvaddwod_w_hu, xxx)
+INSN_LASX(xvaddwod_d_wu, xxx)
+INSN_LASX(xvaddwod_q_du, xxx)
+INSN_LASX(xvsubwev_h_bu, xxx)
+INSN_LASX(xvsubwev_w_hu, xxx)
+INSN_LASX(xvsubwev_d_wu, xxx)
+INSN_LASX(xvsubwev_q_du, xxx)
+INSN_LASX(xvsubwod_h_bu, xxx)
+INSN_LASX(xvsubwod_w_hu, xxx)
+INSN_LASX(xvsubwod_d_wu, xxx)
+INSN_LASX(xvsubwod_q_du, xxx)
+
+INSN_LASX(xvaddwev_h_bu_b, xxx)
+INSN_LASX(xvaddwev_w_hu_h, xxx)
+INSN_LASX(xvaddwev_d_wu_w, xxx)
+INSN_LASX(xvaddwev_q_du_d, xxx)
+INSN_LASX(xvaddwod_h_bu_b, xxx)
+INSN_LASX(xvaddwod_w_hu_h, xxx)
+INSN_LASX(xvaddwod_d_wu_w, xxx)
+INSN_LASX(xvaddwod_q_du_d, xxx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index db2deaff79..2034576d87 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -714,3 +714,48 @@ DEF_HELPER_4(xvhsubw_hu_bu, void, env, i32, i32, i32)
DEF_HELPER_4(xvhsubw_wu_hu, void, env, i32, i32, i32)
DEF_HELPER_4(xvhsubw_du_wu, void, env, i32, i32, i32)
DEF_HELPER_4(xvhsubw_qu_du, void, env, i32, i32, i32)
+
+DEF_HELPER_FLAGS_4(xvaddwev_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwev_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwev_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwev_q_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwod_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwod_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwod_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwod_q_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvsubwev_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsubwev_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsubwev_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsubwev_q_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsubwod_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsubwod_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsubwod_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsubwod_q_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvaddwev_h_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwev_w_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwev_d_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwev_q_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwod_h_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwod_w_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwod_d_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvaddwod_q_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(xvsubwev_h_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsubwev_w_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsubwev_d_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsubwev_q_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsubwod_h_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(xvsubwo
[PATCH v1 02/46] target/loongarch: meson.build support build LASX
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_lasx.c.inc | 6 ++
target/loongarch/lasx_helper.c | 6 ++
target/loongarch/meson.build | 1 +
target/loongarch/translate.c | 1 +
4 files changed, 14 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_lasx.c.inc
create mode 100644 target/loongarch/lasx_helper.c
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
new file mode 100644
index 00..56a9839255
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LASX translate functions
+ * Copyright (c) 2023 Loongson Technology Corporation Limited
+ */
+
diff --git a/target/loongarch/lasx_helper.c b/target/loongarch/lasx_helper.c
new file mode 100644
index 00..1754790a3a
--- /dev/null
+++ b/target/loongarch/lasx_helper.c
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch LASX helper functions.
+ *
+ * Copyright (c) 2023 Loongson Technology Corporation Limited
+ */
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index 1117a51c52..90a5a21977 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -12,6 +12,7 @@ loongarch_tcg_ss.add(files(
'translate.c',
'gdbstub.c',
'lsx_helper.c',
+ 'lasx_helper.c',
))
loongarch_tcg_ss.add(zlib)
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 3146a2d4ac..6bf2d726d6 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -220,6 +220,7 @@ static void set_fpr(int reg_num, TCGv val)
#include "insn_trans/trans_branch.c.inc"
#include "insn_trans/trans_privileged.c.inc"
#include "insn_trans/trans_lsx.c.inc"
+#include "insn_trans/trans_lasx.c.inc"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
--
2.39.1
[PATCH v1 06/46] target/loongarch: Implement xvaddi/xvsubi
This patch includes:
- XVADDI.{B/H/W/D}U;
- XVSUBI.{B/H/W/D}U.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 14
target/loongarch/insn_trans/trans_lasx.c.inc | 37
target/loongarch/insns.decode| 12 ++-
3 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 78e1fd19ac..7b84766fa8 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1708,6 +1708,11 @@ static void output_xxx(DisasContext *ctx, arg_xxx * a,
const char *mnemonic)
output(ctx, mnemonic, "x%d, x%d, x%d", a->xd, a->xj, a->xk);
}
+static void output_xx_i(DisasContext *ctx, arg_xx_i *a, const char *mnemonic)
+{
+output(ctx, mnemonic, "x%d, x%d, 0x%x", a->xd, a->xj, a->imm);
+}
+
static void output_xr(DisasContext *ctx, arg_xr *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, r%d", a->xd, a->rj);
@@ -1724,6 +1729,15 @@ INSN_LASX(xvsub_w, xxx)
INSN_LASX(xvsub_d, xxx)
INSN_LASX(xvsub_q, xxx)
+INSN_LASX(xvaddi_bu, xx_i)
+INSN_LASX(xvaddi_hu, xx_i)
+INSN_LASX(xvaddi_wu, xx_i)
+INSN_LASX(xvaddi_du, xx_i)
+INSN_LASX(xvsubi_bu, xx_i)
+INSN_LASX(xvsubi_hu, xx_i)
+INSN_LASX(xvsubi_wu, xx_i)
+INSN_LASX(xvsubi_du, xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index d394a4f40a..a42e92f930 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -31,6 +31,34 @@ static bool gvec_xxx(DisasContext *ctx, arg_xxx *a, MemOp
mop,
return true;
}
+static bool gvec_xx_i(DisasContext *ctx, arg_xx_i *a, MemOp mop,
+ void (*func)(unsigned, uint32_t, uint32_t,
+ int64_t, uint32_t, uint32_t))
+{
+uint32_t xd_ofs, xj_ofs;
+
+CHECK_ASXE;
+
+xd_ofs = vec_full_offset(a->xd);
+xj_ofs = vec_full_offset(a->xj);
+
+func(mop, xd_ofs, xj_ofs, a->imm , 32, ctx->vl / 8);
+return true;
+}
+
+static bool gvec_xsubi(DisasContext *ctx, arg_xx_i *a, MemOp mop)
+{
+uint32_t xd_ofs, xj_ofs;
+
+CHECK_ASXE;
+
+xd_ofs = vec_full_offset(a->xd);
+xj_ofs = vec_full_offset(a->xj);
+
+tcg_gen_gvec_addi(mop, xd_ofs, xj_ofs, -a->imm, 32, ctx->vl / 8);
+return true;
+}
+
TRANS(xvadd_b, gvec_xxx, MO_8, tcg_gen_gvec_add)
TRANS(xvadd_h, gvec_xxx, MO_16, tcg_gen_gvec_add)
TRANS(xvadd_w, gvec_xxx, MO_32, tcg_gen_gvec_add)
@@ -74,6 +102,15 @@ TRANS(xvsub_h, gvec_xxx, MO_16, tcg_gen_gvec_sub)
TRANS(xvsub_w, gvec_xxx, MO_32, tcg_gen_gvec_sub)
TRANS(xvsub_d, gvec_xxx, MO_64, tcg_gen_gvec_sub)
+TRANS(xvaddi_bu, gvec_xx_i, MO_8, tcg_gen_gvec_addi)
+TRANS(xvaddi_hu, gvec_xx_i, MO_16, tcg_gen_gvec_addi)
+TRANS(xvaddi_wu, gvec_xx_i, MO_32, tcg_gen_gvec_addi)
+TRANS(xvaddi_du, gvec_xx_i, MO_64, tcg_gen_gvec_addi)
+TRANS(xvsubi_bu, gvec_xsubi, MO_8)
+TRANS(xvsubi_hu, gvec_xsubi, MO_16)
+TRANS(xvsubi_wu, gvec_xsubi, MO_32)
+TRANS(xvsubi_du, gvec_xsubi, MO_64)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 2eab7f6a98..0bed748216 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1303,7 +1303,7 @@ vstelm_b 0011 000110 . .
@vr_i8i4
&xxx xd xj xk
&xr xd rj
-
+&xx_i xd xj imm
#
# LASX Formats
@@ -1311,6 +1311,7 @@ vstelm_b 0011 000110 . .
@vr_i8i4
@xxx . xk:5 xj:5 xd:5&xxx
@xr . . rj:5 xd:5&xr
+@xx_ui5 . imm:5 xj:5 xd:5&xx_i
xvadd_b 0111 0100 10100 . . .@xxx
xvadd_h 0111 0100 10101 . . .@xxx
@@ -1323,6 +1324,15 @@ xvsub_w 0111 0100 11010 . . .
@xxx
xvsub_d 0111 0100 11011 . . .@xxx
xvsub_q 0111 01010010 11011 . . .@xxx
+xvaddi_bu0111 01101000 10100 . . .@xx_ui5
+xvaddi_hu0111 01101000 10101 . . .@xx_ui5
+xvaddi_wu0111 01101000 10110 . . .@xx_ui5
+xvaddi_du0111 01101000 10111 . . .@xx_ui5
+xvsubi_bu0111 01101000 11000 . . .@xx_ui5
+xvsubi_hu0111 01101000 11001 . . .@xx_ui5
+xvsubi_wu0111 01101000 11010 . . .@xx_ui5
+xvsubi_du0111 01101000 11011 . . .@xx_ui5
+
xvreplgr2vr_b0111 01101001 0 0 . .@xr
xvreplgr2vr_h0111 01101001 0 1 . .
Re: [PATCH v2] vfio/migration: Refactor and fix print of "Migration disabled"
On 20/06/2023 09:55, Duan, Zhenzhong wrote:
>> -Original Message-
>> From: Joao Martins
>> Sent: Tuesday, June 20, 2023 4:23 PM
>> To: Duan, Zhenzhong ; Avihai Horon
>> ; qemu-devel@nongnu.org
>> Cc: alex.william...@redhat.com; c...@redhat.com; Peng, Chao P
>>
>> Subject: Re: [PATCH v2] vfio/migration: Refactor and fix print of "Migration
>> disabled"
>>
>> On 20/06/2023 04:04, Duan, Zhenzhong wrote:
-Original Message-
From: Avihai Horon
Sent: Monday, June 19, 2023 7:14 PM
>>> ...
> a/hw/vfio/migration.c b/hw/vfio/migration.c index
> 6b58dddb8859..bc51aa765cb8 100644
> --- a/hw/vfio/migration.c
> +++ b/hw/vfio/migration.c
> @@ -632,42 +632,41 @@ int64_t vfio_mig_bytes_transferred(void)
> return bytes_transferred;
> }
>
> -int vfio_migration_realize(VFIODevice *vbasedev, Error **errp)
> +bool vfio_migration_realize(VFIODevice *vbasedev, Error **errp)
> {
> -int ret = -ENOTSUP;
> +int ret;
>
> -if (!vbasedev->enable_migration) {
> +if (!vbasedev->enable_migration || vfio_migration_init(vbasedev)) {
> +error_setg(&vbasedev->migration_blocker,
> + "VFIO device doesn't support migration");
> goto add_blocker;
> }
>
> -ret = vfio_migration_init(vbasedev);
> -if (ret) {
> +if (vfio_block_multiple_devices_migration(errp)) {
> +error_setg(&vbasedev->migration_blocker,
> + "Migration is currently not supported with multiple "
> + "VFIO devices");
> goto add_blocker;
> }
Here you are tying the multiple devices blocker to a specific device.
This could be problematic:
If you add vfio device #1 and then device #2 then the blocker will be
added to device #2. If you then remove device #1, migration will
still be blocked although it shouldn't.
I think we should keep it as a global blocker and not a per-device blocker.
>>>
>>> Thanks for point out, you are right, seems I need to restore the multiple
>> devices part code.
>>
>> It's the same for vIOMMU migration blocker. You could have a machine with
>> default_bus_bypass_iommu=on and add device #1 with bypass_iommu=off
>> attribute in pxb PCI port, and then add device #2 with bypass_iommu=on. The
>> blocker is added because of device #1 but then it will remain blocked if you
>> remove it.
>
> Right, thanks for point out, I'm thinking about changing vfio_viommu_preset()
> to check corresponding device's address space rather than all vfio devices'.
>
> Let me know if you prefer to restore vIOMMU blocker as global too, then I'll
> not
> try with my idea furtherly.
The vIOMMU migration blocker doesn't need to be global, true, as it doesn't care
about others address space -- if each device has a blocker as long as the one
device blocker is removed it should become make VM migratable again (but atm we
will be blocked by the multi device blocker anyway). This should consolidate
things into a single migration blocker and avoid the special path. I am not
enterily sure if the refactor will give *that* much gain but that's probably
because I haven't seen the final result.
IIUC the problem with this patch is that you remove what unblocks the migration,
and I guess that need to stay there for the global case.
Re: [PATCH 4/4] spapr: Allow up to 8 threads SMT on POWER8 and newer
On 6/5/23 16:53, Nicholas Piggin wrote:
PPC TCG now supports multi-threaded CPU configuration for non-hypervisor
state. This requires PIR and TIR be set, because that's how sibling thread
matching is done.
spapr's nested-HV capability does not currently coexist with SMT. This
is quite analogous to LPAR-per-core mode on real hardware which also
does not support KVM.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 16
hw/ppc/spapr_caps.c | 14 ++
hw/ppc/spapr_cpu_core.c | 7 +--
3 files changed, 31 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index dcb7f1c70a..deb8b507e3 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2524,10 +2524,18 @@ static void spapr_set_vsmt_mode(SpaprMachineState
*spapr, Error **errp)
int ret;
unsigned int smp_threads = ms->smp.threads;
-if (!kvm_enabled() && (smp_threads > 1)) {
-error_setg(errp, "TCG cannot support more than 1 thread/core "
- "on a pseries machine");
-return;
+if (!kvm_enabled()) {
Can we make it a check for tcg_enabled() which would be more appropriate
or as Cedric suggested, may be include this one along with your series:
https://lore.kernel.org/qemu-devel/20230620074802.86898-1-phi...@linaro.org/
regards,
Harsh
+if (!ppc_type_check_compat(ms->cpu_type, CPU_POWERPC_LOGICAL_2_07, 0,
+ spapr->max_compat_pvr)) {
+error_setg(errp, "TCG only supports SMT on POWER8 or newer CPUs");
+return;
+}
+
+if (smp_threads > 8) {
+error_setg(errp, "TCG cannot support more than 8 threads/core "
+ "on a pseries machine");
+return;
+}
}
if (!is_power_of_2(smp_threads)) {
error_setg(errp, "Cannot support %d threads/core on a pseries "
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 3fd45a6dec..03f02b4af3 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -473,6 +473,20 @@ static void cap_nested_kvm_hv_apply(SpaprMachineState
*spapr,
error_append_hint(errp,
"Try appending -machine
cap-nested-hv=off\n");
}
+} else {
+MachineState *ms = MACHINE(spapr);
+unsigned int smp_threads = ms->smp.threads;
+
+/*
+ * Nested-HV vCPU env state to L2, so SMT-shared SPR updates, for
+ * example, do not necessarily update the correct SPR value on sibling
+ * threads that are in a different guest/host context.
+ */
+if (smp_threads > 1) {
+error_setg(errp, "TCG does not support nested-HV with SMT");
+error_append_hint(errp, "Try appending -machine cap-nested-hv=off "
+"or use threads=1 with -smp\n");
+}
}
}
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 9b88dd549a..a4e3c2fadd 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -255,7 +255,7 @@ static void spapr_cpu_core_unrealize(DeviceState *dev)
}
static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
- SpaprCpuCore *sc, Error **errp)
+ SpaprCpuCore *sc, int thread_index, Error
**errp)
{
CPUPPCState *env = &cpu->env;
CPUState *cs = CPU(cpu);
@@ -267,6 +267,9 @@ static bool spapr_realize_vcpu(PowerPCCPU *cpu,
SpaprMachineState *spapr,
cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
kvmppc_set_papr(cpu);
+env->spr_cb[SPR_PIR].default_value = cs->cpu_index;
+env->spr_cb[SPR_TIR].default_value = thread_index;
+
/* Set time-base frequency to 512 MHz. vhyp must be set first. */
cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
@@ -337,7 +340,7 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
for (i = 0; i < cc->nr_threads; i++) {
sc->threads[i] = spapr_create_vcpu(sc, i, errp);
if (!sc->threads[i] ||
-!spapr_realize_vcpu(sc->threads[i], spapr, sc, errp)) {
+!spapr_realize_vcpu(sc->threads[i], spapr, sc, i, errp)) {
spapr_cpu_core_unrealize(dev);
return;
}
Re: [PATCH v7] Emulate dip switch language layout settings on SUN keyboard
On Sun, Jun 11, 2023 at 01:47:51AM +0200, Henrik Carlqvist wrote: > I have now changed the patch to instead use > > -global escc.chnA-sunkbd-layout= > > and documented in docs/system/keyboard.rst which I have linked from > target-sparc.rst. Unfortunately, I am not very used to these .rst files > and have not found out how to create html files from them, so I don't know > for sure if my formatting is correct. Typing "make help" seems to indicate > that it should be possible to type "make html", but that did not seem to work. Assuming you have docutils installed, QEMU will build the manual by default and print any issues on console during build. You can point your browser to $BUILD/docs/manual/system/index.html to see the result. For future reference, if you want to put some questions/notes in the submission, it is best to keep them separate from the commit message text, as the questions/notes shouldn't end up in git history. To separate them, put questions immediately after the '---' that separate the commit message from the diffstat > > SUN Type 4, 5 and 5c keyboards have dip switches to choose > the language layout of the keyboard. Solaris makes an ioctl to query the > value of the dipswitches and uses that value to select keyboard layout. Also > the SUN bios like the one in the file ss5.bin uses this value to support at > least some keyboard layouts. However, the OpenBIOS provided with qemu is > hardcoded to always use an US keyboard layout. > > Before this patch, qemu allways gave dip switch value 0x21 (US keyboard), > this patch uses a command line switch like > "-global escc.chnA-sunkbd-layout=de" to select dip switch value. A table is > used to lookup values from arguments like: > > -global escc.chnA-sunkbd-layout=fr > -global escc.chnA-sunkbd-layout=es > > But the patch also accepts numeric dip switch values directly: > > -global escc.chnA-sunkbd-layout=0x2b > -global escc.chnA-sunkbd-layout=43 > > Both values above are the same and select swedish keyboard as explained in > table 3-15 at > https://docs.oracle.com/cd/E19683-01/806-6642/new-43/index.html > > Unless you want to do a full Solaris installation but happen to have > access to a Sun bios file, the easiest way to test that the patch works > is to: > > qemu-system-sparc -global escc.chnA-sunkbd-layout=sv -bios /path/to/ss5.bin > > If you already happen to have a Solaris installation in a qemu disk image > file you can easily try different keyboard layouts after this patch is > applied. > > Signed-off-by: Henrik Carlqvist > --- notes/questions go here > docs/system/keyboard.rst | 127 +++ > docs/system/target-sparc.rst | 2 +- > hw/char/escc.c | 76 - > include/hw/char/escc.h | 1 + > 4 files changed, 204 insertions(+), 2 deletions(-) > create mode 100644 docs/system/keyboard.rst > > diff --git a/docs/system/keyboard.rst b/docs/system/keyboard.rst > new file mode 100644 > index 00..b489c607f8 > --- /dev/null > +++ b/docs/system/keyboard.rst > @@ -0,0 +1,127 @@ > +.. _keyboard: > + > +Sparc32 keyboard > + > +SUN Type 4, 5 and 5c keyboards have dip switches to choose the language > layout > +of the keyboard. Solaris makes an ioctl to query the value of the > dipswitches > +and uses that value to select keyboard layout. Also the SUN bios like the > one > +in the file ss5.bin uses this value to support at least some keyboard > layouts. > +However, the OpenBIOS provided with qemu is hardcoded to always use an > +US keyboard layout. > + > +With the escc.chnA-sunkbd-layout driver property it is possible to select > +keyboard layout. Example: > + > +"-global escc.chnA-sunkbd-layout=de" > + > +Depending on type of keyboard, the keyboard can have 6 or 5 dip-switches to > +select keyboard layout, giving up to 64 different layouts. Not all > +combinations are supported by Solaris and even less by Sun OpenBoot BIOS. > + > +The dip switch settings can be given as hexadecimal number, decimal number > +or in some cases as a language string. Examples: > + > +-global escc.chnA-sunkbd-layout=0x2b > +-global escc.chnA-sunkbd-layout=43 > +-global escc.chnA-sunkbd-layout=sv > + > +The above 3 examples all select a swedish keyboard layout. Table 3-15 at > +https://docs.oracle.com/cd/E19683-01/806-6642/new-43/index.html explains > which > +keytable file is used for different dip switch settings. The information > +in that table can be summarized in this table: > + > +.. list-table:: Language selection values for escc.chnA-sunkbd-layout > + :widths: 10 10 10 > + :header-rows: 1 > + > + * - Hexadecimal value > + - Decimal value > + - Language code > + * - 0x21 > + - 33 > + - en-us > + * - 0x23 > + - 35 > + - fr > + * - 0x24 > + - 36 > + - da > + * - 0x25 > + - 37 > + - de > + * - 0x26 > + - 38 > + - it > + * - 0x27 > + - 39 > + - nl > + * - 0x28 >
Re: [QEMU PATCH 1/1] virtgpu: do not destroy resources when guest suspend
Hi Gerd Hoffmann On 2023/6/19 20:51, Gerd Hoffmann wrote: > Hi, >> Adding a new command requires new feature flag (and maybe it should be in >> the <0x1000 range instead) >> >> But I am not sure we need a new message at the virtio-gpu level. Gerd, wdyt? >> >> Maybe it's not a good place to reset all GPU resources during QEMU reset() >> after all, if it's called during s3 and there is no mechanism to restore >> it. Damien? > > The guest driver should be able to restore resources after resume. Thank you for your suggestion! As far as I know, resources are created on host side and guest has no backup, if resources are destroyed, guest can't restore them. Or do you mean guest driver need to send commands to re-create resources after resume? If so, I have some questions. Can guest re-create resources by using object(virtio_vpu_object) or others? Can the new resources replace the destroyed resources to continue the suspended display tasks after resume? I think those will help me improve my implementation, thank you! > > take care, > Gerd > -- Best regards, Jiqian Chen.
Re: [PATCH 8/9] ppc/pnv: Rephrase error when run with KVM
On 6/20/23 07:59, Cédric Le Goater wrote: Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 7/9] ppc/bamboo: Report an error when run with KVM
On 6/20/23 07:59, Cédric Le Goater wrote: The 'bamboo' machine was used as a KVM platform in the early days (~2008). It clearly doesn't support it anymore. Signed-off-by: Cédric Le Goater --- hw/ppc/ppc440_bamboo.c | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 5/9] ppc/pegasos2: Report an error when run with KVM
On 6/20/23 07:59, Cédric Le Goater wrote: The 'pegasos2' machine never supported KVM. This piece of code was inherited from another model. Cc: BALATON Zoltan Signed-off-by: Cédric Le Goater --- hw/ppc/pegasos2.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 4/9] ppc/prep: Report an error when run with KVM
On 6/20/23 07:59, Cédric Le Goater wrote: The 'prep' machine never supported KVM. This piece of code was probably inherited from another model. Cc: Hervé Poussineau Signed-off-by: Cédric Le Goater --- hw/ppc/prep.c | 20 +++- 1 file changed, 7 insertions(+), 13 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 6/9] ppc/sam460ex: Report an error when run with KVM
On 6/20/23 07:59, Cédric Le Goater wrote: The 'sam460ex' machine never supported KVM. This piece of code was inherited from another model. Cc: BALATON Zoltan Signed-off-by: Cédric Le Goater --- hw/ppc/sam460ex.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 3/9] MAINTAINERS: Add reviewer for XIVE
On 6/20/23 07:59, Cédric Le Goater wrote: Fred discusses frequently with the IBM HW designers, he is fluent in XIVE logic, add him as a reviewer. Cc: Frédéric Barrat Signed-off-by: Cédric Le Goater --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) Reviewed-by: Richard Henderson r~
Re: [PATCH 2/9] MAINTAINERS: Add reviewer for PowerPC TCG CPUs
On 6/20/23 07:59, Cédric Le Goater wrote: Nick has great knowledge of the PowerPC CPUs, software and hardware. Add him as a reviewer on CPU TCG modeling. Cc: Nicholas Piggin Signed-off-by: Cédric Le Goater --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) Reviewed-by: Richard Henderson r~
Re: [PATCH 1/9] MAINTAINERS: Add reviewers for PowerNV baremetal emulation
On 6/20/23 07:59, Cédric Le Goater wrote: Fred and Nick have been hacking baremetal POWER systems (OPAL) for many years. They use and modify the QEMU models regularly. Add them as PowerNV reviewers. Cc: Frédéric Barrat Cc: Nicholas Piggin Signed-off-by: Cédric Le Goater --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) Reviewed-by: Richard Henderson r~
Re: [PATCH 9/9] target/ppc: Fix timer register accessors when !KVM
On 6/20/23 07:59, Cédric Le Goater wrote:
When the Timer Control and Timer Status registers are modified, avoid
calling the KVM backend when not available
Signed-off-by: Cédric Le Goater
---
target/ppc/kvm.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index a7f2de9d1018..a8a935e26726 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -1728,6 +1728,10 @@ int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t
tsr_bits)
.addr = (uintptr_t) &bits,
};
+if (!kvm_enabled()) {
+return 0;
+}
assert(kvm_enabled()) ?
r~
Re: [PATCH v3 08/34] target/arm/tcg: Un-inline VFP translation helpers
On 6/19/23 17:42, Philippe Mathieu-Daudé wrote: In order to restrict lookup_cp_reg() and set_rmode() helpers to VFP translation, un-inline gen_lookup_cp_reg and gen_set / gen_restore_rmode. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/tcg/translate.h | 22 +++--- target/arm/tcg/translate-vfp.c | 21 + 2 files changed, 24 insertions(+), 19 deletions(-) While set_rmode is vfp, lookup_cp_reg is not. However, you could uninline lookup_cp_reg to translate.c. r~
Re: [PATCH v4] hw/pci: enforce use of slot only slot 0 when devices have an upstream PCIE port
On Tue, 20 Jun 2023 12:48:05 +0530
Ani Sinha wrote:
> When a device has an upstream PCIE port, we can only use slot 0. Non-zero
> slots
> are invalid.
> This change ensures that we throw an error if the user
> tries to hotplug a device with an upstream PCIE port to a non-zero slot.
Isn't the same true for coldplugged devices?
Why you limit it only to hotplug?
>
> CC: jus...@redhat.com
> CC: imamm...@redhat.com
> Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=2128929
> Signed-off-by: Ani Sinha
> ---
> hw/pci/pci.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> changelog:
> v2: addressed issue with multifunction pcie root ports. Should allow
> hotplug on functions other than function 0.
> v3: improved commit message.
> v4: improve commit message and code comments further. Some more
> improvements might come in v5. No claims made here that this is
> the final one :-)
>
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index bf38905b7d..30ce6a78cb 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -64,6 +64,7 @@ bool pci_available = true;
> static char *pcibus_get_dev_path(DeviceState *dev);
> static char *pcibus_get_fw_dev_path(DeviceState *dev);
> static void pcibus_reset(BusState *qbus);
> +static bool pcie_has_upstream_port(PCIDevice *dev);
>
> static Property pci_props[] = {
> DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
> @@ -1182,6 +1183,11 @@ static PCIDevice *do_pci_register_device(PCIDevice
> *pci_dev,
> } else if (dev->hotplugged &&
> !pci_is_vf(pci_dev) &&
> pci_get_function_0(pci_dev)) {
> +/*
> + * populating function 0 triggers a bus scan from the guest that
> + * exposes other non-zero functions. Hence we need to ensure that
> + * function 0 wasn't added yet.
> + */
> error_setg(errp, "PCI: slot %d function 0 already occupied by %s,"
> " new func %s cannot be exposed to guest.",
> PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
> @@ -1189,6 +1195,18 @@ static PCIDevice *do_pci_register_device(PCIDevice
> *pci_dev,
> name);
>
> return NULL;
> +} else if (dev->hotplugged &&
> + !pci_is_vf(pci_dev) &&
> + pcie_has_upstream_port(pci_dev) && PCI_SLOT(devfn)) {
> +/*
> + * If the device has an upstream PCIE port, like a pcie root port,
> + * we only support functions on slot 0.
> + */
> +error_setg(errp, "PCI: slot %d is not valid for %s,"
> + " only functions on slot 0 is supported for devices"
> + " with an upstream PCIE port.",
upstream port language is confusing here and elsewhere you mention it.
It would be better to use root-port instead.
> + PCI_SLOT(devfn), name);
> +return NULL;
> }
>
> pci_dev->devfn = devfn;
Re: [PATCH] x86_64/atomic128-ldst.h: fix arch include guard
On 6/20/23 10:39, Frédéric Pétrot wrote: Fix arch name in the define that prevents multiple inclusions. Signed-off-by: Frédéric Pétrot --- host/include/x86_64/host/atomic128-ldst.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Whoopsie. Reviewed-by: Richard Henderson r~ diff --git a/host/include/x86_64/host/atomic128-ldst.h b/host/include/x86_64/host/atomic128-ldst.h index adc9332f91..d0240d4212 100644 --- a/host/include/x86_64/host/atomic128-ldst.h +++ b/host/include/x86_64/host/atomic128-ldst.h @@ -8,8 +8,8 @@ * atomic primitive is meant to provide. */ -#ifndef AARCH64_ATOMIC128_LDST_H -#define AARCH64_ATOMIC128_LDST_H +#ifndef X86_64_ATOMIC128_LDST_H +#define X86_64_ATOMIC128_LDST_H #ifdef CONFIG_INT128_TYPE #include "host/cpuinfo.h" @@ -65,4 +65,4 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) #include "host/include/generic/host/atomic128-ldst.h" #endif -#endif /* AARCH64_ATOMIC128_LDST_H */ +#endif /* X86_64_ATOMIC128_LDST_H */
RE: [PATCH v2] vfio/migration: Refactor and fix print of "Migration disabled"
>-Original Message-
>From: Joao Martins
>Sent: Tuesday, June 20, 2023 4:23 PM
>To: Duan, Zhenzhong ; Avihai Horon
>; qemu-devel@nongnu.org
>Cc: alex.william...@redhat.com; c...@redhat.com; Peng, Chao P
>
>Subject: Re: [PATCH v2] vfio/migration: Refactor and fix print of "Migration
>disabled"
>
>On 20/06/2023 04:04, Duan, Zhenzhong wrote:
>>> -Original Message-
>>> From: Avihai Horon
>>> Sent: Monday, June 19, 2023 7:14 PM
>> ...
a/hw/vfio/migration.c b/hw/vfio/migration.c index
6b58dddb8859..bc51aa765cb8 100644
--- a/hw/vfio/migration.c
+++ b/hw/vfio/migration.c
@@ -632,42 +632,41 @@ int64_t vfio_mig_bytes_transferred(void)
return bytes_transferred;
}
-int vfio_migration_realize(VFIODevice *vbasedev, Error **errp)
+bool vfio_migration_realize(VFIODevice *vbasedev, Error **errp)
{
-int ret = -ENOTSUP;
+int ret;
-if (!vbasedev->enable_migration) {
+if (!vbasedev->enable_migration || vfio_migration_init(vbasedev)) {
+error_setg(&vbasedev->migration_blocker,
+ "VFIO device doesn't support migration");
goto add_blocker;
}
-ret = vfio_migration_init(vbasedev);
-if (ret) {
+if (vfio_block_multiple_devices_migration(errp)) {
+error_setg(&vbasedev->migration_blocker,
+ "Migration is currently not supported with multiple "
+ "VFIO devices");
goto add_blocker;
}
>>>
>>> Here you are tying the multiple devices blocker to a specific device.
>>> This could be problematic:
>>> If you add vfio device #1 and then device #2 then the blocker will be
>>> added to device #2. If you then remove device #1, migration will
>>> still be blocked although it shouldn't.
>>>
>>> I think we should keep it as a global blocker and not a per-device blocker.
>>
>> Thanks for point out, you are right, seems I need to restore the multiple
>devices part code.
>
>It's the same for vIOMMU migration blocker. You could have a machine with
>default_bus_bypass_iommu=on and add device #1 with bypass_iommu=off
>attribute in pxb PCI port, and then add device #2 with bypass_iommu=on. The
>blocker is added because of device #1 but then it will remain blocked if you
>remove it.
Right, thanks for point out, I'm thinking about changing vfio_viommu_preset()
to check corresponding device's address space rather than all vfio devices'.
Let me know if you prefer to restore vIOMMU blocker as global too, then I'll not
try with my idea furtherly.
Regards
Zhenzhong
Re: [PATCH] hw/ppc/spapr: Test whether TCG is enabled with tcg_enabled()
On Tue, Jun 20, 2023 at 09:48:02AM +0200, Philippe Mathieu-Daudé wrote:
> Although the PPC target only supports the TCG and KVM
> accelerators, QEMU supports more. We can no assume that
> '!kvm == tcg', so test for the correct accelerator. This
> also eases code review, because here we don't care about
> KVM, we really want to test for TCG.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: David Gibson
> ---
> hw/ppc/spapr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index dcb7f1c70a..c4b666587b 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -2524,7 +2524,7 @@ static void spapr_set_vsmt_mode(SpaprMachineState
> *spapr, Error **errp)
> int ret;
> unsigned int smp_threads = ms->smp.threads;
>
> -if (!kvm_enabled() && (smp_threads > 1)) {
> +if (tcg_enabled() && (smp_threads > 1)) {
> error_setg(errp, "TCG cannot support more than 1 thread/core "
> "on a pseries machine");
> return;
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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[PATCH] x86_64/atomic128-ldst.h: fix arch include guard
Fix arch name in the define that prevents multiple inclusions. Signed-off-by: Frédéric Pétrot --- host/include/x86_64/host/atomic128-ldst.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/host/include/x86_64/host/atomic128-ldst.h b/host/include/x86_64/host/atomic128-ldst.h index adc9332f91..d0240d4212 100644 --- a/host/include/x86_64/host/atomic128-ldst.h +++ b/host/include/x86_64/host/atomic128-ldst.h @@ -8,8 +8,8 @@ * atomic primitive is meant to provide. */ -#ifndef AARCH64_ATOMIC128_LDST_H -#define AARCH64_ATOMIC128_LDST_H +#ifndef X86_64_ATOMIC128_LDST_H +#define X86_64_ATOMIC128_LDST_H #ifdef CONFIG_INT128_TYPE #include "host/cpuinfo.h" @@ -65,4 +65,4 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) #include "host/include/generic/host/atomic128-ldst.h" #endif -#endif /* AARCH64_ATOMIC128_LDST_H */ +#endif /* X86_64_ATOMIC128_LDST_H */ -- 2.30.2
