CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Fri May 3 07:24:31 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: cpu_subr.c
Log Message:
Small simplification. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/cpu_subr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/cpu_subr.c
diff -u src/sys/arch/riscv/riscv/cpu_subr.c:1.4 src/sys/arch/riscv/riscv/cpu_subr.c:1.5
--- src/sys/arch/riscv/riscv/cpu_subr.c:1.4 Sun Sep 3 08:48:20 2023
+++ src/sys/arch/riscv/riscv/cpu_subr.c Fri May 3 07:24:31 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_subr.c,v 1.4 2023/09/03 08:48:20 skrll Exp $ */
+/* $NetBSD: cpu_subr.c,v 1.5 2024/05/03 07:24:31 skrll Exp $ */
/*-
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#include "opt_riscv_debug.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.4 2023/09/03 08:48:20 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.5 2024/05/03 07:24:31 skrll Exp $");
#include
#include
@@ -212,7 +212,7 @@ cpu_ipi_wait(const char *s, const kcpuse
kcpuset_t *kcp = ci->ci_watchcpus;
/* some finite amount of time */
- for (u_long limit = curcpu()->ci_cpu_freq /* / 10 */; !done && limit--; ) {
+ for (u_long limit = ci->ci_cpu_freq /* / 10 */; !done && limit--; ) {
kcpuset_copy(kcp, watchset);
kcpuset_intersect(kcp, wanted);
done = kcpuset_match(kcp, wanted);
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Fri May 3 07:24:31 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: cpu_subr.c Log Message: Small simplification. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/cpu_subr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: riastradh
Date: Sun Apr 7 22:59:13 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c
Log Message:
riscv: Schedule next hardclock tick in the future, not the past.
If we have missed hardclock ticks, schedule up to one tick interval
in the future anyway; don't try to play hardclock catchup by
scheduling for when the next hardclock tick _should_ have been, in
the past, leading to ticking as fast as possible until we've caught
up. as fast as possible until we've caught up.
Playing hardclock catchup triggers heartbeat panics when continuing
from ddb, if you've been in ddb for >15sec. Other hardclock drivers
like x86 lapic don't play hardclock catchup either.
PR kern/57920
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/riscv/clock_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/clock_machdep.c
diff -u src/sys/arch/riscv/riscv/clock_machdep.c:1.7 src/sys/arch/riscv/riscv/clock_machdep.c:1.8
--- src/sys/arch/riscv/riscv/clock_machdep.c:1.7 Thu Jan 18 07:41:50 2024
+++ src/sys/arch/riscv/riscv/clock_machdep.c Sun Apr 7 22:59:13 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: clock_machdep.c,v 1.7 2024/01/18 07:41:50 skrll Exp $ */
+/* $NetBSD: clock_machdep.c,v 1.8 2024/04/07 22:59:13 riastradh Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: clock_machdep.c,v 1.7 2024/01/18 07:41:50 skrll Exp $");
+__RCSID("$NetBSD: clock_machdep.c,v 1.8 2024/04/07 22:59:13 riastradh Exp $");
#include
#include
@@ -124,6 +124,10 @@ riscv_timer_intr(void *arg)
ci->ci_ev_timer.ev_count++;
ci->ci_lastintr_scheduled += timer_ticks_per_hz;
+ while (__predict_false(ci->ci_lastintr_scheduled < now)) {
+ ci->ci_lastintr_scheduled += timer_ticks_per_hz;
+ /* XXX count missed timer interrupts */
+ }
sbi_set_timer(ci->ci_lastintr_scheduled);
hardclock(cf);
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: riastradh Date: Sun Apr 7 22:59:13 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: clock_machdep.c Log Message: riscv: Schedule next hardclock tick in the future, not the past. If we have missed hardclock ticks, schedule up to one tick interval in the future anyway; don't try to play hardclock catchup by scheduling for when the next hardclock tick _should_ have been, in the past, leading to ticking as fast as possible until we've caught up. as fast as possible until we've caught up. Playing hardclock catchup triggers heartbeat panics when continuing from ddb, if you've been in ddb for >15sec. Other hardclock drivers like x86 lapic don't play hardclock catchup either. PR kern/57920 To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/riscv/clock_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: riastradh
Date: Sun Apr 7 22:52:53 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: cpu.c
Log Message:
riscv: Make sure cpu0->ci_cpu_freq is initialized by cpu_attach.
Otherwise this stays zero, which screws up cpu_ipi_wait.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/cpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/cpu.c
diff -u src/sys/arch/riscv/riscv/cpu.c:1.5 src/sys/arch/riscv/riscv/cpu.c:1.6
--- src/sys/arch/riscv/riscv/cpu.c:1.5 Sun Sep 3 08:48:20 2023
+++ src/sys/arch/riscv/riscv/cpu.c Sun Apr 7 22:52:53 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.5 2023/09/03 08:48:20 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.6 2024/04/07 22:52:53 riastradh Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.5 2023/09/03 08:48:20 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.6 2024/04/07 22:52:53 riastradh Exp $");
#include
@@ -184,6 +184,7 @@ cpu_attach(device_t dv, cpuid_t hartid)
ci = curcpu();
KASSERTMSG(ci == _info_store[0], "ci %p", ci);
ci->ci_cpuid = hartid;
+ ci->ci_cpu_freq = riscv_timer_frequency_get();
} else {
#ifdef MULTIPROCESSOR
if ((boothowto & RB_MD1) != 0) {
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: riastradh Date: Sun Apr 7 22:52:53 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: cpu.c Log Message: riscv: Make sure cpu0->ci_cpu_freq is initialized by cpu_attach. Otherwise this stays zero, which screws up cpu_ipi_wait. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/cpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Apr 6 13:41:03 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: copy.S Log Message: Fix riscv32 build To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/copy.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/copy.S diff -u src/sys/arch/riscv/riscv/copy.S:1.1 src/sys/arch/riscv/riscv/copy.S:1.2 --- src/sys/arch/riscv/riscv/copy.S:1.1 Sat Apr 6 10:08:54 2024 +++ src/sys/arch/riscv/riscv/copy.S Sat Apr 6 13:41:03 2024 @@ -118,6 +118,7 @@ ENTRY(_ucas_32) END(_ucas_32) +#ifdef _LP64 /* * int _ucas_64(volatile uint64_t *ptr, uint64_t old, * uint64_t new, uint64_t *ret) @@ -156,3 +157,4 @@ ENTRY(_ucas_64) li a0, EFAULT ret END(_ucas_64) +#endif
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Apr 6 13:41:03 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: copy.S Log Message: Fix riscv32 build To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/copy.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Mon Apr 1 16:24:01 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Return the correct error from {fetch,store}_user_data and fix
futex_wake_op_op: [0.273033s] Failed:
/usr/src/tests/lib/libc/sys/t_futex_ops.c:942: Expected errno 14, got 1, in
__futex(_word, FUTEX_WAKE_OP | flags, 0, NULL, NULL, 0, op) == -1
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Mon Apr 1 16:24:01 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Return the correct error from {fetch,store}_user_data and fix
futex_wake_op_op: [0.273033s] Failed:
/usr/src/tests/lib/libc/sys/t_futex_ops.c:942: Expected errno 14, got 1, in
__futex(_word, FUTEX_WAKE_OP | flags, 0, NULL, NULL, 0, op) == -1
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.24 src/sys/arch/riscv/riscv/trap.c:1.25
--- src/sys/arch/riscv/riscv/trap.c:1.24 Thu Sep 7 12:48:49 2023
+++ src/sys/arch/riscv/riscv/trap.c Mon Apr 1 16:24:01 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.24 2023/09/07 12:48:49 skrll Exp $ */
+/* $NetBSD: trap.c,v 1.25 2024/04/01 16:24:01 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.24 2023/09/07 12:48:49 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.25 2024/04/01 16:24:01 skrll Exp $");
#include
@@ -672,7 +672,7 @@ fetch_user_data(const void *uaddr, void
if (__predict_false(uva > VM_MAXUSER_ADDRESS - size))
return EFAULT;
- if ((error = cpu_set_onfault(, 1)) != 0)
+ if ((error = cpu_set_onfault(, EFAULT)) != 0)
return error;
csr_sstatus_set(SR_SUM);
@@ -737,7 +737,7 @@ store_user_data(void *uaddr, const void
if (__predict_false(uva > VM_MAXUSER_ADDRESS - size))
return EFAULT;
- if ((error = cpu_set_onfault(, 1)) != 0)
+ if ((error = cpu_set_onfault(, EFAULT)) != 0)
return error;
csr_sstatus_set(SR_SUM);
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Thu Feb 8 18:25:58 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: bus_dma.c Log Message: Define _RISCV_NEED_BUS_DMA_BOUNCE. Pointed out as being needed by jmcneill. Thanks! To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/bus_dma.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Thu Feb 8 18:25:58 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: bus_dma.c Log Message: Define _RISCV_NEED_BUS_DMA_BOUNCE. Pointed out as being needed by jmcneill. Thanks! To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/bus_dma.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/bus_dma.c diff -u src/sys/arch/riscv/riscv/bus_dma.c:1.1 src/sys/arch/riscv/riscv/bus_dma.c:1.2 --- src/sys/arch/riscv/riscv/bus_dma.c:1.1 Sun May 7 12:41:48 2023 +++ src/sys/arch/riscv/riscv/bus_dma.c Thu Feb 8 18:25:58 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: bus_dma.c,v 1.1 2023/05/07 12:41:48 skrll Exp $ */ +/* $NetBSD: bus_dma.c,v 1.2 2024/02/08 18:25:58 skrll Exp $ */ /*- * Copyright (c) 1996, 1997, 1998, 2020 The NetBSD Foundation, Inc. @@ -31,9 +31,10 @@ */ #define _RISCV_BUS_DMA_PRIVATE +#define _RISCV_NEED_BUS_DMA_BOUNCE #include -__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.1 2023/05/07 12:41:48 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.2 2024/02/08 18:25:58 skrll Exp $"); #include
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Fri Jan 19 09:09:39 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: autoconf.c Log Message: Use fdt_cpu_rootconf To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/autoconf.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Fri Jan 19 09:09:39 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: autoconf.c
Log Message:
Use fdt_cpu_rootconf
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/autoconf.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/autoconf.c
diff -u src/sys/arch/riscv/riscv/autoconf.c:1.5 src/sys/arch/riscv/riscv/autoconf.c:1.6
--- src/sys/arch/riscv/riscv/autoconf.c:1.5 Mon Jul 10 07:04:20 2023
+++ src/sys/arch/riscv/riscv/autoconf.c Fri Jan 19 09:09:39 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.5 2023/07/10 07:04:20 rin Exp $ */
+/* $NetBSD: autoconf.c,v 1.6 2024/01/19 09:09:39 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: autoconf.c,v 1.5 2023/07/10 07:04:20 rin Exp $");
+__RCSID("$NetBSD: autoconf.c,v 1.6 2024/01/19 09:09:39 skrll Exp $");
#include
@@ -57,10 +57,26 @@ cpu_configure(void)
spl0();
}
+/*
+ * Set up the root device from the boot args.
+ *
+ * cpu_bootconf() is called before RAIDframe root detection,
+ * and cpu_rootconf() is called after.
+ */
void
-cpu_rootconf(void)
+cpu_bootconf(void)
{
+#ifndef MEMORY_DISK_IS_ROOT
+ fdt_cpu_rootconf();
+#endif
+}
+void
+cpu_rootconf(void)
+{
+ cpu_bootconf();
+ aprint_normal("boot device: %s\n",
+ booted_device != NULL ? device_xname(booted_device) : "");
rootconf();
}
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Thu Jan 18 07:41:50 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c riscv_machdep.c
Log Message:
Provide a working delay(9)
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/clock_machdep.c
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/clock_machdep.c
diff -u src/sys/arch/riscv/riscv/clock_machdep.c:1.6 src/sys/arch/riscv/riscv/clock_machdep.c:1.7
--- src/sys/arch/riscv/riscv/clock_machdep.c:1.6 Wed Jul 26 06:13:44 2023
+++ src/sys/arch/riscv/riscv/clock_machdep.c Thu Jan 18 07:41:50 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: clock_machdep.c,v 1.6 2023/07/26 06:13:44 skrll Exp $ */
+/* $NetBSD: clock_machdep.c,v 1.7 2024/01/18 07:41:50 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: clock_machdep.c,v 1.6 2023/07/26 06:13:44 skrll Exp $");
+__RCSID("$NetBSD: clock_machdep.c,v 1.7 2024/01/18 07:41:50 skrll Exp $");
#include
#include
@@ -47,6 +47,7 @@ static void (*_riscv_timer_init)(void) =
static uint32_t timer_frequency;
static uint32_t timer_ticks_per_hz;
+static uint32_t timer_ticks_per_usec;
static u_int
timer_get_timecount(struct timecounter *tc)
@@ -67,6 +68,7 @@ riscv_timer_frequency_set(uint32_t freq)
{
timer_frequency = freq;
timer_ticks_per_hz = freq / hz;
+ timer_ticks_per_usec = freq / 100;
}
uint32_t
@@ -143,3 +145,14 @@ void
setstatclockrate(int newhz)
{
}
+
+void
+delay(unsigned long us)
+{
+const uint64_t ticks = (uint64_t)us * timer_ticks_per_usec;
+const uint64_t finish = csr_time_read() + ticks;
+
+while (csr_time_read() < finish) {
+/* spin, baby spin */
+}
+}
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.35 src/sys/arch/riscv/riscv/riscv_machdep.c:1.36
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.35 Fri Dec 22 08:41:59 2023
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Thu Jan 18 07:41:50 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.35 2023/12/22 08:41:59 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.36 2024/01/18 07:41:50 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "opt_riscv_debug.h"
#include
-__RCSID("$NetBSD: riscv_machdep.c,v 1.35 2023/12/22 08:41:59 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.36 2024/01/18 07:41:50 skrll Exp $");
#include
@@ -136,18 +136,6 @@ SYSCTL_SETUP(sysctl_machdep_setup, "sysc
CTL_MACHDEP, CTL_EOL);
}
-void
-delay(unsigned long us)
-{
- const uint32_t cycles_per_us = curcpu()->ci_data.cpu_cc_freq / 100;
- const uint64_t cycles = (uint64_t)us * cycles_per_us;
- const uint64_t finish = csr_cycle_read() + cycles;
-
- while (csr_cycle_read() < finish) {
- /* spin, baby spin */
- }
-}
-
#ifdef MODULAR
/*
* Push any modules loaded by the boot loader.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Thu Jan 18 07:41:50 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: clock_machdep.c riscv_machdep.c Log Message: Provide a working delay(9) To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/clock_machdep.c cvs rdiff -u -r1.35 -r1.36 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: msaitoh
Date: Thu Jan 18 03:36:24 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: kobj_machdep.c
Log Message:
s/FALLTHOUGH/FALLTHROUGH/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/kobj_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/kobj_machdep.c
diff -u src/sys/arch/riscv/riscv/kobj_machdep.c:1.5 src/sys/arch/riscv/riscv/kobj_machdep.c:1.6
--- src/sys/arch/riscv/riscv/kobj_machdep.c:1.5 Sun May 7 12:41:49 2023
+++ src/sys/arch/riscv/riscv/kobj_machdep.c Thu Jan 18 03:36:24 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: kobj_machdep.c,v 1.5 2023/05/07 12:41:49 skrll Exp $ */
+/* $NetBSD: kobj_machdep.c,v 1.6 2024/01/18 03:36:24 msaitoh Exp $ */
/*-
* Copyright (c) 2014,2023 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: kobj_machdep.c,v 1.5 2023/05/07 12:41:49 skrll Exp $");
+__RCSID("$NetBSD: kobj_machdep.c,v 1.6 2024/01/18 03:36:24 msaitoh Exp $");
#include
#include
@@ -168,7 +168,7 @@ kobj_reloc(kobj_t ko, uintptr_t relocbas
// XXXNH eh? what's with the symidx test?'
if (symidx == 0)
break;
- /* FALLTHOUGH */
+ /* FALLTHROUGH */
case R_RISCV_CALL_PLT:
case R_RISCV_CALL:
@@ -177,7 +177,7 @@ kobj_reloc(kobj_t ko, uintptr_t relocbas
case R_RISCV_RVC_JUMP:
case R_RISCV_32_PCREL:
addend -= (intptr_t)where; /* A -= P */
- /* FALLTHOUGH */
+ /* FALLTHROUGH */
#ifdef _LP64
case R_RISCV_64: /* doubleword64 S + A */
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: msaitoh Date: Thu Jan 18 03:36:24 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: kobj_machdep.c Log Message: s/FALLTHOUGH/FALLTHROUGH/ in comment. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/kobj_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Fri Dec 22 08:41:59 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: db_interface.c riscv_machdep.c
Log Message:
Minor stylistic changes. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/db_interface.c
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/db_interface.c
diff -u src/sys/arch/riscv/riscv/db_interface.c:1.4 src/sys/arch/riscv/riscv/db_interface.c:1.5
--- src/sys/arch/riscv/riscv/db_interface.c:1.4 Sun Sep 3 08:48:20 2023
+++ src/sys/arch/riscv/riscv/db_interface.c Fri Dec 22 08:41:59 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.4 2023/09/03 08:48:20 skrll Exp $ */
+/* $NetBSD: db_interface.c,v 1.5 2023/12/22 08:41:59 skrll Exp $ */
/*
* Mach Operating System
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.4 2023/09/03 08:48:20 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.5 2023/12/22 08:41:59 skrll Exp $");
#ifdef _KERNEL_OPT
#include "opt_multiprocessor.h"
@@ -88,8 +88,6 @@ paddr_t kvtophys(vaddr_t);
int
kdb_trap(int type, db_regs_t *regs)
{
- int s;
-
switch (type) {
case CAUSE_BREAKPOINT: /* breakpoint */
printf("kernel: breakpoint\n");
@@ -106,7 +104,7 @@ kdb_trap(int type, db_regs_t *regs)
break;
}
- s = splhigh();
+ const int s = splhigh();
struct cpu_info * const ci = curcpu();
#if defined(MULTIPROCESSOR)
@@ -130,9 +128,9 @@ kdb_trap(int type, db_regs_t *regs)
ddb_regs = *regs;
ci->ci_ddb_regs = _regs;
db_active++;
- cnpollc(1);
+ cnpollc(true);
db_trap(type, 0 /*code*/);
- cnpollc(0);
+ cnpollc(false);
db_active--;
ci->ci_ddb_regs = NULL;
*regs = ddb_regs;
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.34 src/sys/arch/riscv/riscv/riscv_machdep.c:1.35
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.34 Sun Sep 3 08:48:20 2023
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Fri Dec 22 08:41:59 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.34 2023/09/03 08:48:20 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.35 2023/12/22 08:41:59 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "opt_riscv_debug.h"
#include
-__RCSID("$NetBSD: riscv_machdep.c,v 1.34 2023/09/03 08:48:20 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.35 2023/12/22 08:41:59 skrll Exp $");
#include
@@ -460,13 +460,13 @@ cpu_reboot(int howto, char *bootstr)
printf("\n");
printf("The operating system has halted.\n");
printf("Please press any key to reboot.\n\n");
- cnpollc(1); /* for proper keyboard command handling */
+ cnpollc(true); /* for proper keyboard command handling */
if (cngetc() == 0) {
/* no console attached, so just hlt */
printf("No keyboard - cannot reboot after all.\n");
goto spin;
}
- cnpollc(0);
+ cnpollc(false);
}
printf("rebooting...\n");
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Fri Dec 22 08:41:59 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: db_interface.c riscv_machdep.c Log Message: Minor stylistic changes. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/db_interface.c cvs rdiff -u -r1.34 -r1.35 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Thu Sep 7 12:48:49 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: trap.c Log Message: Handle CAUSE_LOAD_PAGE_FAULT in trap_pagefault_fixup To generate a diff of this commit: cvs rdiff -u -r1.23 -r1.24 src/sys/arch/riscv/riscv/trap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Thu Sep 7 12:48:49 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Handle CAUSE_LOAD_PAGE_FAULT in trap_pagefault_fixup
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.23 src/sys/arch/riscv/riscv/trap.c:1.24
--- src/sys/arch/riscv/riscv/trap.c:1.23 Tue Aug 22 07:11:15 2023
+++ src/sys/arch/riscv/riscv/trap.c Thu Sep 7 12:48:49 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.23 2023/08/22 07:11:15 rin Exp $ */
+/* $NetBSD: trap.c,v 1.24 2023/09/07 12:48:49 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.23 2023/08/22 07:11:15 rin Exp $");
+__RCSID("$NetBSD: trap.c,v 1.24 2023/09/07 12:48:49 skrll Exp $");
#include
@@ -358,6 +358,12 @@ trap_pagefault_fixup(struct trapframe *t
npte = opte;
switch (cause) {
+ case CAUSE_LOAD_PAGE_FAULT:
+ if ((npte & PTE_R) == 0) {
+npte |= PTE_A;
+attr |= VM_PAGEMD_REFERENCED;
+ }
+ break;
case CAUSE_STORE_ACCESS:
if ((npte & PTE_W) != 0) {
npte |= PTE_A | PTE_D;
@@ -380,8 +386,8 @@ trap_pagefault_fixup(struct trapframe *t
#endif
break;
default:
- panic("%s: Unhandled cause! 0x%016lx (%s)", __func__,
- (long)cause, cause_name(cause));
+ panic("%s: Unhandled cause (%#" PRIxREGISTER
+ ") for addr %lx", __func__, cause, addr);
}
if (attr == 0)
return false;
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Mon Aug 28 11:12:42 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: cpu.c
Log Message:
Remove duplicate .ci_cpl initialiser.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/cpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/cpu.c
diff -u src/sys/arch/riscv/riscv/cpu.c:1.3 src/sys/arch/riscv/riscv/cpu.c:1.4
--- src/sys/arch/riscv/riscv/cpu.c:1.3 Sat Jun 24 07:23:07 2023
+++ src/sys/arch/riscv/riscv/cpu.c Mon Aug 28 11:12:42 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.3 2023/06/24 07:23:07 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.4 2023/08/28 11:12:42 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2023/06/24 07:23:07 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.4 2023/08/28 11:12:42 skrll Exp $");
#include
@@ -102,7 +102,6 @@ struct cpu_info cpu_info_store[NCPUINFO]
[0] = {
.ci_cpl = IPL_HIGH,
.ci_curlwp = ,
- .ci_cpl = IPL_HIGH,
.ci_tlb_info = _tlb0_info,
#ifdef MULTIPROCESSOR
.ci_flags = CPUF_PRIMARY | CPUF_PRESENT | CPUF_RUNNING,
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Mon Aug 28 11:12:42 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: cpu.c Log Message: Remove duplicate .ci_cpl initialiser. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/cpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: rin
Date: Thu Aug 24 05:46:55 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
riscv: cpu_setmcontext: Do not unconditionally update tp register
Conserve tp register for _UC_CPU and update later if _UC_TLSBASE is
specified. This is what powerpc does, which also uses a general
purpose register for TLS pointer.
Found by tests/lib/libpthread/t_swapcontext:swapcontext1, which
successfully passes now.
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.32 src/sys/arch/riscv/riscv/riscv_machdep.c:1.33
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.32 Fri Aug 4 09:06:33 2023
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Thu Aug 24 05:46:55 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.32 2023/08/04 09:06:33 mrg Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.33 2023/08/24 05:46:55 rin Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "opt_riscv_debug.h"
#include
-__RCSID("$NetBSD: riscv_machdep.c,v 1.32 2023/08/04 09:06:33 mrg Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.33 2023/08/24 05:46:55 rin Exp $");
#include
@@ -302,8 +302,12 @@ cpu_setmcontext(struct lwp *l, const mco
if (error)
return error;
- /* Save register context. */
+ /*
+ * Avoid updating TLS register here.
+ */
+ const __greg_t saved_tp = tf->tf_reg[_REG_TP];
tf->tf_regs = *(const struct reg *)gr;
+ tf->tf_reg[_REG_TP] = saved_tp;
}
/* Restore the private thread context */
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: rin Date: Thu Aug 24 05:46:55 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: riscv_machdep.c Log Message: riscv: cpu_setmcontext: Do not unconditionally update tp register Conserve tp register for _UC_CPU and update later if _UC_TLSBASE is specified. This is what powerpc does, which also uses a general purpose register for TLS pointer. Found by tests/lib/libpthread/t_swapcontext:swapcontext1, which successfully passes now. To generate a diff of this commit: cvs rdiff -u -r1.32 -r1.33 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: rin
Date: Tue Aug 22 07:11:15 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
riscv/trap.c: Dump cause register for unhandled page fault
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.22 src/sys/arch/riscv/riscv/trap.c:1.23
--- src/sys/arch/riscv/riscv/trap.c:1.22 Tue Aug 22 07:10:39 2023
+++ src/sys/arch/riscv/riscv/trap.c Tue Aug 22 07:11:15 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.22 2023/08/22 07:10:39 rin Exp $ */
+/* $NetBSD: trap.c,v 1.23 2023/08/22 07:11:15 rin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.22 2023/08/22 07:10:39 rin Exp $");
+__RCSID("$NetBSD: trap.c,v 1.23 2023/08/22 07:11:15 rin Exp $");
#include
@@ -380,7 +380,8 @@ trap_pagefault_fixup(struct trapframe *t
#endif
break;
default:
- panic("%s: Unhandled cause!", __func__);
+ panic("%s: Unhandled cause! 0x%016lx (%s)", __func__,
+ (long)cause, cause_name(cause));
}
if (attr == 0)
return false;
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: rin Date: Tue Aug 22 07:11:15 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: trap.c Log Message: riscv/trap.c: Dump cause register for unhandled page fault To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/sys/arch/riscv/riscv/trap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: rin
Date: Tue Aug 22 07:10:39 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
riscv/trap.c: Handle userland breakpoint exception
Now, gdb 13 works for riscv64 to some extent :)
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.21 src/sys/arch/riscv/riscv/trap.c:1.22
--- src/sys/arch/riscv/riscv/trap.c:1.21 Sun May 7 12:41:49 2023
+++ src/sys/arch/riscv/riscv/trap.c Tue Aug 22 07:10:39 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.21 2023/05/07 12:41:49 skrll Exp $ */
+/* $NetBSD: trap.c,v 1.22 2023/08/22 07:10:39 rin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.21 2023/05/07 12:41:49 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.22 2023/08/22 07:10:39 rin Exp $");
#include
@@ -541,6 +541,26 @@ trap_misalignment(struct trapframe *tf,
return false;
}
+static bool
+trap_breakpoint(struct trapframe *tf, register_t epc, register_t status,
+register_t cause, register_t tval, bool usertrap_p, ksiginfo_t *ksi)
+{
+ if (usertrap_p) {
+ trap_ksi_init(ksi, SIGTRAP, TRAP_BRKPT,
+ (intptr_t)tval, cause);
+ } else {
+ dump_trapframe(tf, printf);
+#if defined(DDB)
+ kdb_trap(cause, tf);
+ PC_BREAK_ADVANCE(tf);
+#else
+ panic("%s: unknown kernel trap", __func__);
+#endif
+ return true;
+ }
+ return false;
+}
+
void
cpu_trap(struct trapframe *tf, register_t epc, register_t status,
register_t cause, register_t tval)
@@ -583,15 +603,8 @@ cpu_trap(struct trapframe *tf, register_
ok = trap_misalignment(tf, epc, status, cause, addr,
usertrap_p, );
} else if (fault_mask & BREAKPOINT_TRAP_MASK) {
- if (!usertrap_p) {
- dump_trapframe(tf, printf);
-#if defined(DDB)
- kdb_trap(cause, tf);
- PC_BREAK_ADVANCE(tf);
- return; /* KERN */
-#endif
- panic("%s: unknown kernel trap", __func__);
- }
+ ok = trap_breakpoint(tf, epc, status, cause, addr,
+ usertrap_p, );
}
if (usertrap_p) {
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: rin Date: Tue Aug 22 07:10:39 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: trap.c Log Message: riscv/trap.c: Handle userland breakpoint exception Now, gdb 13 works for riscv64 to some extent :) To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/riscv/trap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Wed Jul 26 06:13:44 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c
Log Message:
Attach the clock event counter for each cpu^Whart.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/clock_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/clock_machdep.c
diff -u src/sys/arch/riscv/riscv/clock_machdep.c:1.5 src/sys/arch/riscv/riscv/clock_machdep.c:1.6
--- src/sys/arch/riscv/riscv/clock_machdep.c:1.5 Mon Jun 12 19:04:14 2023
+++ src/sys/arch/riscv/riscv/clock_machdep.c Wed Jul 26 06:13:44 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: clock_machdep.c,v 1.5 2023/06/12 19:04:14 skrll Exp $ */
+/* $NetBSD: clock_machdep.c,v 1.6 2023/07/26 06:13:44 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,10 +31,11 @@
#include
-__RCSID("$NetBSD: clock_machdep.c,v 1.5 2023/06/12 19:04:14 skrll Exp $");
+__RCSID("$NetBSD: clock_machdep.c,v 1.6 2023/07/26 06:13:44 skrll Exp $");
#include
#include
+#include
#include
#include
@@ -90,6 +91,9 @@ riscv_timer_init(void)
{
struct cpu_info * const ci = curcpu();
+ evcnt_attach_dynamic(>ci_ev_timer, EVCNT_TYPE_INTR,
+ NULL, device_xname(ci->ci_dev), "timer");
+
ci->ci_lastintr = csr_time_read();
uint64_t next = ci->ci_lastintr + timer_ticks_per_hz;
ci->ci_lastintr_scheduled = next;
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Wed Jul 26 06:13:44 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: clock_machdep.c Log Message: Attach the clock event counter for each cpu^Whart. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/clock_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: rin
Date: Mon Jul 10 07:04:20 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: autoconf.c riscv_machdep.c
Log Message:
riscv: Add FDT-based initrd, rndseed, and efirng support.
Can be used from our in-tree bootrisv64.efi.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/autoconf.c
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/autoconf.c
diff -u src/sys/arch/riscv/riscv/autoconf.c:1.4 src/sys/arch/riscv/riscv/autoconf.c:1.5
--- src/sys/arch/riscv/riscv/autoconf.c:1.4 Sun May 7 12:41:48 2023
+++ src/sys/arch/riscv/riscv/autoconf.c Mon Jul 10 07:04:20 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.4 2023/05/07 12:41:48 skrll Exp $ */
+/* $NetBSD: autoconf.c,v 1.5 2023/07/10 07:04:20 rin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: autoconf.c,v 1.4 2023/05/07 12:41:48 skrll Exp $");
+__RCSID("$NetBSD: autoconf.c,v 1.5 2023/07/10 07:04:20 rin Exp $");
#include
@@ -44,6 +44,8 @@ __RCSID("$NetBSD: autoconf.c,v 1.4 2023/
#include
+#include
+
void
cpu_configure(void)
{
@@ -63,6 +65,10 @@ cpu_rootconf(void)
}
void
-device_register(device_t dv, void *aux)
+device_register(device_t self, void *aux)
{
+
+ if (device_is_a(self, "mainbus")) {
+ fdt_setup_initrd();
+ }
}
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.30 src/sys/arch/riscv/riscv/riscv_machdep.c:1.31
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.30 Mon Jul 10 07:01:48 2023
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Mon Jul 10 07:04:20 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.30 2023/07/10 07:01:48 rin Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.31 2023/07/10 07:04:20 rin Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "opt_riscv_debug.h"
#include
-__RCSID("$NetBSD: riscv_machdep.c,v 1.30 2023/07/10 07:01:48 rin Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.31 2023/07/10 07:04:20 rin Exp $");
#include
@@ -537,6 +537,9 @@ cpu_startup(void)
#endif
fdtbus_intr_init();
+
+ fdt_setup_rndseed();
+ fdt_setup_efirng();
}
static void
@@ -769,9 +772,17 @@ init_riscv(register_t hartid, paddr_t dt
VPRINTF("%s: memory start %" PRIx64 " end %" PRIx64 " (len %"
PRIx64 ")\n", __func__, memory_start, memory_end, memory_size);
+ /* Parse ramdisk, rndseed, and firmware's RNG from EFI */
+ fdt_probe_initrd();
+ fdt_probe_rndseed();
+ fdt_probe_efirng();
+
fdt_memory_remove_reserved(memory_start, memory_end);
fdt_memory_remove_range(dtb, dtbsize);
+ fdt_reserve_initrd();
+ fdt_reserve_rndseed();
+ fdt_reserve_efirng();
/* Perform PT build and VM init */
cpu_kernel_vm_init(memory_start, memory_end);
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: rin Date: Mon Jul 10 07:04:20 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: autoconf.c riscv_machdep.c Log Message: riscv: Add FDT-based initrd, rndseed, and efirng support. Can be used from our in-tree bootrisv64.efi. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/autoconf.c cvs rdiff -u -r1.30 -r1.31 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Jun 24 07:23:07 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: cpu.c Log Message: Always initialise ci_tlb_info in cpu_info_store[0]. Fixes non-MP boot for me. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/cpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/cpu.c diff -u src/sys/arch/riscv/riscv/cpu.c:1.2 src/sys/arch/riscv/riscv/cpu.c:1.3 --- src/sys/arch/riscv/riscv/cpu.c:1.2 Mon Jun 12 19:04:14 2023 +++ src/sys/arch/riscv/riscv/cpu.c Sat Jun 24 07:23:07 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.c,v 1.2 2023/06/12 19:04:14 skrll Exp $ */ +/* $NetBSD: cpu.c,v 1.3 2023/06/24 07:23:07 skrll Exp $ */ /*- * Copyright (c) 2023 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #include "opt_multiprocessor.h" #include -__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.2 2023/06/12 19:04:14 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2023/06/24 07:23:07 skrll Exp $"); #include @@ -103,8 +103,8 @@ struct cpu_info cpu_info_store[NCPUINFO] .ci_cpl = IPL_HIGH, .ci_curlwp = , .ci_cpl = IPL_HIGH, -#ifdef MULTIPROCESSOR .ci_tlb_info = _tlb0_info, +#ifdef MULTIPROCESSOR .ci_flags = CPUF_PRIMARY | CPUF_PRESENT | CPUF_RUNNING, #endif }
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Jun 24 07:23:07 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: cpu.c Log Message: Always initialise ci_tlb_info in cpu_info_store[0]. Fixes non-MP boot for me. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/cpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Jun 10 09:18:50 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: spl.S Log Message: Remove magic numbers. NFCI. Copyright maintenance while I'm here. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/spl.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sat Jun 10 09:18:50 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: spl.S
Log Message:
Remove magic numbers. NFCI.
Copyright maintenance while I'm here.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/spl.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/spl.S
diff -u src/sys/arch/riscv/riscv/spl.S:1.6 src/sys/arch/riscv/riscv/spl.S:1.7
--- src/sys/arch/riscv/riscv/spl.S:1.6 Sun May 7 12:41:49 2023
+++ src/sys/arch/riscv/riscv/spl.S Sat Jun 10 09:18:50 2023
@@ -1,11 +1,11 @@
-/* $NetBSD: spl.S,v 1.6 2023/05/07 12:41:49 skrll Exp $ */
+/* $NetBSD: spl.S,v 1.7 2023/06/10 09:18:50 skrll Exp $ */
/*-
- * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * Copyright (c) 2014,2023 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
- * by Matt Thomas of 3am Software Foundry.
+ * by Matt Thomas of 3am Software Foundry, and Nick Hudson.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -32,7 +32,9 @@
#include
#include "assym.h"
-__RCSID("$NetBSD: spl.S,v 1.6 2023/05/07 12:41:49 skrll Exp $")
+__RCSID("$NetBSD: spl.S,v 1.7 2023/06/10 09:18:50 skrll Exp $")
+
+#define SZINT (1 << INT_SCALESHIFT)
.data
.globl _C_LABEL(ipl_sie_map)
@@ -55,8 +57,7 @@ ENTRY_NP(splx)
INT_L t0, CI_CPL(a3) // get current IPL
bge a0, t0, 2f
-
- sll t2, a0, 2 // INT_SCALESHIFT
+ sll t2, a0, INT_SCALESHIFT
PTR_LA a1, _C_LABEL(ipl_sie_map)
add a1, a1, t2
INT_L a1, 0(a1)
@@ -124,51 +125,51 @@ END(spl0)
ENTRY_NP(splsoftclock)
li t1, IPL_SOFTCLOCK
- INT_L t0, _C_LABEL(ipl_sie_map) + 4 * IPL_SOFTCLOCK
+ INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SOFTCLOCK
j _splraise
END(splsoftclock)
ENTRY_NP(splsoftbio)
li t1, IPL_SOFTBIO
- INT_L t0, _C_LABEL(ipl_sie_map) + 4 * IPL_SOFTBIO
+ INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SOFTBIO
j _splraise
END(splsoftbio)
ENTRY_NP(splsoftnet)
li t1, IPL_SOFTNET
- INT_L t0, _C_LABEL(ipl_sie_map) + 4 * IPL_SOFTNET
+ INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SOFTNET
j _splraise
END(splsoftnet)
ENTRY_NP(splsoftserial)
li t1, IPL_SOFTSERIAL
- INT_L t0, _C_LABEL(ipl_sie_map) + 4 * IPL_SOFTSERIAL
+ INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SOFTSERIAL
j _splraise
END(splsoftserial)
ENTRY_NP(splvm)
li t1, IPL_VM
- INT_L t0, _C_LABEL(ipl_sie_map) + 4 * IPL_VM
+ INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_VM
j _splraise
END(splvm)
ENTRY_NP(splsched)
li t1, IPL_SCHED
- INT_L t0, _C_LABEL(ipl_sie_map) + 4 * IPL_SCHED
+ INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SCHED
j _splraise
END(splsched)
#if 0
ENTRY_NP(splddb)
li t1, IPL_DDB
- INT_L t0, _C_LABEL(ipl_sie_map) + 4 * IPL_DDB
+ INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_DDB
j _splraise
END(splddb)
#endif
ENTRY_NP(splhigh)
li t1, IPL_HIGH
- INT_L t0, _C_LABEL(ipl_sie_map) + 4 * IPL_HIGH
+ INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_HIGH
j _splraise
END(splhigh)
@@ -177,7 +178,7 @@ END(splhigh)
ENTRY_NP(splraise)
// a0 = new higher IPL
mv t1, a0
- sll t2, a0, 2 // INT_SCALESHIFT
+ sll t2, a0, INT_SCALESHIFT
PTR_LA a1, _C_LABEL(ipl_sie_map)
add a1, a1, t2
INT_L t0, 0(a1)
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sat Jun 10 07:02:26 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
Whitespace.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/pmap_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/pmap_machdep.c
diff -u src/sys/arch/riscv/riscv/pmap_machdep.c:1.16 src/sys/arch/riscv/riscv/pmap_machdep.c:1.17
--- src/sys/arch/riscv/riscv/pmap_machdep.c:1.16 Sun May 7 12:41:49 2023
+++ src/sys/arch/riscv/riscv/pmap_machdep.c Sat Jun 10 07:02:26 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap_machdep.c,v 1.16 2023/05/07 12:41:49 skrll Exp $ */
+/* $NetBSD: pmap_machdep.c,v 1.17 2023/06/10 07:02:26 skrll Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#define __PMAP_PRIVATE
#include
-__RCSID("$NetBSD: pmap_machdep.c,v 1.16 2023/05/07 12:41:49 skrll Exp $");
+__RCSID("$NetBSD: pmap_machdep.c,v 1.17 2023/06/10 07:02:26 skrll Exp $");
#include
#include
@@ -170,7 +170,7 @@ pmap_md_xtab_activate(struct pmap *pmap,
// struct cpu_info * const ci = curcpu();
struct pmap_asid_info * const pai = PMAP_PAI(pmap, cpu_tlb_info(ci));
- uint64_t satp =
+ uint64_t satp =
#ifdef _LP64
__SHIFTIN(SATP_MODE_SV39, SATP_MODE) |
#else
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Jun 10 07:02:26 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: pmap_machdep.c Log Message: Whitespace. To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/pmap_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun May 28 12:56:56 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: riscv_machdep.c Log Message: Second arg to fdt_memory_remove_range is a size so pass dtbsize and not dtb + dtbsize To generate a diff of this commit: cvs rdiff -u -r1.27 -r1.28 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sun May 28 12:56:56 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Second arg to fdt_memory_remove_range is a size so pass dtbsize and not
dtb + dtbsize
To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.27 src/sys/arch/riscv/riscv/riscv_machdep.c:1.28
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.27 Sun May 14 09:14:30 2023
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Sun May 28 12:56:56 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.27 2023/05/14 09:14:30 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.28 2023/05/28 12:56:56 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#include "opt_riscv_debug.h"
#include
-__RCSID("$NetBSD: riscv_machdep.c,v 1.27 2023/05/14 09:14:30 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.28 2023/05/28 12:56:56 skrll Exp $");
#include
@@ -758,7 +758,7 @@ init_riscv(register_t hartid, paddr_t dt
fdt_memory_remove_reserved(memory_start, memory_end);
- fdt_memory_remove_range(dtb, dtb + dtbsize);
+ fdt_memory_remove_range(dtb, dtbsize);
/* Perform PT build and VM init */
cpu_kernel_vm_init(memory_start, memory_end);
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sun May 14 09:14:30 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Check for RB_HALT in cpu_reboot.
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.26 src/sys/arch/riscv/riscv/riscv_machdep.c:1.27
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.26 Sun May 7 12:41:49 2023
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Sun May 14 09:14:30 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.26 2023/05/07 12:41:49 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.27 2023/05/14 09:14:30 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#include "opt_riscv_debug.h"
#include
-__RCSID("$NetBSD: riscv_machdep.c,v 1.26 2023/05/07 12:41:49 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.27 2023/05/14 09:14:30 skrll Exp $");
#include
@@ -456,8 +456,23 @@ cpu_reboot(int howto, char *bootstr)
/* Make sure IRQ's are disabled */
DISABLE_INTERRUPTS();
- sbi_system_reset(SBI_RESET_TYPE_COLDREBOOT, SBI_RESET_REASON_NONE);
+ if (howto & RB_HALT) {
+ printf("\n");
+ printf("The operating system has halted.\n");
+ printf("Please press any key to reboot.\n\n");
+ cnpollc(1); /* for proper keyboard command handling */
+ if (cngetc() == 0) {
+ /* no console attached, so just hlt */
+ printf("No keyboard - cannot reboot after all.\n");
+ goto spin;
+ }
+ cnpollc(0);
+ }
+ printf("rebooting...\n");
+
+ sbi_system_reset(SBI_RESET_TYPE_COLDREBOOT, SBI_RESET_REASON_NONE);
+spin:
for (;;) {
asm volatile("wfi" ::: "memory");
}
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun May 14 09:14:30 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: riscv_machdep.c Log Message: Check for RB_HALT in cpu_reboot. To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: riastradh Date: Wed Mar 1 08:18:24 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: cpu_switch.S Log Message: riscv: Optimization: Omit needless membar when triggering softint. When we are triggering a softint, it can't already hold any mutexes. So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is always done with atomic r/m/w, and we need not issue any explicit barrier between ci->ci_curlwp = softlwp and a potential load of mtx->mtx_owner in mutex_exit. PR kern/57240 To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/cpu_switch.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/cpu_switch.S diff -u src/sys/arch/riscv/riscv/cpu_switch.S:1.3 src/sys/arch/riscv/riscv/cpu_switch.S:1.4 --- src/sys/arch/riscv/riscv/cpu_switch.S:1.3 Thu Feb 23 14:56:23 2023 +++ src/sys/arch/riscv/riscv/cpu_switch.S Wed Mar 1 08:18:24 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu_switch.S,v 1.3 2023/02/23 14:56:23 riastradh Exp $ */ +/* $NetBSD: cpu_switch.S,v 1.4 2023/03/01 08:18:24 riastradh Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -177,7 +177,13 @@ ENTRY_NP(cpu_fast_switchto) mv tp, a0 // set thread pointer to newlwp fence w,w // for mutex_enter; see cpu_switchto PTR_S tp, CI_CURLWP(t1) // update curlwp - fence w,r // for mutex_enter; see cpu_switchto + /* + * No need for barrier after ci->ci_curlwp = softlwp -- when we + * enter a softint lwp, it can't be holding any mutexes, so it + * can't release any until after it has acquired them, so we + * need not participate in the protocol with mutex_vector_enter + * barriers here. + */ PTR_L sp, L_MD_KTF(tp) // switch to its stack csrw sstatus, t0 // reenable interrupts call _C_LABEL(softint_dispatch)
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: riastradh Date: Wed Mar 1 08:18:24 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: cpu_switch.S Log Message: riscv: Optimization: Omit needless membar when triggering softint. When we are triggering a softint, it can't already hold any mutexes. So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is always done with atomic r/m/w, and we need not issue any explicit barrier between ci->ci_curlwp = softlwp and a potential load of mtx->mtx_owner in mutex_exit. PR kern/57240 To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/cpu_switch.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:56:23 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: cpu_switch.S Log Message: riscv: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/cpu_switch.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/cpu_switch.S diff -u src/sys/arch/riscv/riscv/cpu_switch.S:1.2 src/sys/arch/riscv/riscv/cpu_switch.S:1.3 --- src/sys/arch/riscv/riscv/cpu_switch.S:1.2 Sun Dec 4 16:29:35 2022 +++ src/sys/arch/riscv/riscv/cpu_switch.S Thu Feb 23 14:56:23 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu_switch.S,v 1.2 2022/12/04 16:29:35 skrll Exp $ */ +/* $NetBSD: cpu_switch.S,v 1.3 2023/02/23 14:56:23 riastradh Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -62,7 +62,28 @@ ENTRY_NP(cpu_switchto) mv tp, a1 // # put the new lwp in thread pointer PTR_L t1, L_CPU(tp) // # get curcpu + + /* + * Issue barriers to coordinate mutex_exit on this CPU with + * mutex_vector_enter on another CPU. + * + * 1. Any prior mutex_exit by oldlwp must be visible to other + *CPUs before we set ci_curlwp := newlwp on this one, + *requiring a store-before-store barrier. + * + * 2. ci_curlwp := newlwp must be visible on all other CPUs + *before any subsequent mutex_exit by newlwp can even test + *whether there might be waiters, requiring a + *store-before-load barrier. + * + * See kern_mutex.c for details -- this is necessary for + * adaptive mutexes to detect whether the lwp is on the CPU in + * order to safely block without requiring atomic r/m/w in + * mutex_exit. + */ + fence w,w PTR_S tp, CI_CURLWP(t1) // # update curcpu with the new curlwp + fence w,r REG_L sp, L_MD_KTF(tp) // # load its kernel stack pointer REG_L t4, TF_SR(sp) // # fetch status register @@ -154,14 +175,18 @@ ENTRY_NP(cpu_fast_switchto) PTR_S sp, L_MD_KTF(tp) // save trapframe ptr in oldlwp mv tp, a0 // set thread pointer to newlwp + fence w,w // for mutex_enter; see cpu_switchto PTR_S tp, CI_CURLWP(t1) // update curlwp + fence w,r // for mutex_enter; see cpu_switchto PTR_L sp, L_MD_KTF(tp) // switch to its stack csrw sstatus, t0 // reenable interrupts call _C_LABEL(softint_dispatch) csrrci t0, sstatus, SR_SIE // disable interrupts PTR_L t1, L_CPU(tp) // get curcpu() again mv tp, s0 // return to pinned lwp + fence w,w // for mutex_enter; see cpu_switchto PTR_S tp, CI_CURLWP(t1) // restore curlwp + fence w,r // for mutex_enter; see cpu_switchto csrw sstatus, t0 // reenable interrupts mv sp, s1 // restore stack pointer
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:56:23 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: cpu_switch.S Log Message: riscv: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/cpu_switch.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Dec 4 16:29:35 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: cpu_switch.S Log Message: Restore t5 and t6 from the correct locations in exception_kernexit. >From Simon. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/cpu_switch.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/cpu_switch.S diff -u src/sys/arch/riscv/riscv/cpu_switch.S:1.1 src/sys/arch/riscv/riscv/cpu_switch.S:1.2 --- src/sys/arch/riscv/riscv/cpu_switch.S:1.1 Fri Oct 14 07:58:30 2022 +++ src/sys/arch/riscv/riscv/cpu_switch.S Sun Dec 4 16:29:35 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu_switch.S,v 1.1 2022/10/14 07:58:30 skrll Exp $ */ +/* $NetBSD: cpu_switch.S,v 1.2 2022/12/04 16:29:35 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -278,8 +278,8 @@ exception_kernexit: REG_L t2, TF_T2(sp) // restore t2 REG_L t3, TF_T3(sp) // restore t3 REG_L t4, TF_T4(sp) // restore t4 - REG_L t5, TF_T3(sp) // restore t5 - REG_L t6, TF_T4(sp) // restore t6 + REG_L t5, TF_T5(sp) // restore t5 + REG_L t6, TF_T6(sp) // restore t6 REG_L t0, TF_PC(sp) // fetch exception PC REG_L t1, TF_SR(sp) // fetch status
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Dec 4 16:29:35 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: cpu_switch.S Log Message: Restore t5 and t6 from the correct locations in exception_kernexit. >From Simon. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/cpu_switch.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Dec 4 16:23:48 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: vm_machdep.c Log Message: ASSERT that md_astpending it zero for the new lwp. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/vm_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/vm_machdep.c diff -u src/sys/arch/riscv/riscv/vm_machdep.c:1.6 src/sys/arch/riscv/riscv/vm_machdep.c:1.7 --- src/sys/arch/riscv/riscv/vm_machdep.c:1.6 Tue Nov 15 14:33:33 2022 +++ src/sys/arch/riscv/riscv/vm_machdep.c Sun Dec 4 16:23:48 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: vm_machdep.c,v 1.6 2022/11/15 14:33:33 simonb Exp $ */ +/* $NetBSD: vm_machdep.c,v 1.7 2022/12/04 16:23:48 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.6 2022/11/15 14:33:33 simonb Exp $"); +__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.7 2022/12/04 16:23:48 skrll Exp $"); #define _PMAP_PRIVATE @@ -77,8 +77,7 @@ cpu_lwp_fork(struct lwp *l1, struct lwp struct trapframe *tf; KASSERT(l1 == curlwp || l1 == ); - - l2->l_md.md_astpending = 0; + KASSERT(l2->l_md.md_astpending == 0); /* Copy the PCB from parent. */ *pcb2 = *pcb1;
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Dec 4 16:23:48 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: vm_machdep.c Log Message: ASSERT that md_astpending it zero for the new lwp. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/vm_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sat Nov 19 09:55:11 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Fix CONSADDR and save a label
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/riscv/riscv/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.39 src/sys/arch/riscv/riscv/locore.S:1.40
--- src/sys/arch/riscv/riscv/locore.S:1.39 Sun Oct 16 06:14:53 2022
+++ src/sys/arch/riscv/riscv/locore.S Sat Nov 19 09:55:11 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.39 2022/10/16 06:14:53 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.40 2022/11/19 09:55:11 skrll Exp $ */
/*-
* Copyright (c) 2014, 2022 The NetBSD Foundation, Inc.
@@ -292,7 +292,7 @@ ENTRY_NP(start)
or s0, s0, s7
VPRINTS("cons:")
- VPRINTX(s2)
+ VPRINTX(s9)
VPRINTS(": ")
VPRINTXNL(s0)
@@ -303,7 +303,7 @@ ENTRY_NP(start)
call _C_LABEL(uartputc)
/* Set supervisor trap vector base register */
- PTR_LA t0, .Lmmu_on
+ PTR_LA t0, vstart
add t0, t0, s8
csrw stvec, t0
@@ -319,10 +319,14 @@ ENTRY_NP(start)
csrw satp, t0
.align 2
-.Lmmu_on:
+ .global vstart
+vstart:
// MMU is on!
csrw sscratch, zero // zero in sscratch to mark kernel
+#ifdef CONSADDR
+ add sp, sp, s8
+#endif
li a0, 'M'
call _C_LABEL(uartputc) // uartputs doesn't use stack
li a0, '\n'
@@ -332,8 +336,6 @@ ENTRY_NP(start)
PTR_LA tp, _C_LABEL(lwp0) // put curlwp in tp
- .global vstart
-vstart:
/* Set supervisor trap vector base register */
PTR_LA a0, _C_LABEL(cpu_exception_handler)
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Nov 19 09:55:11 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Fix CONSADDR and save a label To generate a diff of this commit: cvs rdiff -u -r1.39 -r1.40 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: simonb
Date: Thu Nov 17 13:11:08 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Use updated defines for the user-mode sstatus value.
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.24 src/sys/arch/riscv/riscv/riscv_machdep.c:1.25
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.24 Tue Nov 15 14:33:33 2022
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Thu Nov 17 13:11:08 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.24 2022/11/15 14:33:33 simonb Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.25 2022/11/17 13:11:08 simonb Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#include "opt_riscv_debug.h"
#include
-__RCSID("$NetBSD: riscv_machdep.c,v 1.24 2022/11/15 14:33:33 simonb Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.25 2022/11/17 13:11:08 simonb Exp $");
#include
@@ -156,7 +156,7 @@ setregs(struct lwp *l, struct exec_packa
tf->tf_sp = (intptr_t)stack_align(stack);
tf->tf_pc = (intptr_t)pack->ep_entry & ~1;
#ifdef _LP64
- tf->tf_sr = (p->p_flag & PK_32) ? SR_USER32 : SR_USER;
+ tf->tf_sr = (p->p_flag & PK_32) ? SR_USER32 : SR_USER64;
#else
tf->tf_sr = SR_USER;
#endif
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: simonb Date: Thu Nov 17 13:11:08 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: riscv_machdep.c Log Message: Use updated defines for the user-mode sstatus value. To generate a diff of this commit: cvs rdiff -u -r1.24 -r1.25 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: simonb
Date: Mon Oct 31 12:50:49 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: bus_space_generic.S
Log Message:
In bus_space_write_{1,2,4,8} store the correct register in write to device.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/bus_space_generic.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/bus_space_generic.S
diff -u src/sys/arch/riscv/riscv/bus_space_generic.S:1.2 src/sys/arch/riscv/riscv/bus_space_generic.S:1.3
--- src/sys/arch/riscv/riscv/bus_space_generic.S:1.2 Mon Oct 31 12:49:18 2022
+++ src/sys/arch/riscv/riscv/bus_space_generic.S Mon Oct 31 12:50:49 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space_generic.S,v 1.2 2022/10/31 12:49:18 simonb Exp $ */
+/* $NetBSD: bus_space_generic.S,v 1.3 2022/10/31 12:50:49 simonb Exp $ */
/*-
* Copyright (c) 2022 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: bus_space_generic.S,v 1.2 2022/10/31 12:49:18 simonb Exp $")
+RCSID("$NetBSD: bus_space_generic.S,v 1.3 2022/10/31 12:50:49 simonb Exp $")
/* void bs_c_1(a0: tag, a1: src, srcoffset, dst, dstoffset, count); */
@@ -245,7 +245,7 @@ ENTRY_NP(generic_bs_w_1)
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
- sb a0, 0(a2) /* store 8-bit */
+ sb a3, 0(a2) /* store 8-bit */
ret
END(generic_bs_w_1)
@@ -255,7 +255,7 @@ ENTRY_NP(generic_bs_w_2)
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
- sh a0 ,0(a2) /* store 16-bit */
+ sh a3 ,0(a2) /* store 16-bit */
ret
END(generic_bs_w_2)
@@ -265,7 +265,7 @@ ENTRY_NP(generic_bs_w_4)
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
- sw a0, 0(a2) /* store 32-bit */
+ sw a3, 0(a2) /* store 32-bit */
ret
END(generic_bs_w_4)
@@ -276,7 +276,7 @@ ENTRY_NP(generic_bs_w_8)
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
- sd a0, 0(a2) /* store 64-bit */
+ sd a3, 0(a2) /* store 64-bit */
ret
END(generic_bs_w_8)
#endif
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: simonb
Date: Mon Oct 31 12:50:49 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: bus_space_generic.S
Log Message:
In bus_space_write_{1,2,4,8} store the correct register in write to device.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/bus_space_generic.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: simonb Date: Mon Oct 31 12:49:18 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: bus_space_generic.S Log Message: Fix tyop in END for generic_bs_r_8. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/bus_space_generic.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: simonb
Date: Mon Oct 31 12:49:18 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: bus_space_generic.S
Log Message:
Fix tyop in END for generic_bs_r_8.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/bus_space_generic.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/bus_space_generic.S
diff -u src/sys/arch/riscv/riscv/bus_space_generic.S:1.1 src/sys/arch/riscv/riscv/bus_space_generic.S:1.2
--- src/sys/arch/riscv/riscv/bus_space_generic.S:1.1 Sun Sep 11 15:31:12 2022
+++ src/sys/arch/riscv/riscv/bus_space_generic.S Mon Oct 31 12:49:18 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space_generic.S,v 1.1 2022/09/11 15:31:12 skrll Exp $ */
+/* $NetBSD: bus_space_generic.S,v 1.2 2022/10/31 12:49:18 simonb Exp $ */
/*-
* Copyright (c) 2022 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: bus_space_generic.S,v 1.1 2022/09/11 15:31:12 skrll Exp $")
+RCSID("$NetBSD: bus_space_generic.S,v 1.2 2022/10/31 12:49:18 simonb Exp $")
/* void bs_c_1(a0: tag, a1: src, srcoffset, dst, dstoffset, count); */
@@ -85,7 +85,7 @@ ENTRY_NP(generic_bs_r_8)
PTR_ADD a2, a2, a1 /* add to address */
ld a0, 0(a2) /* load 64-bit */
ret
-END(generic_bs_r_4)
+END(generic_bs_r_8)
#endif
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Tue Oct 18 04:24:54 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
remove a stray comment
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.22 src/sys/arch/riscv/riscv/riscv_machdep.c:1.23
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.22 Sun Oct 16 06:19:16 2022
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Tue Oct 18 04:24:54 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.22 2022/10/16 06:19:16 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.23 2022/10/18 04:24:54 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#include "opt_riscv_debug.h"
#include
-__RCSID("$NetBSD: riscv_machdep.c,v 1.22 2022/10/16 06:19:16 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.23 2022/10/18 04:24:54 skrll Exp $");
#include
@@ -516,8 +516,6 @@ init_riscv(register_t hartid, paddr_t dt
parse_bi_bootargs(boot_args);
-
- // initarm_common
extern char __kernel_text[];
extern char _end[];
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Tue Oct 18 04:24:54 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: riscv_machdep.c Log Message: remove a stray comment To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Oct 16 08:43:44 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: pmap_machdep.c Log Message: tlb_update_addr gets called with the KERNEL_PID (ASID) so handle this case. To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/riscv/pmap_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sun Oct 16 08:43:44 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
tlb_update_addr gets called with the KERNEL_PID (ASID) so handle this
case.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/riscv/pmap_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/pmap_machdep.c
diff -u src/sys/arch/riscv/riscv/pmap_machdep.c:1.12 src/sys/arch/riscv/riscv/pmap_machdep.c:1.13
--- src/sys/arch/riscv/riscv/pmap_machdep.c:1.12 Sat Oct 15 06:41:43 2022
+++ src/sys/arch/riscv/riscv/pmap_machdep.c Sun Oct 16 08:43:44 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap_machdep.c,v 1.12 2022/10/15 06:41:43 simonb Exp $ */
+/* $NetBSD: pmap_machdep.c,v 1.13 2022/10/16 08:43:44 skrll Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#define __PMAP_PRIVATE
#include
-__RCSID("$NetBSD: pmap_machdep.c,v 1.12 2022/10/15 06:41:43 simonb Exp $");
+__RCSID("$NetBSD: pmap_machdep.c,v 1.13 2022/10/16 08:43:44 skrll Exp $");
#include
#include
@@ -289,6 +289,7 @@ tlb_set_asid(tlb_asid_t asid, struct pma
voidtlb_invalidate_all(void);
voidtlb_invalidate_globals(void);
#endif
+
void
tlb_invalidate_asids(tlb_asid_t lo, tlb_asid_t hi)
{
@@ -318,11 +319,17 @@ tlb_invalidate_addr(vaddr_t va, tlb_asid
bool
tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert_p)
{
- KASSERT(asid != KERNEL_PID);
- __asm __volatile("sfence.vma %[va], %[asid]"
- : /* output operands */
- : [va] "r" (va), [asid] "r" (asid)
- : "memory");
+ if (asid == KERNEL_PID) {
+ __asm __volatile("sfence.vma %[va]"
+ : /* output operands */
+ : [va] "r" (va)
+ : "memory");
+ } else {
+ __asm __volatile("sfence.vma %[va], %[asid]"
+ : /* output operands */
+ : [va] "r" (va), [asid] "r" (asid)
+ : "memory");
+ }
return false;
}
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Oct 16 06:19:16 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: riscv_machdep.c Log Message: Re-orgnaise a litte. From Simon. To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sun Oct 16 06:19:16 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Re-orgnaise a litte. From Simon.
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.21 src/sys/arch/riscv/riscv/riscv_machdep.c:1.22
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.21 Sun Oct 16 06:14:53 2022
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Sun Oct 16 06:19:16 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.21 2022/10/16 06:14:53 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.22 2022/10/16 06:19:16 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#include "opt_riscv_debug.h"
#include
-__RCSID("$NetBSD: riscv_machdep.c,v 1.21 2022/10/16 06:14:53 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.22 2022/10/16 06:19:16 skrll Exp $");
#include
@@ -57,14 +57,14 @@ __RCSID("$NetBSD: riscv_machdep.c,v 1.21
#include
#include
-int cpu_printfataltraps;
-char machine[] = MACHINE;
-char machine_arch[] = MACHINE_ARCH;
-
#include
#include
#include
+int cpu_printfataltraps;
+char machine[] = MACHINE;
+char machine_arch[] = MACHINE_ARCH;
+
#ifdef VERBOSE_INIT_RISCV
#define VPRINTF(...) printf(__VA_ARGS__)
#else
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sun Oct 16 06:03:14 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Use a local label
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/riscv/riscv/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.37 src/sys/arch/riscv/riscv/locore.S:1.38
--- src/sys/arch/riscv/riscv/locore.S:1.37 Sun Oct 16 05:56:50 2022
+++ src/sys/arch/riscv/riscv/locore.S Sun Oct 16 06:03:14 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.37 2022/10/16 05:56:50 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.38 2022/10/16 06:03:14 skrll Exp $ */
/*-
* Copyright (c) 2014, 2022 The NetBSD Foundation, Inc.
@@ -245,7 +245,7 @@ ENTRY_NP(start)
srli s0, s0, SEGSHIFT // round down to NBSEG, and shift in
slli s0, s0, (SEGSHIFT - PGSHIFT + PTE_PPN_SHIFT) // ... to PPN
or s0, s0, s7
-.Lfill:
+1:
VPRINTS("kern:")
VPRINTX(s9)
VPRINTS(": ")
@@ -255,7 +255,7 @@ ENTRY_NP(start)
add s0, s0, s6 // advance PA in PDE to next segment
add s9, s9, SZREG // advance to next PDE slot
addi s5, s5, -1 // count down segment
- bnez s5, .Lfill // loop if more
+ bnez s5, 1b // loop if more
li s7, PTE_KERN | PTE_R | PTE_W
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Oct 16 06:03:14 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Use a local label To generate a diff of this commit: cvs rdiff -u -r1.37 -r1.38 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sun Oct 16 05:56:50 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
More register re-org
To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/riscv/riscv/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.36 src/sys/arch/riscv/riscv/locore.S:1.37
--- src/sys/arch/riscv/riscv/locore.S:1.36 Sun Oct 16 05:48:15 2022
+++ src/sys/arch/riscv/riscv/locore.S Sun Oct 16 05:56:50 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.36 2022/10/16 05:48:15 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.37 2022/10/16 05:56:50 skrll Exp $ */
/*-
* Copyright (c) 2014, 2022 The NetBSD Foundation, Inc.
@@ -227,10 +227,8 @@ ENTRY_NP(start)
VPRINTS("\n\r")
#endif // _LP64
-#if ((VM_MIN_KERNEL_ADDRESS >> SEGSHIFT) & (NPDEPG - 1)) * SZREG
li t1, ((VM_MIN_KERNEL_ADDRESS >> SEGSHIFT) & (NPDEPG - 1)) * SZREG
- add s2, s2, t1
-#endif
+ add s9, s2, t1
#if PGSHIFT < PTE_PPN_SHIFT
#error Code assumes PGSHIFT is greater than PTE_PPN_SHIFT
@@ -249,13 +247,13 @@ ENTRY_NP(start)
or s0, s0, s7
.Lfill:
VPRINTS("kern:")
- VPRINTX(s2)
+ VPRINTX(s9)
VPRINTS(": ")
VPRINTXNL(s0)
- REG_S s0, 0(s2) // store PDE
+ REG_S s0, 0(s9) // store PDE
add s0, s0, s6 // advance PA in PDE to next segment
- add s2, s2, SZREG // advance to next PDE slot
+ add s9, s9, SZREG // advance to next PDE slot
addi s5, s5, -1 // count down segment
bnez s5, .Lfill // loop if more
@@ -268,12 +266,12 @@ ENTRY_NP(start)
or s0, s0, s7
VPRINTS("dtb: ")
- VPRINTX(s2)
+ VPRINTX(s9)
VPRINTS(": ")
VPRINTXNL(s0)
- REG_S s0, 0(s2)
- add s2, s2, SZREG // advance to next PDE slot
+ REG_S s0, 0(s9)
+ add s9, s9, SZREG // advance to next PDE slot
#ifdef CONSADDR
ld s0, .Lconsaddr
@@ -286,8 +284,8 @@ ENTRY_NP(start)
VPRINTS(": ")
VPRINTXNL(s0)
- REG_S s0, 0(s2)
- add s2, s2, SZREG // advance to next PDE slot
+ REG_S s0, 0(s9)
+ add s9, s9, SZREG // advance to next PDE slot
#endif
li a0, 'P'
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Oct 16 05:56:50 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: More register re-org To generate a diff of this commit: cvs rdiff -u -r1.36 -r1.37 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Oct 16 05:48:15 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Fix after register re-org To generate a diff of this commit: cvs rdiff -u -r1.35 -r1.36 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.35 src/sys/arch/riscv/riscv/locore.S:1.36 --- src/sys/arch/riscv/riscv/locore.S:1.35 Sat Oct 15 16:58:16 2022 +++ src/sys/arch/riscv/riscv/locore.S Sun Oct 16 05:48:15 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.35 2022/10/15 16:58:16 skrll Exp $ */ +/* $NetBSD: locore.S,v 1.36 2022/10/16 05:48:15 skrll Exp $ */ /*- * Copyright (c) 2014, 2022 The NetBSD Foundation, Inc. @@ -365,9 +365,9 @@ vstart: .option pop // Now we should ready to start initializing the kernel. - mv a0, s0 // hartid + mv a0, s10 // hartid mv a1, t0 // vdtb - //mv a1, s1 // dtb (physical) + //mv a1, s11 // dtb (physical) li s0, 0 // zero frame pointer call _C_LABEL(init_riscv) // do MD startup
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Oct 16 05:48:15 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Fix after register re-org To generate a diff of this commit: cvs rdiff -u -r1.35 -r1.36 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sat Oct 15 16:58:16 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
More register use re-org.
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/riscv/riscv/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.34 src/sys/arch/riscv/riscv/locore.S:1.35
--- src/sys/arch/riscv/riscv/locore.S:1.34 Sat Oct 15 16:34:29 2022
+++ src/sys/arch/riscv/riscv/locore.S Sat Oct 15 16:58:16 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.34 2022/10/15 16:34:29 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.35 2022/10/15 16:58:16 skrll Exp $ */
/*-
* Copyright (c) 2014, 2022 The NetBSD Foundation, Inc.
@@ -90,8 +90,8 @@ ENTRY_NP(start)
/*
* The BP only executes from here on.
*/
- mv s0, a0 // copy hartid
- mv s1, a1 // copy dtb PA
+ mv s10, a0 // copy hartid
+ mv s11, a1 // copy dtb PA
/* set the stack pointer for boot */
PTR_LA t0, _C_LABEL(bootstk)
@@ -106,10 +106,10 @@ ENTRY_NP(start)
VPRINTXNL(a0)
VPRINTS("hart:")
- VPRINTXNL(s0)
+ VPRINTXNL(s10)
VPRINTS("dtb: ")
- VPRINTXNL(s1)
+ VPRINTXNL(s11)
/*
* Calculate the difference between the VA and PA for start and
@@ -262,7 +262,7 @@ ENTRY_NP(start)
li s7, PTE_KERN | PTE_R | PTE_W
// DTB physical address
- mv s0, s1
+ mv s0, s11
srli s0, s0, SEGSHIFT // round down to NBSEG, and shift in
slli s0, s0, (SEGSHIFT - PGSHIFT + PTE_PPN_SHIFT) // ... to PPN
or s0, s0, s7
@@ -349,13 +349,13 @@ vstart:
PTR_S s8, 0(t0) /* kern_vtopdiff = start(virt) - start(phys) */
#if notyet
- mv a0, s1 // dtb
+ mv a0, s11 // dtb
call _C_LABEL(init_mmu)
#endif
li t0, VM_MIN_KERNEL_ADDRESS + VM_KERNEL_SIZE
li t1, NBSEG - 1
- and t1, s1, t1
+ and t1, s11, t1
or t0, t0, t1
/* Set the global pointer */
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Oct 15 16:58:16 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: More register use re-org. To generate a diff of this commit: cvs rdiff -u -r1.34 -r1.35 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sat Oct 15 16:34:29 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Shuffle some register usage
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/riscv/riscv/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.33 src/sys/arch/riscv/riscv/locore.S:1.34
--- src/sys/arch/riscv/riscv/locore.S:1.33 Sat Oct 15 16:29:56 2022
+++ src/sys/arch/riscv/riscv/locore.S Sat Oct 15 16:34:29 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.33 2022/10/15 16:29:56 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.34 2022/10/15 16:34:29 skrll Exp $ */
/*-
* Copyright (c) 2014, 2022 The NetBSD Foundation, Inc.
@@ -94,8 +94,8 @@ ENTRY_NP(start)
mv s1, a1 // copy dtb PA
/* set the stack pointer for boot */
- PTR_LA s8, _C_LABEL(bootstk)
- mv sp, s8
+ PTR_LA t0, _C_LABEL(bootstk)
+ mv sp, t0
VPRINTS("\n\nNetBSD start\n\n")
VPRINTS("sp: ")
@@ -115,10 +115,10 @@ ENTRY_NP(start)
* Calculate the difference between the VA and PA for start and
* keep in s8. Store this in kern_vtopdiff once the MMU is on.
*/
- PTR_LA s11, start
+ PTR_LA t0, start
PTR_L s8, .Lstart
- sub s8, s8, s11
+ sub s8, s8, t0
PTR_LA s5, _C_LABEL(lwp0uspace)
PTR_LA s6, _C_LABEL(bootstk)
@@ -330,9 +330,9 @@ vstart:
PTR_LA a0, _C_LABEL(cpu_exception_handler)
csrw stvec, a0
- PTR_LA s2, bootstk // top of lwp0uspace
- PTR_S s2, L_PCB(tp) // set uarea of lwp (already zeroed)
- addi sp, s2, -TF_LEN // switch to new stack
+ PTR_LA t0, bootstk // top of lwp0uspace
+ PTR_S t0, L_PCB(tp) // set uarea of lwp (already zeroed)
+ addi sp, t0, -TF_LEN // switch to new stack
PTR_S sp, L_MD_UTF(tp) // store pointer to empty trapframe
PTR_LA t1, _C_LABEL(kernel_pmap_store)
@@ -345,8 +345,8 @@ vstart:
* Store kern_vtopdiff (the difference between the physical
* and virtual address of the "start" symbol).
*/
- PTR_LA s11, _C_LABEL(kern_vtopdiff)
- PTR_S s8, 0(s11) /* kern_vtopdiff = start(virt) - start(phys) */
+ PTR_LA t0, _C_LABEL(kern_vtopdiff)
+ PTR_S s8, 0(t0) /* kern_vtopdiff = start(virt) - start(phys) */
#if notyet
mv a0, s1 // dtb
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Oct 15 16:34:29 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Shuffle some register usage To generate a diff of this commit: cvs rdiff -u -r1.33 -r1.34 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Oct 15 16:29:56 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Comment re-arragement To generate a diff of this commit: cvs rdiff -u -r1.32 -r1.33 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.32 src/sys/arch/riscv/riscv/locore.S:1.33 --- src/sys/arch/riscv/riscv/locore.S:1.32 Sat Oct 15 16:20:32 2022 +++ src/sys/arch/riscv/riscv/locore.S Sat Oct 15 16:29:56 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.32 2022/10/15 16:20:32 skrll Exp $ */ +/* $NetBSD: locore.S,v 1.33 2022/10/15 16:29:56 skrll Exp $ */ /*- * Copyright (c) 2014, 2022 The NetBSD Foundation, Inc. @@ -120,17 +120,17 @@ ENTRY_NP(start) sub s8, s8, s11 + PTR_LA s5, _C_LABEL(lwp0uspace) + PTR_LA s6, _C_LABEL(bootstk) + /* * Our load address is not fixed, but our VA is. We need to construct * an initial PDETAB. + * + * The space for the inital page table is included in the kernel + * .bss size calculation so we know the space exists. */ - PTR_LA s5, _C_LABEL(lwp0uspace) - PTR_LA s6, _C_LABEL(bootstk) - - // The space for the inital page table is included in the kernel - // .bss size calculation so we know the space exists. - li a1, 0 PTR_LA s2, _C_LABEL(l1_pte) mv s4, s2 // last page table
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Oct 15 16:29:56 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Comment re-arragement To generate a diff of this commit: cvs rdiff -u -r1.32 -r1.33 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Oct 15 16:20:32 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Remove unnecessary register assignments To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Oct 15 16:20:32 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Remove unnecessary register assignments To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.31 src/sys/arch/riscv/riscv/locore.S:1.32 --- src/sys/arch/riscv/riscv/locore.S:1.31 Fri Oct 14 08:10:22 2022 +++ src/sys/arch/riscv/riscv/locore.S Sat Oct 15 16:20:32 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.31 2022/10/14 08:10:22 skrll Exp $ */ +/* $NetBSD: locore.S,v 1.32 2022/10/15 16:20:32 skrll Exp $ */ /*- * Copyright (c) 2014, 2022 The NetBSD Foundation, Inc. @@ -125,9 +125,6 @@ ENTRY_NP(start) * an initial PDETAB. */ - li s10, PAGE_SIZE - li s9, USPACE - PTR_LA s5, _C_LABEL(lwp0uspace) PTR_LA s6, _C_LABEL(bootstk)
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Fri Oct 14 08:10:22 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Pretty print
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/riscv/riscv/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.30 src/sys/arch/riscv/riscv/locore.S:1.31
--- src/sys/arch/riscv/riscv/locore.S:1.30 Fri Oct 14 07:58:30 2022
+++ src/sys/arch/riscv/riscv/locore.S Fri Oct 14 08:10:22 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.30 2022/10/14 07:58:30 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.31 2022/10/14 08:10:22 skrll Exp $ */
/*-
* Copyright (c) 2014, 2022 The NetBSD Foundation, Inc.
@@ -212,6 +212,7 @@ ENTRY_NP(start)
#endif
REG_S t0, 0(t1)
+ VPRINTS("l2pde: ")
VPRINTX(t1)
#else
#ifdef notyet
@@ -220,10 +221,11 @@ ENTRY_NP(start)
REG_S t0, 0(s3)
#endif
+ VPRINTS("l2pde: ")
VPRINTX(s3)
#endif
- VPRINTS(": ")
+ VPRINTS(": ")
VPRINTXNL(t0)
VPRINTS("\n\r")
#endif // _LP64
@@ -249,9 +251,9 @@ ENTRY_NP(start)
slli s0, s0, (SEGSHIFT - PGSHIFT + PTE_PPN_SHIFT) // ... to PPN
or s0, s0, s7
.Lfill:
- VPRINTS("kern ")
+ VPRINTS("kern:")
VPRINTX(s2)
- VPRINTS(": ")
+ VPRINTS(": ")
VPRINTXNL(s0)
REG_S s0, 0(s2) // store PDE
@@ -268,9 +270,9 @@ ENTRY_NP(start)
slli s0, s0, (SEGSHIFT - PGSHIFT + PTE_PPN_SHIFT) // ... to PPN
or s0, s0, s7
- VPRINTS("dtb ")
+ VPRINTS("dtb: ")
VPRINTX(s2)
- VPRINTS(": ")
+ VPRINTS(": ")
VPRINTXNL(s0)
REG_S s0, 0(s2)
@@ -282,9 +284,9 @@ ENTRY_NP(start)
slli s0, s0, (SEGSHIFT - PGSHIFT + PTE_PPN_SHIFT) // ... to PPN
or s0, s0, s7
- VPRINTS("cons ")
+ VPRINTS("cons:")
VPRINTX(s2)
- VPRINTS(": ")
+ VPRINTS(": ")
VPRINTXNL(s0)
REG_S s0, 0(s2)
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Fri Oct 14 08:10:22 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Pretty print To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: simonb
Date: Wed Oct 12 07:53:56 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: db_machdep.c
Log Message:
Nuke funny trailing whitespace.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/riscv/db_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/db_machdep.c
diff -u src/sys/arch/riscv/riscv/db_machdep.c:1.9 src/sys/arch/riscv/riscv/db_machdep.c:1.10
--- src/sys/arch/riscv/riscv/db_machdep.c:1.9 Tue Sep 27 08:18:21 2022
+++ src/sys/arch/riscv/riscv/db_machdep.c Wed Oct 12 07:53:56 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.9 2022/09/27 08:18:21 skrll Exp $ */
+/* $NetBSD: db_machdep.c,v 1.10 2022/10/12 07:53:56 simonb Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: db_machdep.c,v 1.9 2022/09/27 08:18:21 skrll Exp $");
+__RCSID("$NetBSD: db_machdep.c,v 1.10 2022/10/12 07:53:56 simonb Exp $");
#include
@@ -274,6 +274,3 @@ db_write_bytes(vaddr_t addr, size_t len,
}
__asm("fence rw,rw; fence.i");
}
-
-
-
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: simonb Date: Wed Oct 12 07:53:56 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: db_machdep.c Log Message: Nuke funny trailing whitespace. To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/riscv/db_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Thu Sep 29 06:51:17 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: exec_machdep.c vm_machdep.c Log Message: Remove unnecessary include of . To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/exec_machdep.c cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/vm_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/exec_machdep.c diff -u src/sys/arch/riscv/riscv/exec_machdep.c:1.2 src/sys/arch/riscv/riscv/exec_machdep.c:1.3 --- src/sys/arch/riscv/riscv/exec_machdep.c:1.2 Wed Nov 4 07:09:46 2020 +++ src/sys/arch/riscv/riscv/exec_machdep.c Thu Sep 29 06:51:17 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: exec_machdep.c,v 1.2 2020/11/04 07:09:46 skrll Exp $ */ +/* $NetBSD: exec_machdep.c,v 1.3 2022/09/29 06:51:17 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -30,14 +30,13 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: exec_machdep.c,v 1.2 2020/11/04 07:09:46 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: exec_machdep.c,v 1.3 2022/09/29 06:51:17 skrll Exp $"); #include "opt_execfmt.h" #include #include #include -#include #include #include #include Index: src/sys/arch/riscv/riscv/vm_machdep.c diff -u src/sys/arch/riscv/riscv/vm_machdep.c:1.4 src/sys/arch/riscv/riscv/vm_machdep.c:1.5 --- src/sys/arch/riscv/riscv/vm_machdep.c:1.4 Wed Nov 4 20:04:01 2020 +++ src/sys/arch/riscv/riscv/vm_machdep.c Thu Sep 29 06:51:17 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: vm_machdep.c,v 1.4 2020/11/04 20:04:01 skrll Exp $ */ +/* $NetBSD: vm_machdep.c,v 1.5 2022/09/29 06:51:17 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.4 2020/11/04 20:04:01 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.5 2022/09/29 06:51:17 skrll Exp $"); #define _PMAP_PRIVATE @@ -39,7 +39,6 @@ __KERNEL_RCSID(0, "$NetBSD: vm_machdep.c #include #include #include -#include #include #include #include
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Thu Sep 29 06:51:17 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: exec_machdep.c vm_machdep.c Log Message: Remove unnecessary include of . To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/exec_machdep.c cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/vm_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Wed Sep 21 07:07:34 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Add some causes and convenience macros
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.16 src/sys/arch/riscv/riscv/trap.c:1.17
--- src/sys/arch/riscv/riscv/trap.c:1.16 Thu Oct 7 07:13:35 2021
+++ src/sys/arch/riscv/riscv/trap.c Wed Sep 21 07:07:34 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.16 2021/10/07 07:13:35 skrll Exp $ */
+/* $NetBSD: trap.c,v 1.17 2022/09/21 07:07:34 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.16 2021/10/07 07:13:35 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.17 2022/09/21 07:07:34 skrll Exp $");
#include
#include
@@ -48,14 +48,28 @@ __RCSID("$NetBSD: trap.c,v 1.16 2021/10/
#include
+#define MACHINE_ECALL_TRAP_MASK (__BIT(CAUSE_MACHINE_ECALL))
+
+#define SUPERVISOR_ECALL_TRAP_MASK \
+(__BIT(CAUSE_SUPERVISOR_ECALL))
+
+#define USER_ECALL_TRAP_MASK (__BIT(CAUSE_USER_ECALL))
+
+#define SYSCALL_TRAP_MASK (__BIT(CAUSE_SYSCALL))
+
+#define BREAKPOINT_TRAP_MASK (__BIT(CAUSE_BREAKPOINT))
+
#define INSTRUCTION_TRAP_MASK (__BIT(CAUSE_ILLEGAL_INSTRUCTION))
-#define FAULT_TRAP_MASK (__BIT(CAUSE_FETCH_ACCESS) \
-|__BIT(CAUSE_LOAD_ACCESS) \
-|__BIT(CAUSE_STORE_ACCESS))
+#define FAULT_TRAP_MASK (__BIT(CAUSE_FETCH_ACCESS) \
+|__BIT(CAUSE_LOAD_ACCESS) \
+|__BIT(CAUSE_STORE_ACCESS) \
+|__BIT(CAUSE_FETCH_PAGE_FAULT) \
+|__BIT(CAUSE_LOAD_PAGE_FAULT) \
+|__BIT(CAUSE_STORE_PAGE_FAULT))
-#define MISALIGNED_TRAP_MASK (__BIT(CAUSE_FETCH_MISALIGNED) \
-|__BIT(CAUSE_LOAD_MISALIGNED) \
+#define MISALIGNED_TRAP_MASK (__BIT(CAUSE_FETCH_MISALIGNED) \
+|__BIT(CAUSE_LOAD_MISALIGNED) \
|__BIT(CAUSE_STORE_MISALIGNED))
static const char * const causenames[] = {
@@ -67,6 +81,10 @@ static const char * const causenames[] =
[CAUSE_STORE_ACCESS] = "store",
[CAUSE_ILLEGAL_INSTRUCTION] = "illegal instruction",
[CAUSE_BREAKPOINT] = "breakpoint",
+ [CAUSE_SYSCALL] = "syscall",
+ [CAUSE_FETCH_PAGE_FAULT] = "instruction page fault",
+ [CAUSE_LOAD_PAGE_FAULT] = "load page fault",
+ [CAUSE_STORE_PAGE_FAULT] = "store page fault",
};
void
@@ -219,11 +237,11 @@ cpu_trapsignal(struct trapframe *tf, ksi
static inline vm_prot_t
get_faulttype(register_t cause)
{
- if (cause == CAUSE_LOAD_ACCESS)
+ if (cause == CAUSE_LOAD_ACCESS || cause == CAUSE_LOAD_PAGE_FAULT)
return VM_PROT_READ;
- if (cause == CAUSE_STORE_ACCESS)
+ if (cause == CAUSE_STORE_ACCESS || cause == CAUSE_STORE_PAGE_FAULT)
return VM_PROT_READ | VM_PROT_WRITE;
- KASSERT(cause == CAUSE_FETCH_ACCESS);
+ KASSERT(cause == CAUSE_FETCH_ACCESS || cause == CAUSE_FETCH_PAGE_FAULT);
return VM_PROT_READ | VM_PROT_EXECUTE;
}
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Wed Sep 21 07:07:34 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: trap.c Log Message: Add some causes and convenience macros To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/trap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Tue Sep 20 06:53:37 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.16 src/sys/arch/riscv/riscv/riscv_machdep.c:1.17
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.16 Tue Sep 20 06:48:29 2022
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Tue Sep 20 06:53:36 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.16 2022/09/20 06:48:29 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.17 2022/09/20 06:53:36 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include
#include "opt_modular.h"
-__RCSID("$NetBSD: riscv_machdep.c,v 1.16 2022/09/20 06:48:29 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.17 2022/09/20 06:53:36 skrll Exp $");
#include
@@ -258,10 +258,10 @@ cpu_need_resched(struct cpu_info *ci, st
if ((flags & RESCHED_KPREEMPT) != 0) {
#ifdef __HAVE_PREEMPTION
if ((flags & RESCHED_REMOTE) != 0) {
-cpu_send_ipi(ci, IPI_KPREEMPT);
+ cpu_send_ipi(ci, IPI_KPREEMPT);
} else {
softint_trigger(SOFTINT_KPREEMPT);
-}
+ }
#endif
return;
}
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Tue Sep 20 06:53:37 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: riscv_machdep.c Log Message: Whitespace To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Tue Sep 20 06:48:29 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.15 src/sys/arch/riscv/riscv/riscv_machdep.c:1.16
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.15 Thu Oct 7 07:13:35 2021
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Tue Sep 20 06:48:29 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.15 2021/10/07 07:13:35 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.16 2022/09/20 06:48:29 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
@@ -32,20 +32,20 @@
#include
#include "opt_modular.h"
-
-__RCSID("$NetBSD: riscv_machdep.c,v 1.15 2021/10/07 07:13:35 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.16 2022/09/20 06:48:29 skrll Exp $");
#include
-#include
+
#include
#include
-#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Tue Sep 20 06:48:29 UTC 2022 Modified Files: src/sys/arch/riscv/riscv: riscv_machdep.c Log Message: KNF To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sat Oct 30 07:18:47 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
Fix thinko in tlb_record_asids memset size calculation.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/riscv/pmap_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/pmap_machdep.c
diff -u src/sys/arch/riscv/riscv/pmap_machdep.c:1.9 src/sys/arch/riscv/riscv/pmap_machdep.c:1.10
--- src/sys/arch/riscv/riscv/pmap_machdep.c:1.9 Thu Oct 7 07:13:35 2021
+++ src/sys/arch/riscv/riscv/pmap_machdep.c Sat Oct 30 07:18:46 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap_machdep.c,v 1.9 2021/10/07 07:13:35 skrll Exp $ */
+/* $NetBSD: pmap_machdep.c,v 1.10 2021/10/30 07:18:46 skrll Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#include
-__RCSID("$NetBSD: pmap_machdep.c,v 1.9 2021/10/07 07:13:35 skrll Exp $");
+__RCSID("$NetBSD: pmap_machdep.c,v 1.10 2021/10/30 07:18:46 skrll Exp $");
#include
@@ -214,7 +214,7 @@ tlb_update_addr(vaddr_t va, tlb_asid_t a
u_int
tlb_record_asids(u_long *ptr, tlb_asid_t asid_max)
{
- memset(ptr, 0xff, PMAP_TLB_NUM_PIDS / (8 * sizeof(u_long)));
+ memset(ptr, 0xff, PMAP_TLB_NUM_PIDS / NBBY);
ptr[0] = -2UL;
return PMAP_TLB_NUM_PIDS - 1;
}
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Oct 30 07:18:47 UTC 2021 Modified Files: src/sys/arch/riscv/riscv: pmap_machdep.c Log Message: Fix thinko in tlb_record_asids memset size calculation. To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/riscv/pmap_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Thu Oct 7 07:13:35 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c riscv_machdep.c syscall.c
trap.c
Log Message:
Hacky build fixes
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/riscv/pmap_machdep.c
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/riscv/riscv_machdep.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/syscall.c
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/pmap_machdep.c
diff -u src/sys/arch/riscv/riscv/pmap_machdep.c:1.8 src/sys/arch/riscv/riscv/pmap_machdep.c:1.9
--- src/sys/arch/riscv/riscv/pmap_machdep.c:1.8 Sat Oct 2 14:28:05 2021
+++ src/sys/arch/riscv/riscv/pmap_machdep.c Thu Oct 7 07:13:35 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap_machdep.c,v 1.8 2021/10/02 14:28:05 skrll Exp $ */
+/* $NetBSD: pmap_machdep.c,v 1.9 2021/10/07 07:13:35 skrll Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#include
-__RCSID("$NetBSD: pmap_machdep.c,v 1.8 2021/10/02 14:28:05 skrll Exp $");
+__RCSID("$NetBSD: pmap_machdep.c,v 1.9 2021/10/07 07:13:35 skrll Exp $");
#include
@@ -57,22 +57,30 @@ pmap_bootstrap(void)
void
pmap_zero_page(paddr_t pa)
{
+#ifdef _LP64
#ifdef PMAP_DIRECT_MAP
memset((void *)PMAP_DIRECT_MAP(pa), 0, PAGE_SIZE);
#else
#error "no direct map"
#endif
+#else
+ KASSERT(false);
+#endif
}
void
pmap_copy_page(paddr_t src, paddr_t dst)
{
+#ifdef _LP64
#ifdef PMAP_DIRECT_MAP
memcpy((void *)PMAP_DIRECT_MAP(dst), (const void *)PMAP_DIRECT_MAP(src),
PAGE_SIZE);
#else
#error "no direct map"
#endif
+#else
+ KASSERT(false);
+#endif
}
struct vm_page *
@@ -113,10 +121,15 @@ paddr_t
pmap_md_direct_mapped_vaddr_to_paddr(vaddr_t va)
{
#ifdef _LP64
+#ifdef PMAP_DIRECT_MAP
return PMAP_DIRECT_UNMAP(va);
#else
#error "no direct map"
#endif
+#else
+ KASSERT(false);
+ return 0;
+#endif
}
vaddr_t
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.14 src/sys/arch/riscv/riscv/riscv_machdep.c:1.15
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.14 Sat May 1 06:53:08 2021
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Thu Oct 7 07:13:35 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.14 2021/05/01 06:53:08 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.15 2021/10/07 07:13:35 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#include "opt_modular.h"
-__RCSID("$NetBSD: riscv_machdep.c,v 1.14 2021/05/01 06:53:08 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.15 2021/10/07 07:13:35 skrll Exp $");
#include
#include
@@ -157,7 +157,9 @@ startlwp(void *arg)
// We've worked hard to make sure struct reg and __gregset_t are the same.
// Ditto for struct fpreg and fregset_t.
+#ifdef _LP64
CTASSERT(sizeof(struct reg) == sizeof(__gregset_t));
+#endif
CTASSERT(sizeof(struct fpreg) == sizeof(__fregset_t));
void
Index: src/sys/arch/riscv/riscv/syscall.c
diff -u src/sys/arch/riscv/riscv/syscall.c:1.2 src/sys/arch/riscv/riscv/syscall.c:1.3
--- src/sys/arch/riscv/riscv/syscall.c:1.2 Sat Mar 14 16:12:16 2020
+++ src/sys/arch/riscv/riscv/syscall.c Thu Oct 7 07:13:35 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: syscall.c,v 1.2 2020/03/14 16:12:16 skrll Exp $ */
+/* $NetBSD: syscall.c,v 1.3 2021/10/07 07:13:35 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: syscall.c,v 1.2 2020/03/14 16:12:16 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: syscall.c,v 1.3 2021/10/07 07:13:35 skrll Exp $");
#include
#include
@@ -81,7 +81,6 @@ EMULNAME(syscall)(struct trapframe *tf)
register_t retval[2];
const struct sysent *callp;
int code, error;
- size_t i;
#ifdef _LP64
const bool pk32_p = (p->p_flag & PK_32) != 0;
register_t copyargs[EMULNAME(SYS_MAXSYSARGS)];
@@ -110,8 +109,8 @@ EMULNAME(syscall)(struct trapframe *tf)
else
callp += code;
- const size_t nargs = callp->sy_narg;
#ifdef _LP64
+ const size_t nargs = callp->sy_narg;
/*
* If there are no 64bit arguments, we still need "sanitize" the
* 32-bit arguments in case they try to slip through a 64-bit pointer.
@@ -141,7 +140,7 @@ EMULNAME(syscall)(struct trapframe *tf)
* encounter a 64 bit argument, we grab two adjacent 32bit
* values and synthesize the 64bit argument.
*/
- for (i = 0; i < nargs + narg64; ) {
+ for (size_t i = 0; i < nargs + narg64; ) {
register_t arg = *args32++;
if (__predict_true((arg64mask & 1) == 0)) {
/*
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.15 src/sys/arch/riscv/riscv/trap.c:1.16
--- src/sys/arch/riscv/riscv/trap.c:1.15 Sun Dec 20 16:38:26
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Thu Oct 7 07:13:35 UTC 2021 Modified Files: src/sys/arch/riscv/riscv: pmap_machdep.c riscv_machdep.c syscall.c trap.c Log Message: Hacky build fixes To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/riscv/pmap_machdep.c cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/riscv/riscv_machdep.c cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/syscall.c cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/riscv/trap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Re: CVS commit: src/sys/arch/riscv/riscv
Hi Matt, On Tue, Mar 31, 2015 at 01:30:50AM +, Matt Thomas wrote: When the cpu gets an exception from kernel mode, the sscratch register will be 0 and curlwp will be in the tp register. When the cpu gets an exception from user mode, the sscratch register will be a pointer to the current lwp. Will the kernel not be confused and choose the wrong path if a userland programs clears the sp register and gets an exception, say be storing a stack frame? by accident or deliberately? Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.1 src/sys/arch/riscv/riscv/locore.S:1.2 --- src/sys/arch/riscv/riscv/locore.S:1.1 Sat Mar 28 16:13:56 2015 +++ src/sys/arch/riscv/riscv/locore.S Tue Mar 31 01:30:50 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.1 2015/03/28 16:13:56 matt Exp $ */ +/* $NetBSD: locore.S,v 1.2 2015/03/31 01:30:50 matt Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. * All rights reserved. @@ -78,10 +78,10 @@ ENTRY_NP(start) callmemset // zero through kernel_end // As a temporary hack, word 0 contains the amount of memory in MB - lw a7, (zero) // load memory size + INT_L a7, (zero) // load memory size sllia7, a7, (20-PGSHIFT)// convert MB to pages - auipc t0, %pcrel_hi(physmem) - sw a7, %pcrel_lo(physmem)(t0) // store it in physmem +.L01:auipc t0, %pcrel_hi(physmem) + INT_S a7, %pcrel_lo(.L01)(t0) // store it in physmem Why are you loading the lower PC relative part of .L01 in stead of physmem? won't that give the wrong lower bits? Isn't there a PTR_S macro to handle this? With regards, Reinoud pgpjQXdqjH9e1.pgp Description: PGP signature
