Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Dan Watson]

This thread really makes me want to do an FPGA timing project. I have a
Papilio One on hand, which uses the Spartan 3E.

But what to do with it? It has to be something much more interesting than
what a PicDiv or simple logic can do to make it worth my time. Hmm...



Dan

On Mon, Jun 8, 2015 at 3:42 PM, cfo  wrote:

> On Mon, 08 Jun 2015 16:27:26 +0100, David C. Partridge wrote:
>
> > I'm up for either ...  My thoughts are to try it out on a development
> > board and if it works, maybe build a few for possible sale, and also
> > release Gerbers and VHDL files.
> >
> > Regards,
> > David Partridge
>
> I have these cheap cards , that might be a nice start.
>
> CPLD Altera EPM240 (make sure you get the blue board)
> Ebay: 271520142479
>
> Fpga (2 onboard PLL's) older Cyclone2 , but prob ok.
> Ebay: 400630255386
>
>
> Programmer:
> Ebay: 200943750380
>
> If they could be the heart of the system, then everybody could get
> started cheap.
>
> I'm using Quartus2 on Linux (Mint17) , works ok.
> But Modelsim needs some extra libs to function.
>
>
> CFO
>
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[cfo]

On Mon, 08 Jun 2015 16:27:26 +0100, David C. Partridge wrote:

> I'm up for either ...  My thoughts are to try it out on a development
> board and if it works, maybe build a few for possible sale, and also
> release Gerbers and VHDL files.
> 
> Regards,
> David Partridge 

I have these cheap cards , that might be a nice start.

CPLD Altera EPM240 (make sure you get the blue board)
Ebay: 271520142479  

Fpga (2 onboard PLL's) older Cyclone2 , but prob ok.
Ebay: 400630255386


Programmer: 
Ebay: 200943750380

If they could be the heart of the system, then everybody could get 
started cheap.

I'm using Quartus2 on Linux (Mint17) , works ok.
But Modelsim needs some extra libs to function.


CFO

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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[David C. Partridge]

I'm up for either ...  My thoughts are to try it out on a development board and 
if it works, maybe build a few for possible sale, and also release Gerbers and 
VHDL files.

Regards,
David Partridge 
-Original Message-
From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of cfo
Sent: 08 June 2015 15:09
To: time-nuts@febo.com
Subject: Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

On Sun, 07 Jun 2015 11:23:40 +0100, David C. Partridge wrote:

> My reading so far of what's been said in this thread is that you might 
> get good results using a CPLD/FPGA as a divider but ... .
..
..
..
> Thanks again Dave

Is this going to be an "open source" project, or something you buy  ?

CFO

--
E-mail:xne...@luna.dyndns.dk

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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[cfo]

On Sun, 07 Jun 2015 11:23:40 +0100, David C. Partridge wrote:

> My reading so far of what's been said in this thread is that you might
> get good results using a CPLD/FPGA as a divider but ... .
..
..
..
> Thanks again Dave

Is this going to be an "open source" project, or something you buy  ?

CFO

-- 
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Bob Camp]

Hi

As always, the real answer is “that depends”. 

If you are dividing to 1 pps from 10 MHz, the CPLD or FPGA is a fine answer to 
the question. It will give you some cool bells and whistles (like sync and 
advance / retard) without adding anything to the budget. If you wish to re-sync 
the output with a single gate D-FF running on the “wrong edge” of the 10 MHz, 
that’s easily done and it adds virtually nothing to the board space or cost. 

If you are building a low noise PLL and going from 160 MHz down to a 40 MHz 
analog phase detector (with a floor of -170 dbc/ Hz), the CLPD or FPGA isn’t a 
good choice. You can do the complete divide with a single package part and get 
lower noise. 

The board with the 160 MHz PLL on it is going to be a single purpose layout and 
it will live it’s life doing one thing. The board with the 1 pps
divider might get re-purposed to do a variety of things. A “universal” FPGA 
board with some basic timing stuff (connectors / re-sync flip flops / input 
gates)  on it might be a very useful thing to have around …..

> On Jun 7, 2015, at 6:23 AM, David C. Partridge 
>  wrote:
> 
> My reading so far of what's been said in this thread is that you might get 
> good results using a CPLD/FPGA as a divider but ... .
> 
> Bruce pointed me to Rubiola's paper 
> ,
>  and while I'm sure the lambda divider is excellent, there's a definite 
> problem of needing to re-square the output after every stage if you want a 
> multi-stage design.  This makes me wonder if you'd end up adding enough 
> additional jitter/phase noise to more than counteract the benefit of the 
> lambda divider (which produces a stepped triangle wave).  TANSTAAFL seems to 
> apply here.
> 
> My biggest concern is that if I build a multi-stage divider (*) using a 
> single CPLD or FPGA, I could end up with cross-talk problems similar that 
> encountered with multi-gate logic packages.

Internal cross talk on FPGA’s and CPLD’s is pretty much a non-issue. That 
assumes that the board is properly laid out and the supplies are 
well bypassed. Input and output cross talk can be reduced (but not always 
eliminated) by running differential inputs and putting “threat” signals on 
different i/o banks from each other. 

The “properly laid out” constraint with a FPGA / CPLD forces you to a > 2 layer 
board pretty fast. Depending on the density and a few other things you may be 
past 6 layers. Yes that costs money. 

Bob

>  I don't think it makes sense to use a CPLD if you need to use a separate 
> package for each stage.
> 
> I'm also a bit concerned by Bob Camp's comment:
> 
>> they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz 
>> you could expect under similar conditions with something like AC or faster 
>> CMOS
> 
> which suggests that it will be (at least 10dB) worse than my existing design 
> :(
> 
> I guess that it might work if the output were re-synched to the input using 
> external D-flops after the main grunt work is done in a CPLD/FPGA.
> 
> I'm also a bothered by the findings in 
> 
>  which indicate that the lowest noise devices tested were the Altera Max 3000 
> series which Altera dsecribe as "Mature" so may be at risk of obsolescence
> 
> Thanks to all for the discussion to date.
> 
> (*) similar to my previous effort made with 74AC logic. 
> 
> Thanks again
> Dave
> 
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[David C. Partridge]

My reading so far of what's been said in this thread is that you might get good 
results using a CPLD/FPGA as a divider but ... .

Bruce pointed me to Rubiola's paper 
, 
and while I'm sure the lambda divider is excellent, there's a definite problem 
of needing to re-square the output after every stage if you want a multi-stage 
design.  This makes me wonder if you'd end up adding enough additional 
jitter/phase noise to more than counteract the benefit of the lambda divider 
(which produces a stepped triangle wave).  TANSTAAFL seems to apply here.

My biggest concern is that if I build a multi-stage divider (*) using a single 
CPLD or FPGA, I could end up with cross-talk problems similar that encountered 
with multi-gate logic packages.  I don't think it makes sense to use a CPLD if 
you need to use a separate package for each stage.

I'm also a bit concerned by Bob Camp's comment:

>they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz you 
>could expect under similar conditions with something like AC or faster CMOS

which suggests that it will be (at least 10dB) worse than my existing design :(

I guess that it might work if the output were re-synched to the input using 
external D-flops after the main grunt work is done in a CPLD/FPGA.

I'm also a bothered by the findings in 

 which indicate that the lowest noise devices tested were the Altera Max 3000 
series which Altera dsecribe as "Mature" so may be at risk of obsolescence

Thanks to all for the discussion to date.

(*) similar to my previous effort made with 74AC logic. 

Thanks again
Dave

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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Bob Camp]

Hi

Last time I saw university multi project wafer prices, the cost was around $5K 
for a
run on a “not state of the art” fab process. That included absolutely nothing
in the way of design assistance. It was strictly “we fab what you told us to 
do”. The
“run date” for the chips was also a bit vague. They used space on other design 
runs, so 
you got about a 3 month window on when your parts might run. Eventually you got 
back
a waffle pack with some die to go wire bond up. 

Often the trick was to take the work of several students and put in on a single 
chip. The
*hope* was that nothing pathogenic happened in any of the designs to render the 
whole thing useless.

The gotcha on ASIC’s os (of course) the running cost of this stuff. If you are 
using a bunch
of parts is’t not to bad. If not, the phone call every 4 years or so about “you 
need to 
buy a new mask set for $XXX,XXX” gets a bit old. For a state of the art process 
add 
at least one more X to that number. 

Coming back to timing. Once you go to an ASIC, the ability to optimize for low
jitter / good ADEV (or whatever) comes into the picture. There is no reason why
there should be any worse performance on the ASIC than on any logic family
you can find. All of the previous caveats about phase noise floors go away.  
That’s
not to say that things like crosstalk between two pads that are 0.05 mm apart 
suddenly
vanishes. You still have to take care of the i/o part of the design. 

Bob

> On Jun 6, 2015, at 1:49 PM, Attila Kinali  wrote:
> 
> On Sat, 6 Jun 2015 09:52:11 -0400
> Bob Camp  wrote:
> 
>>> Was it a simple 
>>> counter or was there enable/up/down/load type gating involved?
>>> 
>>> What would you have done if you needed to run a bit faster?
>> 
>> Bought a faster FPGA or gone to an ASIC. 
>> 
>>> Could you buy a 
>>> faster chip?  
>> 
>> For enough money there’s always a faster chip :)
> 
> Even if it is OT, to give this a little economic perspective:
> Today, an ASIC starts to be cheaper than an FPGA solution at production
> volumes somewhere between 1000 and 10'000 pieces (in total).
> If you have working (synchronous) VHDL code, going ASIC is pretty
> straight forward and is mostly automatic. There are several fabs
> in Europe and Asia that offer node sizes between 180nm and 35nm
> for even very small runs and help you to convert your FPGA code
> to proper ASIC designs.
> 
> A simple ASIC project is cheap enough, that some universities offer
> courses where students (in a master course) design their own chips,
> let them produce and measure their performance later, all cost covered
> by the university. (If i remember correctly, the cost was around 10kUSD
> per design and for 20 dies, half of them in QFP, half as nacked die)
> 
>   Attila Kinali
> 
> 
> -- 
> It is upon moral qualities that a society is ultimately founded. All 
> the prosperity and technological sophistication in the world is of no 
> use without that foundation.
> -- Miss Matheson, The Diamond Age, Neil Stephenson
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Attila Kinali]

On Sat, 6 Jun 2015 09:52:11 -0400
Bob Camp  wrote:

> > Was it a simple 
> > counter or was there enable/up/down/load type gating involved?
> > 
> > What would you have done if you needed to run a bit faster?
> 
> Bought a faster FPGA or gone to an ASIC. 
> 
> >  Could you buy a 
> > faster chip?  
> 
> For enough money there’s always a faster chip :)

Even if it is OT, to give this a little economic perspective:
Today, an ASIC starts to be cheaper than an FPGA solution at production
volumes somewhere between 1000 and 10'000 pieces (in total).
If you have working (synchronous) VHDL code, going ASIC is pretty
straight forward and is mostly automatic. There are several fabs
in Europe and Asia that offer node sizes between 180nm and 35nm
for even very small runs and help you to convert your FPGA code
to proper ASIC designs.

A simple ASIC project is cheap enough, that some universities offer
courses where students (in a master course) design their own chips,
let them produce and measure their performance later, all cost covered
by the university. (If i remember correctly, the cost was around 10kUSD
per design and for 20 dies, half of them in QFP, half as nacked die)

Attila Kinali


-- 
It is upon moral qualities that a society is ultimately founded. All 
the prosperity and technological sophistication in the world is of no 
use without that foundation.
 -- Miss Matheson, The Diamond Age, Neil Stephenson
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Bob Camp]

Hi

Here’s an example:

http://parts.arrow.com/item/detail/arrow-development-tools/bemicromax10#pg2e

https://www.altera.com/products/fpga/max-series/max-10/overview.highResolutionDisplay.html

There are other outfits that make similar parts that are at least as good. This 
is considered a
low end chip right now. The part on the demo board is a mid point for the part 
size wise. 

It will run 400 MHz clocks without much bother at all. It also is quite happy 
doing multiple modulo
divides to take those clocks down to multiple  1 pps outputs *and* have a load 
function on the
counter. You have enough room to use them as time tags on inputs to the FPGA 
and store a few
hours worth of data in memory. 

Can you do better with a faster part? sure can. Can you find cheaper parts? yes 
again. Is there
a competitor’s part that will do it cheaper / faster / easier (pick one) - most 
certainly. 

If you can enter a schematic into free software, you can design a pps divider 
with a part like this. 
No need to learn a programming language to work with one. The process is 
roughly the same as
learning a new pcb layout tool. Yes it runs on Linux and on Windows. 

I can’t buy the parts on the demo board for what they sell the board for. I 
can’t buy an 8 -10 
layer board that size in single piece for what they sell the demo board for. I 
can’t get it assembled
(BGA’s …) in one piece for what they sell the demo board for. I also can’t do 
multiples 
of that counter with discrete logic on a board that size. I also can’t buy all 
the chips that a 
counter that fast going that low would require (plus the board) for what the 
demo board 
costs. Bottom line, to use them, just buy them already on a board and mount 
that on 
whatever you are doing. 

No I’m not trying to sell you that demo board. I’m also not trying to convince 
you that there is one
and only one family of parts that are worth using. The point is - the world 
started going over to
FPGA’s in the mid 1980’s. Discrete logic design started to die out with ASIC’s 
in the early 1970’s.
For large scale stuff it was dead by the end of the 1970’s. Forty years later, 
there are very few 
places (other than i/o) that discrete gates get used. 

The world has changed a lot since the 1970’s. Design any UART’s with discrete 
logic since about 1971?

Bob

> On Jun 5, 2015, at 11:19 PM, Hal Murray  wrote:
> 
> 
> rich...@karlquist.com said:
>> I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
>> timebase.  It was great because you just write a 17 bit counter in VHDL and
>> there it is.  You don't have to know anything about building digital
>> hardware any more (40 years of experience wasted). Nobody cares about look
>> ahead carry, etc. 
> 
> Is that really true?  Or perhaps, what fraction of the digital design space 
> does it apply to?
> 
> How fast was your counter running?  How fast would it run?  Was it a simple 
> counter or was there enable/up/down/load type gating involved?
> 
> What would you have done if you needed to run a bit faster?  Could you buy a 
> faster chip?  How much more could you get with tricky logic?
> 
> I agree that modern tools and parts have allowed a lot more people to build 
> digital circuits.
> 
> 
> 
> -- 
> These are my opinions.  I hate spam.
> 
> 
> 
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Richard (Rick) Karlquist]

The counter only had to run at ~50 MHz, on account of our
mode locked laser ran at that frequency.  I don't remember
what the CPLD was rated at.

Rick

On 6/5/2015 8:19 PM, Hal Murray wrote:


rich...@karlquist.com said:

I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
timebase.  It was great because you just write a 17 bit counter in VHDL and
there it is.  You don't have to know anything about building digital
hardware any more (40 years of experience wasted). Nobody cares about look
ahead carry, etc.


Is that really true?  Or perhaps, what fraction of the digital design space
does it apply to?

How fast was your counter running?  How fast would it run?  Was it a simple
counter or was there enable/up/down/load type gating involved?

What would you have done if you needed to run a bit faster?  Could you buy a
faster chip?  How much more could you get with tricky logic?

I agree that modern tools and parts have allowed a lot more people to build
digital circuits.




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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Bob Camp]

Hi

> On Jun 5, 2015, at 11:19 PM, Hal Murray  wrote:
> 
> 
> rich...@karlquist.com said:
>> I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
>> timebase.  It was great because you just write a 17 bit counter in VHDL and
>> there it is.  You don't have to know anything about building digital
>> hardware any more (40 years of experience wasted). Nobody cares about look
>> ahead carry, etc. 
> 
> Is that really true?  

Yes, it’s really true.

> Or perhaps, what fraction of the digital design space 
> does it apply to?

The portion that does not take the design directly to an ASIC. (at
least in industry). Essentially the only thing done with discrete logic
these days are minor i/o chores. 

> 
> How fast was your counter running?
>  How fast would it run?  

That depends entirely on which FPGA or CPLD you buy. An old 100 MHz part will 
not
go as fast as a 800 MHz part. In this case speed is the toggle rate on the 
counter. 

> Was it a simple 
> counter or was there enable/up/down/load type gating involved?
> 
> What would you have done if you needed to run a bit faster?

Bought a faster FPGA or gone to an ASIC. 

>  Could you buy a 
> faster chip?  

For enough money there’s always a faster chip :)

> How much more could you get with tricky logic?

The days of “tricky logic” ( =  stuff the software does not understand) are now
the days of “hand place (route) the gates in the FPGA”.  It’s routing delay that
gets you before gate speed in most cases. The software routers have gotten 
awfully good ….

> 
> I agree that modern tools and parts have allowed a lot more people to build 
> digital circuits.

They did that only after they had been allowing mass conversion of designs over
to silicon for about two decades. The tools you see today are nothing like what
you had to use in the early 1990’s. 

The other thing that the design software has done is that it’s forced people to 
face up to timing constraints. Just as in the semiconductor industry, there is 
now
a “process spec” that is used to constrain the design. If it passes when fully 
constrained and checked, it will work in production. No more blue wires. No more
“oops!” re-spins on $20,000 pc boards. 

Bob

> 
> 
> 
> -- 
> These are my opinions.  I hate spam.
> 
> 
> 
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Hal Murray]

rich...@karlquist.com said:
> I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
> timebase.  It was great because you just write a 17 bit counter in VHDL and
> there it is.  You don't have to know anything about building digital
> hardware any more (40 years of experience wasted). Nobody cares about look
> ahead carry, etc. 

Is that really true?  Or perhaps, what fraction of the digital design space 
does it apply to?

How fast was your counter running?  How fast would it run?  Was it a simple 
counter or was there enable/up/down/load type gating involved?

What would you have done if you needed to run a bit faster?  Could you buy a 
faster chip?  How much more could you get with tricky logic?

I agree that modern tools and parts have allowed a lot more people to build 
digital circuits.



-- 
These are my opinions.  I hate spam.



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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Richard (Rick) Karlquist]

I used a CPLD in a 900 GHz (that's right 900 GHz) optical
sampling scope timebase.  It was great because you just
write a 17 bit counter in VHDL and there it is.  You
don't have to know anything about building digital
hardware any more (40 years of experience wasted).
Nobody cares about look ahead carry, etc.
I cleaned up the timing with conventional logic, so
I don't know what the jitter of the CPLD was.
We needed jitter in the low fs, so I am sure
the CPLD was not OK without cleaning up, but
then that was a lunatic fringe project.

Rick Karlquist N6RK

On 6/2/2015 6:13 AM, David C. Partridge wrote:

Is this a sensible thing to consider doing?  Or would I be better sticking to 
AC/HC/AHC/LVC logic?

Regards,
David Partridge

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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[jerry shirᴀr]

Thanks Bruce.  That is an excellent option.

I did a paper over a decade ago on the jitter and phase noise for Actel
(Now Microsemi) comparing their eX device to the Xilinx CPLD.  It was
intended to show the eX device was preferable to the Xilinx CPLD.  It makes
a difference as to what device is selected.

Jerry



On Tue, Jun 2, 2015 at 11:17 PM, Bruce Griffiths  wrote:

> You can always cleanup the outputs of the CPLD or FPGA by resynchronising
> the outputs to the input clock using a dedicated D flipflop for each output.
>
> Bruce
>
>
>
>  On Wednesday, 3 June 2015 3:22 PM, Bob Camp  wrote:
>
>
>  Hi
>
> A lot depends on exactly which CPLD or which FPGA you are looking at and
> how
> they put the guts of it together. If you find one that is “just right” it
> *might* be within
> 10 db of high speed CMOS. Since there is a 20 db delta between the HC you
> mention
> and the AC that leaves a bit of room.
>
> If you have a part with a bias generator in it, just forget about using
> it. You will have all
> sorts of strange spurs that come and go. They will be broadband. They will
> take the
> noise floor up into the 100 dbc / Hz range in some cases.
>
> If you are trying to use the internal PLL, it’s phase noise isn’t going to
> be great. Numbers
> like -135 dbc / Hz at 100 KHz offset are not uncommon on an HF output.
>
> As straight dividers, they might get to -16x dbc/ Hz region. That compares
> to the -174 dbc / Hz
> you could expect under similar conditions with something like AC or faster
> CMOS. You
> are more likely to get there on a fast CLPD than on an FPGA. Either way
> you can run
> into bum parts.
>
> Bob
>
> > On Jun 2, 2015, at 9:13 AM, David C. Partridge <
> david.partri...@perdrix.co.uk> wrote:
> >
> > Is this a sensible thing to consider doing?  Or would I be better
> sticking to AC/HC/AHC/LVC logic?
> >
> > Regards,
> > David Partridge
> >
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Bob Camp]

Hi

As always, the real answer it “that depends”. 

If your objective is wide band phase noise and you want to start from 100 MHz 
and get 10 MHz (fig 6 in
the Lamda paper), you can get at least another 6 db with a simple divide by 10 
chip than with all the 
fancy stuff. 

Bob

> On Jun 3, 2015, at 12:17 AM, Bruce Griffiths  
> wrote:
> 
> You can always cleanup the outputs of the CPLD or FPGA by resynchronising the 
> outputs to the input clock using a dedicated D flipflop for each output. 
> 
> Bruce
> 
> 
> 
> On Wednesday, 3 June 2015 3:22 PM, Bob Camp  wrote:
> 
> 
> Hi
> 
> A lot depends on exactly which CPLD or which FPGA you are looking at and how 
> they put the guts of it together. If you find one that is “just right” it 
> *might* be within
> 10 db of high speed CMOS. Since there is a 20 db delta between the HC you 
> mention
> and the AC that leaves a bit of room. 
> 
> If you have a part with a bias generator in it, just forget about using it. 
> You will have all 
> sorts of strange spurs that come and go. They will be broadband. They will 
> take the 
> noise floor up into the 100 dbc / Hz range in some cases. 
> 
> If you are trying to use the internal PLL, it’s phase noise isn’t going to be 
> great. Numbers
> like -135 dbc / Hz at 100 KHz offset are not uncommon on an HF output. 
> 
> As straight dividers, they might get to -16x dbc/ Hz region. That compares to 
> the -174 dbc / Hz
> you could expect under similar conditions with something like AC or faster 
> CMOS. You 
> are more likely to get there on a fast CLPD than on an FPGA. Either way you 
> can run
> into bum parts. 
> 
> Bob
> 
>> On Jun 2, 2015, at 9:13 AM, David C. Partridge 
>>  wrote:
>> 
>> Is this a sensible thing to consider doing?  Or would I be better sticking 
>> to AC/HC/AHC/LVC logic?
>> 
>> Regards,
>> David Partridge 
>> 
>> ___
>> time-nuts mailing list -- time-nuts@febo.com
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> 
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Bruce Griffiths]

You can always cleanup the outputs of the CPLD or FPGA by resynchronising the 
outputs to the input clock using a dedicated D flipflop for each output. 

Bruce
 


 On Wednesday, 3 June 2015 3:22 PM, Bob Camp  wrote:
   

 Hi

A lot depends on exactly which CPLD or which FPGA you are looking at and how 
they put the guts of it together. If you find one that is “just right” it 
*might* be within
10 db of high speed CMOS. Since there is a 20 db delta between the HC you 
mention
and the AC that leaves a bit of room. 

If you have a part with a bias generator in it, just forget about using it. You 
will have all 
sorts of strange spurs that come and go. They will be broadband. They will take 
the 
noise floor up into the 100 dbc / Hz range in some cases. 

If you are trying to use the internal PLL, it’s phase noise isn’t going to be 
great. Numbers
like -135 dbc / Hz at 100 KHz offset are not uncommon on an HF output. 

As straight dividers, they might get to -16x dbc/ Hz region. That compares to 
the -174 dbc / Hz
you could expect under similar conditions with something like AC or faster 
CMOS. You 
are more likely to get there on a fast CLPD than on an FPGA. Either way you can 
run
into bum parts. 

Bob

> On Jun 2, 2015, at 9:13 AM, David C. Partridge 
>  wrote:
> 
> Is this a sensible thing to consider doing?  Or would I be better sticking to 
> AC/HC/AHC/LVC logic?
> 
> Regards,
> David Partridge 
> 
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Gerhard Hoffmann]

Am 02.06.2015 um 21:27 schrieb Tom Van Baak:

Is this a sensible thing to consider doing?  Or would I be better sticking to 
AC/HC/AHC/LVC logic?

Regards,
David Partridge

Yes, please consider it. I would be very interested in the results.


I have made a stamp sized board that has a Xilinx 2C64 Coolrunner II, a 
1.8V regulator for the core
voltage and the programming interface for the standard Xilinx USB-cable. 
(parallel cable may work

but my laptop has no parallel port anymore.) It runs on 3.3V. All I/O pads
are fanned out to a 100 mil grid, so you can mount it easily on square 
pad board or solder it to an
unetched copper clad board. The layout is single sided plus unbroken GND 
on the bottom side.


pic = < 
https://picasaweb.google.com/lh/photo/4Bpcfouj8WH0shNGIyuVUtMTjNZETYmyPJy0liipFm0?feat=directlink 
>


(top right)

The CPLD has 64 Flipflops and enough combinational logic to feed them 
all. It runs happily
at > 200 MHZ. Two of these chips can make a 1pps from 200 MHz in, and 
another 1pps that
can be stepped in 5ns increments from -100nsec to > +1 second. A 2c64 
costs $2 or so at digikey.


BTW, the other stamps on the picture are:

top left:  Crystec CVH950 100 MHz VCXO locked to 10 MHz. I was too slow 
with those 100 MHz Wenzels this week;
  these would have justified a better effort; also sth. 
better than an 4046 ;-)


bottom left: NIST doubler from 100 MHz to 200 MHz using 2*BF862, slight 
gain, Low-Q tuned circuit

  on the output side

bottom right: 200 MHz to 400 MHz Schottky doubler, SAW filter, ERA-4 to 
bring it to 12 dBm again


The boards are home-etched; because of my daytime job my pps generator 
makes only slow progress...


A 1:1 pdf of the layout is available; one can print it to foil if one 
has a good printer (OKI 852 works
nicely) or a print shop that can do offset films will print it to 
document film for €5 to 10 per ISO A4 page+


If someone want to measure it, I can send him one of those Xilinx 
stamps; sooner or later I'll find

the time do it myself but even then the repeatability would be interesting.



Also, this morning I have published an update for my 220pV/sqrt Hz 
preamplifier; 10uF foil
capacitors one actually can buy, circuit diagrams and Gerbers for the 
adventurous. Be warned,
this version has never been fabricated, but the changes from its 
predecessor are relatively small. Most of
the work was the step to Altium Designer 15, Direct-X support on my 
virtual Win7 machine and that my

libraries from Protel-99 times desparately need some work.

The update can be found at  < 
http://www.hoffmann-hochfrequenz.de/downloads/downloads.html >.


regards, Gerhard

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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Hal Murray]

david.partri...@perdrix.co.uk said:
> Is this a sensible thing to consider doing?  Or would I be better sticking
> to AC/HC/AHC/LVC logic?

A CPLD is a fine way to divide by a large number.  Even the smaller FPGAs are 
probably overkill but they should work fine.

If you are interested in jitter, the main problem is due to shared 
power/ground lines.  With things like a CPLD, the usual way to get in trouble 
is to put several unrelated chunks of logic into the same chip.  If you only 
have a single divider in a chip, I'd expect the output to be clean.

You can get the same problem with AC/LVC scale logic with multiple sections 
if you use the sections for unrelated logic.  That's one of the reasons the 
modern single gate packages work so well.  You can't screwup and put two (or 
more) unrelated chunks of logic in the same chip.
 



-- 
These are my opinions.  I hate spam.



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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Bruce Griffiths]

On Tuesday, June 02, 2015 02:13:04 PM David C. Partridge wrote:
> Is this a sensible thing to consider doing?  Or would I be better sticking
> to AC/HC/AHC/LVC logic?
`
> 
> Regards,
> David Partridge
> 
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It makes it easier to implement low noise lambda dividers which overcome 
most of the PN degradation of digital dividers.
Also the FPGA can easily be reconfigured to produce outputs different from 
those originally implemented.

Bruce
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Attila Kinali]

On Tue, 2 Jun 2015 14:13:04 +0100
"David C. Partridge"  wrote:

> Is this a sensible thing to consider doing? 
> Or would I be better sticking to AC/HC/AHC/LVC logic?

It depends ;-)

For most things it should be ok. You can reach lower levels of noise
with single 74xxx parts as you will have lower interference between
different parts of the circuitry. But how much better it might be
and whether other effects might actually make the "discrete" solution
worse, i cannot say.

For some rule of thumb guide lines, the poster/paper by Caloso
which he presented at EFTF last year where they measured noise
parameters of 4 different FPGA families. The main result is that
"the larger the better" is also true for low noise logic gates,
but there are outliers.

"Phase noise jitter in digital electronics", by Calosso and Rubiola, 2014
http://rubiola.org/pdf-articles/conference/2014-eftf-Noise-in-digital-components.pdf

There is quite some data missing there, but I guess they hit the
page limit of the paper. Also testing different FPGA families would
be quite nice.

Attila Kinali

-- 
< _av500_> phd is easy
< _av500_> getting dsl is hard
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Bob Camp]

Hi

A lot depends on exactly which CPLD or which FPGA you are looking at and how 
they put the guts of it together. If you find one that is “just right” it 
*might* be within
10 db of high speed CMOS. Since there is a 20 db delta between the HC you 
mention
and the AC that leaves a bit of room. 

If you have a part with a bias generator in it, just forget about using it. You 
will have all 
sorts of strange spurs that come and go. They will be broadband. They will take 
the 
noise floor up into the 100 dbc / Hz range in some cases. 

If you are trying to use the internal PLL, it’s phase noise isn’t going to be 
great. Numbers
like -135 dbc / Hz at 100 KHz offset are not uncommon on an HF output. 

As straight dividers, they might get to -16x dbc/ Hz region. That compares to 
the -174 dbc / Hz
you could expect under similar conditions with something like AC or faster 
CMOS. You 
are more likely to get there on a fast CLPD than on an FPGA. Either way you can 
run
into bum parts. 

Bob

> On Jun 2, 2015, at 9:13 AM, David C. Partridge 
>  wrote:
> 
> Is this a sensible thing to consider doing?  Or would I be better sticking to 
> AC/HC/AHC/LVC logic?
> 
> Regards,
> David Partridge 
> 
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[jerry shirᴀr]

Programmable logic rocks. If you need a 13 bit counter, you can do that. It
is easy to create alarms and special controls.

Jerry
On Jun 2, 2015 2:22 PM, "David C. Partridge" 
wrote:

> Is this a sensible thing to consider doing?  Or would I be better sticking
> to AC/HC/AHC/LVC logic?
>
> Regards,
> David Partridge
>
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Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider

[Tom Van Baak]

> Is this a sensible thing to consider doing?  Or would I be better sticking to 
> AC/HC/AHC/LVC logic?
> 
> Regards,
> David Partridge 

Yes, please consider it. I would be very interested in the results.

We measured under 2 ps jitter for the PIC dividers [1] used with the cute 
little TADD-2 board [2]. One of these days I should measure your divider board 
with the same setup to see how it compares with a PIC. Like a CPLD/FPGA the PIC 
has the advantage of being fully synchronous and all on one die.

/tvb

[1] http://leapsecond.com/pic/
[2] https://www.tapr.org/kits_t2-mini.html

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[time-nuts] Using CPLD/FPGA or similar for frequency divider

[David C. Partridge]

Is this a sensible thing to consider doing?  Or would I be better sticking to 
AC/HC/AHC/LVC logic?

Regards,
David Partridge 

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