subject:"\[time\-nuts\] low power divide by 5"

Hi

> On Jul 2, 2020, at 6:38 PM, jimlux  wrote:
> 
> On 7/2/20 2:50 PM, Bob kb8tq wrote:
>> Hi
>>> On Jul 2, 2020, at 5:30 PM, jimlux  wrote:
>>> 
>>> On 7/2/20 11:37 AM, ed breya wrote:
 It's been fun reminiscing about all these dividers and techniques, but 
 getting back to the OP, the original search was for a divide by 5 with 
 "low power" and operation from 5 to possibly 3.3V, and clocking properly 
 at 50 MHz. One would assume also minimal size and complexity, and low cost.
>>> 
>>> You forgot to add rad-hard.. I was the OP - This has been a fascinating 
>>> thing - we have a breadboard that uses a fancy clock distribution chip that 
>>> consumes close to a watt (and has too much jitter, as well)..
>> 
>>> 3) It's hard to even find programmable logic that is simple and small. All 
>>> the mfrs tout their latest tiny parts with *only half a million gates* (I 
>>> exaggerate, but you get the picture)
>> If they want to sell you a fully self contained "million gate" device for a 
>> couple bucks, is that really
>> a bad thing?  Sure, if it’s in a thousand pin BGA, it’s a bad thing. If it’s 
>> in a < 40 pin package that
>> you can get on a small board …. maybe not so much.
> 
> yes, if it's in a small pinout package. One other peculiarity that I've been 
> burned by is that a lot of the modern devices with large logic and few I/O 
> pins have power dissipations that are clock rate independent for the internal 
> logic - it's the leakage current that dominates and that's VERY dependent on 
> die temp.
> 
> 
> I think though, that the marketplace is driving towards increased 
> functionality on one chip, with bigger die size. Those of us who want 50 
> gates at medium or low speed are distinctly in the minority.

There are very few applications that require that sort of device. Volume
matters ( a lot !!)

Bob


> 
> 
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Re: [time-nuts] low power divide by 5


On 7/2/20 2:50 PM, Bob kb8tq wrote:

Hi


On Jul 2, 2020, at 5:30 PM, jimlux  wrote:

On 7/2/20 11:37 AM, ed breya wrote:

It's been fun reminiscing about all these dividers and techniques, but getting back to 
the OP, the original search was for a divide by 5 with "low power" and 
operation from 5 to possibly 3.3V, and clocking properly at 50 MHz. One would assume also 
minimal size and complexity, and low cost.


You forgot to add rad-hard.. I was the OP - This has been a fascinating thing - 
we have a breadboard that uses a fancy clock distribution chip that consumes 
close to a watt (and has too much jitter, as well)..



3) It's hard to even find programmable logic that is simple and small. All the 
mfrs tout their latest tiny parts with *only half a million gates* (I 
exaggerate, but you get the picture)


If they want to sell you a fully self contained "million gate" device for a 
couple bucks, is that really
a bad thing?  Sure, if it’s in a thousand pin BGA, it’s a bad thing. If it’s in a 
< 40 pin package that
you can get on a small board …. maybe not so much.


yes, if it's in a small pinout package. One other peculiarity that I've 
been burned by is that a lot of the modern devices with large logic and 
few I/O pins have power dissipations that are clock rate independent 
for the internal logic - it's the leakage current that dominates and 
that's VERY dependent on die temp.



I think though, that the marketplace is driving towards increased 
functionality on one chip, with bigger die size. Those of us who want 50 
gates at medium or low speed are distinctly in the minority.



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Re: [time-nuts] low power divide by 5


On 7/2/20 2:13 PM, Peter McCollum wrote:

Another way to achieve divide-by-N is with a non-retriggerable one-shot,
adjusted to the appropriate time value.
Back in the 40's/50's, the common tube circuit was called a Phantastron
(really, look it up!).
Phantastron dividers were used in several of the early HP counters (i.e.
HP524B), because you could achieve (for example) a decade divider with a
single tube, whereas a 'binary' solution requires 4 tubes (like in the HP
AC-4A decades).

If a 50% duty cycle is needed, then do a divide by N/2 with a Phantastron,
then a single flip-flop gives you 'N' with a 50% duty.

Note that the Phantastron type divider only works if the input freq is
known and fixed, because the one-shot delay has to be adjusted to a
specific value.

Pete



And you can be clever if you can trigger on both rising and falling 
edges, so you get basically a x2 and a divide by 5 in the same circuit, 
followed by the divide by 2 to make the duty cycle 50/50.



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Re: [time-nuts] low power divide by 5

Hi

> On Jul 2, 2020, at 5:30 PM, jimlux  wrote:
> 
> On 7/2/20 11:37 AM, ed breya wrote:
>> It's been fun reminiscing about all these dividers and techniques, but 
>> getting back to the OP, the original search was for a divide by 5 with "low 
>> power" and operation from 5 to possibly 3.3V, and clocking properly at 50 
>> MHz. One would assume also minimal size and complexity, and low cost.
> 
> You forgot to add rad-hard.. I was the OP - This has been a fascinating thing 
> - we have a breadboard that uses a fancy clock distribution chip that 
> consumes close to a watt (and has too much jitter, as well)..
> 
> 
> 
> I was thinking on the long commute to (tele)work from downstairs to upstairs 
> (or maybe on the commute home going the other way).. You know, we don't need 
> all that functionality in the clock chip, there must be a way to do a divide 
> by 5, and that has good noise properties - 2 and 4 are trivially easy (I 
> thought), there's probably some easy way to hook up 3 (or 4) flipflops and 
> get a nice divide by 5, and maybe even 50/50 duty cycle out.
> 
> So I posted the question - because I've seen discussion of good divider 
> designs here, and I was sure that someone would come with a novel suggestion.
> 
> What I have learned is that
> 
> 1) All those clever handbook designs and data sheets that I grew up with in 
> the 70s,80s, and 90s are just the ticket, but you can't actually get the SSI 
> MSI parts any more.
> 
> 2) One can brute force design simple functions by just trying all possible 
> connections and see if it works. What a clever idea!  All that work with 
> Karnaugh maps, etc. trying to come up with minimalist designs, and you can 
> let your idiot savant assistant (the computer) just grind through all 
> possible designs.   Of course, now that you have that clever efficient 
> design, because of #1, you can't build it.
> 
> 3) It's hard to even find programmable logic that is simple and small. All 
> the mfrs tout their latest tiny parts with *only half a million gates* (I 
> exaggerate, but you get the picture)

If they want to sell you a fully self contained "million gate" device for a 
couple bucks, is that really
a bad thing?  Sure, if it’s in a thousand pin BGA, it’s a bad thing. If it’s in 
a < 40 pin package that 
you can get on a small board …. maybe not so much.

Bob


> 
> 4) What I'd be happy to do for a room temperature breadboard probably won't 
> work over temperature - and an "existence proof" that it can be done at room 
> temp doesn't mean you can find parts to build it to work over temp (See #1, 
> again)
> 
> 
> 
> 
>> One piece of info that is missing, is how many of these are needed. If it's 
>> a one-off situation, that's way different from mass production and assured 
>> parts availability. If only one or a few are needed, then I'd contend that 
>> the 74AC390 is the way to go. It definitely will work at the lower end of 
>> the supply range, and is the simplest in parts count - one piece, and no 
>> doubts about external prop delays that would be associated with getting 
>> other types to divide by 5.
> 
> 
> 
>> If there are truly lots of NOS ones out there, it should possible to just 
>> buy a bunch for all anticipated needs. I can't imagine they would be very 
>> expensive, except for the issues of volume versus transaction cost. I've 
>> never tried to buy old parts from these kinds of distributors, but I would 
>> imagine there would be minimum order requirements or fixed cost. So, getting 
>> one piece might cost $100, while getting a hundred pieces may be $110, and 
>> so on. There's no harm in asking and negotiating.
> 
> We *are* building the eventual system to fly, and yeah, we've got tubes and 
> tubes of old ICs at work (JPL) or, as Rick mentioned, there's always 
> Rochester Electronics, who have a warehouse full of old wafers and dice. But 
> I'd rather not.
> 
> For those who come after me, and are perusing the archives (thank you google) 
> - here's some reasons why old parts are a pain (and a curse).
> 
> 1) Reliability people freak out about packages that have not been kept in 
> absolutely pristine conditions with a full paperwork trail of certifications. 
> The humidity might have gone up. Oxygen or Helium might have leaked in. There 
> might have been latent ESD damage.  So you'd have a tube of parts with date 
> codes from the 80s or 90s that *work* (over temp, etc.), but the mission 
> assurance folks will want a bunch of them to do destructive analysis. Making 
> sure there's no latent degradation, etc.  That can cost a lot.
> 
> 2) You CAN get parts from Rochester, and they're freshly packaged, from known 
> good dice, etc. That's not cheap either.  But, is probably cheaper than #1.
> 
> 3) the biggest reason - There are innumerable cases where someone used "end 
> of life" or "flight spare" parts, just this once.  And then, the next mission 
> comes along and wants to do a "build to print" to claim heritage - and you 
>

Re: [time-nuts] low power divide by 5


On 7/2/20 11:37 AM, ed breya wrote:
It's been fun reminiscing about all these dividers and techniques, but 
getting back to the OP, the original search was for a divide by 5 with 
"low power" and operation from 5 to possibly 3.3V, and clocking properly 
at 50 MHz. One would assume also minimal size and complexity, and low cost.


You forgot to add rad-hard.. I was the OP - This has been a fascinating 
thing - we have a breadboard that uses a fancy clock distribution chip 
that consumes close to a watt (and has too much jitter, as well)..




I was thinking on the long commute to (tele)work from downstairs to 
upstairs (or maybe on the commute home going the other way).. You know, 
we don't need all that functionality in the clock chip, there must be a 
way to do a divide by 5, and that has good noise properties - 2 and 4 
are trivially easy (I thought), there's probably some easy way to hook 
up 3 (or 4) flipflops and get a nice divide by 5, and maybe even 50/50 
duty cycle out.


So I posted the question - because I've seen discussion of good divider 
designs here, and I was sure that someone would come with a novel 
suggestion.


What I have learned is that

1) All those clever handbook designs and data sheets that I grew up with 
in the 70s,80s, and 90s are just the ticket, but you can't actually get 
the SSI MSI parts any more.


2) One can brute force design simple functions by just trying all 
possible connections and see if it works. What a clever idea!  All that 
work with Karnaugh maps, etc. trying to come up with minimalist designs, 
and you can let your idiot savant assistant (the computer) just grind 
through all possible designs.   Of course, now that you have that clever 
efficient design, because of #1, you can't build it.


3) It's hard to even find programmable logic that is simple and small. 
All the mfrs tout their latest tiny parts with *only half a million 
gates* (I exaggerate, but you get the picture)


4) What I'd be happy to do for a room temperature breadboard probably 
won't work over temperature - and an "existence proof" that it can be 
done at room temp doesn't mean you can find parts to build it to work 
over temp (See #1, again)







One piece of info that is missing, is how many of these are needed. If 
it's a one-off situation, that's way different from mass production and 
assured parts availability. If only one or a few are needed, then I'd 
contend that the 74AC390 is the way to go. It definitely will work at 
the lower end of the supply range, and is the simplest in parts count - 
one piece, and no doubts about external prop delays that would be 
associated with getting other types to divide by 5.






If there are truly lots of NOS ones out there, it should possible to 
just buy a bunch for all anticipated needs. I can't imagine they would 
be very expensive, except for the issues of volume versus transaction 
cost. I've never tried to buy old parts from these kinds of 
distributors, but I would imagine there would be minimum order 
requirements or fixed cost. So, getting one piece might cost $100, while 
getting a hundred pieces may be $110, and so on. There's no harm in 
asking and negotiating.


We *are* building the eventual system to fly, and yeah, we've got tubes 
and tubes of old ICs at work (JPL) or, as Rick mentioned, there's always 
Rochester Electronics, who have a warehouse full of old wafers and dice. 
But I'd rather not.


For those who come after me, and are perusing the archives (thank you 
google) - here's some reasons why old parts are a pain (and a curse).


1) Reliability people freak out about packages that have not been kept 
in absolutely pristine conditions with a full paperwork trail of 
certifications. The humidity might have gone up. Oxygen or Helium might 
have leaked in. There might have been latent ESD damage.  So you'd have 
a tube of parts with date codes from the 80s or 90s that *work* (over 
temp, etc.), but the mission assurance folks will want a bunch of them 
to do destructive analysis. Making sure there's no latent degradation, 
etc.  That can cost a lot.


2) You CAN get parts from Rochester, and they're freshly packaged, from 
known good dice, etc. That's not cheap either.  But, is probably cheaper 
than #1.


3) the biggest reason - There are innumerable cases where someone used 
"end of life" or "flight spare" parts, just this once.  And then, the 
next mission comes along and wants to do a "build to print" to claim 
heritage - and you spend a lot of time trying to track down NOS parts, 
or in design reviews trying to say "well even though all the parts are 
different, except the resistors, it really isn't a new design".


We used the Xilinx Virtex II in several of our radios that have flown to 
Mars (in the Electra UHF radio on all the rovers since 2003, for 
instance).   I think we have the largest stock of flight qualified 
Virtex IIs in the world, because people still want to use Electra 
radios, as a "build to

Re: [time-nuts] low power divide by 5

2020-07-02 Thread Peter McCollum

Another way to achieve divide-by-N is with a non-retriggerable one-shot,
adjusted to the appropriate time value.
Back in the 40's/50's, the common tube circuit was called a Phantastron
(really, look it up!).
Phantastron dividers were used in several of the early HP counters (i.e.
HP524B), because you could achieve (for example) a decade divider with a
single tube, whereas a 'binary' solution requires 4 tubes (like in the HP
AC-4A decades).

If a 50% duty cycle is needed, then do a divide by N/2 with a Phantastron,
then a single flip-flop gives you 'N' with a 50% duty.

Note that the Phantastron type divider only works if the input freq is
known and fixed, because the one-shot delay has to be adjusted to a
specific value.

Pete

On Thu, Jul 2, 2020 at 2:29 PM Gary Woods  wrote:

> On Thu, 2 Jul 2020 19:23:03 +0200, you wrote:
>
> >Makes me think one could use the input signal edge to synchronize a
> 2N6027 based programmable unijunction oscillator, thus effecting a divide
> by 5. Unlikely the 6027 would be fast enough for 50 MHz, but maybe a 2
> transistor equivalent using RF transistors? Output would be nowhere near
> the 40%-60% range, though. Might just have to build one for fun.
>
> And _that_ makes me think of an early Navy airborne Loran set that
> used step counters to make the time base.  Adjustments were through
> holes in the side of the case, because some poor soul would have to
> tweak them now and again.
> --
> Gary Woods O- K2AHC   Public keys at home.earthlink.net/~garygarlic, or
> get 0x1D64A93D via keyserver
> fingerprint =  E2 6F 50 93 7B C7 F3 CA  1F 8B 3C C0 B0 28 68
>
> --
> This email has been checked for viruses by Avast antivirus software.
> https://www.avast.com/antivirus
>
>
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Re: [time-nuts] low power divide by 5

Hi

> On Jul 2, 2020, at 2:34 PM, Hal Murray  wrote:
> 
> 
>> Funny, just yesterday I was looking at the design of a laboratory cesium
>> beam standard from 1963. Sorry, there's no divide-by-5 example in there.  But
>> the attached images show the 108x multiplier (8.5 MHz to 9180 MHz).  Sure
>> enough, spot the 12AX7 and 6J6 tubes in use... 
> 
> Neat.  Thanks.
> 
> Interesting.  I'd expect transistors to be in use by 1963.

Some at low frequency, not a lot for high speed in production gear. A bit 
faster in 
terms of one of a kind lab devices. 

> 
> When did tubes die out?

They have yet to die out ….. :)

> 
> How fast were transistors back then?

The typical germanium transistor of the day was lucky to have an Ft rated in 
MHz 
(yes a slight exaggeration)

>  How fast could you toggle a 12AX7?

Depends on how fancy you wanted to get …. 10 MHz to 100 MHz.

Bob

> 
> Wikipedia says the first 7090 was installed Dec 1959.  The core memory cycled 
> at 2 microseconds.
> 
> Was 9180 MHz fast enough that it required a tube so it was simpler to use 
> tubes on the rest of the logic?
> 
> -- 
> These are my opinions.  I hate spam.
> 
> 
> 
> 
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Re: [time-nuts] low power divide by 5

2020-07-02 Thread Hal Murray



> Funny, just yesterday I was looking at the design of a laboratory cesium
> beam standard from 1963. Sorry, there's no divide-by-5 example in there.  But
> the attached images show the 108x multiplier (8.5 MHz to 9180 MHz).  Sure
> enough, spot the 12AX7 and 6J6 tubes in use... 

Neat.  Thanks.

Interesting.  I'd expect transistors to be in use by 1963.

When did tubes die out?

How fast were transistors back then?  How fast could you toggle a 12AX7?

Wikipedia says the first 7090 was installed Dec 1959.  The core memory cycled 
at 2 microseconds.

Was 9180 MHz fast enough that it required a tube so it was simpler to use 
tubes on the rest of the logic?

-- 
These are my opinions.  I hate spam.




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Re: [time-nuts] low power divide by 5

2020-07-02 Thread Gary Woods

On Thu, 2 Jul 2020 19:23:03 +0200, you wrote:

>Makes me think one could use the input signal edge to synchronize a 2N6027 
>based programmable unijunction oscillator, thus effecting a divide by 5. 
>Unlikely the 6027 would be fast enough for 50 MHz, but maybe a 2 transistor 
>equivalent using RF transistors? Output would be nowhere near the 40%-60% 
>range, though. Might just have to build one for fun.

And _that_ makes me think of an early Navy airborne Loran set that
used step counters to make the time base.  Adjustments were through
holes in the side of the case, because some poor soul would have to
tweak them now and again.
-- 
Gary Woods O- K2AHC   Public keys at home.earthlink.net/~garygarlic, or get 
0x1D64A93D via keyserver
fingerprint =  E2 6F 50 93 7B C7 F3 CA  1F 8B 3C C0 B0 28 68 

-- 
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus


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Re: [time-nuts] low power divide by 5


On 7/2/20 6:48 AM, Tom Van Baak wrote:

 > I'm surprised nobody has suggested using the 12AX7 or 6J6 dual triodes.

Jim,

Funny, just yesterday I was looking at the design of a laboratory cesium 
beam standard from 1963. Sorry, there's no divide-by-5 example in there. 
But the attached images show the 108x multiplier (8.5 MHz to 9180 MHz). 
Sure enough, spot the 12AX7 and 6J6 tubes in use...


/tvb




Yeah, but I think those are multipliers, not dividers.


So then, what shall we call it. PICDIV draws from the PIC.  Next thing 
from TAPR,  catering to the retropunk style, will be a TUBEDIV or EJDIV 
(Eccles-Jordan homage) - what better to drive your nixie (or stacked 
neon bulb) display than a 19" rack full of modules.


I'm sure if one looks at pictures from WW 2 era, there's plenty of this 
around.


If I didn't have many other projects going, that might be a cool one. 
Lots of folks have binary clocks on their desks at work, but they're LED 
and solid state.  A few have Nixie clocks, but solid state driven.


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Re: [time-nuts] low power divide by 5

2020-07-02 Thread ed breya

It's been fun reminiscing about all these dividers and techniques, but 
getting back to the OP, the original search was for a divide by 5 with 
"low power" and operation from 5 to possibly 3.3V, and clocking properly 
at 50 MHz. One would assume also minimal size and complexity, and low cost.


One piece of info that is missing, is how many of these are needed. If 
it's a one-off situation, that's way different from mass production and 
assured parts availability. If only one or a few are needed, then I'd 
contend that the 74AC390 is the way to go. It definitely will work at 
the lower end of the supply range, and is the simplest in parts count - 
one piece, and no doubts about external prop delays that would be 
associated with getting other types to divide by 5.


If there are truly lots of NOS ones out there, it should possible to 
just buy a bunch for all anticipated needs. I can't imagine they would 
be very expensive, except for the issues of volume versus transaction 
cost. I've never tried to buy old parts from these kinds of 
distributors, but I would imagine there would be minimum order 
requirements or fixed cost. So, getting one piece might cost $100, while 
getting a hundred pieces may be $110, and so on. There's no harm in 
asking and negotiating.


Ed


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Re: [time-nuts] low power divide by 5

2020-07-02 Thread Robert LaJeunesse

Makes me think one could use the input signal edge to synchronize a 2N6027 
based programmable unijunction oscillator, thus effecting a divide by 5. 
Unlikely the 6027 would be fast enough for 50 MHz, but maybe a 2 transistor 
equivalent using RF transistors? Output would be nowhere near the 40%-60% 
range, though. Might just have to build one for fun.

> Sent: Thursday, July 02, 2020 at 8:37 AM
> From: "jimlux" 
> To: time-nuts@lists.febo.com
> Subject: Re: [time-nuts] low power divide by 5
...
> I'm surprised nobody has suggested using the 12AX7 or 6J6 dual triodes.


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Re: [time-nuts] low power divide by 5

2020-07-02 Thread Richard (Rick) Karlquist


The sum of propagation delay (~15 ns) and setup time (~5 ns)
in the 74AC161 gives just enough time to operate at 50 MHz,
based on the data sheet.  Of course, at room temp, the chip
will beat the data sheet by an undetermined margin.

The fact that the clock frequency is specified at 103 MHz
applies only to a free running configuration (divide by
2, 4, 8, or 16 only) and is irrelevant to dividing by 5.
If only there were a 74HC160 version.  Actually, you
can get them from Rochester Electronics ... but you have
to buy $250 worth minimum.

As noted, my favorite trick of connecting pin 11 to pin 9
is no help in this logic family because they finally did
the carry out correctly.

Rick N6RK

On 7/2/2020 7:03 AM, ew via time-nuts wrote:

161 and 163 are candidates. Back in the early 70's my favorite for my counter 
work  was the 74S112 dual JK. So I went to DigiKey to check on CD74AC112 they 
have in stock so with two of those along with an AND gate you can make as many 
divide as 5 as you need.  Just like the S112 it clocks over 100 MHz!
Bert Kehren
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Re: [time-nuts] low power divide by 5

2020-07-02 Thread John Ackermann

That's a very early use of "MHz" rather than "Mc"!

On Jul 2, 2020, 9:50 AM, at 9:50 AM, Tom Van Baak  wrote:
>> I'm surprised nobody has suggested using the 12AX7 or 6J6 dual
>triodes.
>
>Jim,
>
>Funny, just yesterday I was looking at the design of a laboratory
>cesium 
>beam standard from 1963. Sorry, there's no divide-by-5 example in
>there. 
>But the attached images show the 108x multiplier (8.5 MHz to 9180 MHz).
>
>Sure enough, spot the 12AX7 and 6J6 tubes in use...
>
>/tvb
>
>
>
>
>
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Re: [time-nuts] low power divide by 5

Hi

For vacuum tube divide by 5 / 10 circuits, take a look at the schematics of the 
Beckman EPUT meters…..

Bob

> On Jul 2, 2020, at 9:48 AM, Tom Van Baak  wrote:
> 
> > I'm surprised nobody has suggested using the 12AX7 or 6J6 dual triodes.
> 
> Jim,
> 
> Funny, just yesterday I was looking at the design of a laboratory cesium beam 
> standard from 1963. Sorry, there's no divide-by-5 example in there. But the 
> attached images show the 108x multiplier (8.5 MHz to 9180 MHz). Sure enough, 
> spot the 12AX7 and 6J6 tubes in use...
> 
> /tvb
> 
> <1963-cesium-1.jpg><1963-cesium-2.jpg><1963-cesium-3.jpg>___
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Re: [time-nuts] low power divide by 5

2020-07-02 Thread ew via time-nuts

161 and 163 are candidates. Back in the early 70's my favorite for my counter 
work  was the 74S112 dual JK. So I went to DigiKey to check on CD74AC112 they 
have in stock so with two of those along with an AND gate you can make as many 
divide as 5 as you need.  Just like the S112 it clocks over 100 MHz!
Bert Kehren
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Re: [time-nuts] low power divide by 5


On 7/1/20 11:21 PM, Gerhard Hoffmann wrote:


Am 02.07.20 um 00:35 schrieb jimlux:

On 7/1/20 1:41 PM, ed breya wrote:

Yeah, I know. I was just lamenting the lack of nice medium-density 
count functions in 74AC. It's hard to beat the simplicity of a '390 
when you 


16 bore holes just to deploy 4 flip flops is not what I'd call 
simplicity. And Fairchild
recognized that as well. The 390 did not make it into the 1987 Fairchild 
Advanced CMOS

(FACT) data book.
They expected other chips to sell better, like the 74ACT488 GPIB / HPIB 
/ IEEE488 bus
interface. Ever used one? The market for Nixie clocks with one counter + 
one decoder

per digit must have been smaller, even back then.



Anyway, I've always liked having a wide assortment of MSI logic 
devices available in all families, that you just hook up and it goes 
- no setup, no programming. I've saved lots of counter types for 
possible use. One obscure one is the MC14566, with divide 6 counters 
for clock time readout and generation, in the old days.


That's sort of the design goal for the 22V10 and earlier PAL devices - 
keep them in familiar DIP packages, power on the corners like the IC 
gods intended, and you can program it to replicate a whole variety of 
MSI functionality, often with the same pinout.



Corner pinning for Vcc and GND is not what any gods intended. In FACT, 
(pun intended)
it's evil. Remember ground bounce? The corners are the worst locations 
on a DIL chip
you can find for that job. And fig leaf capacitors across the chip are 
just that.


Certainly, but when wire wrapping that big panel, and using a different 
color of wire for the V+ and V-, it sure makes it easier. 




At 100 MHz, they simply are not there. The optical illusion helps only 
to hide that.
The 3  ACT chips on the experiment board posted yesterday reminded me of 
the

last pages of this:

< 
http://www.hoffmann-hochfrequenz.de/downloads/experiments_with_decoupling_capacitors.pdf 
 >


The golden times of logic design are now, not then!


I'm surprised nobody has suggested using the 12AX7 or 6J6 dual triodes.

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Re: [time-nuts] low power divide by 5

2020-07-02 Thread Detlef Schuecker via time-nuts

Hi,

yes, it is self-clearing. It cycles 0 4 6 7 1 (leftmost FF MSB), 2 clears 
to 7, 3->1, 5->2. On one output you get 3/5 duty cycle, on the other two 
you get 2/5. 

Detlef Schücker




Von:"Robert LaJeunesse" 
An: time-nuts@lists.febo.com
Datum:  01.07.2020 09:30
Betreff:    Re: [time-nuts] low power divide by 5
Gesendet von:   "time-nuts" 



Take a look at the "modified" shift-register like counter in the attached 
jpg file. When simulated online it behaved as expected for a divide by 5. 
I believe it also is self-clearing from illegal states, but the other 
simulator I tested that in wasn't good for documenting the design.

Bob L.

> Sent: Tuesday, June 30, 2020 at 6:47 PM
> From: "dschuecker" 
> To: time-nuts@lists.febo.com
> Subject: Re: [time-nuts] low power divide by 5
>
> Hi,
> 
> a divide by five should possible with a synchronous state-machine made 
> of 3 ( sufficiently fast-) JK-FlipFlops.
> 
> All 3 FFs are clocked with the input freq. , the outputs of the FFs are 
> fed back to the the JK-inputs,  the divided freq. is output of one of 
> the FFs.
> 
> Additional constraints: no external ANDs or ORs or NOTs, the 
> state-machine does not get stuck in the 3 unused states.
> 
> This turned out to be a very interesting problem and I do not yet come 
> up with a solution. Maybe there is none. Analytical solutions all 
> failed, I will try a brute force enumeration attack tomorrow.
> 
> lots of fun !
> 
> Cheers
> 
> Detlef
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Re: [time-nuts] low power divide by 5

2020-07-02 Thread Gerhard Hoffmann



Am 02.07.20 um 00:35 schrieb jimlux:

On 7/1/20 1:41 PM, ed breya wrote:

Yeah, I know. I was just lamenting the lack of nice medium-density 
count functions in 74AC. It's hard to beat the simplicity of a '390 
when you 


16 bore holes just to deploy 4 flip flops is not what I'd call 
simplicity. And Fairchild
recognized that as well. The 390 did not make it into the 1987 Fairchild 
Advanced CMOS

(FACT) data book.
They expected other chips to sell better, like the 74ACT488 GPIB / HPIB 
/ IEEE488 bus
interface. Ever used one? The market for Nixie clocks with one counter + 
one decoder

per digit must have been smaller, even back then.



Anyway, I've always liked having a wide assortment of MSI logic 
devices available in all families, that you just hook up and it goes 
- no setup, no programming. I've saved lots of counter types for 
possible use. One obscure one is the MC14566, with divide 6 counters 
for clock time readout and generation, in the old days.


That's sort of the design goal for the 22V10 and earlier PAL devices - 
keep them in familiar DIP packages, power on the corners like the IC 
gods intended, and you can program it to replicate a whole variety of 
MSI functionality, often with the same pinout.



Corner pinning for Vcc and GND is not what any gods intended. In FACT, 
(pun intended)
it's evil. Remember ground bounce? The corners are the worst locations 
on a DIL chip
you can find for that job. And fig leaf capacitors across the chip are 
just that.
At 100 MHz, they simply are not there. The optical illusion helps only 
to hide that.
The 3  ACT chips on the experiment board posted yesterday reminded me of 
the

last pages of this:

< 
http://www.hoffmann-hochfrequenz.de/downloads/experiments_with_decoupling_capacitors.pdf 
>


The golden times of logic design are now, not then!

Gerhard

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Re: [time-nuts] low power divide by 5

2020-07-01 Thread jimlux


On 7/1/20 1:41 PM, ed breya wrote:

Yeah, I know. I was just lamenting the lack of nice medium-density count 
functions in 74AC. It's hard to beat the simplicity of a '390 when you 




Anyway, I've always liked having a wide assortment of MSI logic devices 
available in all families, that you just hook up and it goes - no setup, 
no programming. I've saved lots of counter types for possible use. One 
obscure one is the MC14566, with divide 6 counters for clock time 
readout and generation, in the old days.


That's sort of the design goal for the 22V10 and earlier PAL devices - 
keep them in familiar DIP packages, power on the corners like the IC 
gods intended, and you can program it to replicate a whole variety of 
MSI functionality, often with the same pinout.


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Re: [time-nuts] low power divide by 5

2020-07-01 Thread Richard (Rick) Karlquist


I designed a marine radio in 1976 that used 74LS161's.
They could do something like 15 MHz on a good day
at room temperature.  I did a lot of characterization
on them.  100 MHz?  In your dreams...

BTW, if you want to divide by ten in the LS family,
the 74LS160 is a better choice, because it will
divide by 10 without any logic feedback.  It still
won't do 100 MHz.

73
Rick N6RK

On 7/1/2020 1:37 PM, Perry Sandeen via time-nuts wrote:

Learned List

When I was looking for a 100 MHz divide by 10 in a dip package I was advised by 
someone on the list to use the 74LS161.
  It's available on Ebay on ebay from several sources for reasonable prices.
Regards,
Perrier
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Re: [time-nuts] low power divide by 5

2020-07-01 Thread Alex Pummer

There was once upon the time a very good data/application-book from 
Fairchild for TTL logic, they published many different modulo frequency 
dividers with 50% duty-cycle for the "9316" which is the functional 
equivalent grandfather  for 74161 and therefore for the AC161 to.
For frequency division, if the output is used  for analog application it 
is preferable to have 50% duty-cycle.

Alex
KJ6UHN

On 7/1/2020 2:03 PM, Peter McCollum wrote:

When I was looking for a 100 MHz divide by 10 in a dip package I was

advised by someone on the list to use the 74LS161.
  It's available on Ebay on ebay from several sources for reasonable
prices.

74LS161 won't go that fast - 20-25 MHz is max.

Pete


On Wed, Jul 1, 2020 at 2:46 PM Perry Sandeen via time-nuts <
time-nuts@lists.febo.com> wrote:


Learned List

When I was looking for a 100 MHz divide by 10 in a dip package I was
advised by someone on the list to use the 74LS161.
  It's available on Ebay on ebay from several sources for reasonable prices.
Regards,
Perrier
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Re: [time-nuts] low power divide by 5

2020-07-01 Thread Peter McCollum

>When I was looking for a 100 MHz divide by 10 in a dip package I was
advised by someone on the list to use the 74LS161.
 It's available on Ebay on ebay from several sources for reasonable
prices.

74LS161 won't go that fast - 20-25 MHz is max.

Pete


On Wed, Jul 1, 2020 at 2:46 PM Perry Sandeen via time-nuts <
time-nuts@lists.febo.com> wrote:

> Learned List
>
> When I was looking for a 100 MHz divide by 10 in a dip package I was
> advised by someone on the list to use the 74LS161.
>  It's available on Ebay on ebay from several sources for reasonable prices.
> Regards,
> Perrier
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Re: [time-nuts] low power divide by 5

2020-07-01 Thread ed breya

Tom wrote:
"Ed, For division, there's less need for a dedicated divide-by-10
counter since the '161 and '163 are *presettable* synchronous binary
counters. As such you can wire them to divide by anything from 2 to 16,
which includes 10. In addition they are *cascadable*, which means that
you can create synchronous 8- or 12- or 16- or 20-bit or even larger
dividers. The datasheets for these counters sometimes show examples of
multi-chip dividers. Attached is a photo of a 'LS00 plus 3 'LS161
counters configured as divide-by-1173 counter. The 2nd photo is a
divide-by-3295 count. You can see it's just a matter of changing the
jumpers on the preset pins.

/On 6/29/2020 3:32 PM, ed breya wrote:Looks like the AC161 and AC163 are
readily available, so they may be />/rigged for divide 5. It seems that of the counters surviving into AC, />/only binary ones are included, and the oddballs like decade are />/considered unnecessary - apparently nobody divides by 10 anymore, />/except inside of a processor."/

Yeah, I know. I was just lamenting the lack of nice medium-density count
functions in 74AC. It's hard to beat the simplicity of a '390 when you
want divide 5s and 10s, having two complete bi-quinary counters in one
package, ready to go. I've used HC390s and 393s often for up to 20 MHz,
and always assumed I could get the AC versions if needed, although I
usually go with ECL above that anyway, so this issue never came up for me.

I haven't looked at my 74AC parts inventory in a while, but I think I
may have a couple '390s or '393s - I guess I'll have to hang on to them
for "special" occasions. One thing I found interesting in my recent
searching for AC parts, is that the AC4040 is available. That's my
favorite counter for dividing by big numbers, good for any integer to
4095, in one package, plus some simple external diode or glue logic
feedback.

Anyway, I've always liked having a wide assortment of MSI logic devices
available in all families, that you just hook up and it goes - no setup,
no programming. I've saved lots of counter types for possible use. One
obscure one is the MC14566, with divide 6 counters for clock time
readout and generation, in the old days.

Ed
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[time-nuts] low power divide by 5

2020-07-01 Thread Perry Sandeen via time-nuts

Learned List

When I was looking for a 100 MHz divide by 10 in a dip package I was advised by 
someone on the list to use the 74LS161. 
 It's available on Ebay on ebay from several sources for reasonable prices.
Regards,
Perrier
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Re: [time-nuts] low power divide by 5

2020-07-01 Thread jimlux


On 7/1/20 5:24 AM, Detlef Schuecker via time-nuts wrote:

Hi,

there are three JK-FF, with Q1 as MSB, Q3 as LSB. J1,K1 ist input to Q1,
etc. .
There are 8^6 possibilties (6 inputs to the Qx or QxNOT or to HIGH or to
LOW) of which
2069 generate a cycle length of 5.

The following wiring will generate the cycle 1 3 5 2 4 :

J1=Q2
K1=Q1
J2=Q3
K2=Q2
J3=Q2NOT
K3=Q1

Q3 is output with a 3/5 duty cycle.
The unused state 0 will migrate to 1,6->0,7->0.
So the machine does not get stuck.

Cheers
Detlef





And one can still buy 74AC109 dual JK which supposedly toggle at >100MHz.



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Re: [time-nuts] low power divide by 5

2020-07-01 Thread Dan Kemppainen


Just a thought:

https://www.analog.com/media/en/technical-documentation/data-sheets/hmc438.pdf

Although it isn't really 'low power', and the input and output ranges 
are somewhat limited. Certainly not logic level.


Dan




On 7/1/2020 2:50 AM, time-nuts-requ...@lists.febo.com wrote:

Message: 4
Date: Wed, 1 Jul 2020 00:47:32 +0200
From: dschuecker
To:time-nuts@lists.febo.com
Subject: Re: [time-nuts] low power divide by 5
Message-ID:
Content-Type: text/plain; charset=utf-8; format=flowed

Hi,

a divide by five should possible with a synchronous state-machine made
of 3 ( sufficiently fast-) JK-FlipFlops.

All 3 FFs are clocked with the input freq. , the outputs of the FFs are
fed back to the the JK-inputs,? the divided freq. is output of one of
the FFs.

Additional constraints: no external ANDs or ORs or NOTs, the
state-machine does not get stuck in the 3 unused states.

This turned out to be a very interesting problem and I do not yet come
up with a solution. Maybe there is none. Analytical solutions all
failed, I will try a brute force enumeration attack tomorrow.

lots of fun !

Cheers


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[time-nuts] low power divide by 5

2020-07-01 Thread Detlef Schuecker via time-nuts

Hi,

there are three JK-FF, with Q1 as MSB, Q3 as LSB. J1,K1 ist input to Q1, 
etc. .
There are 8^6 possibilties (6 inputs to the Qx or QxNOT or to HIGH or to 
LOW) of which
2069 generate a cycle length of 5.

The following wiring will generate the cycle 1 3 5 2 4 :

J1=Q2
K1=Q1
J2=Q3
K2=Q2
J3=Q2NOT
K3=Q1

Q3 is output with a 3/5 duty cycle.
The unused state 0 will migrate to 1,6->0,7->0.
So the machine does not get stuck.

Cheers
Detlef 


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Re: [time-nuts] low power divide by 5

2020-07-01 Thread dschuecker


hm,

first example of divide by 5 needs an additional AND, second example 
gets stuck in an unused state :(


Cheers

Detlef

Am 01.07.2020 um 02:14 schrieb David:

Here's a web page with several JK flip-flop dividers, including divide
by 5:

http://www.play-hookey.com/digital/counters/frequency_dividers.html

Dave

On 2020-06-30 15:47, dschuecker wrote:


Hi,

a divide by five should possible with a synchronous state-machine made of 3 ( 
sufficiently fast-) JK-FlipFlops.

All 3 FFs are clocked with the input freq. , the outputs of the FFs are fed 
back to the the JK-inputs,  the divided freq. is output of one of the FFs.

Additional constraints: no external ANDs or ORs or NOTs, the state-machine does 
not get stuck in the 3 unused states.

This turned out to be a very interesting problem and I do not yet come up with 
a solution. Maybe there is none. Analytical solutions all failed, I will try a 
brute force enumeration attack tomorrow.

lots of fun !

Cheers

Detlef

Am 30.06.2020 um 08:37 schrieb Hal Murray: You might try the 74AC161, which 
works to 73MHz at 3.3V or 103 MHz at 5V, -40
to 85C.
Set the data inputs to DCBA = 1011 and connect an inverter from the carry
output (pin 15) to the Load input (pin 9) to divide by 5. See http://
www.techlib.com/electronics/74161Divider.htm [1] You didn't read the data sheet 
carefully enough.  That 73 MHz is the bragging
number for sales people, often not useful.  For something like this, you need
to add the clock-to-out for the ripple carry, prop time through inverter, and
setup time at the load input.

I was going to ask whether 73MHz included the delay through the inverter, but
it's much worse than that.  The clock to out on the RCO pin is 21 ns.  Even
without the inverter, it won't make 50 MHz.

You can save a few ns if you use a FF with inverting output instead of an
inverter.  That adds a pipeline stage so you have to adjust the constant that
gets loaded.  Setup time on a 3V AC74 is 4.3 ns which gets to 40 MHz (actually
only 39.5).

At 5V,
AC161 clk-RCO is 15.2
AC74 setup is 3.1
So that works - 54.6 MHz.

Using an inverter:
AC161 clk-RCO is 15.2
AC04 prop 5.9
AC161 setup 5.3
That's 37.9 MHz

(That's all assuming I didn't fatfinger anything.)

I like Richard Karlquist's trick of using a data bit to reload.
Unfortunately, for the AC161, the data out isn't significantly faster than the
carry out.

If I did the numbers correctly, that's 35 MHz at 3.3V and 49.3 MHz at 5V.

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Links:
--
[1] http://www.techlib.com/electronics/74161Divider.htm
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Re: [time-nuts] low power divide by 5

2020-07-01 Thread Gerhard Hoffmann



Am 01.07.20 um 03:04 schrieb Hal Murray:

What logic family might be appropriate for a divide by 5 from 50 to 10MHz,
low power, running off 3.3 or 5V?

How important is the "low" power?  Do you have other logic/CPU around?

Do you need 50/50 duty cycle (or close) or is 20/80 OK?

How about a CPU with a counter/timer block setup to divide by 5 and the CPU
sleeping (if it doesn't have anything else to do)?

What is available in the small FPGA or PAL space?

In the divide-by-81 thread I have proposed a Xilinx Coolrunner, with
VHDL code, and a link to a prefabricated Chinese board. Just replace
the 81 by 5 and choose the new On/Off ratio.

< 
https://www.digikey.de/product-detail/de/xilinx-inc/XC2C64A-5VQG44C/122-1420-ND/966601 
    >



Prices are slowly rising, that's Xilinx' way of saying: we don't like it 
anymore,

but we usually don't obsolete anything.
I'm just doing a custom reciprocal frequency counter with SPI interface 
in one,
and my crystal oven infrastructure board uses such a 2C64 for its 1pps 
generator
and switchable direction 2FF phase detector. You can do a lot of things 
with just 64


flipflops. It's weird, but Coolrunner Flipflops can act on both rising 
and falling


clock edge if required.


Much modern logic is aimed at the high speed market which usually means thin
oxide which leaks.  I'm pretty sure I've seen some FPGA/PAL families that are
old but still very active just because their idle power is very low - the last
family before things started to leak.

When it was new, Xilinx demonstrated the Coolrunner with a battery
made from 3 apples or oranges and some wire.





How about a shift register?  It needs a reset signal to get started.




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Re: [time-nuts] low power divide by 5

2020-07-01 Thread Mike Ingle

Hi,

As suggested by others, another approach could be to use a cpld of some
type, for example look at the lattice mach  or the old cool-runner
varieties.
You can usually DDR the clock.  This should give the same symmetry as the
input clock.  With a 50% duty cycle 50MHz input this should give a 10MHz
50% output;
In VHDL for example:

process(clk)
begin
if (rising_edge(clk) or falling_edge(clk)) then
  if (cnt < 5) then
cnt <= cnt + 1;
  else
cnt <= 0;
divided_by_five <= not(divided_by_five);
  end if;
 end if;
end process;

and there are usually built in DDR IP's from the vendors.

-- mike

On Wed, Jul 1, 2020 at 8:50 AM Robert LaJeunesse 
wrote:

> Take a look at the "modified" shift-register like counter in the attached
> jpg file. When simulated online it behaved as expected for a divide by 5. I
> believe it also is self-clearing from illegal states, but the other
> simulator I tested that in wasn't good for documenting the design.
>
> Bob L.
>
> > Sent: Tuesday, June 30, 2020 at 6:47 PM
> > From: "dschuecker" 
> > To: time-nuts@lists.febo.com
> > Subject: Re: [time-nuts] low power divide by 5
> >
> > Hi,
> >
> > a divide by five should possible with a synchronous state-machine made
> > of 3 ( sufficiently fast-) JK-FlipFlops.
> >
> > All 3 FFs are clocked with the input freq. , the outputs of the FFs are
> > fed back to the the JK-inputs,  the divided freq. is output of one of
> > the FFs.
> >
> > Additional constraints: no external ANDs or ORs or NOTs, the
> > state-machine does not get stuck in the 3 unused states.
> >
> > This turned out to be a very interesting problem and I do not yet come
> > up with a solution. Maybe there is none. Analytical solutions all
> > failed, I will try a brute force enumeration attack tomorrow.
> >
> > lots of fun !
> >
> > Cheers
> >
> > Detlef
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Re: [time-nuts] low power divide by 5

2020-07-01 Thread Robert LaJeunesse

Take a look at the "modified" shift-register like counter in the attached jpg 
file. When simulated online it behaved as expected for a divide by 5. I believe 
it also is self-clearing from illegal states, but the other simulator I tested 
that in wasn't good for documenting the design.

Bob L.

> Sent: Tuesday, June 30, 2020 at 6:47 PM
> From: "dschuecker" 
> To: time-nuts@lists.febo.com
> Subject: Re: [time-nuts] low power divide by 5
>
> Hi,
> 
> a divide by five should possible with a synchronous state-machine made 
> of 3 ( sufficiently fast-) JK-FlipFlops.
> 
> All 3 FFs are clocked with the input freq. , the outputs of the FFs are 
> fed back to the the JK-inputs,  the divided freq. is output of one of 
> the FFs.
> 
> Additional constraints: no external ANDs or ORs or NOTs, the 
> state-machine does not get stuck in the 3 unused states.
> 
> This turned out to be a very interesting problem and I do not yet come 
> up with a solution. Maybe there is none. Analytical solutions all 
> failed, I will try a brute force enumeration attack tomorrow.
> 
> lots of fun !
> 
> Cheers
> 
> Detlef
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Re: [time-nuts] low power divide by 5

2020-07-01 Thread jimlux


On 6/30/20 5:04 PM, Richard (Rick) Karlquist wrote:


On 6/30/2020 3:47 PM, dschuecker wrote:

Hi,

a divide by five should possible with a synchronous state-machine made 
of 3 ( sufficiently fast-) JK-FlipFlops.


All 3 FFs are clocked with the input freq. , the outputs of the FFs 
are fed back to the the JK-inputs,  the divided freq. is output of one 
of the FFs.



Detlef




Nice ideas, but JK flip flops seem to have become extinct in
newer logic families.

It might be interesting to see what could be done
using one of those programmable logic devices (PLD).





Oddly, those too are hard to find.. The venerable 22V10 (which I used in 
the 1980s) is still available (as the ATF22V10 from Microchip/semi), 
targeting the military market (probably to "build to print" stuff 
designed in the 80s and 90s)


But it's interesting - lots of 20k gate FPGAs and such, not so many 
"dozen flip flops and 2 dozen gates" devices.




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Re: [time-nuts] low power divide by 5

2020-07-01 Thread Hal Murray



> What logic family might be appropriate for a divide by 5 from 50 to 10MHz,
> low power, running off 3.3 or 5V?

How important is the "low" power?  Do you have other logic/CPU around?

Do you need 50/50 duty cycle (or close) or is 20/80 OK?

How about a CPU with a counter/timer block setup to divide by 5 and the CPU 
sleeping (if it doesn't have anything else to do)?

What is available in the small FPGA or PAL space?

Much modern logic is aimed at the high speed market which usually means thin 
oxide which leaks.  I'm pretty sure I've seen some FPGA/PAL families that are 
old but still very active just because their idle power is very low - the last 
family before things started to leak.

How about a shift register?  It needs a reset signal to get started.


-- 
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Re: [time-nuts] low power divide by 5

2020-06-30 Thread Richard (Rick) Karlquist



On 6/30/2020 3:47 PM, dschuecker wrote:

Hi,

a divide by five should possible with a synchronous state-machine made 
of 3 ( sufficiently fast-) JK-FlipFlops.


All 3 FFs are clocked with the input freq. , the outputs of the FFs are 
fed back to the the JK-inputs,  the divided freq. is output of one of 
the FFs.



Detlef




Nice ideas, but JK flip flops seem to have become extinct in
newer logic families.

It might be interesting to see what could be done
using one of those programmable logic devices (PLD).

Rick N6RK

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Re: [time-nuts] low power divide by 5

2020-06-30 Thread David

Here's a web page with several JK flip-flop dividers, including divide
by 5: 

http://www.play-hookey.com/digital/counters/frequency_dividers.html 

Dave 

On 2020-06-30 15:47, dschuecker wrote:

> Hi,
> 
> a divide by five should possible with a synchronous state-machine made of 3 ( 
> sufficiently fast-) JK-FlipFlops.
> 
> All 3 FFs are clocked with the input freq. , the outputs of the FFs are fed 
> back to the the JK-inputs,  the divided freq. is output of one of the FFs.
> 
> Additional constraints: no external ANDs or ORs or NOTs, the state-machine 
> does not get stuck in the 3 unused states.
> 
> This turned out to be a very interesting problem and I do not yet come up 
> with a solution. Maybe there is none. Analytical solutions all failed, I will 
> try a brute force enumeration attack tomorrow.
> 
> lots of fun !
> 
> Cheers
> 
> Detlef
> 
> Am 30.06.2020 um 08:37 schrieb Hal Murray: You might try the 74AC161, which 
> works to 73MHz at 3.3V or 103 MHz at 5V, -40
> to 85C.
> Set the data inputs to DCBA = 1011 and connect an inverter from the carry
> output (pin 15) to the Load input (pin 9) to divide by 5. See http://
> www.techlib.com/electronics/74161Divider.htm [1] You didn't read the data 
> sheet carefully enough.  That 73 MHz is the bragging
> number for sales people, often not useful.  For something like this, you need
> to add the clock-to-out for the ripple carry, prop time through inverter, and
> setup time at the load input.
> 
> I was going to ask whether 73MHz included the delay through the inverter, but
> it's much worse than that.  The clock to out on the RCO pin is 21 ns.  Even
> without the inverter, it won't make 50 MHz.
> 
> You can save a few ns if you use a FF with inverting output instead of an
> inverter.  That adds a pipeline stage so you have to adjust the constant that
> gets loaded.  Setup time on a 3V AC74 is 4.3 ns which gets to 40 MHz (actually
> only 39.5).
> 
> At 5V,
> AC161 clk-RCO is 15.2
> AC74 setup is 3.1
> So that works - 54.6 MHz.
> 
> Using an inverter:
> AC161 clk-RCO is 15.2
> AC04 prop 5.9
> AC161 setup 5.3
> That's 37.9 MHz
> 
> (That's all assuming I didn't fatfinger anything.)
> 
> I like Richard Karlquist's trick of using a data bit to reload.
> Unfortunately, for the AC161, the data out isn't significantly faster than the
> carry out.
> 
> If I did the numbers correctly, that's 35 MHz at 3.3V and 49.3 MHz at 5V.

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Links:
--
[1] http://www.techlib.com/electronics/74161Divider.htm
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Re: [time-nuts] low power divide by 5

2020-06-30 Thread dschuecker


Hi,

a divide by five should possible with a synchronous state-machine made 
of 3 ( sufficiently fast-) JK-FlipFlops.


All 3 FFs are clocked with the input freq. , the outputs of the FFs are 
fed back to the the JK-inputs,  the divided freq. is output of one of 
the FFs.


Additional constraints: no external ANDs or ORs or NOTs, the 
state-machine does not get stuck in the 3 unused states.


This turned out to be a very interesting problem and I do not yet come 
up with a solution. Maybe there is none. Analytical solutions all 
failed, I will try a brute force enumeration attack tomorrow.


lots of fun !

Cheers

Detlef



Am 30.06.2020 um 08:37 schrieb Hal Murray:

You might try the 74AC161, which works to 73MHz at 3.3V or 103 MHz at 5V, -40
to 85C.
Set the data inputs to DCBA = 1011 and connect an inverter from the carry
output (pin 15) to the Load input (pin 9) to divide by 5. See http://
www.techlib.com/electronics/74161Divider.htm

You didn't read the data sheet carefully enough.  That 73 MHz is the bragging
number for sales people, often not useful.  For something like this, you need
to add the clock-to-out for the ripple carry, prop time through inverter, and
setup time at the load input.

I was going to ask whether 73MHz included the delay through the inverter, but
it's much worse than that.  The clock to out on the RCO pin is 21 ns.  Even
without the inverter, it won't make 50 MHz.

You can save a few ns if you use a FF with inverting output instead of an
inverter.  That adds a pipeline stage so you have to adjust the constant that
gets loaded.  Setup time on a 3V AC74 is 4.3 ns which gets to 40 MHz (actually
only 39.5).

At 5V,
   AC161 clk-RCO is 15.2
   AC74 setup is 3.1
So that works - 54.6 MHz.

Using an inverter:
   AC161 clk-RCO is 15.2
   AC04 prop 5.9
   AC161 setup 5.3
That's 37.9 MHz

(That's all assuming I didn't fatfinger anything.)

I like Richard Karlquist's trick of using a data bit to reload.
Unfortunately, for the AC161, the data out isn't significantly faster than the
carry out.

If I did the numbers correctly, that's 35 MHz at 3.3V and 49.3 MHz at 5V.










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Re: [time-nuts] low power divide by 5

2020-06-30 Thread Hal Murray



> You might try the 74AC161, which works to 73MHz at 3.3V or 103 MHz at 5V, -40
> to 85C.

> Set the data inputs to DCBA = 1011 and connect an inverter from the carry
> output (pin 15) to the Load input (pin 9) to divide by 5. See http://
> www.techlib.com/electronics/74161Divider.htm 

You didn't read the data sheet carefully enough.  That 73 MHz is the bragging 
number for sales people, often not useful.  For something like this, you need 
to add the clock-to-out for the ripple carry, prop time through inverter, and 
setup time at the load input.

I was going to ask whether 73MHz included the delay through the inverter, but 
it's much worse than that.  The clock to out on the RCO pin is 21 ns.  Even 
without the inverter, it won't make 50 MHz.

You can save a few ns if you use a FF with inverting output instead of an 
inverter.  That adds a pipeline stage so you have to adjust the constant that 
gets loaded.  Setup time on a 3V AC74 is 4.3 ns which gets to 40 MHz (actually 
only 39.5).

At 5V,
  AC161 clk-RCO is 15.2
  AC74 setup is 3.1
So that works - 54.6 MHz.

Using an inverter:
  AC161 clk-RCO is 15.2
  AC04 prop 5.9
  AC161 setup 5.3
That's 37.9 MHz

(That's all assuming I didn't fatfinger anything.)

I like Richard Karlquist's trick of using a data bit to reload.  
Unfortunately, for the AC161, the data out isn't significantly faster than the 
carry out.

If I did the numbers correctly, that's 35 MHz at 3.3V and 49.3 MHz at 5V.








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Re: [time-nuts] low power divide by 5

2020-06-29 Thread Richard (Rick) Karlquist


To divide by 5 with a '161/'163 counter, connect
the 8's bit output to the /preset enable input.
Then set the input bits to 12.  The counter will
count:  12, 13, 14, 15, 0, 12, 13, 14, 15, 0 ...
This is the fastest configuration.  It avoids
external gate delay and the slower carry output.
You can only divide by up to 9 this way.

I have been doing this for at least 40 years with
various logic families du jour.

Rick N6RK

On 6/29/2020 3:32 PM, ed breya wrote:
Looks like the AC161 and AC163 are readily available, so they may be 
rigged for divide 5. It seems that of the counters surviving into AC, 
only binary ones are included, and the oddballs like decade are 
considered unnecessary - apparently nobody divides by 10 anymore, except 
inside of a processor.


Ed


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Re: [time-nuts] low power divide by 5

2020-06-29 Thread Gerhard Hoffmann



Am 29.06.20 um 18:43 schrieb jimlux:
What logic family might be appropriate for a divide by 5 from 50 to 
10MHz, low power, running off 3.3 or 5V? 


In the picture is probably what you need, and maybe more.
The left third is a comparator that generates valid CMOS levels from a 
vaguely defined sine signal.
The right third determines if there is a valid reference and tells the 
PLL (not in the picture) to use

or ignore it.
If you have a valid CMOS signal, the middle is all that is needed. 
LVC163 + LVC04. Good enough for
150 MHz+.  On terminal count, the inverter forces the counter to load 
the P0..3 pins on the next
clock.  The value on P0..3 determines the division ratio, from 2 to 16. 
Large numbers  = few clocks
until the next terminal count. The example is divide by 5, which happens 
to fit your problem.


IIRC, the 74AC191 could have done that without the external inverter, 
but it did not make it

into the 74LVC series.

That's what I used to lock my DG8SAQ vector network analyzer V2+  to an 
external 10 MHz reference

before  that was available in V3. The PLL chip was a 74lvc4046.

https://www.digikey.de/product-detail/de/nexperia-usa-inc/74LVC163PW-118/1727-3097-2-ND/946683

Cheers, Gerhard
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Re: [time-nuts] low power divide by 5

Looks like the AC161 and AC163 are readily available, so they may be 
rigged for divide 5. It seems that of the counters surviving into AC, 
only binary ones are included, and the oddballs like decade are 
considered unnecessary - apparently nobody divides by 10 anymore, except 
inside of a processor.


Ed


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Re: [time-nuts] low power divide by 5

Well, data sheets are out there, but I don't know about the actual 
parts. Unfortunately, the 74AC family has far fewer members than the 
74HC and others. I think each step in the evolution loses some types 
that aren't expected to be high enough in volume for the most modern 
applications. For instance, if you look back through the history of TTL 
and its descendants, there are a lot of numbers that have gone extinct, 
and new ones born.


I know the 74AC parts are plentiful in the high speed bus type stuff 
('374, '244, '541, etc) and glue logic. It seems that many counters 
should still be around too. Here's a '390 datasheet I found:


https://pdf1.alldatasheet.com/datasheet-pdf/view/106913/TOSHIBA/TC74AC390F.html

So, it must have existed sometime, but maybe it didn't make the 
evolutionary cut. In any case, I think there must be some available 
somewhere, even if obsolete. 74AC may be available in other counters 
like '160 or '190 families. I haven't looked in a while.


I can't offhand remember all the HC counters, but I don't think any will 
be acceptable for 50 MHz. Gotta go with AC or more modern low-level 
families. If worse came to worse, you can definitely get some AC74s and 
build your own machine, but it won't be as nice as dropping in a single 
AC390 and having dividers to spare.


Ed

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Re: [time-nuts] low power divide by 5

I just looked around for some AC390s - it appears they may have been 
made only by Toshiba and Hitachi, and have gone obsolete. Looks like you 
can't just call Mouser to order some up. But, looking at this site, it 
appears that a lot exist - at least a million pieces floating around out 
there, if these inventory numbers are true.


https://www.digchip.com/datasheets/quote.php?action=search=74AC390

Ed

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Re: [time-nuts] low power divide by 5

2020-06-29 Thread Jim Harman

You might try the 74AC161, which works to 73MHz at 3.3V or 103 MHz at 5V,
-40 to 85C.

Set the data inputs to DCBA = 1011 and connect an inverter from the carry
output (pin 15) to the Load input (pin 9) to divide by 5. See
http://www.techlib.com/electronics/74161Divider.htm

On Mon, Jun 29, 2020 at 12:49 PM jimlux  wrote:

> What logic family might be appropriate for a divide by 5 from 50 to
> 10MHz, low power, running off 3.3 or 5V?
>
>
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Re: [time-nuts] low power divide by 5

2020-06-29 Thread jimlux


On 6/29/20 10:41 AM, ed breya wrote:
74AC logic would do it just fine, but needs 5V nominal for full-speed 
specs. Lower supply voltage should work, but probably not all the way 
down to 3.3V with 50 MHz clocking. The spec sheets should indicate the 
possible range.


The 74AC390 can provide divide by 5 directly, with another divide 5 and 
two divide 2 sections left over - lots of capability.


Ed
Couldn't find the AC390 - did find HC390, but it only goes to 35 MHz (at 
room temp, less over temp)


However, you got me started hunting for decade counters, and there's 
things like the 74HC4017 which claims fmax=60 MHz on the data sheet 
front page, but only claims 35 MHz down in the AC specs


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Re: [time-nuts] low power divide by 5

I just looked at the 74AC390 sheet - it does say it will run to 60 MHz 
clocking with 3.3V supply, but that's at 25 deg C Tj. So, it looks 
doable, but depends on your desired operating temperature range.


Ed

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Re: [time-nuts] low power divide by 5