date:20150611

From: Stuart Yoder stuart.yo...@freescale.com

Stream IDs on ls2085a devices are not hardwired and are
programmed by sw.  There are a limited number of stream IDs
available, and the partitioning of them is scenario dependent.
This header defines the partitioning between legacy, PCI,
and DPAA2 devices.

Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset

 .../include/asm/arch-fsl-lsch3/ls2085a_stream_id.h | 64 ++
 drivers/net/fsl-mc/mc.c|  2 +-
 include/configs/ls2085a_common.h   |  1 +
 include/fsl-mc/fsl_mc.h|  4 --
 4 files changed, 66 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h 
b/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h
new file mode 100644
index 000..5c94530
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#ifndef __FSL_STREAM_ID_H
+#define __FSL_STREAM_ID_H
+
+/* Stream IDs on ls2085a devices are not hardwired and are
+ * programmed by sw.  There are a limited number of stream IDs
+ * available, and the partitioning of them is scenario dependent.
+ * This header defines the partitioning between legacy, PCI,
+ * and DPAA2 devices.
+ *
+ * This partitiong can be customized in this file depending
+ * on the specific hardware config-- e.g. perhaps not all
+ * PEX controllers are in use.
+ *
+ * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for
+ * each of the different bus masters.  The relationship between
+ * the AMQ registers and stream IDs is defined in the table below:
+ *  AMQ bitstreamID bit
+ *  ---
+ *   PL[18] 9
+ *  BMT[17] 8
+ *   VA[16] 7
+ * [15] -
+ * ICID[14:7]   -
+ * ICID[6:0]6-0
+ * 
+ */
+
+#define AMQ_PL_MASK(0x1  18)   /* priviledge bit */
+#define AMQ_BMT_MASK   (0x1  17)   /* bypass bit */
+
+#define FSL_INVALID_STREAM_ID  0
+
+#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
+
+/* legacy devices */
+#define FSL_USB1_STREAM_ID 1
+#define FSL_USB2_STREAM_ID 2
+#define FSL_SDMMC_STREAM_ID3
+#define FSL_SATA1_STREAM_ID4
+#define FSL_SATA2_STREAM_ID5
+#define FSL_DMA_STREAM_ID  6
+
+/* PCI - programmed in PEXn_LUT by OS */
+/*   4 IDs per controller */
+#define FSL_PEX1_STREAM_ID_START   7
+#define FSL_PEX1_STREAM_ID_END 10
+#define FSL_PEX2_STREAM_ID_START   11
+#define FSL_PEX2_STREAM_ID_END 14
+#define FSL_PEX3_STREAM_ID_START   15
+#define FSL_PEX3_STREAM_ID_END 18
+#define FSL_PEX4_STREAM_ID_START   19
+#define FSL_PEX4_STREAM_ID_END 22
+
+/* DPAA2 - set in MC DPC and alloced by MC */
+#define FSL_DPAA2_STREAM_ID_START  23
+#define FSL_DPAA2_STREAM_ID_END63
+
+#endif
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index c4406c6..8bb8f7b 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -474,7 +474,7 @@ int mc_init(void)
out_le32(mc_ccsr_regs-reg_mcfbalr, reg_mcfbalr);
out_le32(mc_ccsr_regs-reg_mcfbahr,
 (u32)(mc_ram_aligned_base_addr  32));
-   out_le32(mc_ccsr_regs-reg_mcfapr, MCFAPR_BYPASS_ICID_MASK);
+   out_le32(mc_ccsr_regs-reg_mcfapr, FSL_BYPASS_AMQ);
 
/*
 * Tell the MC that we want delayed DPL deployment.
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 47c836d..8ff4372 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -19,6 +19,7 @@
 #define CONFIG_ARM_ERRATA_828024
 #define CONFIG_ARM_ERRATA_826974
 
+#include asm/arch-fsl-lsch3/ls2085a_stream_id.h
 #include asm/arch-fsl-lsch3/config.h
 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
 #defineCONFIG_SYS_HAS_SERDES
diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h
index 0e799f5..9106f25 100644
--- a/include/fsl-mc/fsl_mc.h
+++ b/include/fsl-mc/fsl_mc.h
@@ -21,10 +21,6 @@
 #define GCR1_M2_DE_RST BIT(14)
 #define GCR1_M_ALL_DE_RST  (GCR1_M1_DE_RST | GCR1_M2_DE_RST)
 #define GSR_FS_MASK0x3fff
-#define MCFAPR_PL_MASK (0x1  18)
-#define MCFAPR_BMT_MASK(0x1  17)
-#define MCFAPR_BYPASS_ICID_MASK\
-   (MCFAPR_PL_MASK | MCFAPR_BMT_MASK)
 
 #define SOC_MC_PORTALS_BASE_ADDR((void __iomem *)0x00080C00)
 #define SOC_QBMAN_PORTALS_BASE_ADDR ((void __iomem *)0x00081800)
--

[U-Boot] [PATCH 07/14][v2] drivers: fsl-mc: Return error for major version mismatch

Management complex major version should match to the firmware present in flash.

Return error during mismatch of major version.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset

 drivers/net/fsl-mc/mc.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 2094595..c4406c6 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -518,9 +518,14 @@ int mc_init(void)
goto out;
}
 
-   if (MC_VER_MAJOR != mc_ver_info.major)
+   if (MC_VER_MAJOR != mc_ver_info.major) {
printf(fsl-mc: ERROR: Firmware major version mismatch (found: 
%d, expected: %d)\n,
   mc_ver_info.major, MC_VER_MAJOR);
+   printf(fsl-mc: Update the Management Complex firmware\n);
+
+   error = 1;
+   goto out;
+   }
 
if (MC_VER_MINOR != mc_ver_info.minor)
printf(fsl-mc: WARNING: Firmware minor version mismatch 
(found: %d, expected: %d)\n,
-- 
1.9.1


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[U-Boot] [PATCH 03/14][v2] driver/ldpaa_eth:Flush buffer before seeding BMAN after TX_conf

Flush buffer before releasing to BMan after TX_conf to ensure, the core does
not have any cachelines that the WRIOP will DMA to.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset

 drivers/net/ldpaa_eth/ldpaa_eth.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c 
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index d4be1ba..5636511 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -153,6 +153,7 @@ static void ldpaa_eth_tx_conf(struct ldpaa_eth_priv *priv,
}
}
 
+   flush_dcache_range(fd_addr, fd_addr + LDPAA_ETH_RX_BUFFER_SIZE);
qbman_release_desc_clear(releasedesc);
qbman_release_desc_set_bpid(releasedesc, dflt_dpbp-dpbp_attr.bpid);
do {
-- 
1.9.1


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[U-Boot] [PATCH 05/14][v2] drivers: fsl-mc: Update flibs to mc-0.6.0.1

Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects
Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in
dpio_attr. These are now offsets from the SoC QBMan portals base.

Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset

 drivers/net/fsl-mc/dpni.c  |   2 +-
 drivers/net/fsl-mc/mc.c|  12 ++--
 include/fsl-mc/fsl_dpio.h  |  32 --
 include/fsl-mc/fsl_dpmng.h |   2 +-
 include/fsl-mc/fsl_dpni.h  | 144 ++---
 include/fsl-mc/fsl_dprc.h  |  64 +---
 include/fsl-mc/fsl_mc.h|   1 +
 7 files changed, 199 insertions(+), 58 deletions(-)

diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c
index b384401..7bc2504 100644
--- a/drivers/net/fsl-mc/dpni.c
+++ b/drivers/net/fsl-mc/dpni.c
@@ -313,7 +313,7 @@ int dpni_set_counter(struct fsl_mc_io *mc_io,
 
 int dpni_set_link_cfg(struct fsl_mc_io *mc_io,
  uint16_t token,
-struct dpni_link_cfg *cfg)
+const struct dpni_link_cfg *cfg)
 {
struct mc_command cmd = { 0 };
 
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 2b38b50..2094595 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -610,14 +610,16 @@ int dpio_init(struct dprc_obj_desc obj_desc)
printf(dpio_enable() failed %d\n, err);
goto err_get_enable;
}
-   debug(ce_paddr=0x%llx, ci_paddr=0x%llx, portalid=%d, prios=%d\n,
- attr.qbman_portal_ce_paddr,
- attr.qbman_portal_ci_paddr,
+   debug(ce_offset=0x%llx, ci_offset=0x%llx, portalid=%d, prios=%d\n,
+ attr.qbman_portal_ce_offset,
+ attr.qbman_portal_ci_offset,
  attr.qbman_portal_id,
  attr.num_priorities);
 
-   p_des.cena_bar = (void *)attr.qbman_portal_ce_paddr;
-   p_des.cinh_bar = (void *)attr.qbman_portal_ci_paddr;
+   p_des.cena_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
+   + attr.qbman_portal_ce_offset);
+   p_des.cinh_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
+   + attr.qbman_portal_ci_offset);
 
dflt_dpio-sw_portal = qbman_swp_init(p_des);
if (dflt_dpio-sw_portal == NULL) {
diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h
index e84b419..e779909 100644
--- a/include/fsl-mc/fsl_dpio.h
+++ b/include/fsl-mc/fsl_dpio.h
@@ -8,8 +8,8 @@
 #define _FSL_DPIO_H
 
 /* DPIO Version */
-#define DPIO_VER_MAJOR 2
-#define DPIO_VER_MINOR 1
+#define DPIO_VER_MAJOR 3
+#define DPIO_VER_MINOR 0
 
 /* Command IDs */
 #define DPIO_CMDID_CLOSE   0x800
@@ -31,8 +31,8 @@ do { \
MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr-qbman_portal_id);\
MC_RSP_OP(cmd, 0, 48, 8,  uint8_t,  attr-num_priorities);\
MC_RSP_OP(cmd, 0, 56, 4,  enum dpio_channel_mode, attr-channel_mode);\
-   MC_RSP_OP(cmd, 1, 0,  64, uint64_t, attr-qbman_portal_ce_paddr);\
-   MC_RSP_OP(cmd, 2, 0,  64, uint64_t, attr-qbman_portal_ci_paddr);\
+   MC_RSP_OP(cmd, 1, 0,  64, uint64_t, attr-qbman_portal_ce_offset);\
+   MC_RSP_OP(cmd, 2, 0,  64, uint64_t, attr-qbman_portal_ci_offset);\
MC_RSP_OP(cmd, 3, 0,  16, uint16_t, attr-version.major);\
MC_RSP_OP(cmd, 3, 16, 16, uint16_t, attr-version.minor);\
 } while (0)
@@ -42,6 +42,7 @@ do { \
  */
 
 struct fsl_mc_io;
+
 /**
  * dpio_open() - Open a control session for the specified object
  * @mc_io: Pointer to MC portal's I/O object
@@ -61,18 +62,9 @@ struct fsl_mc_io;
 int dpio_open(struct fsl_mc_io *mc_io, int dpio_id, uint16_t *token);
 
 /**
- * dpio_open() - Open a control session for the specified object
+ * dpio_close() - Close the control session of the object
  * @mc_io: Pointer to MC portal's I/O object
- * @dpio_id:   DPIO unique ID
- * @token: Returned token; use in subsequent API calls
- *
- * This function can be used to open a control session for an
- * already created object; an object may have been declared in
- * the DPL or by calling the dpio_create() function.
- * This function returns a unique authentication token,
- * associated with the specific object ID and the specific MC
- * portal; this token must be used in all subsequent commands for
- * this specific object.
+ * @token: Token of DPIO object
  *
  * Return: '0' on Success; Error code otherwise.
  */
@@ -121,10 +113,8 @@ int dpio_reset(struct fsl_mc_io *mc_io, uint16_t token);
  * struct dpio_attr - Structure representing DPIO attributes
  * @id: DPIO object ID
  * @version: DPIO version
- * @qbman_portal_ce_paddr: Physical address of the software portal
- * cache-enabled area
- *

[U-Boot] [PATCH 06/14][v2] drivers: fsl-mc: Update qbman driver

Update qbman driver
 - As per latest available qbman driver
 - Use of atomic APIs

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
CC: Geoff Thorpe geoff.tho...@freescale.com
CC: Haiying Wang haiying.w...@freescale.com
CC: Roy Pledge roy.ple...@freescale.com
---
Changes for v2: Sending as it is for patchset

 drivers/net/fsl-mc/dpio/qbman_portal.c  | 66 ++---
 drivers/net/fsl-mc/dpio/qbman_portal.h  | 22 ---
 drivers/net/fsl-mc/dpio/qbman_private.h |  2 +-
 3 files changed, 53 insertions(+), 37 deletions(-)

diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.c 
b/drivers/net/fsl-mc/dpio/qbman_portal.c
index dd2a7de..5fa8d95 100644
--- a/drivers/net/fsl-mc/dpio/qbman_portal.c
+++ b/drivers/net/fsl-mc/dpio/qbman_portal.c
@@ -64,7 +64,7 @@ enum qbman_sdqcr_fc {
 struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
 {
int ret;
-   struct qbman_swp *p = kmalloc(sizeof(*p), GFP_KERNEL);
+   struct qbman_swp *p = malloc(sizeof(struct qbman_swp));
 
if (!p)
return NULL;
@@ -77,7 +77,7 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc 
*d)
qb_attr_code_encode(code_sdqcr_dct, p-sdq, qbman_sdqcr_dct_prio_ics);
qb_attr_code_encode(code_sdqcr_fc, p-sdq, qbman_sdqcr_fc_up_to_3);
qb_attr_code_encode(code_sdqcr_tok, p-sdq, 0xbb);
-   p-vdq.busy = 0; /* TODO: convert to atomic_t */
+   atomic_set(p-vdq.busy, 1);
p-vdq.valid_bit = QB_VALID_BIT;
p-dqrr.next_idx = 0;
p-dqrr.valid_bit = QB_VALID_BIT;
@@ -165,7 +165,6 @@ static struct qb_attr_code code_eq_qd_bin = QB_CODE(4, 0, 
16);
 static struct qb_attr_code code_eq_qd_pri = QB_CODE(4, 16, 4);
 static struct qb_attr_code code_eq_rsp_stash = QB_CODE(5, 16, 1);
 static struct qb_attr_code code_eq_rsp_lo = QB_CODE(6, 0, 32);
-static struct qb_attr_code code_eq_rsp_hi = QB_CODE(7, 0, 32);
 
 enum qbman_eq_cmd_e {
/* No enqueue, primarily for plugging ORP gaps for dropped frames */
@@ -197,8 +196,7 @@ void qbman_eq_desc_set_response(struct qbman_eq_desc *d,
 {
uint32_t *cl = qb_cl(d);
 
-   qb_attr_code_encode(code_eq_rsp_lo, cl, lower32(storage_phys));
-   qb_attr_code_encode(code_eq_rsp_hi, cl, upper32(storage_phys));
+   qb_attr_code_encode_64(code_eq_rsp_lo, (uint64_t *)cl, storage_phys);
qb_attr_code_encode(code_eq_rsp_stash, cl, !!stash);
 }
 
@@ -253,7 +251,6 @@ static struct qb_attr_code code_pull_numframes = QB_CODE(0, 
8, 4);
 static struct qb_attr_code code_pull_token = QB_CODE(0, 16, 8);
 static struct qb_attr_code code_pull_dqsource = QB_CODE(1, 0, 24);
 static struct qb_attr_code code_pull_rsp_lo = QB_CODE(2, 0, 32);
-static struct qb_attr_code code_pull_rsp_hi = QB_CODE(3, 0, 32);
 
 enum qb_pull_dt_e {
qb_pull_dt_channel,
@@ -282,8 +279,7 @@ void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
}
qb_attr_code_encode(code_pull_rls, cl, 1);
qb_attr_code_encode(code_pull_stash, cl, !!stash);
-   qb_attr_code_encode(code_pull_rsp_lo, cl, lower32(storage_phys));
-   qb_attr_code_encode(code_pull_rsp_hi, cl, upper32(storage_phys));
+   qb_attr_code_encode_64(code_pull_rsp_lo, (uint64_t *)cl, storage_phys);
 }
 
 void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, uint8_t 
numframes)
@@ -316,10 +312,10 @@ int qbman_swp_pull(struct qbman_swp *s, struct 
qbman_pull_desc *d)
uint32_t *p;
uint32_t *cl = qb_cl(d);
 
-   /* TODO: convert to atomic_t */
-   if (s-vdq.busy)
+   if (!atomic_dec_and_test(s-vdq.busy)) {
+   atomic_inc(s-vdq.busy);
return -EBUSY;
-   s-vdq.busy = 1;
+   }
s-vdq.storage = *(void **)cl[4];
s-vdq.token = qb_attr_code_decode(code_pull_token, cl);
p = qbman_cena_write_start(s-sys, QBMAN_CENA_SWP_VDQCR);
@@ -359,36 +355,44 @@ const struct ldpaa_dq *qbman_swp_dqrr_next(struct 
qbman_swp *s)
 {
uint32_t verb;
uint32_t response_verb;
-   const struct ldpaa_dq *dq = qbman_cena_read(s-sys,
-   QBMAN_CENA_SWP_DQRR(s-dqrr.next_idx));
-   const uint32_t *p = qb_cl(dq);
+   uint32_t flags;
+   const struct ldpaa_dq *dq;
+   const uint32_t *p;
 
+   dq = qbman_cena_read(s-sys, QBMAN_CENA_SWP_DQRR(s-dqrr.next_idx));
+   p = qb_cl(dq);
verb = qb_attr_code_decode(code_dqrr_verb, p);
-   /* If the valid-bit isn't of the expected polarity, nothing there */
+
+   /* If the valid-bit isn't of the expected polarity, nothing there. Note,
+* in the DQRR reset bug workaround, we shouldn't need to skip these
+* check, because we've already determined that a new entry is available
+* and we've invalidated the cacheline before reading it, so the
+* valid-bit behaviour is repaired and should tell us what we already
+* knew from reading PI.
+*/
if ((verb  QB_VALID_BIT) !=

[U-Boot] [PATCH 09/14][v2] drivers/fsl-mc: dynamically create ICID pool in DPC

From: Stuart Yoder stuart.yo...@freescale.com

delete any existing ICID pools in the DPC and create
a new one based on the stream ID partitioning for
the SoC

Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset

 drivers/net/fsl-mc/mc.c | 36 
 1 file changed, 36 insertions(+)

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 8bb8f7b..2820883 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -3,8 +3,11 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
+#include common.h
 #include errno.h
 #include asm/io.h
+#include libfdt.h
+#include fdt_support.h
 #include fsl-mc/fsl_mc.h
 #include fsl-mc/fsl_mc_sys.h
 #include fsl-mc/fsl_mc_private.h
@@ -185,6 +188,36 @@ static int calculate_mc_private_ram_params(u64 
mc_private_ram_start_addr,
return 0;
 }
 
+static int mc_fixup_dpc(u64 dpc_addr)
+{
+   void *blob = (void *)dpc_addr;
+   int nodeoffset;
+
+   /* delete any existing ICID pools */
+   nodeoffset = fdt_path_offset(blob, /resources/icid_pools);
+   if (fdt_del_node(blob, nodeoffset)  0)
+   printf(\nfsl-mc: WARNING: could not delete ICID pool\n);
+
+   /* add a new pool */
+   nodeoffset = fdt_path_offset(blob, /resources);
+   if (nodeoffset  0) {
+   printf(\nfsl-mc: ERROR: DPC is missing /resources\n);
+   return -EINVAL;
+   }
+   nodeoffset = fdt_add_subnode(blob, nodeoffset, icid_pools);
+   nodeoffset = fdt_add_subnode(blob, nodeoffset, icid_pool@0);
+   do_fixup_by_path_u32(blob, /resources/icid_pools/icid_pool@0,
+base_icid, FSL_DPAA2_STREAM_ID_START, 1);
+   do_fixup_by_path_u32(blob, /resources/icid_pools/icid_pool@0,
+num,
+FSL_DPAA2_STREAM_ID_END -
+FSL_DPAA2_STREAM_ID_START + 1, 1);
+
+   flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob));
+
+   return 0;
+}
+
 static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size)
 {
u64 mc_dpc_offset;
@@ -239,6 +272,9 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size)
  (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset);
 #endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */
 
+   if (mc_fixup_dpc(mc_ram_addr + mc_dpc_offset))
+   return -EINVAL;
+
dump_ram_words(DPC, (void *)(mc_ram_addr + mc_dpc_offset));
return 0;
 }
-- 
1.9.1


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[U-Boot] [PATCH 04/14][v2] drivers/fsl-mc: Autoload AOIP image from NOR flash

From: J. German Rivera german.riv...@freescale.com

Load AIOP image from NOR flash into DDR so that the MC firmware
the MC fw can start it at boot time

Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset

 drivers/net/fsl-mc/mc.c  | 23 +++
 include/configs/ls2085a_common.h |  2 ++
 include/configs/ls2085aqds.h |  2 ++
 include/configs/ls2085ardb.h |  2 ++
 4 files changed, 29 insertions(+)

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index d02da9d..2b38b50 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -321,6 +321,23 @@ static unsigned long get_mc_boot_timeout_ms(void)
return timeout_ms;
 }
 
+#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+static int load_mc_aiop_img(u64 mc_ram_addr, size_t mc_ram_size)
+{
+   void *aiop_img;
+
+   /*
+* Load the MC AIOP image in the MC private DRAM block:
+*/
+
+   aiop_img = (void *)CONFIG_SYS_LS_MC_AIOP_IMG_ADDR;
+   mc_copy_image(MC AIOP image,
+ (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
+ mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+
+   return 0;
+}
+#endif
 static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
 {
u32 reg_gsr;
@@ -440,6 +457,12 @@ int mc_init(void)
if (error != 0)
goto out;
 
+#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+   error = load_mc_aiop_img(mc_ram_addr, mc_ram_size);
+   if (error != 0)
+   goto out;
+#endif
+
debug(mc_ccsr_regs %p\n, mc_ccsr_regs);
dump_mc_ccsr_regs(mc_ccsr_regs);
 
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 45306c1..47c836d 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -174,6 +174,8 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET0x00F0
 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH0x2
 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET0x00F2
+#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH   0x20
+#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET  0x0700
 
 /*
  * Carve out a DDR region which will not be used by u-boot/Linux
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index 731eca2..3d9655d 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -261,6 +261,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_LS_MC_DPC_ADDR  0x58080ULL
 
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x58090ULL
 
 /*
  * I2C
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index a0f0f6c..9f0a96f 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -234,6 +234,8 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_LS_MC_DPC_ADDR  0x58080ULL
 
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x58090ULL
 
 /*
  * I2C
-- 
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[U-Boot] [PATCH 01/14][v2] armv8/ls2085a: define CONFIG_PCI

LS2085A has 4 PCIe controller. Enable CONFIG_PCI to init PCIe

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 include/configs/ls2085a_common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index cf51909..45306c1 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -189,6 +189,7 @@ unsigned long long get_qixis_addr(void);
 #endif
 
 /* PCIe */
+#define CONFIG_PCI
 #define CONFIG_PCIE1   /* PCIE controler 1 */
 #define CONFIG_PCIE2   /* PCIE controler 2 */
 #define CONFIG_PCIE3   /* PCIE controler 3 */
-- 
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[U-Boot] [PATCH 02/14][v2] drivers/fsl-mc: Make MC boot error messages more readable

From: J. German Rivera german.riv...@freescale.com

Make it easier for the user to notice when the MC firmware
had problems booting.

Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset

 drivers/net/fsl-mc/mc.c | 31 +--
 1 file changed, 13 insertions(+), 18 deletions(-)

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index f4a050a..d02da9d 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -224,13 +224,13 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t 
mc_ram_size)
 * Don't return with error here, since the MC firmware can
 * still boot without a DPC
 */
-   printf(fsl-mc: WARNING: No DPC image found\n);
+   printf(\nfsl-mc: WARNING: No DPC image found);
return 0;
}
 
dpc_size = fdt_totalsize(dpc_fdt_hdr);
if (dpc_size  CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) {
-   printf(fsl-mc: ERROR: Bad DPC image (too large: %d)\n,
+   printf(\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n,
   dpc_size);
return -EINVAL;
}
@@ -278,13 +278,13 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t 
mc_ram_size)
 
error = fdt_check_header(dpl_fdt_hdr);
if (error != 0) {
-   printf(fsl-mc: ERROR: Bad DPL image (bad header)\n);
+   printf(\nfsl-mc: ERROR: Bad DPL image (bad header)\n);
return error;
}
 
dpl_size = fdt_totalsize(dpl_fdt_hdr);
if (dpl_size  CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
-   printf(fsl-mc: ERROR: Bad DPL image (too large: %d)\n,
+   printf(\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n,
   dpl_size);
return -EINVAL;
}
@@ -329,7 +329,6 @@ static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
 
dmb();
-   debug(Polling mc_ccsr_regs-reg_gsr ...\n);
assert(timeout_ms  0);
for (;;) {
udelay(1000);   /* throttle polling */
@@ -344,10 +343,7 @@ static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
}
 
if (timeout_ms == 0) {
-   if (booting_mc)
-   printf(fsl-mc: timeout booting management complex 
firmware\n);
-   else
-   printf(fsl-mc: timeout deploying data path layout\n);
+   printf(ERROR: timeout\n);
 
/* TODO: Get an error status from an MC CCSR register */
return -ETIMEDOUT;
@@ -360,15 +356,13 @@ static int wait_for_mc(bool booting_mc, u32 
*final_reg_gsr)
 * appropriate errno, so that the status property is set to
 * failure in the fsl,dprc device tree node.
 */
-   if (booting_mc) {
-   printf(fsl-mc: WARNING: Firmware booted with error 
(GSR: %#x)\n,
-  reg_gsr);
-   } else {
-   printf(fsl-mc: WARNING: Data path layout deployed with 
error (GSR: %#x)\n,
-  reg_gsr);
-   }
+   printf(WARNING: Firmware returned an error (GSR: %#x)\n,
+  reg_gsr);
+   } else {
+   printf(SUCCESS\n);
}
 
+
*final_reg_gsr = reg_gsr;
return 0;
 }
@@ -464,7 +458,7 @@ int mc_init(void)
 */
out_le32(mc_ccsr_regs-reg_gsr, 0xDD00);
 
-   printf(\nfsl-mc: Booting Management Complex ...\n);
+   printf(\nfsl-mc: Booting Management Complex ... );
 
/*
 * Deassert reset and release MC core 0 to run
@@ -517,10 +511,11 @@ int mc_init(void)
 * Tell the MC to deploy the DPL:
 */
out_le32(mc_ccsr_regs-reg_gsr, 0x0);
-   printf(\nfsl-mc: Deploying data path layout ...\n);
+   printf(fsl-mc: Deploying data path layout ... );
error = wait_for_mc(false, reg_gsr);
if (error != 0)
goto out;
+
 out:
if (error != 0)
mc_boot_status = -error;
-- 
1.9.1


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[U-Boot] [PATCH 11/14][v2] driver/ldpaa_eth: Retry enqueue if portal was busy

Do not immediately return if the enqueue function returns -EBUSY; re-try
mulitple times.

if timeout occures, release the buffer.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset

 drivers/net/ldpaa_eth/ldpaa_eth.c | 26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c 
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 5636511..2716f6c 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -221,8 +221,11 @@ static int ldpaa_eth_tx(struct eth_device *net_dev, void 
*buf, int len)
struct dpaa_fd fd;
u64 buffer_start;
int data_offset, err;
+   u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
+   u32 time_start;
struct qbman_swp *swp = dflt_dpio-sw_portal;
struct qbman_eq_desc ed;
+   struct qbman_release_desc releasedesc;
 
/* Setup the FD fields */
memset(fd, 0, sizeof(fd));
@@ -258,9 +261,18 @@ static int ldpaa_eth_tx(struct eth_device *net_dev, void 
*buf, int len)
qbman_eq_desc_clear(ed);
qbman_eq_desc_set_no_orp(ed, 0);
qbman_eq_desc_set_qd(ed, priv-tx_qdid, priv-tx_flow_id, 0);
-   err = qbman_swp_enqueue(swp, ed, (const struct qbman_fd *)(fd));
+
+   time_start = get_timer(0);
+
+   while (get_timer(time_start)  timeo) {
+   err = qbman_swp_enqueue(swp, ed,
+   (const struct qbman_fd *)(fd));
+   if (err != -EBUSY)
+   break;
+   }
+
if (err  0)
-   printf(error enqueueing Tx frame\n);
+   goto error;
 
mdelay(1);
 
@@ -269,6 +281,16 @@ static int ldpaa_eth_tx(struct eth_device *net_dev, void 
*buf, int len)
printf(error Tx Conf frame\n);
 
return err;
+
+error:
+   qbman_release_desc_clear(releasedesc);
+   qbman_release_desc_set_bpid(releasedesc, dflt_dpbp-dpbp_attr.bpid);
+   do {
+   /* Release buffer into the QBMAN */
+   err = qbman_swp_release(swp, releasedesc, buffer_start, 1);
+   } while (err == -EBUSY);
+
+   return err;
 }
 
 static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
-- 
1.9.1


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[U-Boot] [PATCH] avr32: move CONFIG_SYS_GENERIC_BOARD to Kconfig

Now all the AVR32 boards have been converted into Generic Board.
Select it in Kconfig and clean up defines in header files.

Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---

 arch/Kconfig   | 1 +
 include/configs/atngw100.h | 1 -
 include/configs/atngw100mkii.h | 1 -
 include/configs/atstk1002.h| 1 -
 include/configs/grasshopper.h  | 1 -
 5 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index 200588a..96db5c5 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -25,6 +25,7 @@ config ARM
 config AVR32
bool AVR32 architecture
select HAVE_GENERIC_BOARD
+   select SYS_GENERIC_BOARD
 
 config BLACKFIN
bool Blackfin architecture
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 56bd7f8..c4a6952 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -14,7 +14,6 @@
 #define CONFIG_AT32AP7000
 #define CONFIG_ATNGW100
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
index ea1fb58..868ec3a 100644
--- a/include/configs/atngw100mkii.h
+++ b/include/configs/atngw100mkii.h
@@ -16,7 +16,6 @@
 #define CONFIG_AT32AP7000
 #define CONFIG_ATNGW100MKII
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 64b5519..4beb068 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -95,7 +95,6 @@
 #define CONFIG_BOOTP_GATEWAY
 
 /* generic board */
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 
diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h
index 99d2389..e183f51 100644
--- a/include/configs/grasshopper.h
+++ b/include/configs/grasshopper.h
@@ -62,7 +62,6 @@
 #define CONFIG_USART_BASE  ATMEL_BASE_USART1
 #define CONFIG_USART_ID1
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 
-- 
1.9.1

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[U-Boot] [PATCH] board/BuR/common: support timer5 for pwm-backlight

2015-06-11 Thread Hannes Schmelzer

in future we support yet another br am335x based board, where Timer 5 is
wired to backlight-driver.

So we introduce a new driver-type '2' to setup timer5 instead timer6.

Signed-off-by: Hannes Schmelzer oe5...@oevsv.at

---

 board/BuR/common/common.c | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index 7830d1a..441465c 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -64,8 +64,7 @@ void lcdbacklight(int on)
unsigned int pwmfrq = getenv_ulong(ds1_pwmfreq, 10, ~0UL);
 #endif
unsigned int tmp;
-
-   struct gptimer *const timerhw = (struct gptimer *)DM_TIMER6_BASE;
+   struct gptimer *timerhw;
 
if (on)
bright = bright != ~0UL ? bright : 50;
@@ -73,6 +72,14 @@ void lcdbacklight(int on)
bright = 0;
 
switch (driver) {
+   case 2:
+   timerhw = (struct gptimer *)DM_TIMER5_BASE;
+   break;
+   default:
+   timerhw = (struct gptimer *)DM_TIMER6_BASE;
+   }
+
+   switch (driver) {
case 0: /* PMIC LED-Driver */
/* brightness level */
tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
@@ -83,7 +90,8 @@ void lcdbacklight(int on)
   bright != 0 ? 0x0A : 0x02,
   0xFF);
break;
-   case 1: /* PWM using timer6 */
+   case 1:
+   case 2: /* PWM using timer */
if (pwmfrq != ~0UL) {
timerhw-tiocp_cfg = TCFG_RESET;
udelay(10);
-- 
2.1.4

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[U-Boot] [PATCH v2 1/8] imx: mx6 correct is_soc_rev usage

is_soc_rev should return a bool value, so use ==, but not -,
change (is_soc_rev(CHIP_REV_1_0)  0) to (soc_rev()  CHIP_REV_1_0).
This patch also add space between  for cpu_type(rev) macro.

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v2:
 new patch

 arch/arm/imx-common/timer.c   | 4 ++--
 arch/arm/include/asm/arch-mx6/sys_proto.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index e522990..c12556a 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -44,8 +44,8 @@ static inline int gpt_has_clk_source_osc(void)
 {
 #if defined(CONFIG_MX6)
if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) 
-(is_soc_rev(CHIP_REV_1_0)  0)) || is_cpu_type(MXC_CPU_MX6DL) ||
- is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
+   (soc_rev()  CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
+is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
return 1;
 
return 0;
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h 
b/arch/arm/include/asm/arch-mx6/sys_proto.h
index c583291..9756708 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -12,7 +12,7 @@
 #include ../arch-imx/cpu.h
 
 #define soc_rev() (get_cpu_rev()  0xFF)
-#define is_soc_rev(rev)(soc_rev() - rev)
+#define is_soc_rev(rev) (soc_rev() == rev)
 
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);
@@ -20,7 +20,7 @@ u32 get_cpu_speed_grade_hz(void);
 u32 get_cpu_temp_grade(int *minc, int *maxc);
 
 /* returns MXC_CPU_ value */
-#define cpu_type(rev) (((rev)  12)0xff)
+#define cpu_type(rev) (((rev)  12)  0xff)
 
 /* both macros return/take MXC_CPU_ constants */
 #define get_cpu_type() (cpu_type(get_cpu_rev()))
-- 
1.8.4


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[U-Boot] [PATCH v2 5/8] imx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QP

From: Ye.Li b37...@freescale.com

Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround
for i.MX6QP.

Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---

Changes v2:
 None

 arch/arm/cpu/armv7/mx6/hab.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c
index 8dee595..bf7dbf0 100644
--- a/arch/arm/cpu/armv7/mx6/hab.c
+++ b/arch/arm/cpu/armv7/mx6/hab.c
@@ -252,7 +252,8 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t 
image_size)
 * do cache flushes. don't think any
 * exist, so we ignore them.
 */
-   writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
+   if (!is_mx6dqp())
+   writel(1, 
MX6DQ_PU_IROM_MMU_EN_VAR);
} else if (is_cpu_type(MXC_CPU_MX6DL) ||
   is_cpu_type(MXC_CPU_MX6SOLO)) {
writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
-- 
1.8.4


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[U-Boot] [PATCH v2 3/8] imx: mx6 introuduce macro is_mx6dqp

Add a new revision CHIP_REV_2_0.
Introudce macro is_mx6dqp, dqp means Dual/Quad Plus.
Since Dual/Quad Plus use same cpu type with Dual/Quad, but different
revision(Major Lower), we use this macro for Dual/Quad Plus.

Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---

Changes v2:
 Split from PATCH v1 2/8, use soc_rev but not is_soc_rev

 arch/arm/include/asm/arch-mx6/imx-regs.h  | 1 +
 arch/arm/include/asm/arch-mx6/sys_proto.h | 4 
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 0d38d45..35a324c 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -312,6 +312,7 @@
 #define CHIP_REV_1_0 0x10
 #define CHIP_REV_1_2 0x12
 #define CHIP_REV_1_5 0x15
+#define CHIP_REV_2_0 0x20
 #ifndef CONFIG_MX6SX
 #define IRAM_SIZE0x0004
 #else
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h 
b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 9756708..28c77a4 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -30,6 +30,10 @@ const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
 void set_chipselect_size(int const);
 
+#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
+is_cpu_type(MXC_CPU_MX6D))  \
+(soc_rev() = CHIP_REV_2_0))
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
-- 
1.8.4


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[U-Boot] [PATCH v2 4/8] imx: mx6: ccm: Change the clock settings for i.MX6QP

Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.

In c files, use runtime check and discard #ifdef.

A new CONFIG_MX6QP is introduced here and is used for the CCM difference,
only used in header files for different bits.
At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP.

Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---

Changes v2:
 1. Remove #ifdef, but use runtime check
 2. A few bit definitions are introduced in c files, because to other platforms
the macro will make compilation fail, also there are no other places refer
the bit macro definitions.

 arch/arm/cpu/armv7/mx6/clock.c   | 33 ++--
 arch/arm/cpu/armv7/mx6/soc.c |  5 -
 arch/arm/include/asm/arch-mx6/crm_regs.h | 33 +---
 include/configs/mx6_common.h |  3 +++
 4 files changed, 48 insertions(+), 26 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ae99945..0d862b2 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -323,10 +323,13 @@ static u32 get_ipg_per_clk(void)
u32 reg, perclk_podf;
 
reg = __raw_readl(imx_ccm-cscmr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
-   if (reg  MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
-   return MXC_HCLK; /* OSC 24Mhz */
-#endif
+   if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+   is_mx6dqp()) {
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1  6)
+   if (reg  MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
+   return MXC_HCLK; /* OSC 24Mhz */
+   }
+
perclk_podf = reg  MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 
return get_ipg_clk() / (perclk_podf + 1);
@@ -337,10 +340,14 @@ static u32 get_uart_clk(void)
u32 reg, uart_podf;
u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(imx_ccm-cscdr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
-   if (reg  MXC_CCM_CSCDR1_UART_CLK_SEL)
-   freq = MXC_HCLK;
-#endif
+
+   if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+   is_mx6dqp()) {
+#define MXC_CCM_CSCDR1_UART_CLK_SEL (1  6)
+   if (reg  MXC_CCM_CSCDR1_UART_CLK_SEL)
+   freq = MXC_HCLK;
+   }
+
reg = MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
uart_podf = reg  MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 
@@ -352,8 +359,14 @@ static u32 get_cspi_clk(void)
u32 reg, cspi_podf;
 
reg = __raw_readl(imx_ccm-cscdr2);
-   reg = MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
-   cspi_podf = reg  MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+   cspi_podf = (reg  MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) 
+MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+   if (is_mx6dqp()) {
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1  18)
+   if (reg  MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
+   return MXC_HCLK / (cspi_podf + 1);
+   }
 
return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 29de624..bcfa2f6 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -335,9 +335,12 @@ static void set_ahb_rate(u32 val)
 static void clear_mmdc_ch_mask(void)
 {
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+   u32 reg;
+   reg = readl(mxc_ccm-ccdr);
 
/* Clear MMDC channel mask */
-   writel(0, mxc_ccm-ccdr);
+   reg = ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+   writel(reg, mxc_ccm-ccdr);
 }
 
 static void init_bandgap(void)
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h 
b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 887d048..2ff1005 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -113,7 +113,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCR_WB_COUNT_MASK  0x7
 #define MXC_CCM_CCR_WB_COUNT_OFFSET(1  16)
 #define MXC_CCM_CCR_COSC_EN(1  12)
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6QP))
 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
 #else
 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
@@ -123,6 +123,9 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK  (1  16)
 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK  (1  17)
+#ifdef CONFIG_MX6QP
+#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG  (1  18)
+#endif
 
 /* Define the bits in register CSR */
 #define MXC_CCM_CSR_COSC_READY (1  5)
@@ -196,7 +199,11 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK  (0x3  4)
 #define

Re: [U-Boot] [PATCH] README.scrapyard: add entries for dead AVR32 boards

2015-06-11 Thread Andreas Bießmann

On 06/11/2015 12:13 PM, Masahiro Yamada wrote:
 Some AVR32 boards were dropped by the following commits:
  9eb45aabe078 (avr32: delete non generic board favr-32-ezkit)
  e36930764471 (avr32: delete non generic board hammerhead)
  c62d2f8fc5c6 (avr32: delete non generic board mimc200)
  e5354b8a9e2a (avr32: delete non generic board's atstk100{3, 4, 6})
 
 Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
 ---

Acked-by: Andreas Bießmann andreas.de...@googlemail.com

@Tom: Could you please pick it up directly?

Andreas

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Re: [U-Boot] [PATCH] avr32: move CONFIG_SYS_GENERIC_BOARD to Kconfig

2015-06-11 Thread Andreas Bießmann

On 06/11/2015 12:14 PM, Masahiro Yamada wrote:
 Now all the AVR32 boards have been converted into Generic Board.
 Select it in Kconfig and clean up defines in header files.
 
 Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
 ---
 

Acked-by: Andreas Bießmann andreas.de...@googlemail.com

@Tom: Could you please pick it up directly?

Andreas

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Re: [U-Boot] [PATCH v3] armv8: caches: Added routine to set non cacheable region

2015-06-11 Thread Mark Rutland

On Thu, Jun 11, 2015 at 08:17:15AM +0100, Siva Durga Prasad Paladugu wrote:

 Hi Mark,

  -Original Message-
  From: Mark Rutland [mailto:mark.rutl...@arm.com]
  Sent: Thursday, May 28, 2015 3:10 PM
  To: Siva Durga Prasad Paladugu
  Cc: u-boot@lists.denx.de; Michal Simek; Siva Durga Prasad Paladugu
  Subject: Re: [PATCH v3] armv8: caches: Added routine to set non cacheable
  region

  Hi,

   +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
   +enum dcache_option option)
   +{
   +   u64 *page_table = arch_get_page_table();
   +   u64 upto, end;
   +
   +   if (page_table == NULL)
   +   return;
   +
   +   end = ALIGN(start + size, (1  MMU_SECTION_SHIFT)) 
   + MMU_SECTION_SHIFT;
   +   start = start  MMU_SECTION_SHIFT;
   +   for (upto = start; upto  end; upto++) {
   +   page_table[upto] = ~PMD_ATTRINDX_MASK;
   +   page_table[upto] |= PMD_ATTRINDX(option);
   +   }

  These writes might not be visible to the page table walkers immediately, and
  the TLBs might still contain stale values for a while afterwards.
  That could render the cache maintenance useless (as speculative fetches
  could still occur due to cacheable attributes still being in place).

  You need a DSB to ensure writes are visible to the page table walkers (with 
  a
  compiler barrier to ensure that the writes actually occur before the DSB), 
  and
  some TLB maintenance (complete with another DSB) to ensure that the TLBs
  don't contain stale values by the time to get to the cache afterwards.
 The flush_dcache _range() below contains a dsb. Isn't it fine enough?
 Or we need a separte dsb in the for loopafter we changed the cache
 attribute.

The DSB in flush_dcache_range() is not sufficient. You need a DSB
between the page table modifications and the TLB invalidation, and the
TLB invalidation must be completed before the cache maintenance begins.

 Regarding the TLB maintenance if we have _asm_invalidate_tlb_all()
 after the flush dcache range below it should be fine right?

No. The TLB maintenance must be complete _before_ the cache maintenance,
or the cache can be refilled while the maintenance is ongoing (e.g. the
CPU could make speculative prefetches).

You need a strictly-ordered sequence:

1) Modify the page tables

2) DSB

   This ensures the updates are visible to the page table walker(s).

3) TLB invalidation

4) DSB

   This ensures that the TLB invalidation is complete (i.e. from this
   point on the TLBs cannot hold entries for the region with cacheable
   attributes).

5) ISB

   This ensures that the effects of TLB invalidation are visible to
   later instructions. Otherwise instructions later could be using stale
   attributes fetched earlier by the CPU from the TLB, before the TLB
   invalidation completed (and hence could allocate in the caches).

6) Cache maintenance 

7) DSB to complete cache maintenance

Thanks,
Mark.
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[U-Boot] [PATCH v2 7/8] imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support

1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
   and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.

Build target: mx6qpsabreauto_config

Boot Log:
U-Boot 2015.07-rc2-00034-gba46bb1 (Jun 11 2015 - 16:46:41 +0800)

CPU:   Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 26C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C:   ready
DRAM:  2 GiB
PMIC:  PFUZE100 ID=0x10
Flash: 32 MiB
NAND:  4096 MiB
MMC:   FSL_SDHC: 0
No panel detected: default to HDMI
Display: HDMI (1024x768)
In:serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Signed-off-by: Robin Gong b38...@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---

Changes v2:
 1. Remove unused macro in current upstream uboot.
 2. setup_fec, remove non 6qp code. Add comments for gpr setting.
 3. mx6qp.cfg is still same with v1. The settings is from IC and passed
memory ddr stress test. Since we current have no plan to add SPL,
so leave settings unchanged.

 board/freescale/mx6qsabreauto/mx6qp.cfg   | 143 ++
 board/freescale/mx6qsabreauto/mx6qsabreauto.c |  29 --
 configs/mx6qpsabreauto_defconfig  |   5 +
 include/configs/mx6qsabreauto.h   |   5 +-
 4 files changed, 175 insertions(+), 7 deletions(-)
 create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg
 create mode 100644 configs/mx6qpsabreauto_defconfig

diff --git a/board/freescale/mx6qsabreauto/mx6qp.cfg 
b/board/freescale/mx6qsabreauto/mx6qp.cfg
new file mode 100644
index 000..0370636
--- /dev/null
+++ b/board/freescale/mx6qsabreauto/mx6qp.cfg
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
+
+#define __ASSEMBLY__
+#include config.h
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+BOOT_FROM  sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type   AddressValue
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address   absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000C
+DATA 4 0x020e0758 0x
+DATA 4 0x020e0588 0x0030
+DATA 4 0x020e0594 0x0030
+DATA 4 0x020e056c 0x0030
+DATA 4 0x020e0578 0x0030
+DATA 4 0x020e074c 0x0030
+DATA 4 0x020e057c 0x0030
+DATA 4 0x020e058c 0x
+DATA 4 0x020e059c 0x0030
+DATA 4 0x020e05a0 0x0030
+DATA 4 0x020e078c 0x0030
+DATA 4 0x020e0750 0x0002
+DATA 4 0x020e05a8 0x0030
+DATA 4 0x020e05b0 0x0030
+DATA 4 0x020e0524 0x0030
+DATA 4 0x020e051c 0x0030
+DATA 4 0x020e0518 0x0030
+DATA 4 0x020e050c 0x0030
+DATA 4 0x020e05b8 0x0030
+DATA 4 0x020e05c0 0x0030
+DATA 4 0x020e0774 0x0002
+DATA 4 0x020e0784 0x0030
+DATA 4 0x020e0788 0x0030
+DATA 4 0x020e0794 0x0030
+DATA 4 0x020e079c 0x0030
+DATA 4 0x020e07a0 0x0030
+DATA 4 0x020e07a4 0x0030
+DATA 4 0x020e07a8 0x0030
+DATA 4 0x020e0748 0x0030
+DATA 4 0x020e05ac 0x0030
+DATA 4 0x020e05b4 0x0030
+DATA 4 0x020e0528 0x0030
+DATA 4 0x020e0520 0x0030
+DATA 4 0x020e0514 0x0030
+DATA 4 0x020e0510 0x0030
+DATA 4 0x020e05bc 0x0030
+DATA 4 0x020e05c4 0x0030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001b001e
+DATA 4 0x021b0810 0x002e0029
+DATA 4 0x021b480c 0x001b002a
+DATA 4 0x021b4810 0x0019002c
+DATA 4 0x021b083c 0x43240334
+DATA 4 0x021b0840 0x0324031a
+DATA 4 0x021b483c 0x43340344
+DATA 4 0x021b4840 0x03280276
+DATA 4 0x021b0848 0x44383A3E
+DATA 4 0x021b4848 0x3C3C3846
+DATA 4 0x021b0850 0x2e303230
+DATA 4 0x021b4850 0x38283E34
+DATA 4 0x021b081c 0x
+DATA 4 0x021b0820 0x
+DATA 4 0x021b0824 0x
+DATA 4 0x021b0828 0x
+DATA 4 0x021b481c 0x
+DATA 4 0x021b4820 0x
+DATA 4 0x021b4824 0x
+DATA 4 0x021b4828 0x
+DATA 4 0x021b08b8 0x0800
+DATA 4 0x021b48b8 0x0800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x898E7955
+DATA 4 0x021b0010 0xFF328F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x1740
+DATA 4 0x021b001c 0x8000
+
+DATA 4 0x021b002c 0x26d2
+DATA 4 0x021b0030 0x008E1023
+DATA 4 0x021b0040 0x0047
+DATA 4 0x021b0400 0x1242
+DATA 4 0x021b 0x841A
+DATA 4 0x00bb0008 0x0004
+DATA 4 0x00bb000c 0x2891E41A

[U-Boot] [PATCH v2 2/8] imx: mx6 correct get_cpu_rev

The DIGPROG register map:
23 --- 16 | 15 -- 8 | 7 --- 0 |
 Major upper  | Major Lower |  Minor  |

We also need to account for Major Lower.

Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---

Changes v2:
 split from PATCH v1 2/8. This piece code should be in a single patch.

 arch/arm/cpu/armv7/mx6/soc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index b21bd03..29de624 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -62,6 +62,7 @@ u32 get_cpu_rev(void)
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
u32 reg = readl(anatop-digprog_sololite);
u32 type = ((reg  16)  0xff);
+   u32 major;
 
if (type != MXC_CPU_MX6SL) {
reg = readl(anatop-digprog);
@@ -79,8 +80,9 @@ u32 get_cpu_rev(void)
}
 
}
+   major = ((reg  8)  0xff);
reg = 0xff;/* mx6 silicon revision */
-   return (type  12) | (reg + 0x10);
+   return (type  12) | (reg + (0x10 * (major + 1)));
 }
 
 /*
-- 
1.8.4


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[U-Boot] [PATCH v2 8/8] imx: mx6qp: Adjust AQos settings for peripherals

To resolve USB camera bandwidth issue, increase the priority
to make peripheral can fetch data from memory in time. Recommended
AQoS setting from IC team value for peripheral and only on imx6qp.

The address is: 0xbb0608, the value is: 0x8201

Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---

Changes v2:
 improve comments

 arch/arm/cpu/armv7/mx6/soc.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index bcfa2f6..e3e1494 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -424,6 +424,14 @@ int arch_cpu_init(void)
 
init_src();
 
+   /*
+* To resolve USB camera bandwidth issue, increase the priority
+* to make pheripheral can fetch data from memory in time. Recommended
+* AQoS setting from IC team value for peripheral and only on imx6qp.
+*/
+   if (is_mx6dqp())
+   writel(0x8201, 0xbb0608);
+
return 0;
 }
 
-- 
1.8.4


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[U-Boot] [PATCH v2 6/8] imx: mx6qp Enable PRG clock and AQoS setting for IPU

The i.MX6DQP has a PRG module, need to enable its clock for using IPU.

Bypass QoS for IPU and increase bankwidth threshold for PRE to get
better performance for video.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Brown Oliver b37...@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
---

Changes v2:
 1. runtime check
 2. introduce ipu qos settings for better performance

 arch/arm/cpu/armv7/mx6/clock.c | 39 +++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 0d862b2..7106df0 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -862,6 +862,30 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const argv[])
 }
 
 #ifndef CONFIG_MX6SX
+static void ipu_qos_setting(void)
+{
+   /* Bypass IPU1 QoS generator */
+   writel(0x0002, 0x00bb048c);
+   /* Bypass IPU2 QoS generator */
+   writel(0x0002, 0x00bb050c);
+   /* Bandwidth THR for of PRE0 */
+   writel(0x0200, 0x00bb0690);
+   /* Bandwidth THR for of PRE1 */
+   writel(0x0200, 0x00bb0710);
+   /* Bandwidth THR for of PRE2 */
+   writel(0x0200, 0x00bb0790);
+   /* Bandwidth THR for of PRE3 */
+   writel(0x0200, 0x00bb0810);
+   /* Saturation THR for of PRE0 */
+   writel(0x0010, 0x00bb0694);
+   /* Saturation THR for of PRE1 */
+   writel(0x0010, 0x00bb0714);
+   /* Saturation THR for of PRE2 */
+   writel(0x0010, 0x00bb0794);
+   /* Saturation THR for of PRE */
+   writel(0x0010, 0x00bb0814);
+}
+
 void enable_ipu_clock(void)
 {
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -869,7 +893,22 @@ void enable_ipu_clock(void)
reg = readl(mxc_ccm-CCGR3);
reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
writel(reg, mxc_ccm-CCGR3);
+
+   if (is_mx6dqp()) {
+#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3  24)
+   reg = readl(mxc_ccm-CCGR6);
+   reg |= MXC_CCM_CCGR6_PRG_CLK0_MASK;
+   writel(reg, mxc_ccm-CCGR6);
+
+   reg = readl(mxc_ccm-CCGR3);
+   reg |= MXC_CCM_CCGR3_IPU2_IPU_MASK;
+   writel(reg, mxc_ccm-CCGR3);
+
+   /* See Network Interconnect Bus for detailed info */
+   ipu_qos_setting();
+   }
 }
+
 #endif
 /***/
 
-- 
1.8.4


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[U-Boot] [PATCH] board/BuR/tseries: remove lpj= from environment-variable

2015-06-11 Thread Hannes Schmelzer

since we have now various processor-speeds it isn't useful anymore to
preinitialize kernels-delay loop.

Rather we want the kernel to calibrate it on every boot.
This wastes around 80ms boottime but is compatible to all CPU-speeds.

Signed-off-by: Hannes Schmelzer oe5...@oevsv.at

---

 include/configs/tseries.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index f3f71f1..cd8ba2b 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -162,7 +162,7 @@ BUR_COMMON_ENV \
 kernel=zImage\0 \
 ramdisk=rootfs.cpio.uboot\0 \
 console=ttyO0,115200n8\0 \
-optargs=consoleblank=0 quiet lpj=1191936 panic=2\0 \
+optargs=consoleblank=0 quiet panic=2\0 \
 nfsroot=/tftpboot/tseries/rootfs-small\0 \
 nfsopts=nolock\0 \
 ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0 \
-- 
2.1.4

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[U-Boot] [PATCH] DM: crypto/rsa_mod_exp - Correct copyright on rsa-mod-exp.h

2015-06-11 Thread Ruchika Gupta

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
---
 include/u-boot/rsa-mod-exp.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h
index fce445a..d250694 100644
--- a/include/u-boot/rsa-mod-exp.h
+++ b/include/u-boot/rsa-mod-exp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, Ruchika Gupta.
+ * Copyright (c) 2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:GPL-2.0+
 */
-- 
1.8.1.4

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[U-Boot] [PATCH 13/14][v2] driver/ldpaa_eth: Avoid TX conf frames

Polling of TX conf frames is not a mandatory option.
Packets can be transferred via WRIOP without TX conf frame.

Configure ldpaa_eth driver to use TX path without confirmation frame

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Changes for v2: Sending as it is for patchset

 drivers/net/ldpaa_eth/ldpaa_eth.c | 114 ++
 drivers/net/ldpaa_eth/ldpaa_eth.h |   1 -
 2 files changed, 4 insertions(+), 111 deletions(-)

diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c 
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index adb964c..839e78a 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -112,7 +112,7 @@ static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
debug(No frame delivered\n);
 
qbman_swp_dqrr_consume(swp, dq);
-   break;
+   continue;
}
 
fd = ldpaa_dq_fd(dq);
@@ -131,98 +131,6 @@ static int ldpaa_eth_pull_dequeue_rx(struct eth_device 
*dev)
return err;
 }
 
-static void ldpaa_eth_tx_conf(struct ldpaa_eth_priv *priv,
- const struct dpaa_fd *fd)
-{
-   uint64_t fd_addr;
-   struct ldpaa_fas *fas;
-   uint32_t status, err;
-   struct qbman_release_desc releasedesc;
-   struct qbman_swp *swp = dflt_dpio-sw_portal;
-
-   fd_addr = ldpaa_fd_get_addr(fd);
-
-
-   debug(TX Conf frame:data addr=0x%p\n, (u64 *)fd_addr);
-
-   /* Check the status from the Frame Annotation */
-   if (fd-simple.frc  LDPAA_FD_FRC_FASV) {
-   fas = (struct ldpaa_fas *)
-   ((uint8_t *)(fd_addr) +
-   priv-buf_layout.private_data_size);
-   status = le32_to_cpu(fas-status);
-   if (status  LDPAA_ETH_TXCONF_ERR_MASK) {
-   printf(TxConf frame error(s): 0x%08x\n,
-  status  LDPAA_ETH_TXCONF_ERR_MASK);
-   }
-   }
-
-   flush_dcache_range(fd_addr, fd_addr + LDPAA_ETH_RX_BUFFER_SIZE);
-   qbman_release_desc_clear(releasedesc);
-   qbman_release_desc_set_bpid(releasedesc, dflt_dpbp-dpbp_attr.bpid);
-   do {
-   /* Release buffer into the QBMAN */
-   err = qbman_swp_release(swp, releasedesc, fd_addr, 1);
-   } while (err == -EBUSY);
-}
-
-static int ldpaa_eth_pull_dequeue_tx_conf(struct ldpaa_eth_priv *priv)
-{
-   const struct ldpaa_dq *dq;
-   const struct dpaa_fd *fd;
-   int err = 0;
-   int i = 5, status;
-   u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
-   u32 time_start;
-   static struct qbman_pull_desc pulldesc;
-   struct qbman_swp *swp = dflt_dpio-sw_portal;
-
-   while (--i) {
-   qbman_pull_desc_clear(pulldesc);
-   qbman_pull_desc_set_numframes(pulldesc, 1);
-   qbman_pull_desc_set_fq(pulldesc, priv-tx_conf_fqid);
-
-   err =  qbman_swp_pull(swp, pulldesc);
-   if (err  0) {
-   printf(Dequeue TX conf frames error:0x%08x\n, err);
-   continue;
-   }
-
-   time_start = get_timer(0);
-
-do {
-   dq = qbman_swp_dqrr_next(swp);
-   } while (get_timer(time_start)  timeo  !dq);
-
-   if (dq) {
-   /* Check for valid frame. If not sent a consume
-* confirmation to QBMAN otherwise give it to NADK
-* application and then send consume confirmation to
-* QBMAN.
-*/
-   status = (uint8_t)ldpaa_dq_flags(dq);
-   if ((status  LDPAA_DQ_STAT_VALIDFRAME) == 0) {
-   debug(Dequeue TX conf frames:);
-   debug(No frame is delivered\n);
-
-   qbman_swp_dqrr_consume(swp, dq);
-   break;
-   }
-   fd = ldpaa_dq_fd(dq);
-
-   ldpaa_eth_tx_conf(priv, fd);
-   qbman_swp_dqrr_consume(swp, dq);
-   break;
-   } else {
-   err = -1;
-   debug(No DQRR entries\n);
-   break;
-   }
-   }
-
-   return err;
-}
-
 static int ldpaa_eth_tx(struct eth_device *net_dev, void *buf, int len)
 {
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev-priv;
@@ -282,12 +190,6 @@ static int ldpaa_eth_tx(struct eth_device *net_dev, void 
*buf, int len)
if (err  0)
goto error;
 
-   mdelay(1);
-
-   err = ldpaa_eth_pull_dequeue_tx_conf(priv);
-   if (err  0)
-   printf(error Tx Conf frame\n);
-
return err;
 
 error:
@@

[U-Boot] [PATCH 10/14][v2] armv8/fsl-lsch3: device tree fixups for PCI stream IDs

From: Stuart Yoder stuart.yo...@freescale.com

This patch adds the infrastructure to update device
tree nodes to convey SMMU stream IDs in the device
tree.  Fixups are implemented for PCI controllers
initially.

Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
changes for v2
  - define in fdt_fixup_smmu_pcie in fdt.h
  - put fdt_fixup_smmu_pcie in CONFIG_PCI 

 arch/arm/cpu/armv8/fsl-lsch3/fdt.c| 110 ++
 arch/arm/include/asm/arch-fsl-lsch3/fdt.h |  10 +++
 drivers/pci/pcie_layerscape.c |  62 +
 3 files changed, 182 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/fdt.h

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c 
b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
index b9fd559..567c419 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
@@ -7,6 +7,7 @@
 #include common.h
 #include libfdt.h
 #include fdt_support.h
+#include asm/arch-fsl-lsch3/fdt.h
 #ifdef CONFIG_FSL_ESDHC
 #include fsl_esdhc.h
 #endif
@@ -58,6 +59,113 @@ void ft_fixup_cpu(void *blob)
 }
 #endif
 
+/*
+ * the burden is on the the caller to not request a count
+ * exceeding the bounds of the stream_ids[] array
+ */
+void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt)
+{
+   int i;
+
+   if (count  max_cnt) {
+   printf(\n%s: ERROR: max per-device stream ID count exceed\n,
+  __func__);
+   return;
+   }
+
+   for (i = 0; i  count; i++)
+   stream_ids[i] = start_id++;
+}
+
+/*
+ * This function updates the mmu-masters property on the SMMU
+ * node as per the SMMU binding-- phandle and list of stream IDs
+ * for each MMU master.
+ */
+void append_mmu_masters(void *blob, const char *smmu_path,
+   const char *master_name, u32 *stream_ids, int count)
+{
+   u32 phandle;
+   int smmu_nodeoffset;
+   int master_nodeoffset;
+   int i;
+
+   /* get phandle of mmu master device */
+   master_nodeoffset = fdt_path_offset(blob, master_name);
+   if (master_nodeoffset  0) {
+   printf(\n%s: ERROR: master not found\n, __func__);
+   return;
+   }
+   phandle = fdt_get_phandle(blob, master_nodeoffset);
+   if (!phandle) { /* if master has no phandle, create one */
+   phandle = fdt_create_phandle(blob, master_nodeoffset);
+   if (!phandle) {
+   printf(\n%s: ERROR: unable to create phandle\n,
+  __func__);
+   return;
+   }
+   }
+
+   /* append it to mmu-masters */
+   smmu_nodeoffset = fdt_path_offset(blob, smmu_path);
+   if (fdt_appendprop_u32(blob, smmu_nodeoffset, mmu-masters,
+  phandle)  0) {
+   printf(\n%s: ERROR: unable to update SMMU node\n, __func__);
+   return;
+   }
+
+   /* for each stream ID, append to mmu-masters */
+   for (i = 0; i  count; i++) {
+   fdt_appendprop_u32(blob, smmu_nodeoffset, mmu-masters,
+  stream_ids[i]);
+   }
+
+   /* fix up #stream-id-cells with stream ID count */
+   if (fdt_setprop_u32(blob, master_nodeoffset, #stream-id-cells,
+   count)  0)
+   printf(\n%s: ERROR: unable to update #stream-id-cells\n,
+  __func__);
+}
+
+
+/*
+ * The info below summarizes how streamID partitioning works
+ * for ls2085a and how it is conveyed to the OS via the device tree.
+ *
+ *  -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
+ * -all legacy devices get a unique ICID assigned and programmed in
+ *  their AMQR registers by u-boot
+ * -u-boot updates the hardware device tree with streamID properties
+ *  for each platform/legacy device (smmu-masters property)
+ *
+ *  -PCIe
+ * -for each PCI controller that is active (as per RCW settings),
+ *  u-boot will allocate a range of ICID and convey that to Linux via
+ *  the device tree (smmu-masters property)
+ *
+ *  -DPAA2
+ * -u-boot will allocate a range of ICIDs to be used by the Management
+ *  Complex for containers and will set these values in the MC DPC image.
+ * -the MC is responsible for allocating and setting up ICIDs
+ *  for all DPAA2 devices.
+ *
+ */
+static void fdt_fixup_smmu(void *blob)
+{
+   int nodeoffset;
+
+   nodeoffset = fdt_path_offset(blob, /iommu@500);
+   if (nodeoffset  0) {
+   printf(\n%s: WARNING: no SMMU node found\n, __func__);
+   return;
+   }
+
+   /* fixup for all PCI controllers */
+#ifdef CONFIG_PCI
+   fdt_fixup_smmu_pcie(blob);
+#endif
+}
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_MP
@@ -76,4 +184,6 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #if

[U-Boot] [PATCH 14/14][v2] driver/ldpaa_eth:Avoid infinite loop in QBMAN buf release

Change infinite loop mechanism to timer based polling.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset

 drivers/net/ldpaa_eth/ldpaa_eth.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c 
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 839e78a..fe8f189 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -31,6 +31,8 @@ static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv,
uint32_t fd_length;
struct ldpaa_fas *fas;
uint32_t status, err;
+   u32 timeo = (CONFIG_SYS_HZ * 2) / 1000;
+   u32 time_start;
struct qbman_release_desc releasedesc;
struct qbman_swp *swp = dflt_dpio-sw_portal;
 
@@ -65,10 +67,15 @@ error:
flush_dcache_range(fd_addr, fd_addr + LDPAA_ETH_RX_BUFFER_SIZE);
qbman_release_desc_clear(releasedesc);
qbman_release_desc_set_bpid(releasedesc, dflt_dpbp-dpbp_attr.bpid);
+   time_start = get_timer(0);
do {
/* Release buffer into the QBMAN */
err = qbman_swp_release(swp, releasedesc, fd_addr, 1);
-   } while (err == -EBUSY);
+   } while (get_timer(time_start)  timeo  err == -EBUSY);
+
+   if (get_timer(time_start) = timeo)
+   printf(Rx frame: QBMAN buffer release fails\n);
+
return;
 }
 
@@ -195,11 +202,13 @@ static int ldpaa_eth_tx(struct eth_device *net_dev, void 
*buf, int len)
 error:
qbman_release_desc_clear(releasedesc);
qbman_release_desc_set_bpid(releasedesc, dflt_dpbp-dpbp_attr.bpid);
+   time_start = get_timer(0);
do {
/* Release buffer into the QBMAN */
err = qbman_swp_release(swp, releasedesc, buffer_start, 1);
-   } while (err == -EBUSY);
+   } while (get_timer(time_start)  timeo  err == -EBUSY);
 
+   printf(TX data: QBMAN buffer release fails\n);
return err;
 }
 
-- 
1.9.1


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[U-Boot] [PATCH 12/14][v2] driver/ldpaa_eth: Add timeout handling DQRR entry read

Volatile command does not return frame immidiately, need to wait till a frame
is available in DQRR. Ideally it should be a blocking call.

Add timeout handling for DQRR frame instead of retry counter.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset

 drivers/net/ldpaa_eth/ldpaa_eth.c | 36 ++--
 1 file changed, 22 insertions(+), 14 deletions(-)

diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c 
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 2716f6c..adb964c 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -77,7 +77,9 @@ static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev-priv;
const struct ldpaa_dq *dq;
const struct dpaa_fd *fd;
-   int i = 5, err = 0, status, loop = 20;
+   int i = 5, err = 0, status;
+   u32 timeo = (CONFIG_SYS_HZ * 2) / 1000;
+   u32 time_start;
static struct qbman_pull_desc pulldesc;
struct qbman_swp *swp = dflt_dpio-sw_portal;
 
@@ -92,13 +94,11 @@ static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
continue;
}
 
-   do {
-   loop--;
-   dq = qbman_swp_dqrr_next(swp);
+   time_start = get_timer(0);
 
-   if (!loop)
-   break;
-   } while (!dq);
+do {
+   dq = qbman_swp_dqrr_next(swp);
+   } while (get_timer(time_start)  timeo  !dq);
 
if (dq) {
/* Check for valid frame. If not sent a consume
@@ -121,6 +121,10 @@ static int ldpaa_eth_pull_dequeue_rx(struct eth_device 
*dev)
ldpaa_eth_rx(priv, fd);
qbman_swp_dqrr_consume(swp, dq);
break;
+   } else {
+   err = -1;
+   debug(No DQRR entries\n);
+   break;
}
}
 
@@ -167,7 +171,9 @@ static int ldpaa_eth_pull_dequeue_tx_conf(struct 
ldpaa_eth_priv *priv)
const struct ldpaa_dq *dq;
const struct dpaa_fd *fd;
int err = 0;
-   int i = 5, status, loop = 20;
+   int i = 5, status;
+   u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
+   u32 time_start;
static struct qbman_pull_desc pulldesc;
struct qbman_swp *swp = dflt_dpio-sw_portal;
 
@@ -182,13 +188,11 @@ static int ldpaa_eth_pull_dequeue_tx_conf(struct 
ldpaa_eth_priv *priv)
continue;
}
 
-   do {
-   loop--;
-   dq = qbman_swp_dqrr_next(swp);
+   time_start = get_timer(0);
 
-   if (!loop)
-   break;
-   } while (!dq);
+do {
+   dq = qbman_swp_dqrr_next(swp);
+   } while (get_timer(time_start)  timeo  !dq);
 
if (dq) {
/* Check for valid frame. If not sent a consume
@@ -209,6 +213,10 @@ static int ldpaa_eth_pull_dequeue_tx_conf(struct 
ldpaa_eth_priv *priv)
ldpaa_eth_tx_conf(priv, fd);
qbman_swp_dqrr_consume(swp, dq);
break;
+   } else {
+   err = -1;
+   debug(No DQRR entries\n);
+   break;
}
}
 
-- 
1.9.1


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[U-Boot] [PATCH] README.scrapyard: add entries for dead AVR32 boards

Some AVR32 boards were dropped by the following commits:
 9eb45aabe078 (avr32: delete non generic board favr-32-ezkit)
 e36930764471 (avr32: delete non generic board hammerhead)
 c62d2f8fc5c6 (avr32: delete non generic board mimc200)
 e5354b8a9e2a (avr32: delete non generic board's atstk100{3, 4, 6})

Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---

 doc/README.scrapyard | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index a62bd0b..f029a0f 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,12 @@ The list should be sorted in reverse chronological order.
 
 BoardArchCPUCommit  Removed Last known 
maintainer/contact
 
=
+atstk1003avr32   -  e5354b8a2015-06-10  Haavard 
Skinnemoen haavard.skinnem...@atmel.com
+atstk1004avr32   -  e5354b8a2015-06-10  Haavard 
Skinnemoen haavard.skinnem...@atmel.com
+atstk1006avr32   -  e5354b8a2015-06-10  Haavard 
Skinnemoen haavard.skinnem...@atmel.com
+mimc200  avr32   -  c62d2f8f2015-06-10  Mark 
Jackson m...@mimc.co.uk
+hammerhead   avr32   -  e36930762015-06-10  Alex 
Raimondi alex.raimo...@miromico.ch
+favr-32-ezkitavr32   -  9eb45aab2015-06-10  
Hans-Christian Egtvedt hans-christian.egtv...@atmel.com
 afeb9260 arm arm926ejs  f6b42c142015-05-13  Sergey 
Lapin sla...@ossfans.org
 tny_a9260arm arm926ejs  f6b42c142015-05-13  Albin 
Tonnerre albin.tonne...@free-electrons.com
 sbc35_a9g20  arm arm926ejs  f6b42c142015-05-13  Albin 
Tonnerre albin.tonne...@free-electrons.com
-- 
1.9.1

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[U-Boot] [PATCH] blackfin: fix undefined reference to srand and rand

Commit 9ba9e85f3f1c (net: Fix NET_RANDOM_ETHADDR dependencies)
accidentally dropped CONFIG_LIB_RAND defines for 14 Blackfin boards.

Prior to that commit, those boards defined CONFIG_LIB_RAND, but not
CONFIG_NET_RANDOM_ETHADDR.  So, commit 9ba9e85f3f1c should not have
touched them, but in fact it ripped CONFIG_LIB_RAND off from all the
header files, which caused undefined reference to srand and rand.
CONFIG_LIB_RAND=y must be revived for such boards.

BTW, this commit indeed makes it better, but even with this fix,
three boards (bf533-stamp, bf538f-ezkit, cm-bf548) still can not
build due to region 'ram' overflowed error.  This was cause by
commit 6eed3786c68c (net: Move the CMD_NET config to defconfigs)
because CMD_NET selects NET, and NET selects REGEX.  Eventually,
some boards were newly enabled with CONFIG_REGEX, increasing the
memory footprint.  A patch is expected to fix the build error.

Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---

 configs/bf527-ezkit-v2_defconfig | 1 +
 configs/bf533-ezkit_defconfig| 1 +
 configs/bf533-stamp_defconfig| 1 +
 configs/bf538f-ezkit_defconfig   | 1 +
 configs/bf548-ezkit_defconfig| 1 +
 configs/bf561-acvilon_defconfig  | 1 +
 configs/bf561-ezkit_defconfig| 1 +
 configs/bf609-ezkit_defconfig| 1 +
 configs/br4_defconfig| 1 +
 configs/cm-bf533_defconfig   | 1 +
 configs/cm-bf548_defconfig   | 1 +
 configs/cm-bf561_defconfig   | 1 +
 configs/ibf-dsp561_defconfig | 1 +
 configs/pr1_defconfig| 1 +
 lib/Kconfig  | 4 +++-
 15 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig
index f963502..dd48d6a 100644
--- a/configs/bf527-ezkit-v2_defconfig
+++ b/configs/bf527-ezkit-v2_defconfig
@@ -3,3 +3,4 @@ CONFIG_TARGET_BF527_EZKIT=y
 CONFIG_SYS_EXTRA_OPTIONS=BF527_EZKIT_REV_2_1
 CONFIG_CMD_NET=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+CONFIG_LIB_RAND=y
diff --git a/configs/bf533-ezkit_defconfig b/configs/bf533-ezkit_defconfig
index 66c1145..04210d8 100644
--- a/configs/bf533-ezkit_defconfig
+++ b/configs/bf533-ezkit_defconfig
@@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF533_EZKIT=y
 CONFIG_CMD_NET=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+CONFIG_LIB_RAND=y
diff --git a/configs/bf533-stamp_defconfig b/configs/bf533-stamp_defconfig
index ca1202d..191e2d6 100644
--- a/configs/bf533-stamp_defconfig
+++ b/configs/bf533-stamp_defconfig
@@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF533_STAMP=y
 CONFIG_CMD_NET=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+CONFIG_LIB_RAND=y
diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig
index 84449ec..f8ae21b 100644
--- a/configs/bf538f-ezkit_defconfig
+++ b/configs/bf538f-ezkit_defconfig
@@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF538F_EZKIT=y
 CONFIG_CMD_NET=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+CONFIG_LIB_RAND=y
diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig
index 46c8fe2..6bd9e9b 100644
--- a/configs/bf548-ezkit_defconfig
+++ b/configs/bf548-ezkit_defconfig
@@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF548_EZKIT=y
 CONFIG_CMD_NET=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+CONFIG_LIB_RAND=y
diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig
index b558066..7a65892 100644
--- a/configs/bf561-acvilon_defconfig
+++ b/configs/bf561-acvilon_defconfig
@@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF561_ACVILON=y
 CONFIG_CMD_NET=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+CONFIG_LIB_RAND=y
diff --git a/configs/bf561-ezkit_defconfig b/configs/bf561-ezkit_defconfig
index 0ef1a1c..e8a1ea4 100644
--- a/configs/bf561-ezkit_defconfig
+++ b/configs/bf561-ezkit_defconfig
@@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF561_EZKIT=y
 CONFIG_CMD_NET=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+CONFIG_LIB_RAND=y
diff --git a/configs/bf609-ezkit_defconfig b/configs/bf609-ezkit_defconfig
index 72e0606..d8c2629 100644
--- a/configs/bf609-ezkit_defconfig
+++ b/configs/bf609-ezkit_defconfig
@@ -3,3 +3,4 @@ CONFIG_NETDEVICES=y
 CONFIG_TARGET_BF609_EZKIT=y
 CONFIG_CMD_NET=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_LIB_RAND=y
diff --git a/configs/br4_defconfig b/configs/br4_defconfig
index e6970a4..7247b9c 100644
--- a/configs/br4_defconfig
+++ b/configs/br4_defconfig
@@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_BR4=y
 CONFIG_CMD_NET=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+CONFIG_LIB_RAND=y
diff --git a/configs/cm-bf533_defconfig b/configs/cm-bf533_defconfig
index 42d568e..89a5c0f 100644
--- a/configs/cm-bf533_defconfig
+++ b/configs/cm-bf533_defconfig
@@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF533=y
 CONFIG_CMD_NET=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+CONFIG_LIB_RAND=y
diff --git a/configs/cm-bf548_defconfig b/configs/cm-bf548_defconfig
index 906a9bd..b9b6044 100644
--- a/configs/cm-bf548_defconfig
+++ b/configs/cm-bf548_defconfig
@@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF548=y

[U-Boot] [PATCH] common/cmd_bdinfo: show gd-board_type

2015-06-11 Thread Hannes Schmelzer

sometimes it is usefull to know if board-detection has
written the correct value into gd-board_type.

For this we add some output to the bdinfo command.

Signed-off-by: Hannes Schmelzer oe5...@oevsv.at

---

 common/cmd_bdinfo.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index f16d5c7..ed3b935 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -400,6 +400,9 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
printf(DSP frequency = %ld MHz\n, gd-bd-bi_dsp_freq);
printf(DDR frequency = %ld MHz\n, gd-bd-bi_ddr_freq);
 #endif
+#ifdef CONFIG_BOARD_TYPES
+   printf(Board Type  = %ld\n, gd-board_type);
+#endif
return 0;
 }
 
-- 
2.1.4

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Re: [U-Boot] [PATCH v2 22/22] x86: Add support for Intel Minnowboard Max

2015-06-11 Thread Andrew Bradford

Hi Simon,

On 05/28 10:30, Simon Glass wrote:
Hi Andrew,

On 27 May 2015 at 08:39, Andrew Bradford and...@bradfordembedded.com wrote:
On 05/27 13:19, Bin Meng wrote:
Hi Simon,

-8--

I just noticed that Intel has released FSP specification v1.1 [1] in
April. After a rough read of the 1.1 spec, it looks to me that Intel
changed the fsp_init() design by breaking it down into 3 sub-routines:
FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might
be more logical to adapt U-Boot, but again I am not sure if the stack
migration stuff is still there. So far I don't see any new FSP
releases using the 1.1 spec.

[1]
https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-architecture-spec-v1-1.html

There's also a very good overview of how to use an FSP v1.1 firmware at
[1]. It states that the problem in v1.0 for bootloaders was that when
you call FspInit() that temporary ram was torn down unconditionally.
Now, in v1.1, it says after calling FspMemoryInit() that control will be
given back to the bootloader running in the temporary ram (CAR?). Then
the bootloader is responsible for migrating to main memory and to call
TempRamExit() so that temporary memory can be cleaned up.

This sounds like what u-boot would want and what Simon described above,
for u-boot to be in charge of relocating from CAR to main memory, right?
If so, likely things will be much easier once there's a v1.1 FSP for
baytrail...

Indeed, care to ping them to find out when this might happen?

It seems like there are no current plans to implement an FSP v1.1 compliant
firmware release for Bay Trail [1], which is unfortunate.

[1]:https://embedded.communities.intel.com/thread/8218

I will continue to pester my contacts at Intel.

Thanks,
Andrew
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Re: [U-Boot] Please pull u-boot-sunxi master

2015-06-11 Thread Tom Rini

On Thu, Jun 11, 2015 at 03:44:10PM +0200, Hans de Goede wrote:
 Hi,
 
 On 11-06-15 14:56, Tom Rini wrote:
 On Thu, Jun 11, 2015 at 09:41:29AM +0200, Hans de Goede wrote:
 Hi,
 
 On 11-06-15 04:49, Simon Glass wrote:
 Hi,
 
 On 10 June 2015 at 08:56, Tom Rini tr...@konsulko.com wrote:
 On Wed, Jun 10, 2015 at 04:54:50PM +0200, Hans de Goede wrote:
 
 Hi Tom,
 
 Please pull u-boot-sunxi/master into master for 2 small bug-fixes:
 
 The following changes since commit 
 3d0158ae18bef2ac89979f4c90419d3add436c71:
 
Prepare v2015.07-rc2 (2015-06-08 17:48:33 -0400)
 
 are available in the git repository at:
 
http://git.denx.de/u-boot-sunxi.git master
 
 for you to fetch changes up to 0751b138064db28f0866f0c2439afb8b3975180c:
 
sunxi: Enable CONFIG_SYS_64BIT_LBA when AHCI is used (2015-06-10 
  16:52:12 +0200)
 
 
 Applied to u-boot/master, thanks!
 
 I don't see this patch on the mailing list or I would reply there.
 
 Hmm, I asked the submitter to Cc the list when he suggested this patch on 
 irc,
 I guess he only send it to me and I did not notice.
 
 But for my toolchain I get errors:
 
 crosfw -b Orangepi_mini -w
 #
 # configuration written to .config
 #
 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/arm-linux-gnueabihf-ld.bfd:
 error: 
 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/../lib/gcc/arm-linux-gnueabihf/4.8.2/libgcc.a(bpabi.o)
 uses VFP register arguments, u-boot does not
 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/arm-linux-gnueabihf-ld.bfd:
 failed to merge target specific data of file
 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/../lib/gcc/arm-linux-gnueabihf/4.8.2/libgcc.a(bpabi.o)
 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/arm-linux-gnueabihf-ld.bfd:
 error: 
 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/../lib/gcc/arm-linux-gnueabihf/4.8.2/libgcc.a(_divdi3.o)
 uses VFP register arguments, u-boot does not
 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/arm-linux-gnueabihf-ld.bfd:
 failed to merge target specific data of file
 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/../lib/gcc/arm-linux-gnueabihf/4.8.2/libgcc.a(_divdi3.o)
 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/arm-linux-gnueabihf-ld.bfd:
 error: 
 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/../lib/gcc/arm-linux-gnueabihf/4.8.2/libgcc.a(_udivdi3.o)
 uses VFP register arguments, u-boot does not
 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/arm-linux-gnueabihf-ld.bfd:
 failed to merge target specific data of file
 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/../lib/gcc/arm-linux-gnueabihf/4.8.2/libgcc.a(_udivdi3.o)
 make[1]: *** [u-boot] Error 1
 make[1]: *** Waiting for unfinished jobs
 
 I'm not sure what todo about this, it works for me, and supporting disks
 larger then 2TB seems like a desirable feature in this time and age.
 
 Ug.  Yes, but you have to use do_div and friends and we've got another
 case where something snuck past not using those helpers.  I forget the
 right incantation to use on either nm or objdump to figure out just
 which function/file is doing it wrong.
 
 Ok, so hopefully someone reading the list remembers and can provide us with a 
 list of
 culprits. I can probably make some time to fix this even if the problem is 
 not in sunxi
 code (all the commit does is enable CONFIG_SYS_64BIT_LBA which AFAIK does not 
 directly
 influence any sunxi code).
 
 So for now lets keep this in master and try to get it fixed, if it is not 
 fixed in say
 2 rc-s from now then we should probably revert the sunxi commit (and break 
 large
 disks again).
 

OK, so I dug out the magic again (since there's a few other boards that
fail on different toolchain with the same type of problem but another
place).
First:
$ arm-linux-gnueabihf-nm 
/opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.10_linux/bin/../lib/gcc/arm-linux-gnueabihf/4.8.2/libgcc.a
 | grep -A 4 _udivdi3.o
This will show you all of the functions provided there.
Second:
$ for F in `find output-dir -name *.o`;do arm-linux-gnueabihf-nm $F 21
| grep -q THATSYMBOL  echo $F;done

This will show you what object files have the function in question.
Third: 
arm-linux-gnueabihf-objdump -d ONE/OBJ/FILE.o | $PAGER
And hunt around for what function(s) here are calling the incorrect math
function.
Fourth: Examine the C in question until you spot the bad division,
correct to use a helper from include/linux/math64.h (and yes we have
some other helpers too that are home grown but I am in favor of using
the kernel ones).

-- 
Tom


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Re: [U-Boot] MinnowBoard Max uboot

2015-06-11 Thread Beaman, Thomas

Hi Simon,

I have enclosed both kernel boot files

Thanks,
Tom

-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Wednesday, June 10, 2015 9:15 PM
To: Beaman, Thomas
Cc: u-boot@lists.denx.de
Subject: Re: MinnowBoard Max uboot

Hi Thomas,

On 10 June 2015 at 12:38, Beaman, Thomas thomas.bea...@xerox.com wrote:
 Hi Simon,

 I have just picked up u-boot-2015.07-rc2 with your support for multiple CPUs 
 on the minnowboard max. I can see using the uboot cpu list command that both 
 CPUs now show up.  But the kernel does not see 2 CPUs in /proc/cpuinfo. If I 
 boot the same kernel using an EFI BIOS I do see 2 CPUs in /proc/cpuinfo. Is 
 there some uboot to kernel hand off I do not have configured properly ? I am 
 not sure how the number of CPUs gets transferred from the boot to the kernel.

 Thanks for any input you may have.
 Tom

 = cpu list
   0: cpu@0  Intel(R) Atom(TM) CPU  E3825  @ 1.33GHz
   1: cpu@1  Intel(R) Atom(TM) CPU  E3825  @ 1.33GHz

 ## minnow max when booted from uboot 2015-07.rc2 root@atom_230:~# cat 
 /proc/cpuinfo | grep processor
 processor   : 0

 ## minnow max when booted from BIOS
 root@atom_230:~# cat /proc/cpuinfo | grep processor
 processor   : 0
 processor   : 1

Do you have the output from the kernel boot please?

Regards,
Simon




 -Original Message-
 From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
 Sent: Tuesday, March 10, 2015 1:21 PM
 To: Beaman, Thomas
 Cc: u-boot@lists.denx.de; Bin Meng; gabriel huau
 Subject: Re: MinnowBoard Max uboot

 Hi Tom,

 On 10 March 2015 at 05:24, Beaman, Thomas thomas.bea...@xerox.com wrote:
 Hi Simon,

 Do you know what will be the timeframe of when someone may be able to 
 look at this in more detail. I will be able to help test any updates 
 if needed


 I will take a look once I have things lined up for the next release, likely 
 mid April.

 Regards,
 Simon

 Thanks,
 Tom

 -Original Message-
 From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
 Sent: Monday, March 09, 2015 11:49 AM
 To: Beaman, Thomas
 Cc: u-boot@lists.denx.de; Bin Meng; gabriel huau
 Subject: Re: MinnowBoard Max uboot

 +Bin and Gabriel

 Hi Tom,

 On 9 March 2015 at 08:08, Beaman, Thomas thomas.bea...@xerox.com wrote:


 Hi Simon,



 I see you have put support for the MinnowBoard Max in the u-boot mainline.
 Thanks this is a very useful addition.  I have been able to follow 
 your readme and build a working bare metal uboot. Using the built 
 uboot I can load and bring up a Linux Kernel.



 What I noticed from the running kernel is that only one of the two 
 cores on the E3825 is running. In the power PC uboots I usually see 
 a section for the multiple cores in the .dts file. My questions is 
 how do I get both CPUs running on this board. Is it a uboot .dts 
 file setup that will enable this, or is something in the kernel start up 
 that does this.



 As a test I boot the same kernel using the EFI BIOS on the minnow 
 board and both CPUs are running.



 Any suggestions or comments you have would be welcomed.



 My guess is that the LAPIC CPU start-up is missing. It isn't 100% clear what 
 the FSP does and does not do, but perhaps it does not do that.

 I did make something of a start on this with ivybridge but it isn't 
 complete, and it seems to be needed here.

 Regards,
 Simon




  Booting `minnow max'

error: no suitable video mode found.
Booting in blind mode
Initializing cgroup subsys cpuset
Initializing cgroup subsys cpu
Initializing cgroup subsys cpuacct
Linux version 3.10.55-ltsi-WR6.0.0.16_standard (tbeaman@varelse) (gcc version 
4.8.1 (Wind River Linux Sourcery CodeBench 4.8-40) ) #1 SMP PREEMPT Thu Feb 19 
15:50:54 EST 2015
Command line: BOOT_IMAGE=(memdisk)/boot/grub/netboot.bzImage 
console=ttyS0,115200n8 ramdisk_size=30
KERNEL supported cpus:
  Intel GenuineIntel
  AMD AuthenticAMD
  Centaur CentaurHauls
e820: BIOS-provided physical RAM map:
BIOS-e820: [mem 0x-0x0008efff] usable
BIOS-e820: [mem 0x0008f000-0x0008] ACPI NVS
BIOS-e820: [mem 0x0009-0x0009dfff] usable
BIOS-e820: [mem 0x0009e000-0x0009] reserved
BIOS-e820: [mem 0x0010-0x1fff] usable
BIOS-e820: [mem 0x2000-0x200f] reserved
BIOS-e820: [mem 0x2010-0x79c64fff] usable
BIOS-e820: [mem 0x79c65000-0x7a490fff] reserved
BIOS-e820: [mem 0x7a491000-0x7a590fff] ACPI NVS
BIOS-e820: [mem 0x7a591000-0x7a5d0fff] ACPI data
BIOS-e820: [mem 0x7a5d1000-0x7aff] usable
BIOS-e820: [mem 0xe00f8000-0xe00f8fff] reserved
BIOS-e820: [mem 0xfed01000-0xfed01fff] reserved
NX (Execute Disable) protection: active
efi: EFI v2.40 by EDK II
efi:  ACPI=0x7a5d  ACPI 2.0=0x7a5d0014  SMBIOS=0x79c8c000
efi: mem00: type=7,

[U-Boot] [PATCH 08/10] drivers/net/vsc9953: Add VLAN commands for VSC9953

2015-06-11 Thread Codrin Ciubotariu

The new added commands can be used to configure VLANs for a port
on both ingress and egress.

The new commands are:
ethsw [port port_no] pvid { [help] | show | pvid }
 - set/show PVID (ingress and egress VLAN tagging) for a port;
ethsw [port port_no] vlan { [help] | show | add vid | del vid }
 - add a VLAN to a port (VLAN members);
ethsw [port port_no] untagged { [help] | show | all | none | pvid }
 - set egress tagging mod for a port
ethsw [port port_no] egress tag { [help] | show | pvid | classified }
 - Configure VID source for egress tag. Tag's VID could be the
   frame's classified VID or the PVID of the port

Signed-off-by: Johnson Leung johnson.le...@freescale.com
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
Change-Id: If55943254f6f865d4bc2e18a4ab0620ab787fbc1
---
 drivers/net/vsc9953.c | 678 +-
 include/vsc9953.h |   3 +
 2 files changed, 680 insertions(+), 1 deletion(-)

diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c
index ef7b50c..b78a941 100644
--- a/drivers/net/vsc9953.c
+++ b/drivers/net/vsc9953.c
@@ -270,6 +270,31 @@ static void vsc9953_port_vlan_pvid_set(int port_no, int 
pvid)
field_set(pvid, CONFIG_VSC9953_PORT_VLAN_CFG_VID_MASK));
 }
 
+#ifdef CONFIG_VSC9953_CMD
+/* Set PVID for a VSC9953 port */
+static int vsc9953_port_vlan_pvid_get(int port_nr, int *pvid)
+{
+   u32 val;
+   struct vsc9953_analyzer *l2ana_reg;
+
+   /* Administrative down */
+   if ((!vsc9953_l2sw.port[port_nr].enabled)) {
+   printf(Port %d is administrative down\n, port_nr);
+   return -1;
+   }
+
+   l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+   VSC9953_ANA_OFFSET);
+
+   /* Get ingress PVID */
+   val = in_le32(l2ana_reg-port[port_nr].vlan_cfg);
+   *pvid = field_get(val  CONFIG_VSC9953_VLAN_CFG_VID_MASK,
+ CONFIG_VSC9953_VLAN_CFG_VID_MASK);
+
+   return 0;
+}
+#endif
+
 static void vsc9953_port_all_vlan_pvid_set(int pvid)
 {
int i;
@@ -407,6 +432,75 @@ static void vsc9953_port_vlan_egr_untag_set(int port_no,
}
 }
 
+#ifdef CONFIG_VSC9953_CMD
+/* Get egress tagging configuration for a VSC9953 port */
+static int vsc9953_port_vlan_egr_untag_get(int port_no,
+  enum egress_untag_mode *mode)
+{
+   u32 val;
+   struct vsc9953_rew_reg  *l2rew_reg;
+
+   /* Administrative down */
+   if ((!vsc9953_l2sw.port[port_no].enabled)) {
+   printf(Port %d is administrative down\n, port_no);
+   return -1;
+   }
+
+   l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET +
+   VSC9953_REW_OFFSET);
+
+   val = in_le32(l2rew_reg-port[port_no].port_tag_cfg);
+
+   switch (val  CONFIG_VSC9953_TAG_CFG_MASK) {
+   case CONFIG_VSC9953_TAG_CFG_NONE:
+   *mode = EGRESS_UNTAG_ALL;
+   return 0;
+   case CONFIG_VSC9953_TAG_CFG_ALL_PVID_ZERO:
+   *mode = EGRESS_UNTAG_PVID_AND_ZERO;
+   return 0;
+   case CONFIG_VSC9953_TAG_CFG_ALL_ZERO:
+   *mode = EGRESS_UNTAG_ZERO;
+   return 0;
+   case CONFIG_VSC9953_TAG_CFG_ALL:
+   *mode = EGRESS_UNTAG_NONE;
+   return 0;
+   default:
+   printf(Unknown egress tagging configuration for port %d\n,
+  port_no);
+   return -1;
+   }
+}
+
+/* Shiw egress tagging configuration for a VSC9953 port */
+static void vsc9953_port_vlan_egr_untag_show(int port_no)
+{
+   enum egress_untag_mode mode;
+
+   if (vsc9953_port_vlan_egr_untag_get(port_no, mode)) {
+   printf(%7d\t%17s\n, port_no, -);
+   return;
+   }
+
+   printf(%7d\t, port_no);
+   switch (mode) {
+   case EGRESS_UNTAG_ALL:
+   printf(%17s\n, none);
+   break;
+   case EGRESS_UNTAG_NONE:
+   printf(%17s\n, all);
+   break;
+   case EGRESS_UNTAG_PVID_AND_ZERO:
+   printf(%17s\n, all but PVID and 0);
+   break;
+   case EGRESS_UNTAG_ZERO:
+   printf(%17s\n, all but 0);
+   break;
+   default:
+   printf(%17s\n, -);
+   }
+}
+#endif
+
 static void vsc9953_port_all_vlan_egress_untagged_set(
enum egress_untag_mode mode)
 {
@@ -954,6 +1048,102 @@ static void vsc9953_port_statistics_clear(int port_no)
 CONFIG_VSC9953_STAT_CLEAR_DR);
 }
 
+/* Add/remove a port to/from a VLAN */
+static void vsc9953_vlan_table_membership_set(int vid, u32 port_no, u8 add)
+{
+   struct vsc9953_analyzer *l2ana_reg;
+
+   l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+   VSC9953_ANA_OFFSET);
+
+   if (!vsc9953_vlan_table_poll_idle()) {
+

Re: [U-Boot] [PATCH] net: davinci_emac: don't teardown inactive rx channel

Hi Jeroen,

On Thu, Jun 11, 2015 at 12:51 AM, Tony Lindgren t...@atomide.com wrote:
 * Joe Hershberger joe.hershber...@gmail.com [150610 07:26]:
 Hi Jeroen,

 On Sun, Jun 7, 2015 at 10:30 AM, Jeroen Hofstee jer...@myspectrum.nl wrote:
  Tearing down an unitialized rx channel causes a pending address hole
  event to be queued. When booting linux it will report this pending
  as something like Address Hole seen by USB_OTG  at address 57fff584,
  since u-boot did not handled this interrupt. Prevent that by not
  tearing down the rx channel, when not receiving.
 
  Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl
  ---
  To replicate this:
   - ROMcode must not use the emac
   - U-Boot must use the emac
   - only on cold start
  ---

 I don't know the hardware, but it sounds like a reasonable
 explanation. Look good to you, Tony?

 Sure.

 Tony

OK, I'll pull this into u-boot-net.

Cheers,
-Joe
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Re: [U-Boot] [PATCH] sunxi: Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default

Hi Tom,

On Wed, Jun 3, 2015 at 5:12 PM, Tom Rini tr...@konsulko.com wrote:
 On Wed, Jun 03, 2015 at 08:12:16PM +0200, Hans de Goede wrote:

 Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then
 needing to have this in every sunxi defconfig file.

 This also fixes the Merrii_A80_Optimus defconfig no longer building.

 Cc: Maxin B. John maxin.j...@enea.com
 Reported-by: Maxin B. John maxin.j...@enea.com
 Signed-off-by: Hans de Goede hdego...@redhat.com

 Joe? Masahiro?  It feels like something has gone wrong with the
 conversion here.  Or do people need to get used to the defconfig files
 being a non-trivial size?  Or do we need some more default y if ...
 lines around things?  Or a few of the above?  Thanks!

I'm surprised you pulled this in for -rc2. I guess we can always revert it.

-Joe
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[U-Boot] [PATCH 01/10] drivers/net/vsc9953: Cleanup patch

2015-06-11 Thread Codrin Ciubotariu

This patch groups some macros defined for registers and
replaces some magic numbers from vsc9953 with macros. Also,
port and port_nr keywords are replaced with port_no.

Also, in some places, this patch replaces in_le32 and out_le32
with clrbits_le32 and setbits_le32 to reduce the number of code
lines and to assure that only intended bits of a register are
changed.

Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
Change-Id: Ib5f7d94bd6a39b909bf7b70bb12e15156a7e45c9
---
 drivers/net/vsc9953.c | 100 +-
 include/vsc9953.h |  47 
 2 files changed, 88 insertions(+), 59 deletions(-)

diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c
index fed7358..720ae47 100644
--- a/drivers/net/vsc9953.c
+++ b/drivers/net/vsc9953.c
@@ -25,44 +25,44 @@ static struct vsc9953_info vsc9953_l2sw = {
.port[9] = VSC9953_PORT_INFO_INITIALIZER(9),
 };
 
-void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus)
+void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus)
 {
-   if (!VSC9953_PORT_CHECK(port))
+   if (!VSC9953_PORT_CHECK(port_no))
return;
 
-   vsc9953_l2sw.port[port].bus = bus;
+   vsc9953_l2sw.port[port_no].bus = bus;
 }
 
-void vsc9953_port_info_set_phy_address(int port, int address)
+void vsc9953_port_info_set_phy_address(int port_no, int address)
 {
-   if (!VSC9953_PORT_CHECK(port))
+   if (!VSC9953_PORT_CHECK(port_no))
return;
 
-   vsc9953_l2sw.port[port].phyaddr = address;
+   vsc9953_l2sw.port[port_no].phyaddr = address;
 }
 
-void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int)
+void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int)
 {
-   if (!VSC9953_PORT_CHECK(port))
+   if (!VSC9953_PORT_CHECK(port_no))
return;
 
-   vsc9953_l2sw.port[port].enet_if = phy_int;
+   vsc9953_l2sw.port[port_no].enet_if = phy_int;
 }
 
-void vsc9953_port_enable(int port)
+void vsc9953_port_enable(int port_no)
 {
-   if (!VSC9953_PORT_CHECK(port))
+   if (!VSC9953_PORT_CHECK(port_no))
return;
 
-   vsc9953_l2sw.port[port].enabled = 1;
+   vsc9953_l2sw.port[port_no].enabled = 1;
 }
 
-void vsc9953_port_disable(int port)
+void vsc9953_port_disable(int port_no)
 {
-   if (!VSC9953_PORT_CHECK(port))
+   if (!VSC9953_PORT_CHECK(port_no))
return;
 
-   vsc9953_l2sw.port[port].enabled = 0;
+   vsc9953_l2sw.port[port_no].enabled = 0;
 }
 
 static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr,
@@ -148,21 +148,21 @@ static int init_phy(struct eth_device *dev)
return 0;
 }
 
-static int vsc9953_port_init(int port)
+static int vsc9953_port_init(int port_no)
 {
struct eth_device   *dev;
 
/* Internal ports never have a PHY */
-   if (VSC9953_INTERNAL_PORT_CHECK(port))
+   if (VSC9953_INTERNAL_PORT_CHECK(port_no))
return 0;
 
/* alloc eth device */
dev = (struct eth_device *)calloc(1, sizeof(struct eth_device));
if (!dev)
-   return 1;
+   return -1;
 
-   sprintf(dev-name, SW@PORT%d, port);
-   dev-priv = vsc9953_l2sw.port[port];
+   sprintf(dev-name, SW@PORT%d, port_no);
+   dev-priv = vsc9953_l2sw.port[port_no];
dev-init = NULL;
dev-halt = NULL;
dev-send = NULL;
@@ -170,7 +170,7 @@ static int vsc9953_port_init(int port)
 
if (init_phy(dev)) {
free(dev);
-   return 1;
+   return -1;
}
 
return 0;
@@ -255,8 +255,8 @@ void vsc9953_init(bd_t *bis)
out_le32(l2dev_gmii_reg-mac_cfg_status.mac_hdx_cfg, hdx_cfg);
out_le32(l2sys_reg-sys.front_port_mode[i],
 CONFIG_VSC9953_FRONT_PORT_MODE);
-   out_le32(l2qsys_reg-sys.switch_port_mode[i],
-CONFIG_VSC9953_PORT_ENA);
+   setbits_le32(l2qsys_reg-sys.switch_port_mode[i],
+CONFIG_VSC9953_PORT_ENA);
out_le32(l2dev_gmii_reg-mac_cfg_status.mac_maxlen_cfg,
 CONFIG_VSC9953_MAC_MAX_LEN);
out_le32(l2sys_reg-pause_cfg.pause_cfg[i],
@@ -312,25 +312,23 @@ void vsc9953_init(bd_t *bis)
 
 #ifdef CONFIG_VSC9953_CMD
 /* Enable/disable status of a VSC9953 port */
-static void vsc9953_port_status_set(int port_nr, u8 enabled)
+static void vsc9953_port_status_set(int port_no, u8 enabled)
 {
-   u32 val;
struct vsc9953_qsys_reg *l2qsys_reg;
 
/* Administrative down */
-   if (vsc9953_l2sw.port[port_nr].enabled == 0)
+   if (!vsc9953_l2sw.port[port_no].enabled)
return;
 
l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
VSC9953_QSYS_OFFSET);
 
-   val =

Re: [U-Boot] [PATCH] blackfin: fix undefined reference to srand and rand

Hi Masahiro-san,

On Thu, Jun 11, 2015 at 5:16 AM, Masahiro Yamada
yamada.masah...@socionext.com wrote:
 Commit 9ba9e85f3f1c (net: Fix NET_RANDOM_ETHADDR dependencies)
 accidentally dropped CONFIG_LIB_RAND defines for 14 Blackfin boards.

 Prior to that commit, those boards defined CONFIG_LIB_RAND, but not
 CONFIG_NET_RANDOM_ETHADDR.  So, commit 9ba9e85f3f1c should not have
 touched them, but in fact it ripped CONFIG_LIB_RAND off from all the
 header files, which caused undefined reference to srand and rand.
 CONFIG_LIB_RAND=y must be revived for such boards.

 BTW, this commit indeed makes it better, but even with this fix,
 three boards (bf533-stamp, bf538f-ezkit, cm-bf548) still can not
 build due to region 'ram' overflowed error.  This was cause by
 commit 6eed3786c68c (net: Move the CMD_NET config to defconfigs)
 because CMD_NET selects NET, and NET selects REGEX.  Eventually,
 some boards were newly enabled with CONFIG_REGEX, increasing the
 memory footprint.  A patch is expected to fix the build error.

 Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
 ---

This is surprising. I would have expected moveconfig.py to take care
of this... but I guess since the LIB_RAND option was not selectable it
only dropped the headers and did not add it to the defconfigs. I guess
there's a lesson to learn there about how to use the tool... making
sure to make the option selectable when running it, and only making it
hidden if nothing selects it. I should have have thought of that when
cleaning up Michal's patch. Apologies.

Acked-by: Joe Hershberger joe.hershber...@ni.com

Thanks,
-Joe
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Re: [U-Boot] [PATCH] blackfin: fix undefined reference to srand and rand

2015-06-11 23:25 GMT+09:00 Joe Hershberger joe.hershber...@gmail.com:
 Hi Masahiro-san,

 On Thu, Jun 11, 2015 at 5:16 AM, Masahiro Yamada
 yamada.masah...@socionext.com wrote:
 Commit 9ba9e85f3f1c (net: Fix NET_RANDOM_ETHADDR dependencies)
 accidentally dropped CONFIG_LIB_RAND defines for 14 Blackfin boards.

 Prior to that commit, those boards defined CONFIG_LIB_RAND, but not
 CONFIG_NET_RANDOM_ETHADDR.  So, commit 9ba9e85f3f1c should not have
 touched them, but in fact it ripped CONFIG_LIB_RAND off from all the
 header files, which caused undefined reference to srand and rand.
 CONFIG_LIB_RAND=y must be revived for such boards.

 BTW, this commit indeed makes it better, but even with this fix,
 three boards (bf533-stamp, bf538f-ezkit, cm-bf548) still can not
 build due to region 'ram' overflowed error.  This was cause by
 commit 6eed3786c68c (net: Move the CMD_NET config to defconfigs)
 because CMD_NET selects NET, and NET selects REGEX.  Eventually,
 some boards were newly enabled with CONFIG_REGEX, increasing the
 memory footprint.  A patch is expected to fix the build error.

 Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
 ---

 This is surprising. I would have expected moveconfig.py to take care
 of this... but I guess since the LIB_RAND option was not selectable it
 only dropped the headers and did not add it to the defconfigs. I guess
 there's a lesson to learn there about how to use the tool... making
 sure to make the option selectable when running it, and only making it
 hidden if nothing selects it. I should have have thought of that when
 cleaning up Michal's patch. Apologies.


Another lesson to learn:
Please do build test before sending/applying a patch.


-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH] sunxi: Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default