Re: [PATCH] Actions: S700 Calculate SDRAM size

[Manivannan Sadhasivam]

On Sat, May 02, 2020 at 06:55:20PM +0530, Amit Singh Tomar wrote:
> Calculate the SDRAM size from DDR capacity register registers instead of using
> hard-coded value. This is quite useful to get correct size on differnt boards
> based on S700 SoC.
> 
> There is no documentation available that talks about DDR registers, and this
> is very much taken from vendor source.
> 
> This commit lets Linux boot on Cubieboard7-lite (based on S700).
> 
> Signed-off-by: Amit Singh Tomar 
> ---
> There is bit of a story about it:
>  
> Wasn't really aware that working on a board (CubieBoard7-Lite) that actually
> has only 1GB of RAM untill I see the Kernel crash[1], and DDR size is
> hard-coded to 2GB(as CubieBoard7 comes with 2 GB). With this set-up Kernel
> was trying to access the memory that doesn't exist leads to the crash.
> 
> [1]:
>  
> Starting kernel ...
> 
> [0.00] Booting Linux on physical CPU 0x00 [0x410fd034]
> [0.00] Linux version 5.6.0-rc6-00012-g7080a8a-dirty 
> (amit@amit-ThinkPad-X230) (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 
> revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) 
> #10 SMP PREEMPT Fri Mar 27 21:52:07 IST 2020
> [0.00] Machine model: CubieBoard7
> [0.00] earlycon: owl0 at MMIO 0xe0126000 (options '')
> [0.00] printk: bootconsole [owl0] enabled
> [0.00] efi: Getting EFI parameters from FDT:
> [0.00] efi: UEFI not found.
> [0.00] cma: Reserved 32 MiB at 0x7e00
> [0.00] NUMA: No NUMA configuration found
> [0.00] NUMA: Faking a node at [mem 
> 0x-0x7fff]
> [0.00] NUMA: NODE_DATA [mem 0x7dbfb100-0x7dbfcfff]
> [0.00] Zone ranges:
> [0.00]   DMA  [mem 0x-0x3fff]
> [0.00]   DMA32[mem 0x4000-0x7fff]
> [0.00]   Normal   empty
> [0.00] Movable zone start for each node
> [0.00] Early memory node ranges
> [0.00]   node   0: [mem 0x-0x1eff]
> [0.00]   node   0: [mem 0x2000-0x7fff]
> [0.00] Initmem setup node 0 [mem 
> 0x-0x7fff]
> [0.00] psci: probing for conduit method from DT.
> [0.00] psci: PSCIv0.2 detected in firmware.
> [0.00] psci: Using standard PSCI v0.2 function IDs
> [0.00] psci: Trusted OS migration not required
> [0.00] percpu: Embedded 23 pages/cpu s53272 r8192 d32744 u94208
> [0.00] Detected VIPT I-cache on CPU0
> [0.00] CPU features: detected: ARM erratum 845719
> [0.00] Built 1 zonelists, mobility grouping on.  Total pages: 512000
> [0.00] Policy zone: DMA32
> [0.00] Kernel command line: console=ttyOWL,115200 
> earlycon=owl,0xe0126000 root=/dev/mmcblk0p2
> [0.00] Dentry cache hash table entries: 262144 (order: 9, 2097152 
> bytes, linear)
> [0.00] Inode-cache hash table entries: 131072 (order: 8, 1048576 
> bytes, linear)
> [0.00] mem auto-init: stack:off, heap alloc:off, heap free:off
> [0.00] Unable to handle kernel paging request at virtual address 
> 3de18000
> [0.00] Mem abort info:
> [0.00]   ESR = 0x9647
> [0.00]   EC = 0x25: DABT (current EL), IL = 32 bits
> [0.00]   SET = 0, FnV = 0
> [0.00]   EA = 0, S1PTW = 0
> [0.00] Data abort info:
> [0.00]   ISV = 0, ISS = 0x0047
> [0.00]   CM = 0, WnR = 1
> [0.00] swapper pgtable: 4k pages, 48-bit VAs, pgdp=01399000
>   
> ---
>  arch/arm/mach-owl/soc.c | 23 +++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c
> index 409cbd3..f63f1a8 100644
> --- a/arch/arm/mach-owl/soc.c
> +++ b/arch/arm/mach-owl/soc.c
> @@ -13,15 +13,38 @@
>  #include 
>  #include 
>  
> +#define DMM_INTERLEAVE_PER_CH_CFG   (0xe0290028)
> +
>  DECLARE_GLOBAL_DATA_PTR;
>  
> +unsigned int get_owl_ram_size(void)
> +{
> + unsigned int val, cap;
> +
> + /* ddr capacity register initialized by ddr driver
> +  * in early bootloader
> +  * DMM_INTERLEAVE_PER_CH_CFG  bit[10:8]
> +  * (val + 1) * 256
> +  */
> + val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0x7;
> + cap =  (val + 1) * 256;
> +
> + return cap;
> +}
> +
>  /*
>   * dram_init - sets uboots idea of sdram size
>   */
>  int dram_init(void)
>  {
>   gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
> +
> +#if defined(CONFIG_MACH_S700)
> + gd->ram_size = get_owl_ram_size() * 1024 * 1024;
> +#endif

Have you checked if this setting can be reused for S900? IMO we should use
this helper for all Owl SoCs. Using CONFIG_SYS_SDRAM_SIZE won't scale.

Thanks,
Mani

> +
>   return 0;
> +
>  }
>  
>  /* This is called after dram_init() so use get_ram_size result */
> -- 
> 2.7.4
> 

Re: [PATCH v3] cmd: mvebu: bubt: fix quoted string split across lines

[Stefan Roese]

Hi Joel,

On 01.05.20 23:41, Joel Johnson wrote:
Ping for review feedback on this patch, it'd be good to have the fix 
included in the same release as the merge was included.


I'll send the pull request later today.

Thanks,
Stefan


Joel

On 2020-04-25 20:54, Joel Johnson wrote:

Update quoted string alignment to address checkpatch.pl warning
originally introduced in
commit f60a66ef5d7d ("cmd: mvebu: bubt: show image boot device").

Signed-off-by: Joel Johnson 

---


I am sort of inferring that this is the desired fix, preferring line
length infractions over split quoted strings. As such, I've combined the
static part of the string for grepping and left the dynamic parts on the
next line.

v2 change:
  - syntax fix
v3 change:
  - actually add syntax fix...

---
 cmd/mvebu/bubt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index dc0ce01c35..ef53153c46 100644
--- a/cmd/mvebu/bubt.c
+++ b/cmd/mvebu/bubt.c
@@ -730,8 +730,8 @@ static int bubt_check_boot_mode(const struct 
bubt_dev *dst)


 for (int i = 0; i < ARRAY_SIZE(a38x_boot_modes); i++) {
 if (a38x_boot_modes[i].id == hdr->blockid) {
-    printf("Error: A38x image meant to be "
-   "booted from \"%s\", not \"%s\"!\n",
+    printf("Error: A38x image meant to be booted from "
+   "\"%s\", not \"%s\"!\n",
    a38x_boot_modes[i].name, dst->name);
 return -ENOEXEC;
 }



Viele Grüße,
Stefan

--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de

RE: [PATCH v7 04/22] lib: Makefile: build crc7.c when CONFIG_MMC_SPI

[Pragnesh Patel]

>-Original Message-
>From: Jagan Teki 
>Sent: 02 May 2020 21:04
>To: Heinrich Schuchardt ; Pragnesh Patel
>; Bin Meng 
>Cc: U-Boot Mailing List ; Atish Patra
>; Palmer Dabbelt ; Paul
>Walmsley ; Troy Benjegerdes
>; Anup Patel ; Sagar
>Kadam ; Rick Chen ; Peng
>Fan ; Lukasz Majewski ; Simon
>Goldschmidt ; Simon Glass
>; Markus Klotzbuecher
>; Baruch Siach ; Joel
>Johnson ; Anatolij Gustschin ; AKASHI
>Takahiro ; Marek Behún 
>Subject: Re: [PATCH v7 04/22] lib: Makefile: build crc7.c when
>CONFIG_MMC_SPI
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Sat, May 2, 2020 at 6:45 PM Heinrich Schuchardt 
>wrote:
>>
>> Am May 2, 2020 11:47:10 AM UTC schrieb Bin Meng
>:
>> >Hi Heinrich,
>> >
>> >On Sat, May 2, 2020 at 6:30 PM Heinrich Schuchardt
>> >
>> >wrote:
>> >>
>> >> On 5/2/20 12:06 PM, Pragnesh Patel wrote:
>> >> > When build U-Boot SPL, meet an issue of undefined reference to
>> >> > 'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when
>> >> > CONFIG_MMC_SPI selected.
>> >> >
>> >> > Signed-off-by: Pragnesh Patel 
>> >> > Reviewed-by: Jagan Teki 
>> >> > Reviewed-by: Bin Meng 
>> >> > ---
>> >> >  common/spl/Kconfig  | 6 ++
>> >> >  drivers/mmc/Kconfig | 1 +
>> >> >  lib/Makefile| 1 +
>> >> >  3 files changed, 8 insertions(+)
>> >> >
>> >> > diff --git a/common/spl/Kconfig b/common/spl/Kconfig index
>> >> > ef5bf66696..d1f0e6bc4c 100644
>> >> > --- a/common/spl/Kconfig
>> >> > +++ b/common/spl/Kconfig
>> >> > @@ -401,6 +401,12 @@ config SPL_CRC32_SUPPORT
>> >> > for detected accidental image corruption. For secure
>> >applications you
>> >> > should consider SHA1 or SHA256.
>> >> >
>> >> > +config SPL_CRC7_SUPPORT
>> >> > + bool "Support CRC7"
>> >> > + help
>> >> > +   Enable CRC7 hashing for drivers which are using in SPL.
>> >> > +   This is a 32-bit checksum value that can be used to
>> >> > +verify
>> >images.
>> >> > +
>> >> >  config SPL_MD5_SUPPORT
>> >> >   bool "Support MD5"
>> >> >   depends on SPL_FIT
>> >> > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index
>> >> > 8f0df568b9..139599072a 100644
>> >> > --- a/drivers/mmc/Kconfig
>> >> > +++ b/drivers/mmc/Kconfig
>> >> > @@ -49,6 +49,7 @@ if MMC
>> >> >  config MMC_SPI
>> >> >   bool "Support for SPI-based MMC controller"
>> >> >   depends on DM_MMC && DM_SPI
>> >> > + select SPL_CRC7_SUPPORT if SPL
>> >> >   help
>> >> > This selects SPI-based MMC controllers.
>> >> > If you have an MMC controller on a SPI bus, say Y here.
>> >> > diff --git a/lib/Makefile b/lib/Makefile index
>> >> > c6f862b0c2..fcd934857f 100644
>> >> > --- a/lib/Makefile
>> >> > +++ b/lib/Makefile
>> >> > @@ -80,6 +80,7 @@ endif
>> >> >
>> >> >  ifdef CONFIG_SPL_BUILD
>> >> >  obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
>> >> > +obj-$(CONFIG_SPL_CRC7_SUPPORT) += crc7.o
>> >>
>> >> crc7.o is not needed in main U-Boot if MMC_SPI is not selected.
>> >>
>> >> So instead of adding a new configuration variable simply correct
>> >> the existing line in lib/Makefile
>> >>
>> >> -obj-y += crc7.o
>> >> +obj-$(CONFIG_MMC_SPI) += crc7.o
>> >
>> >This looks incorrect to me. CRC7 can be useful for other drivers too.
>> >It should not depend on CONFIG_MMC_SPI.
>>
>> Using this argument you would always compile everything. Compiling files
>that are not used is simply a waste of CPU time.
>>
>> Following your argument. you could also always compile crc7.c for SPL and
>hope the compiler will eliminate it.
>>
>> Either way we do not need a new config symbol.
>
>This is one of the reasons I just suggested that the mark 'depends on
>MMC_SPI' at the very initial patch.
>
>Marking config SPL_CRC7_SUPPORT which depends on MMC_SPI would work
>for me.

@Jagan Teki I think MMC_SPI should be depend on or select SPL_CRC7_SUPPORT.
SPL_CRC7_SUPPORT is not depend on MMC_SPI.

@Heinrich Schuchardt Compiling crc7.o every time is not a good idea. I have 1 
suggestion,
Can we make 1 Kconfig like

+config CRC7_SUPPORT
+   bool "Support CRC7"
+   help
+ Enable CRC7 hashing for drivers.
+ This is a 32-bit checksum value that can be used to verify images.

Which is common for U-Boot proper and U-Boot SPL and compile crc7

+ obj-$(CONFIG_CRC7_SUPPORT) += crc7.o

Any suggestions are welcome ?

>
>Jagan.

RE: [PATCH v7 16/22] riscv: Enable cpu clock if it is present

[Pragnesh Patel]

Hi Sean,

>-Original Message-
>From: Sean Anderson 
>Sent: 03 May 2020 22:47
>To: Pragnesh Patel ; u-boot@lists.denx.de
>Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>bmeng...@gmail.com; Paul Walmsley ;
>ja...@amarulasolutions.com; Troy Benjegerdes
>; anup.pa...@wdc.com; Sagar Kadam
>; r...@andestech.com; Lukas Auer
>
>Subject: Re: [PATCH v7 16/22] riscv: Enable cpu clock if it is present
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On 5/3/20 3:12 AM, Pragnesh Patel wrote:
>> Hi Sean,
>>
>>> -Original Message-
>>> From: Sean Anderson 
>>> Sent: 02 May 2020 23:46
>>> To: Pragnesh Patel ; u-boot@lists.denx.de
>>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>>> bmeng...@gmail.com; Paul Walmsley ;
>>> ja...@amarulasolutions.com; Troy Benjegerdes
>>> ; anup.pa...@wdc.com; Sagar Kadam
>>> ; r...@andestech.com; Lukas Auer
>>> 
>>> Subject: Re: [PATCH v7 16/22] riscv: Enable cpu clock if it is
>>> present
>>>
>>> [External Email] Do not click links or attachments unless you
>>> recognize the sender and know the content is safe
>>>
>>> On 5/2/20 6:06 AM, Pragnesh Patel wrote:
 The cpu clock is probably already enabled if we are executing code
 (though we could be executing from a different core). This patch
 prevents the cpu clock or its parents from being disabled.

 Signed-off-by: Sean Anderson 
>>>
>>> If you make substantial changes can you please make a note of it in
>>> the commit? I did not sign off on *this* code.
>>
>> This patch is copied from your v9 series [1] and I made some changes,
>> so the idea is to give credit to everyone who contributed.
>
>That's fine, just please make a note when you make substantial changes.
>For example, you could write
>
>Signed-off-by: Sean Anderson 
>Reviewed-by: Bin Meng  [set clock frequency from
>clock-frequency property]
>Signed-off-by: Pragnesh Patel 
>
>so it's more clear what changes have been made since this patch was posted
>last.

Will take care in future.

>
>--Sean

Re: [PATCH v2] arm: dts: uDPU: switch default PHY speed to 3.125Gbit

[Stefan Roese]

On 24.04.20 11:24, Jakov Petrina wrote:

This resolves issues with certain SFP modules.

Signed-off-by: Jakov Petrina 
Signed-off-by: Vladimir Vid 
---

v2:
- changed PHY mode as well


Reviewed-by: Stefan Roese 

Thanks,
Stefan


  arch/arm/dts/armada-3720-uDPU.dts | 18 ++
  1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/arch/arm/dts/armada-3720-uDPU.dts 
b/arch/arm/dts/armada-3720-uDPU.dts
index 683dac2a7c..07c7b91175 100644
--- a/arch/arm/dts/armada-3720-uDPU.dts
+++ b/arch/arm/dts/armada-3720-uDPU.dts
@@ -109,11 +109,11 @@
   {
phy0 {
phy-type = ;
-   phy-speed = ;
+   phy-speed = ;
};
  phy1 {
  phy-type = ;
-phy-speed = ;
+phy-speed = ;
  };
  
  phy2 {

@@ -125,22 +125,16 @@
   {
pinctrl-0 = <_pins>;
status = "okay";
-   phy-mode = "sgmii";
+   phy-mode = "2500base-x";
+   managed = "in-band-status";
phy = <>;
-   fixed-link {
-   speed = <1000>;
-   full-duplex;
-   };
  };
  
   {

status = "okay";
-   phy-mode = "sgmii";
+   phy-mode = "2500base-x";
+   managed = "in-band-status";
phy = <>;
-   fixed-link {
-   speed = <1000>;
-   full-duplex;
-   };
  };
  
   {





Viele Grüße,
Stefan

--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de

Re: [PATCH v2 7/7] rockchip: make_fit_atf: add signature handling

[Heiko Stübner]

Hi Kever,

Am Freitag, 1. Mai 2020, 12:32:23 CEST schrieb Kever Yang:
> On 2020/4/21 上午8:23, Heiko Stuebner wrote:
> > From: Heiko Stuebner 
> >
> > If the newly added fit-generator key-options are found, append needed
> > signature nodes to all generated image blocks, so that they can get
> > signed when mkimage later compiles the .itb from the generated .its.
> >
> > Signed-off-by: Heiko Stuebner 
> > ---
> >   arch/arm/mach-rockchip/make_fit_atf.py | 51 +-
> >   1 file changed, 50 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-rockchip/make_fit_atf.py 
> > b/arch/arm/mach-rockchip/make_fit_atf.py
> > index d15c32b303..5b353f9d0a 100755
> > --- a/arch/arm/mach-rockchip/make_fit_atf.py
> > +++ b/arch/arm/mach-rockchip/make_fit_atf.py
> > @@ -14,6 +14,8 @@ import sys
> >   import getopt
> >   import logging
> >   import struct
> > +import Crypto
> > +from Crypto.PublicKey import RSA
> >   
> 
> +Traceback (most recent call last):
> 1395 
> +
>  
> File "arch/arm/mach-rockchip/make_fit_atf.py", line 17, in 
> 1396 
> +
>  
> import Crypto
> 1397 
> +ModuleNotFoundError:
>  
> No module named 'Crypto'
> 
> 
> Please help to update .gitlab-ci.yml, or else it will report the error.

The ci stuff probably needs to install pycrypto from pip (or python-crypto
when using a .deb), but I have no clue how this works or how to test any
changes to that locally.

But I guess something like below might do the trick?

Heiko


diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index beaf9b9042..863c3dea51 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -68,6 +68,7 @@ build all 64bit ARM platforms:
 - virtualenv -p /usr/bin/python3 /tmp/venv
 - . /tmp/venv/bin/activate
 - pip install pyelftools
+- pip install pycrypto
 - ret=0;
   ./tools/buildman/buildman -o /tmp -P -E -W aarch64 || ret=$?;
   if [[ $ret -ne 0 ]]; then

RE: [PATCH V2 resend 1/4] imx: add module fuse support

[Peng Fan]

Hi Stefano,

> Subject: Re: [PATCH V2 resend 1/4] imx: add module fuse support
> 
> Hi Peng,
> 
> On 01.05.20 16:08, Peng Fan wrote:
> > There are different parts from one SoC. Take i.MX6ULL for example,
> > some part might not have ENET, some might have; some might not have
> > USB, some might have. The information could be got from OCOTP, to make
> > one image support the different parts, we need runtime disable linux
> > kernel dts node and uboot driver probe if the corresponding module not
> > exists in the part.
> >
> 
> I admit I was not convinced when you post it the first time, mainly due to add
> another blob as database into the code (mx6_fuse_descs). But I needed
> maybe some timeto think about it...
> 
> I like the idea to get most features directly from the processor, and yes we 
> can
> do it via OTP.

This it to use one software to support one kind of SoC, such as i.MX6UL.
I thought to add into device tree using nvmem, but it is not flexible.

Thanks,
Peng.

> 
> Reviewed-by : Stefano Babic 
> 
> Best regards,
> Stefano
> 
> > Signed-off-by: Peng Fan 
> > ---
> >  arch/arm/include/asm/mach-imx/module_fuse.h | 127 +++
> >  arch/arm/include/asm/mach-imx/sys_proto.h   |   1 +
> >  arch/arm/mach-imx/Kconfig   |   7 +
> >  arch/arm/mach-imx/mx6/Makefile  |   1 +
> >  arch/arm/mach-imx/mx6/module_fuse.c | 322
> 
> >  5 files changed, 458 insertions(+)
> >  create mode 100644 arch/arm/include/asm/mach-imx/module_fuse.h
> >  create mode 100644 arch/arm/mach-imx/mx6/module_fuse.c
> >
> > diff --git a/arch/arm/include/asm/mach-imx/module_fuse.h
> > b/arch/arm/include/asm/mach-imx/module_fuse.h
> > new file mode 100644
> > index 00..a46fc3f1f8
> > --- /dev/null
> > +++ b/arch/arm/include/asm/mach-imx/module_fuse.h
> > @@ -0,0 +1,127 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2019 NXP
> > + */
> > +
> > +#ifndef __MODULE_FUSE_H__
> > +#define __MODULE_FUSE_H__
> > +
> > +enum fuse_module_type {
> > +   MODULE_TSC,
> > +   MODULE_ADC1,
> > +   MODULE_ADC2,
> > +   MODULE_SIM1,
> > +   MODULE_SIM2,
> > +   MODULE_FLEXCAN1,
> > +   MODULE_FLEXCAN2,
> > +   MODULE_SPDIF,
> > +   MODULE_EIM,
> > +   MODULE_SD1,
> > +   MODULE_SD2,
> > +   MODULE_SD3,
> > +   MODULE_SD4,
> > +   MODULE_QSPI1,
> > +   MODULE_QSPI2,
> > +   MODULE_GPMI,
> > +   MODULE_APBHDMA,
> > +   MODULE_LCDIF,
> > +   MODULE_PXP,
> > +   MODULE_CSI,
> > +   MODULE_ENET1,
> > +   MODULE_ENET2,
> > +   MODULE_CAAM,
> > +   MODULE_USB_OTG1,
> > +   MODULE_USB_OTG2,
> > +   MODULE_SAI2,
> > +   MODULE_SAI3,
> > +   MODULE_BEE,
> > +   MODULE_UART1,
> > +   MODULE_UART2,
> > +   MODULE_UART3,
> > +   MODULE_UART4,
> > +   MODULE_UART5,
> > +   MODULE_UART6,
> > +   MODULE_UART7,
> > +   MODULE_UART8,
> > +   MODULE_PWM5,
> > +   MODULE_PWM6,
> > +   MODULE_PWM7,
> > +   MODULE_PWM8,
> > +   MODULE_ECSPI1,
> > +   MODULE_ECSPI2,
> > +   MODULE_ECSPI3,
> > +   MODULE_ECSPI4,
> > +   MODULE_ECSPI5,
> > +   MODULE_I2C1,
> > +   MODULE_I2C2,
> > +   MODULE_I2C3,
> > +   MODULE_I2C4,
> > +   MODULE_GPT1,
> > +   MODULE_GPT2,
> > +   MODULE_EPIT1,
> > +   MODULE_EPIT2,
> > +   MODULE_EPDC,
> > +   MODULE_ESAI,
> > +   MODULE_DCP,
> > +   MODULE_DCP_CRYPTO,
> > +};
> > +
> > +struct fuse_entry_desc {
> > +   enum fuse_module_type module;
> > +   const char *node_path;
> > +   u32 fuse_word_offset;
> > +   u32 fuse_bit_offset;
> > +   u32 status;
> > +};
> > +
> > +#if !CONFIG_IS_ENABLED(IMX_MODULE_FUSE)
> > +static inline u32 check_module_fused(enum fuse_module_type module) {
> > +   return 0;
> > +};
> > +
> > +static inline u32 esdhc_fused(ulong base_addr) {
> > +   return 0;
> > +};
> > +
> > +static inline u32 ecspi_fused(ulong base_addr) {
> > +   return 0;
> > +};
> > +
> > +static inline u32 uart_fused(ulong base_addr) {
> > +   return 0;
> > +};
> > +
> > +static inline u32 usb_fused(ulong base_addr) {
> > +   return 0;
> > +};
> > +
> > +static inline u32 qspi_fused(ulong base_addr) {
> > +   return 0;
> > +};
> > +
> > +static inline u32 i2c_fused(ulong base_addr) {
> > +   return 0;
> > +};
> > +
> > +static inline u32 enet_fused(ulong base_addr) {
> > +   return 0;
> > +};
> > +#else
> > +u32 check_module_fused(enum fuse_module_type module);
> > +u32 esdhc_fused(ulong base_addr);
> > +u32 ecspi_fused(ulong base_addr);
> > +u32 uart_fused(ulong base_addr);
> > +u32 usb_fused(ulong base_addr);
> > +u32 qspi_fused(ulong base_addr);
> > +u32 i2c_fused(ulong base_addr);
> > +u32 enet_fused(ulong base_addr);
> > +#endif
> > +#endif /* __MODULE_FUSE_H__ */
> > diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
> > b/arch/arm/include/asm/mach-imx/sys_proto.h
> > index ba930a2088..48ce4b1e18 100644
> > --- a/arch/arm/include/asm/mach-imx/sys_proto.h
> > +++ b/arch/arm/include/asm/mach-imx/sys_proto.h
> > @@ -9,6 +9,7 @@
> >
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include "../arch-imx/cpu.h"
> >
> > diff --git 

RE: [PATCH 10/13] imx: load calibration parameters from fuse for i.MX8MP

[Peng Fan]

Hi Fabio,

> Subject: Re: [PATCH 10/13] imx: load calibration parameters from fuse for
> i.MX8MP
> 
> Hi Peng and Ye Li,
> 
> On Sun, May 3, 2020 at 10:57 AM Peng Fan  wrote:
> >
> > From: Ye Li 
> >
> > i.MX8MP thermal which has two probes and supports temperature range
> > from -40 to 125.  The driver still uses default 1p HW calibration at
> > 25C and loads calibration parameters from fuse.
> >
> > Reviewed-by: Peng Fan 
> > Signed-off-by: Ye Li 
> > Signed-off-by: Peng Fan 
> 
> Are you able to boot an NXP 5.4.3 kernel on a i.MX8MP EVK board?
> 

5.4.3 upstream kernel + latest upstream uboot?

> I am getting a kernel hang right after the serial console is probed:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpasteb
> in.com%2F3AtvJqWSdata=02%7C01%7Cpeng.fan%40nxp.com%7Cf3d1
> e46ad41e4ca90b0608d7ef73f349%7C686ea1d3bc2b4c6fa92cd99c5c301635
> %7C0%7C0%7C637241153594873754sdata=gjGygSnftYVH58eLW%2By
> 6ZZ4uczLZUM0U0lUk9LQyx5Y%3Dreserved=0
> 
> Any suggestions?
> 
> I am using ATF from 5.4.3, firmware version is 8.6 and I pass 'export
> ATF_LOAD_ADDR=0x96'.
> 
> Any ideas?

I am not holiday, not have a board at handle. I will give a try in a few days.


Disable busfreq, try clk_ignore_unused?

Regards,
Peng.

> 
> Thanks

RE: [PATCH 5/5] power: imx8: Replace SC_R_LAST with SC_R_NONE

[Peng Fan]

> Subject: Re: [PATCH 5/5] power: imx8: Replace SC_R_LAST with SC_R_NONE
> 
> Hi Peng,
> 
> On Sun,  3 May 2020 22:33:23 +0800
> Peng Fan peng@nxp.com wrote:
> ...
> > ---
> >  arch/arm/dts/fsl-imx8dx.dtsi| 619
> 
> 
> Why is this patch removing the dtsi file?

It is a mistake when I cherry-pick the patch from downstream,
will fix in v2.

Thanks,
Peng.

> 
> --
> Anatolij

[PATCH v3 2/4] patman: Suppress empty changelog entries

[Sean Anderson]

Patman outputs a line for every edition of the series in every patch,
regardless of whether any changes were made. This can result in many
redundant lines in patch changelogs, especially when a patch did not exist
before a certain revision. For example, the existing behaviour could result
in a changelog of

Changes in v7: None
Changes in v6: None
Changes in v5:
- Make a change

Changes in v4: None

Changes in v3:
- New

Changes in v2: None

With this patch applied and with --no-empty-changes, the same patch would
look like

(no changes since v5)

Changes in v5:
- Make a change

Changes in v3:
- New

This is entirely aesthetic, but I think it reduces clutter, especially for
patches added later on in a series.

Signed-off-by: Sean Anderson 
---

Changes in v3:
- Document empty changelog suppression in README
- Fix KeyError when running tests
- Fix no changes message being output for revision 1
- Fix no changes message sometimes being output before every
  non-newest-revision change
- Make the newest_version logic more robust (and ugly)
- Update commit subject

Changes in v2:
- Add a note when there are no changes in the current revision
- Make this the default behaviour, and remove the option

 tools/patman/README| 21 
 tools/patman/series.py | 44 +++---
 2 files changed, 54 insertions(+), 11 deletions(-)

diff --git a/tools/patman/README b/tools/patman/README
index 02d5829744..d1d9891c4c 100644
--- a/tools/patman/README
+++ b/tools/patman/README
@@ -474,6 +474,27 @@ print out the command line patman would have used.
 not later when you can't remember which patch you changed. You can always
 go back and change or remove logs from commits.
 
+7. Patches will have no changelog entries for revisions where they did not
+change. For clarity, if there are no changes for this patch in the most
+recent revision of the series, a note will be added. For example, a patch
+with the following tags in the commit
+
+Series-version: 5
+Series-changes: 2
+- Some change
+
+Series-changes: 4
+- Another change
+
+would have a changelog of
+
+(no changes since v4)
+
+Changes in v4:
+- Another change
+
+Changes in v2:
+- Some change
 
 Other thoughts
 ==
diff --git a/tools/patman/series.py b/tools/patman/series.py
index 6d9d48b123..4359442174 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -146,38 +146,60 @@ class Series(dict):
 Changes in v4:
 - Jog the dial back closer to the widget
 
-Changes in v3: None
 Changes in v2:
 - Fix the widget
 - Jog the dial
 
-etc.
+If there are no new changes in a patch, a note will be added
+
+(no changes since v2)
+
+Changes in v2:
+- Fix the widget
+- Jog the dial
 """
+versions = sorted(self.changes, reverse=True)
+newest_version = 1
+try:
+newest_version = max(newest_version, int(self.version))
+except (ValueError, KeyError):
+pass
+try:
+newest_version = max(newest_version, versions[0])
+except IndexError:
+pass
+
 final = []
 process_it = self.get('process_log', '').split(',')
 process_it = [item.strip() for item in process_it]
 need_blank = False
-for change in sorted(self.changes, reverse=True):
+for version in versions:
 out = []
-for this_commit, text in self.changes[change]:
+for this_commit, text in self.changes[version]:
 if commit and this_commit != commit:
 continue
 if 'uniq' not in process_it or text not in out:
 out.append(text)
-line = 'Changes in v%d:' % change
-have_changes = len(out) > 0
 if 'sort' in process_it:
 out = sorted(out)
+have_changes = len(out) > 0
+line = 'Changes in v%d:' % version
 if have_changes:
 out.insert(0, line)
-else:
-out = [line + ' None']
-if need_blank:
-out.insert(0, '')
+if version < newest_version and len(final) == 0:
+out.insert(0, '')
+out.insert(0, '(no changes since v%d)' % version)
+newest_version = 0
+# Only add a new line if we output something
+if need_blank:
+out.insert(0, '')
 final += out
 need_blank = have_changes
-if self.changes:
+
+if len(final) > 0:
 final.append('')
+elif newest_version != 1:
+final = ['(no changes since v1)', '']
 return final
 
 def DoChecks(self):
-- 
2.26.2

[PATCH v3 4/4] patman: Support multi-line changes in changelogs

[Sean Anderson]

This patch adds support to multi-line changes. That is, if one has a line
in a changelog like
- Do a thing but
  it spans multiple lines
Using Series-process-log sort would sort as if those lines were unrelated.
With this patch, any change line starting with whitespace will be
considered part of the change before it.

Signed-off-by: Sean Anderson 
---

(no changes since v2)

Changes in v2:
- New

 tools/patman/README | 10 --
 tools/patman/patchstream.py | 35 +++
 2 files changed, 35 insertions(+), 10 deletions(-)

diff --git a/tools/patman/README b/tools/patman/README
index 5a67a49e88..155736568c 100644
--- a/tools/patman/README
+++ b/tools/patman/README
@@ -270,8 +270,14 @@ Patch-cc: Their Name 
interpreted by git send-email if you use it.
 
 Series-process-log: sort, uniq
-   This tells patman to sort and/or uniq the change logs. It is
-   assumed that each change log entry is only a single line long.
+   This tells patman to sort and/or uniq the change logs. Changes may be
+   multiple lines long, as long as each subsequent line of a change begins
+   with a whitespace character. For example,
+
+- This change
+  continues onto the next line
+- But this change is separate
+
Use 'sort' to sort the entries, and 'uniq' to include only
unique entries. If omitted, no change log processing is done.
Separate each tag with a comma.
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index f29ad87e70..eeac5d268e 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -45,6 +45,9 @@ re_commit = re.compile('^commit ([0-9a-f]*)$')
 # We detect these since checkpatch doesn't always do it
 re_space_before_tab = re.compile('^[+].* \t')
 
+# Match indented lines for changes
+re_leading_whitespace = re.compile('^\s')
+
 # States we can be in - can we use range() and still have comments?
 STATE_MSG_HEADER = 0# Still in the message header
 STATE_PATCH_SUBJECT = 1 # In patch subject (first line of log for a commit)
@@ -72,6 +75,7 @@ class PatchStream:
 self.is_log = is_log # True if indent like git log
 self.in_change = None# Name of the change list we are in
 self.change_version = 0  # Non-zero if we are in a change list
+self.change_lines = []   # Lines of the current change
 self.blank_count = 0 # Number of blank lines stored up
 self.state = STATE_MSG_HEADER# What state are we in?
 self.signoff = []# Contents of signoff line
@@ -130,6 +134,20 @@ class PatchStream:
 raise ValueError("%s: Cannot decode version info '%s'" %
 (self.commit.hash, line))
 
+def FinalizeChange(self):
+"""Finalize a (multi-line) change and add it to the series or commit"""
+if not self.change_lines:
+return
+change = '\n'.join(self.change_lines)
+
+if self.in_change == 'Series':
+self.series.AddChange(self.change_version, self.commit, change)
+elif self.in_change == 'Cover':
+self.series.AddChange(self.change_version, None, change)
+elif self.in_change == 'Commit':
+self.commit.AddChange(self.change_version, change)
+self.change_lines = []
+
 def ProcessLine(self, line):
 """Process a single line of a patch file or commit log
 
@@ -170,6 +188,7 @@ class PatchStream:
 commit_tag_match = re_commit_tag.match(line)
 cover_match = re_cover.match(line)
 signoff_match = re_signoff.match(line)
+leading_whitespace_match = re_leading_whitespace.match(line)
 tag_match = None
 if self.state == STATE_PATCH_HEADER:
 tag_match = re_tag.match(line)
@@ -210,6 +229,7 @@ class PatchStream:
 # is missing, fix it up.
 if self.in_change:
 self.warn.append("Missing 'blank line' in section 
'%s-changes'" % self.in_change)
+self.FinalizeChange()
 self.in_change = None
 self.change_version = 0
 
@@ -264,20 +284,18 @@ class PatchStream:
 elif self.in_change:
 if is_blank:
 # Blank line ends this change list
+self.FinalizeChange()
 self.in_change = None
 self.change_version = 0
 elif line == '---':
+self.FinalizeChange()
 self.in_change = None
 self.change_version = 0
 out = self.ProcessLine(line)
-else:
-if self.is_log:
-if self.in_change == 'Series':
-self.series.AddChange(self.change_version, 
self.commit, line)
-elif self.in_change == 'Cover':
-self.series.AddChange(self.change_version, None, line)
-elif 

[PATCH v3 3/4] patman: Add new tags for finer-grained changelog control

[Sean Anderson]

By default patman generates a combined changelog for the cover letter. This
may not always be desireable.

Many patches may have the same changes. These can be coalesced with
"Series-process-log: uniq", but this is imperfect. Similar changes like
"Move foo to patch 7" will not be merged with the similar "Move foo to this
patch from patch 6".

Changes may not make sense outside of the patch they are written for. For
example, a change line of "Add check for bar" does not make sense outside
of the context in which bar might be checked for. Some changes like "New"
or "Lint" may be repeated many times throughout different change logs, but
carry no useful information in a summary.

Lastly, I like to summarize the broad strokes of the changes I have made in
the cover letter, while documenting all the details in the appropriate
patches. I think this make it easier to get a good feel for what has
changed, without making it difficult to wade through every change in the
whole series.

This patch adds two new tags to add changelog entries which only appear in
the cover letter, or only appear in the commit. Changes documented with
"Commit-changes" will only appear in the commit, and will not appear in the
cover letter. Changes documented with "Cover-changes" will not appear in
any commit, and will only appear in the cover letter.

Signed-off-by: Sean Anderson 
---

(no changes since v2)

Changes in v2:
- Add documentation for new tags
- Switch to using commit tags for changelog control, instead of
  command-line options

 tools/patman/README | 17 +
 tools/patman/patchstream.py | 73 ++---
 tools/patman/patman.py  |  2 +-
 tools/patman/series.py  | 13 ++-
 4 files changed, 73 insertions(+), 32 deletions(-)

diff --git a/tools/patman/README b/tools/patman/README
index d1d9891c4c..5a67a49e88 100644
--- a/tools/patman/README
+++ b/tools/patman/README
@@ -247,6 +247,23 @@ Series-changes: n
to update the log there and then, knowing that the script will
do the rest.
 
+Commit-changes: n
+- This line will not appear in the cover-letter changelog
+
+   This tag is like Series-changes, except changes in this changelog will
+   only appear in the changelog of the commit this tag is in. This is
+   useful when you want to add notes which may not make sense in the cover
+   letter. For example, you can have short changes such as "New" or
+   "Lint".
+
+Cover-changes: n
+- This line will only appear in the cover letter
+
+   This tag is like Series-changes, except changes in this changelog will
+   only appear in the cover-letter changelog. This is useful to summarize
+   changes made with Commit-changes, or to add additional context to
+   changes.
+
 Patch-cc: Their Name 
This copies a single patch to another email address. Note that the
Cc: used by git send-email is ignored by patman, but will be
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index df3eb7483b..f29ad87e70 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -24,11 +24,8 @@ re_allowed_after_test = re.compile('^Signed-off-by:')
 # Signoffs
 re_signoff = re.compile('^Signed-off-by: *(.*)')
 
-# The start of the cover letter
-re_cover = re.compile('^Cover-letter:')
-
-# A cover letter Cc
-re_cover_cc = re.compile('^Cover-letter-cc: *(.*)')
+# Cover letter tag
+re_cover = re.compile('^Cover-([a-z-]*): *(.*)')
 
 # Patch series tag
 re_series_tag = re.compile('^Series-([a-z-]*): *(.*)')
@@ -65,7 +62,7 @@ class PatchStream:
 def __init__(self, series, name=None, is_log=False):
 self.skip_blank = False  # True to skip a single blank line
 self.found_test = False  # Found a TEST= line
-self.lines_after_test = 0# MNumber of lines found after TEST=
+self.lines_after_test = 0# Number of lines found after TEST=
 self.warn = []   # List of warnings we have collected
 self.linenum = 1 # Output line number we are up to
 self.in_section = None   # Name of start...END section we are 
in
@@ -73,7 +70,8 @@ class PatchStream:
 self.section = []# The current section...END section
 self.series = series # Info about the patch series
 self.is_log = is_log # True if indent like git log
-self.in_change = 0   # Non-zero if we are in a change list
+self.in_change = None# Name of the change list we are in
+self.change_version = 0  # Non-zero if we are in a change list
 self.blank_count = 0 # Number of blank lines stored up
 self.state = STATE_MSG_HEADER# What state are we in?
 self.signoff = []# Contents of signoff line
@@ -124,6 +122,14 @@ class PatchStream:
 self.skip_blank = True
 

[PATCH v3 1/4] patman: Modify functional tests for new behavior

[Sean Anderson]

This patch adds or modifies functional tests for the Cover-changes,
Commit-changes, and Series-process-log tags in order to account for new
behavior added in the next several patches. The '(no changes since v1)'
case is not tested for, since that would need an additional commit to test
in addition to testing the existing code paths.

Signed-off-by: Sean Anderson 
---

Changes in v3:
- New

 tools/patman/func_test.py | 58 ---
 .../0001-pci-Correct-cast-for-sandbox.patch   |  3 +
 ...-for-sandbox-in-fdtdec_setup_mem_siz.patch | 12 +++-
 tools/patman/test/test01.txt  | 15 -
 4 files changed, 79 insertions(+), 9 deletions(-)

diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py
index 76319fff37..eedc7f5e18 100644
--- a/tools/patman/func_test.py
+++ b/tools/patman/func_test.py
@@ -85,19 +85,33 @@ class TestFunctional(unittest.TestCase):
 Series-prefix: RFC
 Series-cc: Stefan Brüns 
 Cover-letter-cc: Lord Mëlchett 
-Series-version: 2
+Series-version: 3
+Patch-cc: fred
+Series-process-log: sort, uniq
 Series-changes: 4
 - Some changes
+- Multi
+  line
+  change
+
+Commit-changes: 2
+- Changes only for this commit
+
+Cover-changes: 4
+- Some notes for the cover letter
 
 Cover-letter:
 test: A test patch series
 This is a test of how the cover
-leter
+letter
 works
 END
 
 and this in the first commit:
 
+Commit-changes: 2
+- second revision change
+
 Series-notes:
 some notes
 about some things
@@ -205,7 +219,7 @@ class TestFunctional(unittest.TestCase):
 
 expected = '''
 This is a test of how the cover
-leter
+letter
 works
 
 some notes
@@ -213,7 +227,11 @@ about some things
 from the first commit
 
 Changes in v4:
+- Multi
+  line
+  change
 - Some changes
+- Some notes for the cover letter
 
 Simon Glass (2):
   pci: Correct cast for sandbox
@@ -240,8 +258,34 @@ Simon Glass (2):
 subject = [line for line in lines if line.startswith('Subject')]
 self.assertEqual('Subject: [RFC %d/%d]' % (i + 1, count),
  subject[0][:18])
+
+# Check that we got our commit notes
+start = 0
+expected = ''
+
 if i == 0:
-# Check that we got our commit notes
-self.assertEqual('---', lines[17])
-self.assertEqual('Some notes about', lines[18])
-self.assertEqual('the first commit', lines[19])
+start = 17
+expected = '''---
+Some notes about
+the first commit
+
+(no changes since v2)
+
+Changes in v2:
+- second revision change'''
+elif i == 1:
+start = 17
+expected = '''---
+
+Changes in v4:
+- Multi
+  line
+  change
+- Some changes
+
+Changes in v2:
+- Changes only for this commit'''
+
+if expected:
+expected = expected.splitlines()
+self.assertEqual(expected, lines[start:(start+len(expected))])
diff --git a/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch 
b/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch
index 7191176f75..038943c2c9 100644
--- a/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch
+++ b/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch
@@ -15,6 +15,9 @@ cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of 
type
 Fix it with a cast.
 
 Signed-off-by: Simon Glass 
+Commit-changes: 2
+- Changes only for this commit
+
 Series-notes:
 some notes
 about some things
diff --git 
a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch
 
b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch
index 702c0306ff..56278a6ce9 100644
--- 
a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch
+++ 
b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch
@@ -21,13 +21,23 @@ Series-cc: Stefan Brüns 
 Cover-letter-cc: Lord Mëlchett 
 Series-version: 3
 Patch-cc: fred
+Series-process-log: sort, uniq
 Series-changes: 4
 - Some changes
+- Multi
+  line
+  change
+
+Commit-changes: 2
+- Changes only for this commit
+
+Cover-changes: 4
+- Some notes for the cover letter
 
 Cover-letter:
 test: A test patch series
 This is a test of how the cover
-leter
+letter
 works
 END
 ---
diff --git a/tools/patman/test/test01.txt b/tools/patman/test/test01.txt
index 478ea93674..b238a8b4ba 100644
--- a/tools/patman/test/test01.txt
+++ b/tools/patman/test/test01.txt
@@ -13,6 +13,9 @@ Date:   Sat Apr 15 15:39:08 2017 -0600
 Fix it with a cast.
 
 Signed-off-by: Simon Glass 
+Commit-changes: 2
+ 

[PATCH v3 0/4] patman: Add changelog customization options

[Sean Anderson]

This series adds a few changes I have been using locally as new tags for
patman. This series has itself been developed using these patches, and the
unprocessed commits can be viewed at [1].

[1] https://github.com/Forty-Bot/u-boot/tree/patman

Changes in v3:
- Document empty changelog suppression in README
- Fix KeyError when running tests
- Fix some corner cases for no changes messages
- Modify tests for new behavior
- Update commit subjects

Changes in v2:
- Add a note when there are no changes in the current revision
- Add documentation for new tags
- Add patch for multi-line changes in changelogs
- Switch to using commit tags for changelog control, instead of
  command-line options

Sean Anderson (4):
  patman: Modify functional tests for new behavior
  patman: Suppress empty changelog entries
  patman: Add new tags for finer-grained changelog control
  patman: Support multi-line changes in changelogs

 tools/patman/README   | 48 +-
 tools/patman/func_test.py | 58 +--
 tools/patman/patchstream.py   | 96 +--
 tools/patman/patman.py|  2 +-
 tools/patman/series.py| 53 +++---
 .../0001-pci-Correct-cast-for-sandbox.patch   |  3 +
 ...-for-sandbox-in-fdtdec_setup_mem_siz.patch | 12 ++-
 tools/patman/test/test01.txt  | 15 ++-
 8 files changed, 233 insertions(+), 54 deletions(-)

-- 
2.26.2

Re: Bisected: mmc cause reboot loops on N900

[Pali Rohár]

Pavel suggested to add Tomi into the loop as Jean is not with TI anymore.

Tomi, could you please look at this mmc related problem? See details below.

On Sunday 26 April 2020 00:20:07 Pali Rohár wrote:
> On Saturday 25 April 2020 23:26:15 Pali Rohár wrote:
> > Adding Jean to the loop. Could you please look at this problem? Your
> > commit (described below) is causing reboot loop on Nokia N900 hardware.
> > 
> > On Saturday 25 April 2020 13:50:45 Pali Rohár wrote:
> > > On Saturday 25 April 2020 06:36:58 Adam Ford wrote:
> > > > On Sat, Apr 25, 2020 at 5:42 AM Pali Rohár  wrote:
> > > > >
> > > > > On Thursday 02 April 2020 20:42:31 Pali Rohár wrote:
> > > > > > On Wednesday 01 April 2020 12:32:29 Merlijn Wajer wrote:
> > ...
> > > > > > > U-Boot 2020.04-rc4-00033-g7dbafe0634-dirty (Apr 01 2020 - 
> > > > > > > 12:15:47 +0200)
> > > > > > >
> > > > > > > OMAP3530-HS ES3.1, CPU-OPP2, L3-165MHz, Max CPU Clock 600 MHz
> > > > > > > Nokia RX-51 + LPDDR/OneNAND
> > > > > > > I2C:   ready
> > > > > > > DRAM:  256 MiB
> > > > > > > NAND:  0 Bytes
> > ...
> > > > > > > MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
> > ...
> > > > > > > OMAP die ID: 0314002404036ac10b01100f
> > > > > > > OMAP3530-HS ES3.1, CPU-OPP2, L3-165MHz, Max CPU Clock 600 MHz
> > > > > > >
> > > > > >
> > > > > > And then U-Boot freeze, right?
> > > > > >
> > > > > > Any idea how to debug this issue?
> > > > > >
> > > > > > On my N900 I'm getting "data abort" error on display and then 
> > > > > > instant
> > > > > > reboot.
> > > > >
> > > > > It looks like that omap hs mmc code cause that freeze/reboot on real 
> > > > > HW.
> > > > > Was there some significat change to OMAP3 or omap hs mmc?
> > > > 
> > > > I booted by board from MMC as shown above.  I also use the pinctrl
> > > > features from the device tree to mux the pins in U-Boot (not SPL), so
> > > > my SPL only does manual muxing the essential components it needs
> > > > during the SPL phase, and lets U-Boot do the rest.   I only  mention
> > > > the pinmux because of message regarding pads/pull-ups.
> > > > 
> > > > adam
> > > 
> > > I debugged this problem more. I disabled all preboot commands to get
> > > clean U-Boot setup. And it worked.
> > > 
> > > After I called any "mmc" command (e.g. "mmc info") I got that instant
> > > board reboot. Preboot commands for n900 try to read some files from mmc,
> > > so this is reason why it get into reboot loop.
> > > 
> > > Is there any reason why "mmc info" command can cause "data abort" and
> > > instant reboot of board?
> > > 
> > > And do you know what is needed for proper initialization of omap mmc
> > > controller for omap3 board? Because it looks like something fundamental
> > > is missing.
> > > 
> > > Currently there are just calls for "omap_mmc_init()" functions and
> > > "twl4030_power_mmc_init()" functions. See:
> > > https://gitlab.denx.de/u-boot/u-boot/-/blob/master/board/nokia/rx51/rx51.c
> > 
> > Now I tried git bisect and here is problematic commit which caused whole
> > reboot loop:
> > 
> > 04a2ea248f58b3b6216d0cd0a6b8698df8b14355 is the first bad commit
> > commit 04a2ea248f58b3b6216d0cd0a6b8698df8b14355
> > Author: Jean-Jacques Hiblot 
> > Date:   Thu Sep 21 16:30:08 2017 +0200
> > 
> > mmc: disable UHS modes if Vcc cannot be switched on and off
> > 
> > If a power cycle cannot be done on Vcc, it is safer not to try the UHS
> > modes because we wouldn't be able to recover from an error occurring
> > during the UHS initialization.
> > 
> > Signed-off-by: Jean-Jacques Hiblot 
> > 
> > :04 04 04de51428c8311a4b2fb3ad876ac3f6071ab57ee 
> > ea7a7959a4bd591c92a2c3d413d5643a8457d2ff M  drivers
> > :04 04 03f639baf2a2f55003cb750981fd8accc5b4a993 
> > fbcb9607d37959f0b5240f5d727133f58cc35379 M  include
> > 
> > It changes only core mmc code, nothing platform / board specific.
> > U-Boot compiled from commit before above has fully working eMMC access
> > on real Nokia N900. I can read files on FAT eMMC partition without any
> > problem.
> > 
> > I'm not sure what is happening here, but it looks like that omap hs mmc
> > driver used on Nokia N900 is maybe not correctly hooked for UHS support.
> > 
> > The most suspicious it that this problem cannot be reproduced in qemu
> > n900 emulator. It happens only on real N900 hw.
> 
> I took main change from above commit, reverted it on master and U-Boot
> stopped crashing! No reboot loop anymore. Here is change which fixes
> reboot loop on Nokia N900:
> 
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index 523c055967..d07c7745da 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -2786,18 +2786,7 @@ int mmc_get_op_cond(struct mmc *mmc)
> MMC_QUIRK_RETRY_APP_CMD;
>  #endif
>  
> - err = mmc_power_cycle(mmc);
> - if (err) {
> - /*
> -  * if power cycling is not supported, we should not try
> -  * to use the UHS modes, because we wouldn't be able to
> - 

[PATCH v2] video: omap: change include order

[Dario Binacchi]

Apply u-boot coding style on include files order as described by the
wiki https://www.denx.de/wiki/U-Boot/CodingStyle.

Signed-off-by: Dario Binacchi 

---

Changes in v2:
- Add reference to code style wiki

 drivers/video/am335x-fb.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index eb5add2a20..0f066df451 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -13,15 +13,15 @@
  */
 #include 
 #include 
-#include 
+#include 
+#include 
+#include 
 #include 
 #include 
-#include 
 #include 
+#include 
 #include 
 #include 
-#include 
-#include 
 #include "am335x-fb.h"
 
 #define LCDC_FMAX  2
-- 
2.17.1

[RFC PATCH 3/3] net: tsec: convert fsl_pq_mdio to DM_MDIO

[Vladimir Oltean]

From: Vladimir Oltean 

For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.

Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing otherwise.

Signed-off-by: Vladimir Oltean 
---
 drivers/net/fsl_mdio.c | 66 ++
 drivers/net/tsec.c | 50 ++--
 include/fsl_mdio.h |  4 +--
 3 files changed, 78 insertions(+), 42 deletions(-)

diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 894b52ee66f4..284508062c8e 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -8,9 +8,11 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 
 void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
int dev_addr, int regnum, int value)
@@ -56,11 +58,8 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem 
*phyregs, int port_addr,
return value;
 }
 
-static int fsl_pq_mdio_reset(struct mii_dev *bus)
+int fsl_pq_mdio_reset(struct tsec_mii_mng __iomem *regs)
 {
-   struct tsec_mii_mng __iomem *regs =
-   (struct tsec_mii_mng __iomem *)bus->priv;
-
/* Reset MII (due to new addresses) */
out_be32(>miimcfg, MIIMCFG_RESET_MGMT);
 
@@ -72,6 +71,7 @@ static int fsl_pq_mdio_reset(struct mii_dev *bus)
return 0;
 }
 
+#ifndef CONFIG_DM_MDIO
 int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
 {
struct tsec_mii_mng __iomem *phyregs =
@@ -91,6 +91,11 @@ int tsec_phy_write(struct mii_dev *bus, int addr, int 
dev_addr, int regnum,
return 0;
 }
 
+static int tsec_mdio_reset(struct mii_dev *bus)
+{
+   return fsl_pq_mdio_reset(bus->priv);
+}
+
 int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
 {
struct mii_dev *bus = mdio_alloc();
@@ -102,10 +107,61 @@ int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info 
*info)
 
bus->read = tsec_phy_read;
bus->write = tsec_phy_write;
-   bus->reset = fsl_pq_mdio_reset;
+   bus->reset = tsec_mdio_reset;
strcpy(bus->name, info->name);
 
bus->priv = (void *)info->regs;
 
return mdio_register(bus);
 }
+#endif
+
+#ifdef CONFIG_DM_MDIO
+static int dm_fsl_pq_mdio_read(struct udevice *dev, int addr, int devad,
+  int reg)
+{
+   struct fsl_pq_mdio_info *info = dev_get_priv(dev);
+
+   return tsec_local_mdio_read(info->regs, addr, devad, reg);
+}
+
+static int dm_fsl_pq_mdio_write(struct udevice *dev, int addr, int devad,
+   int reg, u16 val)
+{
+   struct fsl_pq_mdio_info *info = dev_get_priv(dev);
+
+   tsec_local_mdio_write(info->regs, addr, devad, reg, val);
+
+   return 0;
+}
+
+static int fsl_pq_mdio_probe(struct udevice *dev)
+{
+   struct fsl_pq_mdio_info *info = dev_get_priv(dev);
+   fdt_addr_t reg;
+
+   reg = devfdt_get_addr(dev);
+   info->regs = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0, MAP_NOCACHE);
+
+   return fsl_pq_mdio_reset(info->regs);
+}
+
+static const struct mdio_ops fsl_pq_mdio_ops = {
+   .read   = dm_fsl_pq_mdio_read,
+   .write  = dm_fsl_pq_mdio_write,
+};
+
+static const struct udevice_id fsl_pq_mdio_ids[] = {
+   { .compatible = "fsl,etsec2-mdio" },
+   { }
+};
+
+U_BOOT_DRIVER(fsl_pq_mdio) = {
+   .name   = "fsl_pq_mdio",
+   .id = UCLASS_MDIO,
+   .of_match   = fsl_pq_mdio_ids,
+   .probe  = fsl_pq_mdio_probe,
+   .ops= _pq_mdio_ops,
+   .priv_auto_alloc_size   = sizeof(struct fsl_pq_mdio_info),
+};
+#endif
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 842cddf2297a..93f151a8a6db 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -679,8 +680,15 @@ static int init_phy(struct tsec_private *priv)
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
tsec_configure_serdes(priv);
 
+#ifdef CONFIG_DM_ETH
+   if (ofnode_valid(ofnode_find_subnode(priv->dev->node, "fixed-link")))
+   phydev = phy_connect(NULL, 0, priv->dev, priv->interface);
+   else
+   phydev = dm_eth_phy_connect(priv->dev);
+#else
phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
 priv->interface);
+#endif
if (!phydev)
return 0;
 
@@ -785,14 +793,17 @@ int tsec_standard_init(bd_t *bis)
return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
 }
 #else /* CONFIG_DM_ETH */
+
+#ifndef CONFIG_DM_MDIO
+#error "TSEC with DM_ETH also requires DM_MDIO"
+#endif
+
 int tsec_probe(struct udevice *dev)
 {
struct eth_pdata *pdata = 

[RFC PATCH 2/3] configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN

[Vladimir Oltean]

From: Vladimir Oltean 

The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid
build errors, enable DM_MDIO in these boards' configs before we actually
add DM_MDIO support to tsec.

Signed-off-by: Vladimir Oltean 
---
 configs/ls1021atsn_qspi_defconfig   | 1 +
 configs/ls1021atsn_sdcard_defconfig | 1 +
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig| 1 +
 configs/ls1021atwr_nor_defconfig| 1 +
 configs/ls1021atwr_nor_lpuart_defconfig | 1 +
 configs/ls1021atwr_qspi_defconfig   | 1 +
 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
 configs/ls1021atwr_sdcard_ifc_defconfig | 1 +
 configs/ls1021atwr_sdcard_qspi_defconfig| 1 +
 9 files changed, 9 insertions(+)

diff --git a/configs/ls1021atsn_qspi_defconfig 
b/configs/ls1021atsn_qspi_defconfig
index f1c010b5e916..debd52f2b236 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -38,6 +38,7 @@ CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
diff --git a/configs/ls1021atsn_sdcard_defconfig 
b/configs/ls1021atsn_sdcard_defconfig
index 3550d16af8d6..de66c84314f4 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -50,6 +50,7 @@ CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig 
b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 85c19a66cda0..0e80182d7bee 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -39,6 +39,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 88462493a553..a71e036b4a49 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -39,6 +39,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig 
b/configs/ls1021atwr_nor_lpuart_defconfig
index 5ec13aaafd67..60daf3ef2b2d 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -41,6 +41,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atwr_qspi_defconfig 
b/configs/ls1021atwr_qspi_defconfig
index 82339c98cf38..09a6a2918c39 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -41,6 +41,7 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig 
b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index a18b192176b3..4298b57aead9 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -53,6 +53,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig 
b/configs/ls1021atwr_sdcard_ifc_defconfig
index fac41154456a..571fde20edac 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -54,6 +54,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig 
b/configs/ls1021atwr_sdcard_qspi_defconfig
index 80a0e9171739..6af5289e38bb 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -53,6 +53,7 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
-- 
2.17.1

[RFC PATCH 0/3] DM_MDIO for fsl_tsec driver

[Vladimir Oltean]

From: Vladimir Oltean 

This series converts the MDIO handling portion of the DM_ETH variant of
the tsec driver (currently in use only on LS1021A-TSN and LS1021A-TWR)
to use DM_MDIO. The other (non-DM_ETH) users of tsec are left alone.

Posted as RFC since it depends on Zhiqiang's series
"[PATCHv2,0/3] net: tsec: Fix issues of DM driver":
https://patchwork.ozlabs.org/project/uboot/cover/20200503144843.36949-1-zhiqiang@nxp.com/

Vladimir Oltean (3):
  phy: make phy_connect_fixed work with a null mdio bus
  configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN
  net: tsec: convert fsl_pq_mdio to DM_MDIO

 configs/ls1021atsn_qspi_defconfig |  1 +
 configs/ls1021atsn_sdcard_defconfig   |  1 +
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig  |  1 +
 configs/ls1021atwr_nor_defconfig  |  1 +
 configs/ls1021atwr_nor_lpuart_defconfig   |  1 +
 configs/ls1021atwr_qspi_defconfig |  1 +
 ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig |  1 +
 configs/ls1021atwr_sdcard_ifc_defconfig   |  1 +
 configs/ls1021atwr_sdcard_qspi_defconfig  |  1 +
 drivers/net/fsl_mdio.c| 66 +--
 drivers/net/phy/phy.c |  4 +-
 drivers/net/tsec.c| 50 +-
 include/fsl_mdio.h|  4 +-
 13 files changed, 89 insertions(+), 44 deletions(-)

-- 
2.17.1

[RFC PATCH 1/3] phy: make phy_connect_fixed work with a null mdio bus

[Vladimir Oltean]

From: Vladimir Oltean 

It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.

Signed-off-by: Vladimir Oltean 
---
 drivers/net/phy/phy.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 9a66e62e8974..dcef1aaf2026 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -651,7 +651,7 @@ static struct phy_device *phy_device_create(struct mii_dev 
*bus, int addr,
dev = malloc(sizeof(*dev));
if (!dev) {
printf("Failed to allocate PHY device for %s:%d\n",
-  bus->name, addr);
+  bus ? bus->name : "(null bus)", addr);
return NULL;
}
 
@@ -679,7 +679,7 @@ static struct phy_device *phy_device_create(struct mii_dev 
*bus, int addr,
return NULL;
}
 
-   if (addr >= 0 && addr < PHY_MAX_ADDR)
+   if (addr >= 0 && addr < PHY_MAX_ADDR && phy_id != PHY_FIXED_ID)
bus->phymap[addr] = dev;
 
return dev;
-- 
2.17.1

[PATCH] net: pcnet: fix I/O primitives for memory access

[Daniel Schwierzeck]

Commit 69529c912059 ("net: pcnet: Switch to PCI memory access")
switched from PCI IO access to PCI memory access without updating
the I/O primitives. Contrary to SH, the primitives for memory
access and IO access are implemented differently. Thus doing
memory access with IO port primitives breaks the driver on
MIPS Malta board.

Signed-off-by: Daniel Schwierzeck 

---
Needs to be applied after

[PULL] u-boot-sh/next network cleanup part 1

https://patchwork.ozlabs.org/project/uboot/patch/270da1a6-aa7a-16c6-6642-76a9ea8a7...@denx.de/

 drivers/net/pcnet.c | 34 +++---
 1 file changed, 23 insertions(+), 11 deletions(-)

diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index df82b716a7..8dfcb10a15 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -95,37 +95,49 @@ static pcnet_priv_t *lp;
 
 static u16 pcnet_read_csr(struct eth_device *dev, int index)
 {
-   outw(index, dev->iobase + PCNET_RAP);
-   return inw(dev->iobase + PCNET_RDP);
+   void __iomem *base = (void __iomem *)dev->iobase;
+
+   writew(index, base + PCNET_RAP);
+   return readw(base + PCNET_RDP);
 }
 
 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
 {
-   outw(index, dev->iobase + PCNET_RAP);
-   outw(val, dev->iobase + PCNET_RDP);
+   void __iomem *base = (void __iomem *)dev->iobase;
+
+   writew(index, base + PCNET_RAP);
+   writew(val, base + PCNET_RDP);
 }
 
 static u16 pcnet_read_bcr(struct eth_device *dev, int index)
 {
-   outw(index, dev->iobase + PCNET_RAP);
-   return inw(dev->iobase + PCNET_BDP);
+   void __iomem *base = (void __iomem *)dev->iobase;
+
+   writew(index, base + PCNET_RAP);
+   return readw(base + PCNET_BDP);
 }
 
 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
 {
-   outw(index, dev->iobase + PCNET_RAP);
-   outw(val, dev->iobase + PCNET_BDP);
+   void __iomem *base = (void __iomem *)dev->iobase;
+
+   writew(index, base + PCNET_RAP);
+   writew(val, base + PCNET_BDP);
 }
 
 static void pcnet_reset(struct eth_device *dev)
 {
-   inw(dev->iobase + PCNET_RESET);
+   void __iomem *base = (void __iomem *)dev->iobase;
+
+   readw(base + PCNET_RESET);
 }
 
 static int pcnet_check(struct eth_device *dev)
 {
-   outw(88, dev->iobase + PCNET_RAP);
-   return inw(dev->iobase + PCNET_RAP) == 88;
+   void __iomem *base = (void __iomem *)dev->iobase;
+
+   writew(88, base + PCNET_RAP);
+   return readw(base + PCNET_RAP) == 88;
 }
 
 static int pcnet_init (struct eth_device *dev, bd_t * bis);
-- 
2.26.2

Re: [PATCH v7 16/22] riscv: Enable cpu clock if it is present

[Sean Anderson]

On 5/3/20 3:12 AM, Pragnesh Patel wrote:
> Hi Sean,
> 
>> -Original Message-
>> From: Sean Anderson 
>> Sent: 02 May 2020 23:46
>> To: Pragnesh Patel ; u-boot@lists.denx.de
>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>> bmeng...@gmail.com; Paul Walmsley ;
>> ja...@amarulasolutions.com; Troy Benjegerdes
>> ; anup.pa...@wdc.com; Sagar Kadam
>> ; r...@andestech.com; Lukas Auer
>> 
>> Subject: Re: [PATCH v7 16/22] riscv: Enable cpu clock if it is present
>>
>> [External Email] Do not click links or attachments unless you recognize the
>> sender and know the content is safe
>>
>> On 5/2/20 6:06 AM, Pragnesh Patel wrote:
>>> The cpu clock is probably already enabled if we are executing code
>>> (though we could be executing from a different core). This patch
>>> prevents the cpu clock or its parents from being disabled.
>>>
>>> Signed-off-by: Sean Anderson 
>>
>> If you make substantial changes can you please make a note of it in the
>> commit? I did not sign off on *this* code.
> 
> This patch is copied from your v9 series [1] and I made some changes, so the 
> idea is to
> give credit to everyone who contributed.

That's fine, just please make a note when you make substantial changes.
For example, you could write

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
[set clock frequency from clock-frequency property]
Signed-off-by: Pragnesh Patel 

so it's more clear what changes have been made since this patch was
posted last.

--Sean

[PATCH v4 1/2] drivers: gpio: add broadcom iproc gpio driver support

[Rayagonda Kokatanur]

Add gpio driver support for Broadcom iproc-based socs.

Signed-off-by: Rayagonda Kokatanur 
Signed-off-by: Sheetal Tigadoli 
---
 drivers/gpio/Kconfig  |  11 ++
 drivers/gpio/Makefile |   1 +
 drivers/gpio/iproc_gpio.c | 269 ++
 3 files changed, 281 insertions(+)
 create mode 100644 drivers/gpio/iproc_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 2081520f42..57d2cd2e75 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -135,6 +135,17 @@ config IMX_RGPIO2P
help
  This driver supports i.MX7ULP Rapid GPIO2P controller.
 
+config IPROC_GPIO
+   bool "Broadcom iProc GPIO driver(without pinconf)"
+   default n
+   help
+ The Broadcom iProc based SoCs- Cygnus, NS2, NS3, NSP and Stingray,
+ use the same GPIO Controller IP hence this driver could be used
+ for all.
+
+ The Broadcom iProc based SoCs have multiple GPIO controllers and only
+ the always-ON GPIO controller (CRMU/AON) is supported by this driver.
+
 config HSDK_CREG_GPIO
bool "HSDK CREG GPIO griver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7638259007..5dc5849477 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_CORTINA_GPIO)  += cortina_gpio.o
 obj-$(CONFIG_INTEL_GPIO)   += intel_gpio.o
 obj-$(CONFIG_INTEL_ICH6_GPIO)  += intel_ich6_gpio.o
 obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o
+obj-$(CONFIG_IPROC_GPIO)   += iproc_gpio.o
 obj-$(CONFIG_KIRKWOOD_GPIO)+= kw_gpio.o
 obj-$(CONFIG_KONA_GPIO)+= kona_gpio.o
 obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o
diff --git a/drivers/gpio/iproc_gpio.c b/drivers/gpio/iproc_gpio.c
new file mode 100644
index 00..79ccc58216
--- /dev/null
+++ b/drivers/gpio/iproc_gpio.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier:  GPL-2.0+
+/*
+ * Copyright (C) 2020 Broadcom
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * There are five GPIO bank register. Each bank can configure max of 32 gpios.
+ * BANK0 - gpios 0 to 31
+ * BANK1 - gpios 32 to 63
+ * BANK2 - gpios 64 to 95
+ * BANK3 - gpios 96 to 127
+ * BANK4 - gpios 128 to 150
+ *
+ * Offset difference between consecutive bank register is 0x200
+ */
+#define NGPIO_PER_BANK 32
+#define GPIO_BANK_SIZE 0x200
+#define GPIO_BANK(pin) ((pin) / NGPIO_PER_BANK)
+#define IPROC_GPIO_SHIFT(pin)  ((pin) % NGPIO_PER_BANK)
+#define IPROC_GPIO_REG(pin, reg) (GPIO_BANK_SIZE * GPIO_BANK(pin) + (reg))
+
+/* device register offset */
+#define IPROC_GPIO_DATA_IN_OFFSET   0x00
+#define IPROC_GPIO_DATA_OUT_OFFSET  0x04
+#define IPROC_GPIO_OUT_EN_OFFSET0x08
+
+/**
+ * struct iproc_gpio_pctrl_map - mapping between gpio and pinctrl specfied
+ *  using gpio-ranges parameter in dt.
+ * @gpio_pin:  start of gpio number in gpio-ranges
+ * @pctrl_pin: start of pinctrl number in gpio-ranges
+ * @npins: total number of pins in gpio-ranges
+ * @node:  list node
+ */
+struct iproc_gpio_pctrl_map {
+   u32 gpio_pin;
+   u32 pctrl_pin;
+   u32 npins;
+   struct list_head node;
+};
+
+/**
+ * struct iproc_gpio_pctrl_map - gpio device instance
+ * @pinctrl_dev:pointer to pinctrl device
+ * @gpiomap:   list node having mapping between gpio and pinctrl
+ * @base:  I/O register base address of gpio device
+ * @name:  gpio device name, ex GPIO0, GPIO1
+ * @ngpios:total number of gpios
+ */
+struct iproc_gpio_platdata {
+   struct udevice *pinctrl_dev;
+   struct list_head gpiomap;
+   void __iomem *base;
+   char *name;
+   u32 ngpios;
+};
+
+/**
+ *  iproc_gpio_set_bit - set or clear one bit (corresponding to the GPIO pin)
+ *  in a iproc GPIO register
+ *
+ *  @iproc_gpio: Iproc GPIO device
+ *  @reg: register offset
+ *  @gpio: GPIO pin
+ *  @set: set or clear
+ */
+static inline void iproc_gpio_set_bit(struct iproc_gpio_platdata *plat,
+ u32 reg, u32 gpio, bool set)
+{
+   u32 offset = IPROC_GPIO_REG(gpio, reg);
+   u32 shift = IPROC_GPIO_SHIFT(gpio);
+
+   clrsetbits_le32(plat->base + offset, BIT(shift),
+   (set ? BIT(shift) : 0));
+}
+
+static inline bool iproc_gpio_get_bit(struct iproc_gpio_platdata *plat,
+ u32 reg, u32 gpio)
+{
+   u32 offset = IPROC_GPIO_REG(gpio, reg);
+   u32 shift = IPROC_GPIO_SHIFT(gpio);
+
+   return readl(plat->base + offset) & BIT(shift);
+}
+
+static u32 iproc_get_pctrl_from_gpio(struct iproc_gpio_platdata *plat, u32 
gpio)
+{
+   struct iproc_gpio_pctrl_map *range = NULL;
+   struct list_head *pos, *tmp;
+   u32 ret = 0;
+
+   list_for_each_safe(pos, tmp, >gpiomap) {
+   range = list_entry(pos, struct iproc_gpio_pctrl_map, node);
+   if (gpio == range->gpio_pin ||

[PATCH v4 2/2] gpio: do not include on TARGET_BCMNS3

[Rayagonda Kokatanur]

As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include  for
arch bcmns3.

Signed-off-by: Rayagonda Kokatanur 
Reviewed-by: Simon Glass 
---
 arch/arm/include/asm/gpio.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 333e407b66..c067eeb649 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -6,7 +6,7 @@
!defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \
!defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \
!defined(CONFIG_ARCH_LS1046A) && !defined(CONFIG_ARCH_U8500) && \
-   !defined(CONFIG_CORTINA_PLATFORM)
+   !defined(CONFIG_CORTINA_PLATFORM) && !defined(CONFIG_TARGET_BCMNS3)
 #include 
 #endif
 #include 
-- 
2.17.1

[PATCH v4 0/2] add brcm iproc gpio driver

[Rayagonda Kokatanur]

Add support for broadcom iproc gpio driver.

Changes from v3:
 -Address review comments from Simon Glass,
  Rearrange header file,
  Add struct comment taking about members,
  Use clrsetbits_le32(),
  Add new line before return etc.
 
Changes from v2:
 -remove ununsed variable "node" in iproc_get_gpio_pctrl_mapping()
  func to fix compilation warning.

Changes from v1:
 -Address review comments from Simon Glass,
  Use dev_read_...() instead of fdtdec_...().

Rayagonda Kokatanur (2):
  drivers: gpio: add broadcom iproc gpio driver support
  gpio: do not include  on TARGET_BCMNS3

 arch/arm/include/asm/gpio.h |   2 +-
 drivers/gpio/Kconfig|  11 ++
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/iproc_gpio.c   | 269 
 4 files changed, 282 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpio/iproc_gpio.c

-- 
2.17.1

Re: [PATCHv2 3/3] net: tsec: Access TBI PHY through the corresponding MII

[Vladimir Oltean]

On Sun, 3 May 2020 at 17:53, Zhiqiang Hou  wrote:
>
> From: Hou Zhiqiang 
>
> When an eTSEC is configured to use TBI, configuration of the
> TBI is done through the MIIM registers for that eTSEC.
> For example, if a TBI interface is required on eTSEC2, then
> the MIIM registers starting at offset 0x2_5520 are used to
> configure it.
>
> Fixes: 9a1d6af55ecd ("net: tsec: Add driver model ethernet support")
> Signed-off-by: Hou Zhiqiang 
> Reviewed-by: Vladimir Oltean 
> Tested-by: Vladimir Oltean 
> ---

Looks good, thanks!
Out of curiosity, are you also working on DM_MDIO for the tsec driver?
Some of this code should go away when we do that conversion.

> V2:
>  - Added error message for getting the internal TBI PHY MII reg.
>  - Only try to get TBI PHY MII reg under the condition "tbi-handle".
>
>  drivers/net/tsec.c | 25 +
>  1 file changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
> index 541f964d2e..842cddf229 100644
> --- a/drivers/net/tsec.c
> +++ b/drivers/net/tsec.c
> @@ -789,6 +789,7 @@ int tsec_probe(struct udevice *dev)
>  {
> struct eth_pdata *pdata = dev_get_platdata(dev);
> struct tsec_private *priv = dev_get_priv(dev);
> +   struct tsec_mii_mng __iomem *ext_phyregs_mii;
> struct ofnode_phandle_args phandle_args;
> u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
> struct fsl_pq_mdio_info mdio_info;
> @@ -822,14 +823,30 @@ int tsec_probe(struct udevice *dev)
> return -ENOENT;
> }
>
> -   priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
> - MAP_NOCACHE);
> +   ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
> + MAP_NOCACHE);
>
> ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
>  _args);
> -   if (ret == 0)
> +   if (ret == 0) {
> ofnode_read_u32(phandle_args.node, "reg", );
>
> +   parent = ofnode_get_parent(phandle_args.node);
> +   if (!ofnode_valid(parent)) {
> +   printf("No parent node for TBI PHY?\n");
> +   return -ENOENT;
> +   }
> +
> +   reg = ofnode_get_addr_index(parent, 0);
> +   if (reg == FDT_ADDR_T_NONE) {
> +   printf("No 'reg' property of MII for TBI PHY\n");
> +   return -ENOENT;
> +   }
> +
> +   priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET,
> + 0, MAP_NOCACHE);
> +   }
> +
> priv->tbiaddr = tbiaddr;
>
> phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
> @@ -846,7 +863,7 @@ int tsec_probe(struct udevice *dev)
> if (priv->interface == PHY_INTERFACE_MODE_SGMII)
> priv->flags |= TSEC_SGMII;
>
> -   mdio_info.regs = priv->phyregs_sgmii;
> +   mdio_info.regs = ext_phyregs_mii;
> mdio_info.name = (char *)dev->name;
> ret = fsl_pq_mdio_init(NULL, _info);
> if (ret)
> --
> 2.17.1
>

Regards,
-Vladimir

[PATCH] sh: Enable ffunction-sections and fdata-sections

[Marek Vasut]

Enable these two options to let compiler eliminate unused code.
On R2Dplus, this results in considerable amount of saved space:

  textdata bss dec hex filename
  - 266580   13196   39076  318852   4dd84 u-boot
  + 220214   12797   38745  271756   4258c u-boot

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
Cc: Tom Rini 
---
 arch/sh/config.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/sh/config.mk b/arch/sh/config.mk
index 6ef44638ab..85dab383e7 100644
--- a/arch/sh/config.mk
+++ b/arch/sh/config.mk
@@ -13,6 +13,6 @@ LDFLAGS_STANDALONE += -EB
 endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
-PLATFORM_RELFLAGS += -fpic
+PLATFORM_RELFLAGS += -fpic -ffunction-sections -fdata-sections
 LDFLAGS_FINAL = --gc-sections
 PLATFORM_RELFLAGS += -ffixed-r13
-- 
2.25.1

Re: [PATCH V2 resend 1/4] imx: add module fuse support

[Stefano Babic]

Hi Peng,

On 01.05.20 16:08, Peng Fan wrote:
> There are different parts from one SoC. Take i.MX6ULL for example,
> some part might not have ENET, some might have; some might not have
> USB, some might have. The information could be got from OCOTP,
> to make one image support the different parts, we need runtime
> disable linux kernel dts node and uboot driver probe if the
> corresponding module not exists in the part.
> 

I admit I was not convinced when you post it the first time, mainly due
to add another blob as database into the code (mx6_fuse_descs). But I
needed maybe some timeto think about it...

I like the idea to get most features directly from the processor, and
yes we can do it via OTP.

Reviewed-by : Stefano Babic 

Best regards,
Stefano

> Signed-off-by: Peng Fan 
> ---
>  arch/arm/include/asm/mach-imx/module_fuse.h | 127 +++
>  arch/arm/include/asm/mach-imx/sys_proto.h   |   1 +
>  arch/arm/mach-imx/Kconfig   |   7 +
>  arch/arm/mach-imx/mx6/Makefile  |   1 +
>  arch/arm/mach-imx/mx6/module_fuse.c | 322 
> 
>  5 files changed, 458 insertions(+)
>  create mode 100644 arch/arm/include/asm/mach-imx/module_fuse.h
>  create mode 100644 arch/arm/mach-imx/mx6/module_fuse.c
> 
> diff --git a/arch/arm/include/asm/mach-imx/module_fuse.h 
> b/arch/arm/include/asm/mach-imx/module_fuse.h
> new file mode 100644
> index 00..a46fc3f1f8
> --- /dev/null
> +++ b/arch/arm/include/asm/mach-imx/module_fuse.h
> @@ -0,0 +1,127 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +#ifndef __MODULE_FUSE_H__
> +#define __MODULE_FUSE_H__
> +
> +enum fuse_module_type {
> + MODULE_TSC,
> + MODULE_ADC1,
> + MODULE_ADC2,
> + MODULE_SIM1,
> + MODULE_SIM2,
> + MODULE_FLEXCAN1,
> + MODULE_FLEXCAN2,
> + MODULE_SPDIF,
> + MODULE_EIM,
> + MODULE_SD1,
> + MODULE_SD2,
> + MODULE_SD3,
> + MODULE_SD4,
> + MODULE_QSPI1,
> + MODULE_QSPI2,
> + MODULE_GPMI,
> + MODULE_APBHDMA,
> + MODULE_LCDIF,
> + MODULE_PXP,
> + MODULE_CSI,
> + MODULE_ENET1,
> + MODULE_ENET2,
> + MODULE_CAAM,
> + MODULE_USB_OTG1,
> + MODULE_USB_OTG2,
> + MODULE_SAI2,
> + MODULE_SAI3,
> + MODULE_BEE,
> + MODULE_UART1,
> + MODULE_UART2,
> + MODULE_UART3,
> + MODULE_UART4,
> + MODULE_UART5,
> + MODULE_UART6,
> + MODULE_UART7,
> + MODULE_UART8,
> + MODULE_PWM5,
> + MODULE_PWM6,
> + MODULE_PWM7,
> + MODULE_PWM8,
> + MODULE_ECSPI1,
> + MODULE_ECSPI2,
> + MODULE_ECSPI3,
> + MODULE_ECSPI4,
> + MODULE_ECSPI5,
> + MODULE_I2C1,
> + MODULE_I2C2,
> + MODULE_I2C3,
> + MODULE_I2C4,
> + MODULE_GPT1,
> + MODULE_GPT2,
> + MODULE_EPIT1,
> + MODULE_EPIT2,
> + MODULE_EPDC,
> + MODULE_ESAI,
> + MODULE_DCP,
> + MODULE_DCP_CRYPTO,
> +};
> +
> +struct fuse_entry_desc {
> + enum fuse_module_type module;
> + const char *node_path;
> + u32 fuse_word_offset;
> + u32 fuse_bit_offset;
> + u32 status;
> +};
> +
> +#if !CONFIG_IS_ENABLED(IMX_MODULE_FUSE)
> +static inline u32 check_module_fused(enum fuse_module_type module)
> +{
> + return 0;
> +};
> +
> +static inline u32 esdhc_fused(ulong base_addr)
> +{
> + return 0;
> +};
> +
> +static inline u32 ecspi_fused(ulong base_addr)
> +{
> + return 0;
> +};
> +
> +static inline u32 uart_fused(ulong base_addr)
> +{
> + return 0;
> +};
> +
> +static inline u32 usb_fused(ulong base_addr)
> +{
> + return 0;
> +};
> +
> +static inline u32 qspi_fused(ulong base_addr)
> +{
> + return 0;
> +};
> +
> +static inline u32 i2c_fused(ulong base_addr)
> +{
> + return 0;
> +};
> +
> +static inline u32 enet_fused(ulong base_addr)
> +{
> + return 0;
> +};
> +#else
> +u32 check_module_fused(enum fuse_module_type module);
> +u32 esdhc_fused(ulong base_addr);
> +u32 ecspi_fused(ulong base_addr);
> +u32 uart_fused(ulong base_addr);
> +u32 usb_fused(ulong base_addr);
> +u32 qspi_fused(ulong base_addr);
> +u32 i2c_fused(ulong base_addr);
> +u32 enet_fused(ulong base_addr);
> +#endif
> +#endif /* __MODULE_FUSE_H__ */
> diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
> b/arch/arm/include/asm/mach-imx/sys_proto.h
> index ba930a2088..48ce4b1e18 100644
> --- a/arch/arm/include/asm/mach-imx/sys_proto.h
> +++ b/arch/arm/include/asm/mach-imx/sys_proto.h
> @@ -9,6 +9,7 @@
>  
>  #include 
>  #include 
> +#include 
>  #include 
>  #include "../arch-imx/cpu.h"
>  
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 329149900a..396f7c9288 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -27,6 +27,13 @@ config IMX_BOOTAUX
>   help
> bootaux [addr] to boot auxiliary core.
>  
> +config IMX_MODULE_FUSE
> + bool "i.MX Module Fuse"
> + depends on ARCH_MX6
> + help
> +   i.MX module fuse to runtime disable some 

Re: [PATCH 10/13] imx: load calibration parameters from fuse for i.MX8MP

[Fabio Estevam]

Hi Peng and Ye Li,

On Sun, May 3, 2020 at 10:57 AM Peng Fan  wrote:
>
> From: Ye Li 
>
> i.MX8MP thermal which has two probes and supports temperature range
> from -40 to 125.  The driver still uses default 1p HW
> calibration at 25C and loads calibration parameters from fuse.
>
> Reviewed-by: Peng Fan 
> Signed-off-by: Ye Li 
> Signed-off-by: Peng Fan 

Are you able to boot an NXP 5.4.3 kernel on a i.MX8MP EVK board?

I am getting a kernel hang right after the serial console is probed:
https://pastebin.com/3AtvJqWS

Any suggestions?

I am using ATF from 5.4.3, firmware version is 8.6 and I pass 'export
ATF_LOAD_ADDR=0x96'.

Any ideas?

Thanks

Re: [PATCH 2/2] net: pcnet: Switch to PCI memory access

[Marek Vasut]

On 5/2/20 5:03 PM, Daniel Schwierzeck wrote:
> 
> 
> Am 02.05.20 um 17:00 schrieb Daniel Schwierzeck:
>> Hi Marek,
>>
>> Am 18.04.20 um 05:15 schrieb Marek Vasut:
>>> Replace the PCI IO access with PCI memory access, the card
>>> supports both, but the former does not work with QEMU SH4.
>>>
>>> Signed-off-by: Marek Vasut 
>>> Cc: Daniel Schwierzeck 
>>> Cc: Joe Hershberger 
>>> ---
>>> Note: It would be good to test this on the mips malta
>>> ---
>>>  drivers/net/pcnet.c | 6 +++---
>>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>>
> ...
>>
>>
>> Contrary to SH there is a difference between memory access and IO access
>> on MIPS. So you have to replace also all inw()/outw() with
>> readw()/writew() like so:
>>
>>  static u16 pcnet_read_csr(struct eth_device *dev, int index)
>>  {
>> -   writew(index, dev->iobase + PCNET_RAP);
>> -   return readw(dev->iobase + PCNET_RDP);
>> +   void __iomem *base = (void __iomem *)dev->iobase;
>> +   writew(index, base + PCNET_RAP);
>> +   return readw(base + PCNET_RDP);
>>  }
> 
> sorry wrong diff, I meant:
> 
>  static u16 pcnet_read_csr(struct eth_device *dev, int index)
>  {
> -   outw(index, dev->iobase + PCNET_RAP);
> -   return inw(dev->iobase + PCNET_RDP);
> +   void __iomem *base = (void __iomem *)dev->iobase;
> +   writew(index, base + PCNET_RAP);
> +   return readw(base + PCNET_RDP);
>  }
I'm CCing Tom. He didn't pick the PR yet.
If you want to send it as separate patch, fine by me, maybe Tom can pick
that one right after the PR ; or I can squash it into the PR. I think
the former would be easier.

-- 
Best regards,
Marek Vasut

[PATCHv2 3/3] net: tsec: Access TBI PHY through the corresponding MII

[Zhiqiang Hou]

From: Hou Zhiqiang 

When an eTSEC is configured to use TBI, configuration of the
TBI is done through the MIIM registers for that eTSEC.
For example, if a TBI interface is required on eTSEC2, then
the MIIM registers starting at offset 0x2_5520 are used to
configure it.

Fixes: 9a1d6af55ecd ("net: tsec: Add driver model ethernet support")
Signed-off-by: Hou Zhiqiang 
Reviewed-by: Vladimir Oltean 
Tested-by: Vladimir Oltean 
---
V2:
 - Added error message for getting the internal TBI PHY MII reg.
 - Only try to get TBI PHY MII reg under the condition "tbi-handle".

 drivers/net/tsec.c | 25 +
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 541f964d2e..842cddf229 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -789,6 +789,7 @@ int tsec_probe(struct udevice *dev)
 {
struct eth_pdata *pdata = dev_get_platdata(dev);
struct tsec_private *priv = dev_get_priv(dev);
+   struct tsec_mii_mng __iomem *ext_phyregs_mii;
struct ofnode_phandle_args phandle_args;
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
struct fsl_pq_mdio_info mdio_info;
@@ -822,14 +823,30 @@ int tsec_probe(struct udevice *dev)
return -ENOENT;
}
 
-   priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
- MAP_NOCACHE);
+   ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
+ MAP_NOCACHE);
 
ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
 _args);
-   if (ret == 0)
+   if (ret == 0) {
ofnode_read_u32(phandle_args.node, "reg", );
 
+   parent = ofnode_get_parent(phandle_args.node);
+   if (!ofnode_valid(parent)) {
+   printf("No parent node for TBI PHY?\n");
+   return -ENOENT;
+   }
+
+   reg = ofnode_get_addr_index(parent, 0);
+   if (reg == FDT_ADDR_T_NONE) {
+   printf("No 'reg' property of MII for TBI PHY\n");
+   return -ENOENT;
+   }
+
+   priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET,
+ 0, MAP_NOCACHE);
+   }
+
priv->tbiaddr = tbiaddr;
 
phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
@@ -846,7 +863,7 @@ int tsec_probe(struct udevice *dev)
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
priv->flags |= TSEC_SGMII;
 
-   mdio_info.regs = priv->phyregs_sgmii;
+   mdio_info.regs = ext_phyregs_mii;
mdio_info.name = (char *)dev->name;
ret = fsl_pq_mdio_init(NULL, _info);
if (ret)
-- 
2.17.1

[PATCHv2 2/3] net: tsec: Access eTSEC registers using virtual address

[Zhiqiang Hou]

From: Hou Zhiqiang 

The current code accesses eTSEC registers using physical
address directly, it's not correct, though no problem on
current platforms. It won't work on platforms, which does
not support 1:1 virtual-physical address map.

Signed-off-by: Hou Zhiqiang 
Reviewed-by: Vladimir Oltean 
Tested-by: Vladimir Oltean 
---
V2:
 - Added error message for getting the external PHY MII reg.

 drivers/net/tsec.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index f85cdcb97e..541f964d2e 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -798,7 +798,7 @@ int tsec_probe(struct udevice *dev)
int ret;
 
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
-   priv->regs = (struct tsec *)pdata->iobase;
+   priv->regs = dev_remap_addr(dev);
 
if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
   _args)) {
@@ -817,8 +817,13 @@ int tsec_probe(struct udevice *dev)
}
 
reg = ofnode_get_addr_index(parent, 0);
-   priv->phyregs_sgmii = (struct tsec_mii_mng *)
-   (reg + TSEC_MDIO_REGS_OFFSET);
+   if (reg == FDT_ADDR_T_NONE) {
+   printf("No 'reg' property of MII for external PHY\n");
+   return -ENOENT;
+   }
+
+   priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
+ MAP_NOCACHE);
 
ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
 _args);
-- 
2.17.1

[PATCHv2 1/3] doc: dt-bindings: tsec: Correct the Ethernet port compatible string

[Zhiqiang Hou]

From: Hou Zhiqiang 

Change the compatible string to "fsl,etsec2" for the Ethernet ports,
which is used in the current driver's match table.

Fixes: 69a00875e3db ("doc: dt-bindings: Describe Freescale TSEC ethernet 
controller")
Signed-off-by: Hou Zhiqiang 
Acked-by: Vladimir Oltean 
---
V2:
 - No change.

 doc/device-tree-bindings/net/fsl-tsec-phy.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt 
b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
index 59989e3b09..8e8574bc97 100644
--- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
+++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
@@ -2,7 +2,7 @@
 
 Properties:
 
-  - compatible : Should be "fsl,tsec"
+  - compatible : Should be "fsl,etsec2"
   - reg : Offset and length of the register set for the device
   - phy-handle : See ethernet.txt file in the same directory.
   - phy-connection-type : See ethernet.txt file in the same directory. This
@@ -12,7 +12,7 @@ Properties:
 
 Example:
ethernet@24000 {
-   compatible = "fsl,tsec";
+   compatible = "fsl,etsec2";
reg = <0x24000 0x1000>;
phy-handle = <>;
phy-connection-type = "sgmii";
-- 
2.17.1

[PATCHv2 0/3] net: tsec: Fix issues of DM driver

[Zhiqiang Hou]

From: Hou Zhiqiang 

This patch set is to fix some issues of eTSEC DM driver.

Hou Zhiqiang (3):
  doc: dt-bindings: tsec: Correct the Ethernet port compatible string
  net: tsec: Access eTSEC registers using virtual address
  net: tsec: Access TBI PHY through the corresponding MII

 doc/device-tree-bindings/net/fsl-tsec-phy.txt |  4 +--
 drivers/net/tsec.c| 32 ---
 2 files changed, 29 insertions(+), 7 deletions(-)

-- 
2.17.1

RE: [PATCH 3/3] net: tsec: Access TBI PHY through the corresponding MII

[Z.q. Hou]

Hi Vladimir,

Thanks a lot for your comments!

> -Original Message-
> From: Vladimir Oltean 
> Sent: 2020年5月3日 22:07
> To: Z.q. Hou 
> Cc: u-boot ; Joe Hershberger
> ; Bin Meng ; Priyanka
> Jain 
> Subject: Re: [PATCH 3/3] net: tsec: Access TBI PHY through the
> corresponding MII
> 
> Hi Zhiqiang,
> 
> On Sun, 3 May 2020 at 16:49, Z.q. Hou  wrote:
> >
> > Hi Vladimir,
> >
> > Thanks a lot for your review and test!
> >
> > > -Original Message-
> > > From: Vladimir Oltean 
> > > Sent: 2020年5月3日 19:35
> > > To: Z.q. Hou 
> > > Cc: u-boot ; Joe Hershberger
> > > ; Bin Meng ;
> Priyanka
> > > Jain 
> > > Subject: Re: [PATCH 3/3] net: tsec: Access TBI PHY through the
> > > corresponding MII
> > >
> > > On Sun, 3 May 2020 at 09:28, Zhiqiang Hou 
> > > wrote:
> > > >
> > > > From: Hou Zhiqiang 
> > > >
> > > > When an eTSEC is configured to use TBI, configuration of the TBI
> > > > is done through the MIIM registers for that eTSEC.
> > > > For example, if a TBI interface is required on eTSEC2, then the
> > > > MIIM registers starting at offset 0x2_5520 are used to configure it.
> > > >
> > > > Fixes: 9a1d6af55ecd ("net: tsec: Add driver model ethernet
> > > > support")
> > > > Signed-off-by: Hou Zhiqiang 
> > > > ---
> > > >  drivers/net/tsec.c | 17 ++---
> > > >  1 file changed, 14 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index
> > > > ce41aec5cf..31056f3117 100644
> > > > --- a/drivers/net/tsec.c
> > > > +++ b/drivers/net/tsec.c
> > > > @@ -789,6 +789,7 @@ int tsec_probe(struct udevice *dev)  {
> > > > struct eth_pdata *pdata = dev_get_platdata(dev);
> > > > struct tsec_private *priv = dev_get_priv(dev);
> > > > +   struct tsec_mii_mng __iomem *ext_phyregs_mii;
> > > > struct ofnode_phandle_args phandle_args;
> > > > u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
> > > > struct fsl_pq_mdio_info mdio_info; @@ -820,8 +821,8 @@
> int
> > > > tsec_probe(struct udevice *dev)
> > > > if (reg == FDT_ADDR_T_NONE)
> > > > return -ENOENT;
> > > >
> > > > -   priv->phyregs_sgmii = map_physmem(reg +
> > > TSEC_MDIO_REGS_OFFSET, 0,
> > > > - MAP_NOCACHE);
> > > > +   ext_phyregs_mii = map_physmem(reg +
> > > TSEC_MDIO_REGS_OFFSET, 0,
> > > > + MAP_NOCACHE);
> > > >
> > > > ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL,
> > > > 0,
> > > 0,
> > > >  _args);
> @@
> > > -830,6
> > > > +831,16 @@ int tsec_probe(struct udevice *dev)
> > > >
> > > > priv->tbiaddr = tbiaddr;
> > > >
> > > > +   parent = ofnode_get_parent(phandle_args.node);
> > > > +   if (!ofnode_valid(parent)) {
> > > > +   printf("No parent node for TBI PHY?\n");
> > > > +   return -ENOENT;
> > > > +   }
> > > > +
> > > > +   reg = ofnode_get_addr_index(parent, 0);
> > >
> > > Missing a check
> > >
> > > if (reg == FDT_ADDR_T_NONE)
> > > return -ENOENT;
> > >
> > > here?
> >
> > Yes, will fix in v2.
> >
> > Thanks,
> > Zhiqiang
> 
> Actually since the TBI PHY is optional (not present on RGMII interfaces and
> such), I don't believe you should return an error, but just skip the
> phyregs_sgmii initialization.

Correct, I just realized it.

Thanks,
Zhiqiang

> 
> >
> > >
> > > > +   priv->phyregs_sgmii = map_physmem(reg +
> > > TSEC_MDIO_REGS_OFFSET, 0,
> > > > + MAP_NOCACHE);
> > > > +
> > > > phy_mode = dev_read_prop(dev, "phy-connection-type",
> NULL);
> > > > if (phy_mode)
> > > > pdata->phy_interface =
> > > > phy_get_interface_by_name(phy_mode);
> > > > @@ -844,7 +855,7 @@ int tsec_probe(struct udevice *dev)
> > > > if (priv->interface == PHY_INTERFACE_MODE_SGMII)
> > > > priv->flags |= TSEC_SGMII;
> > > >
> > > > -   mdio_info.regs = priv->phyregs_sgmii;
> > > > +   mdio_info.regs = ext_phyregs_mii;
> > > > mdio_info.name = (char *)dev->name;
> > > > ret = fsl_pq_mdio_init(NULL, _info);
> > > > if (ret)
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > With that:
> > >
> > > Reviewed-by: Vladimir Oltean 
> > > Tested-by: Vladimir Oltean 
> > >
> > > (on LS1021A)
> > >
> > > Thanks!
> > > -Vladimir
> 
> Thanks,
> -Vladimir

[PATCH 1/1] efi_loader: correct comments for efi_status_t

[Heinrich Schuchardt]

EFI_STATUS is unsigned (UINTN). Hence it cannot be negative.
Correct comments for 'Return:'.

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_setup.c | 2 +-
 lib/efi_loader/efi_signature.c | 2 +-
 lib/efi_loader/efi_variable.c  | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index 1b648c8467..65739aca49 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -86,7 +86,7 @@ out:
 /**
  * efi_init_secure_boot - initialize secure boot state
  *
- * Return: EFI_SUCCESS on success, status code (negative) on error
+ * Return: status code
  */
 static efi_status_t efi_init_secure_boot(void)
 {
diff --git a/lib/efi_loader/efi_signature.c b/lib/efi_loader/efi_signature.c
index 4ad818d5ee..adcb8c9cca 100644
--- a/lib/efi_loader/efi_signature.c
+++ b/lib/efi_loader/efi_signature.c
@@ -528,7 +528,7 @@ out:
  * pointed to by @regs. If @nocheck is false, overlapping among entries
  * will be checked first.
  *
- * Return: 0 on success, status code (negative) on error
+ * Return: status code
  */
 efi_status_t efi_image_region_add(struct efi_image_regions *regs,
  const void *start, const void *end,
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index b9c2e4ebf6..58f8fae358 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -230,7 +230,7 @@ err:
  * Those variables are *read-only* for users, efi_set_variable_common()
  * is called here.
  *
- * Return: EFI_SUCCESS on success, status code (negative) on error
+ * Return: status code
  */
 static efi_status_t efi_transfer_secure_state(enum efi_secure_mode mode)
 {
@@ -284,7 +284,7 @@ err:
 /**
  * efi_init_secure_state - initialize secure boot state
  *
- * Return: EFI_SUCCESS on success, status code (negative) on error
+ * Return: status code
  */
 static efi_status_t efi_init_secure_state(void)
 {
@@ -438,7 +438,7 @@ out:
  * attributes and signed time will also be returned in @env_attr and @time,
  * respectively.
  *
- * Return: EFI_SUCCESS on success, status code (negative) on error
+ * Return: status code
  */
 static efi_status_t efi_variable_authenticate(u16 *variable,
  const efi_guid_t *vendor,
--
2.26.2

[PATCH 1/1] efi_loader: eliminate efi_set_(non)volatile_variable

[Heinrich Schuchardt]

Eliminate superfluous functions efi_set_volatile_variable() and
efi_set_nonvolatile_variable().

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_variable.c | 141 +-
 1 file changed, 37 insertions(+), 104 deletions(-)

diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index ceb6b17b00..b9c2e4ebf6 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -169,12 +169,12 @@ static const char *parse_attr(const char *str, u32 
*attrp, u64 *timep)
return str;
 }

-static efi_status_t efi_set_variable_internal(u16 *variable_name,
- const efi_guid_t *vendor,
- u32 attributes,
- efi_uintn_t data_size,
- const void *data,
- bool ro_check);
+static efi_status_t efi_set_variable_common(u16 *variable_name,
+   const efi_guid_t *vendor,
+   u32 attributes,
+   efi_uintn_t data_size,
+   const void *data,
+   bool ro_check);

 /**
  * efi_set_secure_state - modify secure boot state variables
@@ -196,35 +196,28 @@ static efi_status_t efi_set_secure_state(int sec_boot, 
int setup_mode,
attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS |
 EFI_VARIABLE_RUNTIME_ACCESS |
 READ_ONLY;
-   ret = efi_set_variable_internal(L"SecureBoot",
-   _global_variable_guid,
-   attributes,
-   sizeof(sec_boot), _boot,
-   false);
+   ret = efi_set_variable_common(L"SecureBoot", _global_variable_guid,
+ attributes, sizeof(sec_boot), _boot,
+ false);
if (ret != EFI_SUCCESS)
goto err;

-   ret = efi_set_variable_internal(L"SetupMode",
-   _global_variable_guid,
-   attributes,
-   sizeof(setup_mode), _mode,
-   false);
+   ret = efi_set_variable_common(L"SetupMode", _global_variable_guid,
+ attributes, sizeof(setup_mode),
+ _mode, false);
if (ret != EFI_SUCCESS)
goto err;

-   ret = efi_set_variable_internal(L"AuditMode",
-   _global_variable_guid,
-   attributes,
-   sizeof(audit_mode), _mode,
-   false);
+   ret = efi_set_variable_common(L"AuditMode", _global_variable_guid,
+ attributes, sizeof(audit_mode),
+ _mode, false);
if (ret != EFI_SUCCESS)
goto err;

-   ret = efi_set_variable_internal(L"DeployedMode",
-   _global_variable_guid,
-   attributes,
-   sizeof(deployed_mode), _mode,
-   false);
+   ret = efi_set_variable_common(L"DeployedMode",
+ _global_variable_guid, attributes,
+ sizeof(deployed_mode), _mode,
+ false);
 err:
return ret;
 }
@@ -234,7 +227,7 @@ err:
  * @mode:  new state
  *
  * Depending on @mode, secure boot related variables are updated.
- * Those variables are *read-only* for users, efi_set_variable_internal()
+ * Those variables are *read-only* for users, efi_set_variable_common()
  * is called here.
  *
  * Return: EFI_SUCCESS on success, status code (negative) on error
@@ -252,11 +245,10 @@ static efi_status_t efi_transfer_secure_state(enum 
efi_secure_mode mode)

efi_secure_boot = true;
} else if (mode == EFI_MODE_AUDIT) {
-   ret = efi_set_variable_internal(
-   L"PK", _global_variable_guid,
-   EFI_VARIABLE_BOOTSERVICE_ACCESS |
-   EFI_VARIABLE_RUNTIME_ACCESS,
-   0, NULL, false);
+   ret = efi_set_variable_common(L"PK", _global_variable_guid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ 0, NULL, false);
 

[PATCH V2 7/8] fec: Move imx_get_mac_from_fuse declare to imx file

[Peng Fan]

From: Ye Li 

imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp,
we have two different ENET controllers and both need to call this
function. So decouple its declare from fec driver.

Reviewed-by: Fugang Duan 
Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 arch/arm/include/asm/mach-imx/sys_proto.h | 2 ++
 drivers/net/fec_mxc.h | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 77799f0eba..48ce4b1e18 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -189,4 +189,6 @@ unsigned long call_imx_sip(unsigned long id, unsigned long 
reg0,
 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
unsigned long *reg1, unsigned long reg2,
unsigned long reg3);
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 #endif
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 159aec8967..18f7c727db 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -271,8 +271,6 @@ struct fec_priv {
u32 clk_rate;
 };
 
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
-
 /**
  * @brief Numbers of buffer descriptors for receiving
  *
-- 
2.16.4

[PATCH V2 5/8] net: dwc_eth_qos: add dwc eqos for imx support

[Peng Fan]

From: Fugang Duan 

Add dwc eqos for imx support.

Reviewed-by: Ye Li 
Signed-off-by: Fugang Duan 
Signed-off-by: Peng Fan 
---
 drivers/net/dwc_eth_qos.c | 187 ++
 1 file changed, 173 insertions(+), 14 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index dc2299dd69..3cdc6f1ae9 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -81,6 +81,7 @@ struct eqos_mac_regs {
 #define EQOS_MAC_CONFIGURATION_PS  BIT(15)
 #define EQOS_MAC_CONFIGURATION_FES BIT(14)
 #define EQOS_MAC_CONFIGURATION_DM  BIT(13)
+#define EQOS_MAC_CONFIGURATION_LM  BIT(12)
 #define EQOS_MAC_CONFIGURATION_TE  BIT(1)
 #define EQOS_MAC_CONFIGURATION_RE  BIT(0)
 
@@ -102,11 +103,19 @@ struct eqos_mac_regs {
 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK  0xff
 
+#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT  8
+#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT   2
+#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
+#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT  0
+
 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT  6
 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK   0x1f
 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT  0
 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK   0x1f
 
+#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
+#define EQOS_MAC_HW_FEATURE3_ASP_MASK  0x3
+
 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT16
 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
@@ -154,6 +163,8 @@ struct eqos_mtl_regs {
 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK  0x3f
 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC  BIT(7)
 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF   BIT(5)
+#define EQOS_MTL_RXQ0_OPERATION_MODE_FEP   BIT(4)
+#define EQOS_MTL_RXQ0_OPERATION_MODE_FUP   BIT(3)
 
 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK  0x7fff
@@ -368,7 +379,7 @@ static void eqos_inval_desc_tegra186(void *desc)
 #endif
 }
 
-static void eqos_inval_desc_stm32(void *desc)
+static void eqos_inval_desc_generic(void *desc)
 {
 #ifndef CONFIG_SYS_NONCACHED_MEMORY
unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
@@ -386,7 +397,7 @@ static void eqos_flush_desc_tegra186(void *desc)
 #endif
 }
 
-static void eqos_flush_desc_stm32(void *desc)
+static void eqos_flush_desc_generic(void *desc)
 {
 #ifndef CONFIG_SYS_NONCACHED_MEMORY
unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
@@ -405,7 +416,7 @@ static void eqos_inval_buffer_tegra186(void *buf, size_t 
size)
invalidate_dcache_range(start, end);
 }
 
-static void eqos_inval_buffer_stm32(void *buf, size_t size)
+static void eqos_inval_buffer_generic(void *buf, size_t size)
 {
unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
unsigned long end = roundup((unsigned long)buf + size,
@@ -419,7 +430,7 @@ static void eqos_flush_buffer_tegra186(void *buf, size_t 
size)
flush_cache((unsigned long)buf, size);
 }
 
-static void eqos_flush_buffer_stm32(void *buf, size_t size)
+static void eqos_flush_buffer_generic(void *buf, size_t size)
 {
unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
unsigned long end = roundup((unsigned long)buf + size,
@@ -522,6 +533,7 @@ static int eqos_mdio_write(struct mii_dev *bus, int 
mdio_addr, int mdio_devad,
 
 static int eqos_start_clks_tegra186(struct udevice *dev)
 {
+#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
 
@@ -562,10 +574,12 @@ static int eqos_start_clks_tegra186(struct udevice *dev)
pr_err("clk_enable(clk_tx) failed: %d", ret);
goto err_disable_clk_ptp_ref;
}
+#endif
 
debug("%s: OK\n", __func__);
return 0;
 
+#ifdef CONFIG_CLK
 err_disable_clk_ptp_ref:
clk_disable(>clk_ptp_ref);
 err_disable_clk_rx:
@@ -577,10 +591,12 @@ err_disable_clk_slave_bus:
 err:
debug("%s: FAILED: %d\n", __func__, ret);
return ret;
+#endif
 }
 
 static int eqos_start_clks_stm32(struct udevice *dev)
 {
+#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
 
@@ -611,10 +627,12 @@ static int eqos_start_clks_stm32(struct udevice *dev)
goto err_disable_clk_tx;
}
}
+#endif
 
debug("%s: OK\n", __func__);
return 0;
 
+#ifdef CONFIG_CLK
 err_disable_clk_tx:
clk_disable(>clk_tx);
 err_disable_clk_rx:
@@ -624,10 +642,17 @@ err_disable_clk_master_bus:
 err:
debug("%s: FAILED: %d\n", 

[PATCH V2 8/8] eQos: Implement the read_rom_hwaddr callback

[Peng Fan]

From: Ye Li 

Implement the read_rom_hwaddr callback to load MAC address from fuse
for imx8m platforms.

Reviewed-by: Fugang Duan 
Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/net/dwc_eth_qos.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 15dae20e57..55a35db739 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1145,6 +1145,16 @@ static int eqos_write_hwaddr(struct udevice *dev)
return 0;
 }
 
+static int eqos_read_rom_hwaddr(struct udevice *dev)
+{
+   struct eth_pdata *pdata = dev_get_platdata(dev);
+
+#ifdef CONFIG_ARCH_IMX8M
+   imx_get_mac_from_fuse(dev->req_seq, pdata->enetaddr);
+#endif
+   return !is_valid_ethaddr(pdata->enetaddr);
+}
+
 static int eqos_start(struct udevice *dev)
 {
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -2058,6 +2068,7 @@ static const struct eth_ops eqos_ops = {
.recv = eqos_recv,
.free_pkt = eqos_free_pkt,
.write_hwaddr = eqos_write_hwaddr,
+   .read_rom_hwaddr= eqos_read_rom_hwaddr,
 };
 
 static struct eqos_ops eqos_tegra186_ops = {
-- 
2.16.4

[PATCH V2 6/8] net: eqos: implement callbaks to get interface and set txclk rate

[Peng Fan]

From: Fugang Duan 

Implement the callbacks to get phy mode interface and txclk
rate configuration.

Reviewed-by: Ye Li 
Signed-off-by: Fugang Duan 
Signed-off-by: Peng Fan 
---

V2:
 Fix build break

 drivers/net/dwc_eth_qos.c | 55 ---
 1 file changed, 52 insertions(+), 3 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 3cdc6f1ae9..15dae20e57 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -42,6 +42,10 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_ARCH_IMX8M
+#include 
+#include 
+#endif
 
 /* Core registers */
 
@@ -867,11 +871,19 @@ static ulong eqos_get_tick_clk_rate_stm32(struct udevice 
*dev)
 #endif
 }
 
-static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
+__weak u32 imx_get_eqos_csr_clk(void)
 {
-   /* TODO: retrieve from CSR clock */
return 100 * 100;
 }
+__weak int imx_eqos_txclk_set_rate(unsigned long rate)
+{
+   return 0;
+}
+
+static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
+{
+   return imx_get_eqos_csr_clk();
+}
 
 static int eqos_calibrate_pads_stm32(struct udevice *dev)
 {
@@ -996,6 +1008,33 @@ static int eqos_set_tx_clk_speed_stm32(struct udevice 
*dev)
 
 static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
 {
+   struct eqos_priv *eqos = dev_get_priv(dev);
+   ulong rate;
+   int ret;
+
+   debug("%s(dev=%p):\n", __func__, dev);
+
+   switch (eqos->phy->speed) {
+   case SPEED_1000:
+   rate = 125 * 1000 * 1000;
+   break;
+   case SPEED_100:
+   rate = 25 * 1000 * 1000;
+   break;
+   case SPEED_10:
+   rate = 2.5 * 1000 * 1000;
+   break;
+   default:
+   pr_err("invalid speed %d", eqos->phy->speed);
+   return -EINVAL;
+   }
+
+   ret = imx_eqos_txclk_set_rate(rate);
+   if (ret < 0) {
+   pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
+   return ret;
+   }
+
return 0;
 }
 
@@ -1865,7 +1904,17 @@ static int eqos_probe_resources_imx(struct udevice *dev)
 
 static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
 {
-   return PHY_INTERFACE_MODE_RGMII;
+   const char *phy_mode;
+   phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
+
+   debug("%s(dev=%p):\n", __func__, dev);
+
+   phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+  NULL);
+   if (phy_mode)
+   interface = phy_get_interface_by_name(phy_mode);
+
+   return interface;
 }
 
 static int eqos_remove_resources_tegra186(struct udevice *dev)
-- 
2.16.4

Re: [PATCH 5/5] power: imx8: Replace SC_R_LAST with SC_R_NONE

[Anatolij Gustschin]

Hi Peng,

On Sun,  3 May 2020 22:33:23 +0800
Peng Fan peng@nxp.com wrote:
...
> ---
>  arch/arm/dts/fsl-imx8dx.dtsi| 619 
> 

Why is this patch removing the dtsi file?

--
Anatolij

[PATCH V2 4/8] net: phy: realtek: add rx delay support for RTL8211F

[Peng Fan]

From: Fugang Duan 

Add RX delay enable support for RTL8211F PHY.

Reviewed-by: Ye Li 
Signed-off-by: Fugang Duan 
Signed-off-by: Peng Fan 
---
 drivers/net/phy/realtek.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 8f1d759632..8f0a897a46 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -56,6 +56,7 @@
 
 #define MIIM_RTL8211F_PAGE_SELECT  0x1f
 #define MIIM_RTL8211F_TX_DELAY 0x100
+#define MIIM_RTL8211F_RX_DELAY 0x8
 #define MIIM_RTL8211F_LCR  0x10
 
 static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
@@ -183,6 +184,16 @@ static int rtl8211f_config(struct phy_device *phydev)
reg &= ~MIIM_RTL8211F_TX_DELAY;
 
phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
+
+   /* enable RX-delay for rgmii-id and rgmii-rxid, otherwise disable it */
+   reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x15);
+   if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+   phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+   reg |= MIIM_RTL8211F_RX_DELAY;
+   else
+   reg &= ~MIIM_RTL8211F_RX_DELAY;
+   phy_write(phydev, MDIO_DEVAD_NONE, 0x15, reg);
+
/* restore to default page 0 */
phy_write(phydev, MDIO_DEVAD_NONE,
  MIIM_RTL8211F_PAGE_SELECT, 0x0);
-- 
2.16.4

[PATCH V2 1/8] net: eth-uclass: add return value check

[Peng Fan]

Add return value check

Signed-off-by: Peng Fan 
---
 net/eth-uclass.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 8bf2eabe90..950a48d520 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -40,8 +40,12 @@ static int eth_errno;
 static struct eth_uclass_priv *eth_get_uclass_priv(void)
 {
struct uclass *uc;
+   int ret;
+
+   ret = uclass_get(UCLASS_ETH, );
+   if (ret)
+   return NULL;
 
-   uclass_get(UCLASS_ETH, );
assert(uc);
return uc->priv;
 }
@@ -102,6 +106,7 @@ struct udevice *eth_get_dev_by_name(const char *devname)
struct udevice *it;
struct uclass *uc;
int len = strlen("eth");
+   int ret;
 
/* Must be longer than 3 to be an alias */
if (!strncmp(devname, "eth", len) && strlen(devname) > len) {
@@ -109,7 +114,10 @@ struct udevice *eth_get_dev_by_name(const char *devname)
seq = simple_strtoul(startp, , 10);
}
 
-   uclass_get(UCLASS_ETH, );
+   ret = uclass_get(UCLASS_ETH, );
+   if (ret)
+   return NULL;
+
uclass_foreach_dev(it, uc) {
/*
 * We need the seq to be valid, so try to probe it.
-- 
2.16.4

[PATCH V2 3/8] net: Update eQos driver and FEC driver to use eth phy interfaces

[Peng Fan]

From: Ye Li 

Update eQoS and fec ethernet drivers to support shared MDIO framework

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/net/dwc_eth_qos.c | 45 +++--
 drivers/net/fec_mxc.c | 16 ++--
 2 files changed, 45 insertions(+), 16 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 63f2086dec..dc2299dd69 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -41,6 +41,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /* Core registers */
 
@@ -1083,7 +1084,14 @@ static int eqos_start(struct udevice *dev)
 * don't need to reconnect/reconfigure again
 */
if (!eqos->phy) {
-   eqos->phy = phy_connect(eqos->mii, eqos->phyaddr, dev,
+   int addr = -1;
+#ifdef CONFIG_DM_ETH_PHY
+   addr = eth_phy_get_addr(dev);
+#endif
+#ifdef DWC_NET_PHYADDR
+   addr = DWC_NET_PHYADDR;
+#endif
+   eqos->phy = phy_connect(eqos->mii, addr, dev,
eqos->config->interface(dev));
if (!eqos->phy) {
pr_err("phy_connect() failed");
@@ -1810,23 +1818,32 @@ static int eqos_probe(struct udevice *dev)
goto err_remove_resources_core;
}
 
-   eqos->mii = mdio_alloc();
+#ifdef CONFIG_DM_ETH_PHY
+   eqos->mii = eth_phy_get_mdio_bus(dev);
+#endif
if (!eqos->mii) {
-   pr_err("mdio_alloc() failed");
-   ret = -ENOMEM;
-   goto err_remove_resources_tegra;
-   }
-   eqos->mii->read = eqos_mdio_read;
-   eqos->mii->write = eqos_mdio_write;
-   eqos->mii->priv = eqos;
-   strcpy(eqos->mii->name, dev->name);
+   eqos->mii = mdio_alloc();
+   if (!eqos->mii) {
+   pr_err("mdio_alloc() failed");
+   ret = -ENOMEM;
+   goto err_remove_resources_tegra;
+   }
+   eqos->mii->read = eqos_mdio_read;
+   eqos->mii->write = eqos_mdio_write;
+   eqos->mii->priv = eqos;
+   strcpy(eqos->mii->name, dev->name);
 
-   ret = mdio_register(eqos->mii);
-   if (ret < 0) {
-   pr_err("mdio_register() failed: %d", ret);
-   goto err_free_mdio;
+   ret = mdio_register(eqos->mii);
+   if (ret < 0) {
+   pr_err("mdio_register() failed: %d", ret);
+   goto err_free_mdio;
+   }
}
 
+#ifdef CONFIG_DM_ETH_PHY
+   eth_phy_set_mdio_bus(dev, eqos->mii);
+#endif
+
debug("%s: OK\n", __func__);
return 0;
 
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 32b0a7a816..688dee3a02 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -28,6 +28,7 @@
 #include 
 
 #include "fec_mxc.h"
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -1434,16 +1435,27 @@ static int fecmxc_probe(struct udevice *dev)
fec_reg_setup(priv);
 
priv->dev_id = dev->seq;
+
+#ifdef CONFIG_DM_ETH_PHY
+   bus = eth_phy_get_mdio_bus(dev);
+#endif
+
+   if (!bus) {
 #ifdef CONFIG_FEC_MXC_MDIO_BASE
-   bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
+   bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
 #else
-   bus = fec_get_miibus((ulong)priv->eth, dev->seq);
+   bus = fec_get_miibus((ulong)priv->eth, dev->seq);
 #endif
+   }
if (!bus) {
ret = -ENOMEM;
goto err_mii;
}
 
+#ifdef CONFIG_DM_ETH_PHY
+   eth_phy_set_mdio_bus(dev, bus);
+#endif
+
priv->bus = bus;
priv->interface = pdata->phy_interface;
switch (priv->interface) {
-- 
2.16.4

[PATCH V2 2/8] net: Add eth phy generic driver for shared MDIO

[Peng Fan]

From: Ye Li 

For dual ethernet controllers, the HW design may connect ETH phys to
one MDIO ports. So two different ethernet drivers have to share MDIO bus.
Since two ethernet drivers are independent, we can't ensure their probe
order.

To resolve this problem, introduce an eth phy generic driver and uclass.

After eth-uclass binds, we search the mdio node and binds the phy node
with the eth-phy-generic driver.

When one eth driver get its phy device, the parent of phy device will
probe prior than phy device. So this ensure the eth driver ownes the
MDIO bus will be probed before using its MDIO.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/net/Kconfig  |   6 +++
 drivers/net/Makefile |   1 +
 drivers/net/eth-phy-uclass.c | 122 +++
 include/dm/uclass-id.h   |   1 +
 include/eth_phy.h|  17 ++
 net/eth-uclass.c |   5 ++
 6 files changed, 152 insertions(+)
 create mode 100644 drivers/net/eth-phy-uclass.c
 create mode 100644 include/eth_phy.h

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4d1013c984..d77bb221e0 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -57,6 +57,12 @@ config MDIO_MUX_SANDBOX
 
  This driver is used for testing in test/dm/mdio.c
 
+config DM_ETH_PHY
+   bool "Enable Driver Model for Ethernet Generic PHY drivers"
+   depends on DM
+   help
+ Enable driver model for Ethernet Generic PHY .
+
 menuconfig NETDEVICES
bool "Network device support"
depends on NET
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6e0a68834d..f6c5ae4fe7 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
 obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
 obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
 obj-$(CONFIG_DNET) += dnet.o
+obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
 obj-$(CONFIG_E1000) += e1000.o
 obj-$(CONFIG_E1000_SPI) += e1000_spi.o
 obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c
new file mode 100644
index 00..b383f45527
--- /dev/null
+++ b/drivers/net/eth-phy-uclass.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct eth_phy_device_priv {
+   struct mii_dev *mdio_bus;
+};
+
+int eth_phy_binds_nodes(struct udevice *eth_dev)
+{
+   ofnode mdio_node, phy_node;
+   const char *node_name;
+   int ret;
+
+   mdio_node = dev_read_subnode(eth_dev, "mdio");
+   if (!ofnode_valid(mdio_node)) {
+   debug("%s: %s mdio subnode not found!", __func__,
+ eth_dev->name);
+   return -ENXIO;
+   }
+
+   ofnode_for_each_subnode(phy_node, mdio_node) {
+   node_name = ofnode_get_name(phy_node);
+
+   debug("* Found child node: '%s'\n", node_name);
+
+   ret = device_bind_driver_to_node(eth_dev,
+"eth_phy_generic_drv",
+node_name, phy_node, NULL);
+   if (ret) {
+   debug("  - Eth phy binding error: %d\n", ret);
+   continue;
+   }
+
+   debug("  - bound phy device: '%s'\n", node_name);
+   }
+
+   return 0;
+}
+
+int eth_phy_set_mdio_bus(struct udevice *eth_dev, struct mii_dev *mdio_bus)
+{
+   struct udevice *dev;
+   struct eth_phy_device_priv *uc_priv;
+
+   for (uclass_first_device(UCLASS_ETH_PHY, ); dev;
+uclass_next_device()) {
+   if (dev->parent == eth_dev) {
+   uc_priv = (struct eth_phy_device_priv 
*)(dev->uclass_priv);
+
+   if (!uc_priv->mdio_bus)
+   uc_priv->mdio_bus = mdio_bus;
+   }
+   }
+
+   return 0;
+}
+
+struct mii_dev *eth_phy_get_mdio_bus(struct udevice *eth_dev)
+{
+   int ret;
+   struct udevice *phy_dev;
+   struct eth_phy_device_priv *uc_priv;
+
+   /* Will probe the parent of phy device, then phy device */
+   ret = uclass_get_device_by_phandle(UCLASS_ETH_PHY, eth_dev,
+  "phy-handle", _dev);
+   if (!ret) {
+   if (eth_dev != phy_dev->parent) {
+   /*
+* phy_dev is shared and controlled by
+* other eth controller
+*/
+   uc_priv = (struct eth_phy_device_priv 
*)(phy_dev->uclass_priv);
+   if (uc_priv->mdio_bus)
+   printf("Get shared mii bus on %s\n", 
eth_dev->name);
+   else
+   printf("Can't get shared mii bus on %s\n", 
eth_dev->name);
+
+   

[PATCH 5/5] power: imx8: Replace SC_R_LAST with SC_R_NONE

[Peng Fan]

From: Leonard Crestez 

We are currently using SC_R_LAST as a marker for imx8 power domain tree
nodes without a resource attached. This value is compiled into dtb as
part of the linux build and used by uboot.

The SC_R_LAST constant changes frequently as SCFW resources are added
(by design) and every time we need to update linux and uboot headers
together or boot can fail.

Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE
defined to be 0xFFF0.

Reviewed-by: Peng Fan 
Signed-off-by: Leonard Crestez 
Signed-off-by: Peng Fan 
---
 arch/arm/dts/fsl-imx8dx.dtsi| 619 
 drivers/power/domain/imx8-power-domain-legacy.c |   6 +-
 2 files changed, 3 insertions(+), 622 deletions(-)
 delete mode 100644 arch/arm/dts/fsl-imx8dx.dtsi

diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
deleted file mode 100644
index ae1d1f460b..00
--- a/arch/arm/dts/fsl-imx8dx.dtsi
+++ /dev/null
@@ -1,619 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2018 NXP
- */
-
-#include 
-#include "fsl-imx8-ca35.dtsi"
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-/ {
-   model = "Freescale i.MX8DX";
-   compatible = "fsl,imx8dx", "fsl,imx8qxp";
-   interrupt-parent = <>;
-   #address-cells = <2>;
-   #size-cells = <2>;
-
-   aliases {
-   ethernet0 = 
-   ethernet1 = 
-   serial0 = 
-   mmc0 = 
-   mmc1 = 
-   mmc2 = 
-   i2c0 = 
-   i2c1 = 
-   i2c2 = 
-   i2c3 = 
-   gpio0 = 
-   gpio1 = 
-   gpio2 = 
-   gpio3 = 
-   gpio4 = 
-   gpio5 = 
-   gpio6 = 
-   gpio7 = 
-   };
-
-   memory@8000 {
-   device_type = "memory";
-   reg = <0x 0x8000 0 0x4000>;
- /* DRAM space - 1, size : 1 GB DRAM */
-   };
-
-   reserved-memory {
-   #address-cells = <2>;
-   #size-cells = <2>;
-   ranges;
-
-   /*
-* reserved-memory layout
-* 0x8800_ ~ 0x8FFF_ is reserved for M4
-* Shouldn't be used at A core and Linux side.
-*
-*/
-   decoder_boot: decoder_boot@0x8400 {
-   no-map;
-   reg = <0 0x8400 0 0x200>;
-   };
-   encoder_boot: encoder_boot@0x8600 {
-   no-map;
-   reg = <0 0x8600 0 0x200>;
-   };
-   rpmsg_reserved: rpmsg@0x9000 {
-   no-map;
-   reg = <0 0x9000 0 0x40>;
-   };
-   decoder_rpc: decoder_rpc@0x9040 {
-   no-map;
-   reg = <0 0x9040 0 0x100>;
-   };
-   encoder_rpc: encoder_rpc@0x9140 {
-   no-map;
-   reg = <0 0x9140 0 0x100>;
-   };
-   dsp_reserved: dsp@0x9240 {
-   no-map;
-   reg = <0 0x9240 0 0x200>;
-   };
-   decoder_str: str@0x9440 {
-   no-map;
-   reg = <0 0x9440 0 0x180>;
-   };
-   /* global autoconfigured region for contiguous allocations */
-   linux,cma {
-   compatible = "shared-dma-pool";
-   reusable;
-   size = <0 0x2800>;
-   alloc-ranges = <0 0x9600 0 0x2800>;
-   linux,cma-default;
-   };
-   };
-
-   gic: interrupt-controller@51a0 {
-   compatible = "arm,gic-v3";
-   reg = <0x0 0x51a0 0 0x1>, /* GIC Dist */
- <0x0 0x51b0 0 0xC>; /* GICR (RD_base + SGI_base) 
*/
-   #interrupt-cells = <3>;
-   interrupt-controller;
-   interrupts = ;
-   interrupt-parent = <>;
-   };
-
-   mu: mu@5d1c {
-   compatible = "fsl,imx8-mu";
-   reg = <0x0 0x5d1c 0x0 0x1>;
-   interrupts = ;
-   interrupt-parent = <>;
-   status = "okay";
-
-   clk: clk {
-   compatible = "fsl,imx8qxp-clk";
-   #clock-cells = <1>;
-   };
-
-   iomuxc: iomuxc {
-   compatible = "fsl,imx8qxp-iomuxc";
-   };
-   };
-
-   imx8qx-pm {
-   compatible = "simple-bus";
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   pd_lsio: PD_LSIO {
-

Re: [PATCH] video: omap: change include order

[Lokesh Vutla]

On 02/05/20 9:09 PM, Dario Binacchi wrote:
> Apply u-boot coding style on include files order.

Can you describe more on how you are ordering?

Thanks and regards,
Lokesh

> 
> Signed-off-by: Dario Binacchi 
> ---
> 
>  drivers/video/am335x-fb.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
> index eb5add2a20..0f066df451 100644
> --- a/drivers/video/am335x-fb.c
> +++ b/drivers/video/am335x-fb.c
> @@ -13,15 +13,15 @@
>   */
>  #include 
>  #include 
> -#include 
> +#include 
> +#include 
> +#include 
>  #include 
>  #include 
> -#include 
>  #include 
> +#include 
>  #include 
>  #include 
> -#include 
> -#include 
>  #include "am335x-fb.h"
>  
>  #define LCDC_FMAX2
> 

[PATCH 4/5] power: imx8: Check owned resource in power on

[Peng Fan]

From: Ye Li 

When fspi is assigned to M4, we have to let the fspi probe failed when
its power domain is failed to power up. Because not all devices have power
domain (for example, external devices on the board). Current checking
resource owner in power domain probe is not good, change to check it in
power on.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/power/domain/imx8-power-domain-legacy.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/power/domain/imx8-power-domain-legacy.c 
b/drivers/power/domain/imx8-power-domain-legacy.c
index b68be40766..a5f2f8a445 100644
--- a/drivers/power/domain/imx8-power-domain-legacy.c
+++ b/drivers/power/domain/imx8-power-domain-legacy.c
@@ -91,6 +91,9 @@ static int imx8_power_domain_on(struct power_domain 
*power_domain)
return 0;
 
if (pdata->resource_id != SC_R_LAST) {
+   if (!sc_rm_is_resource_owned(-1, pdata->resource_id))
+   printf("%s [%d] not owned by curr partition\n", 
dev->name, pdata->resource_id);
+
ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id,
SC_PM_PW_MODE_ON);
if (ret) {
-- 
2.16.4

[PATCH 2/5] power: imx8-power-domain: Set DM_FLAG_DEFAULT_PD_CTRL_OFF flag

[Peng Fan]

From: Ye Li 

If without this flag, calling dev_power_domain_ctrl will iteratively remove
the power domain device will causes iteratively power off parent PD. This is
not expected by imx8-power-domain-legacy driver. Power off parent PD is
controlled by the driver internally.

So set DM_FLAG_DEFAULT_PD_CTRL_OFF to avoid such issue

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/power/domain/imx8-power-domain-legacy.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/power/domain/imx8-power-domain-legacy.c 
b/drivers/power/domain/imx8-power-domain-legacy.c
index 2c479744d3..e6e619358c 100644
--- a/drivers/power/domain/imx8-power-domain-legacy.c
+++ b/drivers/power/domain/imx8-power-domain-legacy.c
@@ -341,4 +341,5 @@ U_BOOT_DRIVER(imx8_power_domain) = {
.platdata_auto_alloc_size = sizeof(struct imx8_power_domain_platdata),
.priv_auto_alloc_size = sizeof(struct imx8_power_domain_priv),
.ops = _power_domain_ops,
+   .flags  = DM_FLAG_DEFAULT_PD_CTRL_OFF,
 };
-- 
2.16.4

[PATCH 1/5] imx8: power: Add PD device lookup interface to power domain uclass

[Peng Fan]

Add power_domain_lookup_name interface to power domain uclass to find
a power domain device by its DTB node name, not using its associated
client device.

Through this interface, we can operate the power domain devices directly.
This is needed for non-DM drivers.

Modified from Ye's NXP downstream patch

only for legacy imx8 power domain driver, since we have not migrated
to use new power domain driver.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 arch/arm/include/asm/arch-imx8/sys_proto.h  |  7 +++
 drivers/power/domain/imx8-power-domain-legacy.c | 28 +
 2 files changed, 35 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h 
b/arch/arm/include/asm/arch-imx8/sys_proto.h
index 0e981ae950..fc33e6ed18 100644
--- a/arch/arm/include/asm/arch-imx8/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -5,6 +5,11 @@
 
 #include 
 #include 
+#include 
+#include 
+#include 
+#include 
+#include 
 #include 
 
 struct pass_over_info_t {
@@ -21,3 +26,5 @@ void build_info(void);
 enum boot_device get_boot_device(void);
 int print_bootinfo(void);
 int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate);
+int imx8_power_domain_lookup_name(const char *name,
+ struct power_domain *power_domain);
diff --git a/drivers/power/domain/imx8-power-domain-legacy.c 
b/drivers/power/domain/imx8-power-domain-legacy.c
index 6f01a60b34..2c479744d3 100644
--- a/drivers/power/domain/imx8-power-domain-legacy.c
+++ b/drivers/power/domain/imx8-power-domain-legacy.c
@@ -19,6 +19,34 @@ struct imx8_power_domain_priv {
bool state_on;
 };
 
+int imx8_power_domain_lookup_name(const char *name,
+ struct power_domain *power_domain)
+{
+   struct udevice *dev;
+   struct power_domain_ops *ops;
+   int ret;
+
+   debug("%s(power_domain=%p name=%s)\n", __func__, power_domain, name);
+
+   ret = uclass_get_device_by_name(UCLASS_POWER_DOMAIN, name, );
+   if (ret) {
+   printf("%s fail: %s, ret = %d\n", __func__, name, ret);
+   return ret;
+   }
+
+   ops = (struct power_domain_ops *)dev->driver->ops;
+   power_domain->dev = dev;
+   ret = ops->request(power_domain);
+   if (ret) {
+   debug("ops->request() failed: %d\n", ret);
+   return ret;
+   }
+
+   debug("%s ok: %s\n", __func__, dev->name);
+
+   return 0;
+}
+
 static int imx8_power_domain_request(struct power_domain *power_domain)
 {
debug("%s(power_domain=%p)\n", __func__, power_domain);
-- 
2.16.4

[PATCH 3/5] power: imx8: remove the resource owned check before power off

[Peng Fan]

For all the devices used and set ACTIVE in U-Boot, U-Boot needs
to power off all of them without the check of resource owner.

When we create software partition before booting Linux, the resource
own checkw will return false, and cause the power domain not powered
off. If without the check of resource owner, the power domain in
the other software partition could be powered off with parent
partition could access child partition resources.

Signed-off-by: Peng Fan 
---
 drivers/power/domain/imx8-power-domain-legacy.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/power/domain/imx8-power-domain-legacy.c 
b/drivers/power/domain/imx8-power-domain-legacy.c
index e6e619358c..b68be40766 100644
--- a/drivers/power/domain/imx8-power-domain-legacy.c
+++ b/drivers/power/domain/imx8-power-domain-legacy.c
@@ -137,13 +137,13 @@ static int imx8_power_domain_off_node(struct power_domain 
*power_domain)
}
 
if (pdata->resource_id != SC_R_LAST) {
-   if (!sc_rm_is_resource_owned(-1, pdata->resource_id)) {
-   printf("%s not owned by curr partition\n", dev->name);
-   return 0;
-   }
ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id,
SC_PM_PW_MODE_OFF);
if (ret) {
+   if (!sc_rm_is_resource_owned(-1, pdata->resource_id)) {
+   printf("%s not owned by curr partition %d\n", 
dev->name, pdata->resource_id);
+   return 0;
+   }
printf("Error: %s Power off failed! (error = %d)\n",
   dev->name, ret);
return -EIO;
-- 
2.16.4

[PATCH 1/2] misc: fuse: Update imx8 fuse driver for 8QM

[Peng Fan]

From: Ye Li 

Add the second ECC fuse area for 8QM which is different with 8QXP

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/misc/imx8/fuse.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c
index 1309215d4d..4d7f2f524d 100644
--- a/drivers/misc/imx8/fuse.c
+++ b/drivers/misc/imx8/fuse.c
@@ -15,8 +15,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define FSL_ECC_WORD_START_10x10
 #define FSL_ECC_WORD_END_1  0x10F
 
+#ifdef CONFIG_IMX8QM
+#define FSL_ECC_WORD_START_20x1A0
+#define FSL_ECC_WORD_END_2  0x1FF
+#elif defined(CONFIG_IMX8QXP)
 #define FSL_ECC_WORD_START_20x220
 #define FSL_ECC_WORD_END_2  0x31F
+#endif
 
 #define FSL_QXP_FUSE_GAP_START  0x110
 #define FSL_QXP_FUSE_GAP_END0x21F
-- 
2.16.4

[PATCH 2/2] misc: scu: Increase the timeout for MU communication

[Peng Fan]

From: Ye Li 

When power on some sources in Video system, current timeout 10ms is
too short and returns before SCU response. So increase the timeout
to 1s.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/misc/imx8/scu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c
index a7654a7817..6916b754f6 100644
--- a/drivers/misc/imx8/scu.c
+++ b/drivers/misc/imx8/scu.c
@@ -74,7 +74,7 @@ static int mu_hal_receivemsg(struct mu_type *base, u32 
reg_index, u32 *msg)
assert(reg_index < MU_TR_COUNT);
 
/* Wait RX register to be full. */
-   ret = readl_poll_timeout(>sr, val, val & mask, 1);
+   ret = readl_poll_timeout(>sr, val, val & mask, 100);
if (ret < 0) {
printf("%s timeout\n", __func__);
return -ETIMEDOUT;
-- 
2.16.4

Re: [PATCH 3/3] net: tsec: Access TBI PHY through the corresponding MII

[Vladimir Oltean]

Hi Zhiqiang,

On Sun, 3 May 2020 at 16:49, Z.q. Hou  wrote:
>
> Hi Vladimir,
>
> Thanks a lot for your review and test!
>
> > -Original Message-
> > From: Vladimir Oltean 
> > Sent: 2020年5月3日 19:35
> > To: Z.q. Hou 
> > Cc: u-boot ; Joe Hershberger
> > ; Bin Meng ; Priyanka
> > Jain 
> > Subject: Re: [PATCH 3/3] net: tsec: Access TBI PHY through the
> > corresponding MII
> >
> > On Sun, 3 May 2020 at 09:28, Zhiqiang Hou 
> > wrote:
> > >
> > > From: Hou Zhiqiang 
> > >
> > > When an eTSEC is configured to use TBI, configuration of the TBI is
> > > done through the MIIM registers for that eTSEC.
> > > For example, if a TBI interface is required on eTSEC2, then the MIIM
> > > registers starting at offset 0x2_5520 are used to configure it.
> > >
> > > Fixes: 9a1d6af55ecd ("net: tsec: Add driver model ethernet support")
> > > Signed-off-by: Hou Zhiqiang 
> > > ---
> > >  drivers/net/tsec.c | 17 ++---
> > >  1 file changed, 14 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index
> > > ce41aec5cf..31056f3117 100644
> > > --- a/drivers/net/tsec.c
> > > +++ b/drivers/net/tsec.c
> > > @@ -789,6 +789,7 @@ int tsec_probe(struct udevice *dev)  {
> > > struct eth_pdata *pdata = dev_get_platdata(dev);
> > > struct tsec_private *priv = dev_get_priv(dev);
> > > +   struct tsec_mii_mng __iomem *ext_phyregs_mii;
> > > struct ofnode_phandle_args phandle_args;
> > > u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
> > > struct fsl_pq_mdio_info mdio_info; @@ -820,8 +821,8 @@ int
> > > tsec_probe(struct udevice *dev)
> > > if (reg == FDT_ADDR_T_NONE)
> > > return -ENOENT;
> > >
> > > -   priv->phyregs_sgmii = map_physmem(reg +
> > TSEC_MDIO_REGS_OFFSET, 0,
> > > - MAP_NOCACHE);
> > > +   ext_phyregs_mii = map_physmem(reg +
> > TSEC_MDIO_REGS_OFFSET, 0,
> > > + MAP_NOCACHE);
> > >
> > > ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0,
> > 0,
> > >  _args); @@
> > -830,6
> > > +831,16 @@ int tsec_probe(struct udevice *dev)
> > >
> > > priv->tbiaddr = tbiaddr;
> > >
> > > +   parent = ofnode_get_parent(phandle_args.node);
> > > +   if (!ofnode_valid(parent)) {
> > > +   printf("No parent node for TBI PHY?\n");
> > > +   return -ENOENT;
> > > +   }
> > > +
> > > +   reg = ofnode_get_addr_index(parent, 0);
> >
> > Missing a check
> >
> > if (reg == FDT_ADDR_T_NONE)
> > return -ENOENT;
> >
> > here?
>
> Yes, will fix in v2.
>
> Thanks,
> Zhiqiang

Actually since the TBI PHY is optional (not present on RGMII
interfaces and such), I don't believe you should return an error, but
just skip the phyregs_sgmii initialization.

>
> >
> > > +   priv->phyregs_sgmii = map_physmem(reg +
> > TSEC_MDIO_REGS_OFFSET, 0,
> > > + MAP_NOCACHE);
> > > +
> > > phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
> > > if (phy_mode)
> > > pdata->phy_interface =
> > > phy_get_interface_by_name(phy_mode);
> > > @@ -844,7 +855,7 @@ int tsec_probe(struct udevice *dev)
> > > if (priv->interface == PHY_INTERFACE_MODE_SGMII)
> > > priv->flags |= TSEC_SGMII;
> > >
> > > -   mdio_info.regs = priv->phyregs_sgmii;
> > > +   mdio_info.regs = ext_phyregs_mii;
> > > mdio_info.name = (char *)dev->name;
> > > ret = fsl_pq_mdio_init(NULL, _info);
> > > if (ret)
> > > --
> > > 2.17.1
> > >
> >
> > With that:
> >
> > Reviewed-by: Vladimir Oltean 
> > Tested-by: Vladimir Oltean 
> >
> > (on LS1021A)
> >
> > Thanks!
> > -Vladimir

Thanks,
-Vladimir

[PATCH 3/4] sata: dwc_ahsata: Fix incorrect free

[Peng Fan]

From: Ye Li 

Fix coverity issue CID 43665: Free of address-of expression (BAD_FREE)
incorrect_free: free frees incorrect pointer pp.

pp points the port array field of struct ahci_uc_priv, should not free it.

Acked-by: Peng Fan 
Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/ata/dwc_ahsata.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index 4b37a02338..82fbb50da6 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -450,7 +450,6 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 
port)
 
mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
if (!mem) {
-   free(pp);
printf("No mem for table!\n");
return -ENOMEM;
}
-- 
2.16.4

[PATCH 4/4] sata: dwc_ahsata: Fix memory issue in reset_sata

[Peng Fan]

From: Ye Li 

The reset_sata should reset the sata device info and free the
probe_ent memory. Otherwise, it will cause memory leak if we
init the sata again.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/ata/dwc_ahsata.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index 82fbb50da6..2bc1de8b98 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -918,6 +918,9 @@ int reset_sata(int dev)
while (readl(_mmio->ghc) & SATA_HOST_GHC_HR)
udelay(100);
 
+   free(uc_priv);
+   memset(_dev_desc[dev], 0, sizeof(struct blk_desc));
+
return 0;
 }
 
-- 
2.16.4

[PATCH 2/4] sata: ahsata: Fix wrong operand for checking SERR DIAG_X

[Peng Fan]

From: Ye Li 

Fix coverity issue CID 3261683: Wrong operator used
(CONSTANT_EXPRESSION_RESULT) operator_confusion:
({...; __v;}) | 67108864 is always 1/true regardless of the values
of its operand. This occurs as the logical operand of !

When DIAG_X is set, the PHY COMINIT signal is detected, so
should use '&' to check whether it is set.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/ata/dwc_ahsata.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index a775214792..4b37a02338 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -223,7 +223,7 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv)
 
/* Wait for COMINIT bit 26 (DIAG_X) in SERR */
timeout = 1000;
-   while (!(readl(_mmio->serr) | SATA_PORT_SERR_DIAG_X)
+   while (!(readl(_mmio->serr) & SATA_PORT_SERR_DIAG_X)
&& --timeout)
;
if (timeout <= 0) {
-- 
2.16.4

[PATCH 1/4] sata: ahsata: Fix resource leak

[Peng Fan]

From: Ye Li 

Fix coverity issue CID 3606684: Resource leak (RESOURCE_LEAK)
leaked_storage: Variable uc_priv going out of scope leaks the storage it points 
to

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/ata/dwc_ahsata.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index c2e28fe518..a775214792 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -847,6 +847,9 @@ static int ahci_init_one(int pdev)
struct ahci_uc_priv *uc_priv = NULL;
 
uc_priv = malloc(sizeof(struct ahci_uc_priv));
+   if (!uc_priv)
+   return -ENOMEM;
+
memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
uc_priv->dev = pdev;
 
@@ -871,6 +874,8 @@ static int ahci_init_one(int pdev)
return 0;
 
 err_out:
+   if (uc_priv)
+   free(uc_priv);
return rc;
 }
 
-- 
2.16.4

[PATCH 11/13] imx8mp: Set default SNSR25C for TMU probe1

[Peng Fan]

From: Ye Li 

So far u-boot only load SNSR25C for TMU main probe (probe 0). However,
kernel enables two probes. So it also needs to set default SNSR25C of
TCALIV1 for blank samples.

Reviewed-by: Peng Fan 
Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx8m/soc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index adb444b240..c1e0f01f90 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -443,7 +443,9 @@ void imx_tmu_arch_init(void *reg_base)
!fuse->ana_trim4 && !fuse2->ana_trim5) {
/* Use a default 25C binary codes */
tca25[0] = 1596;
+   tca25[1] = 1596;
writel(tca25[0], (ulong)reg_base + 0x30);
+   writel(tca25[1], (ulong)reg_base + 0x34);
return;
}
 
-- 
2.16.4

[PATCH 13/13] imx: cpu: support tmu

[Peng Fan]

Support tmu when print cpu info

Signed-off-by: peng Fan 
---
 arch/arm/mach-imx/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index bfa85c64c6..2d70b6861d 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -154,7 +154,7 @@ int print_cpuinfo(void)
 
cpurev = get_cpu_rev();
 
-#if defined(CONFIG_IMX_THERMAL)
+#if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
struct udevice *thermal_dev;
int cpu_tmp, minc, maxc, ret;
 
@@ -177,7 +177,7 @@ int print_cpuinfo(void)
mxc_get_clock(MXC_ARM_CLK) / 100);
 #endif
 
-#if defined(CONFIG_IMX_THERMAL)
+#if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
puts("CPU:   ");
switch (get_cpu_temp_grade(, )) {
case TEMP_AUTOMOTIVE:
-- 
2.16.4

[PATCH 12/13] imx: regs: add more fuse bank structure

[Peng Fan]

Add more fuse bank structure for use.

Signed-off-by: Peng Fan 
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h | 41 +-
 1 file changed, 34 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h 
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 62640d996e..3cfa169c97 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -137,6 +137,40 @@ struct fuse_bank1_regs {
u32 rsvd3[3];
 };
 
+struct fuse_bank3_regs {
+   u32 mem_trim0;
+   u32 rsvd0[3];
+   u32 mem_trim1;
+   u32 rsvd1[3];
+   u32 mem_trim2;
+   u32 rsvd2[3];
+   u32 ana0;
+   u32 rsvd3[3];
+};
+
+struct fuse_bank9_regs {
+   u32 mac_addr0;
+   u32 rsvd0[3];
+   u32 mac_addr1;
+   u32 rsvd1[11];
+};
+
+struct fuse_bank38_regs {
+   u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/
+   u32 rsvd0[3];
+   u32 ana_trim2;
+   u32 rsvd1[3];
+   u32 ana_trim3;
+   u32 rsvd2[3];
+   u32 ana_trim4;
+   u32 rsvd3[3];
+};
+
+struct fuse_bank39_regs {
+   u32 ana_trim5;
+   u32 rsvd[15];
+};
+
 #ifdef CONFIG_IMX8MQ
 struct anamix_pll {
u32 audio_pll1_cfg0;
@@ -227,13 +261,6 @@ struct anamix_pll {
 };
 #endif
 
-struct fuse_bank9_regs {
-   u32 mac_addr0;
-   u32 rsvd0[3];
-   u32 mac_addr1;
-   u32 rsvd1[11];
-};
-
 /* System Reset Controller (SRC) */
 struct src {
u32 scr;
-- 
2.16.4

[PATCH 10/13] imx: load calibration parameters from fuse for i.MX8MP

[Peng Fan]

From: Ye Li 

i.MX8MP thermal which has two probes and supports temperature range
from -40 to 125.  The driver still uses default 1p HW
calibration at 25C and loads calibration parameters from fuse.

Reviewed-by: Peng Fan 
Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx8m/soc.c | 45 +++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 1f42455aa0..adb444b240 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -425,4 +425,49 @@ void imx_tmu_arch_init(void *reg_base)
writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
   (ulong)reg_base + 0x30);
}
+#ifdef CONFIG_IMX8MP
+   /* Load TCALIV0/1/m40 and TRIM from fuses */
+   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+   struct fuse_bank *bank = >bank[38];
+   struct fuse_bank38_regs *fuse =
+   (struct fuse_bank38_regs *)bank->fuse_regs;
+   struct fuse_bank *bank2 = >bank[39];
+   struct fuse_bank39_regs *fuse2 =
+   (struct fuse_bank39_regs *)bank2->fuse_regs;
+   u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
+   u32 reg;
+   u32 tca40[2], tca25[2], tca105[2];
+
+   /* For blank sample */
+   if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
+   !fuse->ana_trim4 && !fuse2->ana_trim5) {
+   /* Use a default 25C binary codes */
+   tca25[0] = 1596;
+   writel(tca25[0], (ulong)reg_base + 0x30);
+   return;
+   }
+
+   buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
+   buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
+   bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
+   bgr = (fuse->ana_trim2 & 0xF) >> 16;
+   vlsb = (fuse->ana_trim2 & 0xF0) >> 20;
+   writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
+
+   reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
+   writel(reg, (ulong)reg_base + 0x3c);
+
+   tca40[0] = (fuse->ana_trim3 & 0xFFF) >> 16;
+   tca25[0] = (fuse->ana_trim3 & 0xF000) >> 28;
+   tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
+   tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
+   tca40[1] = (fuse->ana_trim4 & 0xFFF0) >> 20;
+   tca25[1] = fuse2->ana_trim5 & 0xFFF;
+   tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
+
+   /* use 25c for 1p calibration */
+   writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
+   writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
+   writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
+#endif
 }
-- 
2.16.4

[PATCH 09/13] imx: i.MX8MN: Enable loading TASR and TCALIV from fuse

[Peng Fan]

From: Ye Li 

Like iMX8MM, iMX8MN also needs SW to load TMU TASR and TCALIV registers
value from fuse before enabling TMU calibration. Otherwise the calibration
is not exact.

Reviewed-by: Anson Huang 
Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx8m/soc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 6567936f4b..1f42455aa0 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -403,7 +403,7 @@ void reset_cpu(ulong addr)
 
 void imx_tmu_arch_init(void *reg_base)
 {
-   if (is_imx8mm()) {
+   if (is_imx8mm() || is_imx8mn()) {
/* Load TCALIV and TASR from fuses */
struct ocotp_regs *ocotp =
(struct ocotp_regs *)OCOTP_BASE_ADDR;
-- 
2.16.4

[PATCH 02/13] thermal: Add thermal driver for i.MX8M

[Peng Fan]

The driver is ported form Linux Kernel and support driver model.
Users need to provide the tmu node and sensors nodes in DTB.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/thermal/Kconfig   |   9 ++
 drivers/thermal/Makefile  |   1 +
 drivers/thermal/imx_tmu.c | 325 ++
 3 files changed, 335 insertions(+)
 create mode 100644 drivers/thermal/imx_tmu.c

diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index bdf8dc6fef..97d4163e8e 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -26,6 +26,15 @@ config IMX_SCU_THERMAL
  boot is hold to the cool device to throttle CPUs when the passive
  trip is crossed
 
+config IMX_TMU
+bool "Thermal Management Unit driver for NXP i.MX8M"
+depends on ARCH_IMX8M
+help
+  Support for Temperature sensors on NXP i.MX8M.
+  It supports one critical trip point and one passive trip point.
+ The boot is hold to the cool device to throttle CPUs when the
+ passive trip is crossed
+
 config TI_DRA7_THERMAL
 bool "Temperature sensor driver for TI dra7xx SOCs"
 help
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index ef2929d180..15fe847d9f 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o
 obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
 obj-$(CONFIG_IMX_SCU_THERMAL) += imx_scu_thermal.o
 obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o
+obj-$(CONFIG_IMX_TMU) += imx_tmu.o
diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
new file mode 100644
index 00..f496ce03b6
--- /dev/null
+++ b/drivers/thermal/imx_tmu.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017~2020 NXP
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SITES_MAX  16
+
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF   0x0c00
+#define TMTMIR_DEFAULT 0x0002
+#define TIER_DISABLE   0x0
+
+/*
+ * i.MX TMU Registers
+ */
+struct imx_tmu_site_regs {
+   u32 tritsr; /* Immediate Temperature Site Register */
+   u32 tratsr; /* Average Temperature Site Register */
+   u8 res0[0x8];
+};
+
+struct imx_tmu_regs {
+   u32 tmr;/* Mode Register */
+   u32 tsr;/* Status Register */
+   u32 tmtmir; /* Temperature measurement interval Register */
+   u8 res0[0x14];
+   u32 tier;   /* Interrupt Enable Register */
+   u32 tidr;   /* Interrupt Detect Register */
+   u32 tiscr;  /* Interrupt Site Capture Register */
+   u32 ticscr; /* Interrupt Critical Site Capture Register */
+   u8 res1[0x10];
+   u32 tmhtcrh;/* High Temperature Capture Register */
+   u32 tmhtcrl;/* Low Temperature Capture Register */
+   u8 res2[0x8];
+   u32 tmhtitr;/* High Temperature Immediate Threshold */
+   u32 tmhtatr;/* High Temperature Average Threshold */
+   u32 tmhtactr;   /* High Temperature Average Crit Threshold */
+   u8 res3[0x24];
+   u32 ttcfgr; /* Temperature Configuration Register */
+   u32 tscfgr; /* Sensor Configuration Register */
+   u8 res4[0x78];
+   struct imx_tmu_site_regs site[SITES_MAX];
+   u8 res5[0x9f8];
+   u32 ipbrr0; /* IP Block Revision Register 0 */
+   u32 ipbrr1; /* IP Block Revision Register 1 */
+   u8 res6[0x310];
+   u32 ttr0cr; /* Temperature Range 0 Control Register */
+   u32 ttr1cr; /* Temperature Range 1 Control Register */
+   u32 ttr2cr; /* Temperature Range 2 Control Register */
+   u32 ttr3cr; /* Temperature Range 3 Control Register */
+};
+
+struct imx_tmu_plat {
+   int critical;
+   int alert;
+   int polling_delay;
+   int id;
+   bool zone_node;
+   struct imx_tmu_regs *regs;
+};
+
+static int read_temperature(struct udevice *dev, int *temp)
+{
+   struct imx_tmu_plat *pdata = dev_get_platdata(dev);
+   u32 val;
+
+   do {
+   val = readl(>regs->site[pdata->id].tritsr);
+   } while (!(val & 0x8000));
+
+   *temp = (val & 0xff) * 1000;
+
+   return 0;
+}
+
+int imx_tmu_get_temp(struct udevice *dev, int *temp)
+{
+   struct imx_tmu_plat *pdata = dev_get_platdata(dev);
+   int cpu_tmp = 0;
+   int ret;
+
+   ret = read_temperature(dev, _tmp);
+   if (ret)
+   return ret;
+
+   while (cpu_tmp >= pdata->alert) {
+   printf("CPU Temperature (%dC) has beyond alert (%dC), close to 
critical (%dC)", cpu_tmp, pdata->alert, pdata->critical);
+   puts(" waiting...\n");
+   mdelay(pdata->polling_delay);
+   ret = read_temperature(dev, _tmp);
+   if 

[PATCH 05/13] thermal: imx_tmu: Fix for temperature out of range

[Peng Fan]

When the temperature is out of sensor's range, the Valid bit won't be
set in TRITSR register. So the polling loop won't go out.

Change the codes to retry 10 times with 100ms interval for the Valid bit.
If the timeout, we give a warning for the invalid data.

Modifed from Ye's NXP patch

Signed-off-by: Peng Fan 
---
 drivers/thermal/imx_tmu.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index 049f32c39e..2a08d5085c 100644
--- a/drivers/thermal/imx_tmu.c
+++ b/drivers/thermal/imx_tmu.c
@@ -105,15 +105,22 @@ static int read_temperature(struct udevice *dev, int 
*temp)
struct imx_tmu_plat *pdata = dev_get_platdata(dev);
ulong drv_data = dev_get_driver_data(dev);
u32 val;
+   u32 retry = 10;
 
do {
-   if (drv_data & FLAGS_VER2) {
+   mdelay(100);
+   retry--;
+
+   if (drv_data & FLAGS_VER2)
val = readl(>regs->regs_v2.tritsr);
else
val = 
readl(>regs->regs_v1.site[pdata->id].tritsr);
-   } while (!(val & 0x8000));
+   } while (!(val & 0x8000) && retry > 0);
 
-   *temp = (val & 0xff) * 1000;
+   if (retry > 0)
+   *temp = (val & 0xff) * 1000;
+   else
+   return -EINVAL;
 
return 0;
 }
-- 
2.16.4

[PATCH 08/13] imx8mm: Load fuse for TMU TCALIV and TASR

[Peng Fan]

From: Ye Li 

On iMX8MM, the default value of TMU registers TCALIV and TASR need
be loaded from fuse. HW won't do this, it expect SW loads them before
using TMU.

Reviewed-by: Bai Ping 
Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx8m/soc.c | 28 +++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 7fcbd53f30..6567936f4b 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  *
  * Peng Fan 
  */
@@ -400,3 +400,29 @@ void reset_cpu(ulong addr)
}
 }
 #endif
+
+void imx_tmu_arch_init(void *reg_base)
+{
+   if (is_imx8mm()) {
+   /* Load TCALIV and TASR from fuses */
+   struct ocotp_regs *ocotp =
+   (struct ocotp_regs *)OCOTP_BASE_ADDR;
+   struct fuse_bank *bank = >bank[3];
+   struct fuse_bank3_regs *fuse =
+   (struct fuse_bank3_regs *)bank->fuse_regs;
+
+   u32 tca_rt, tca_hr, tca_en;
+   u32 buf_vref, buf_slope;
+
+   tca_rt = fuse->ana0 & 0xFF;
+   tca_hr = (fuse->ana0 & 0xFF00) >> 8;
+   tca_en = (fuse->ana0 & 0x200) >> 25;
+
+   buf_vref = (fuse->ana0 & 0x1F0) >> 20;
+   buf_slope = (fuse->ana0 & 0xF) >> 16;
+
+   writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
+   writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
+  (ulong)reg_base + 0x30);
+   }
+}
-- 
2.16.4

[PATCH 07/13] thermal: imx_tmu: support i.MX8MP

[Peng Fan]

Support i.MX8MP thermal which has two probes and supports
temperature range from -40 to 125. Still uses default 1p HW
calibration at 25C and loads calibration parameters from fuse.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/thermal/imx_tmu.c | 76 ++-
 1 file changed, 69 insertions(+), 7 deletions(-)

diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index c577b0bd6c..4ca22089b8 100644
--- a/drivers/thermal/imx_tmu.c
+++ b/drivers/thermal/imx_tmu.c
@@ -21,6 +21,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define SITES_MAX  16
 #define FLAGS_VER2 0x1
+#define FLAGS_VER3 0x2
 
 #define TMR_DISABLE0x0
 #define TMR_ME 0x8000
@@ -30,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define TER_EN 0x8000
 #define TER_ADC_PD 0x4000
+#define TER_ALPF   0x3
+
 /*
  * i.MX TMU Registers
  */
@@ -86,9 +89,29 @@ struct imx_tmu_regs_v2 {
u32 tcaliv;
 };
 
+struct imx_tmu_regs_v3 {
+   u32 ter;/* TMU enable Register */
+   u32 tps;/* Status Register */
+   u32 tier;   /* Interrupt enable register */
+   u32 tidr;   /* Interrupt detect  register */
+   u32 tmhtitr;/* Monitor high temperature immediate threshold 
register */
+   u32 tmhtatr;/* Monitor high temperature average threshold register 
*/
+   u32 tmhtactr;   /* TMU monitor high temperature average critical  
threshold register */
+   u32 tscr;   /* Sensor value capture register */
+   u32 tritsr; /* Report immediate temperature site register 0 */
+   u32 tratsr; /* Report average temperature site register 0 */
+   u32 tasr;   /* Amplifier setting register */
+   u32 ttmc;   /* Test MUX control */
+   u32 tcaliv0;
+   u32 tcaliv1;
+   u32 tcaliv_m40;
+   u32 trim;
+};
+
 union tmu_regs {
struct imx_tmu_regs regs_v1;
struct imx_tmu_regs_v2 regs_v2;
+   struct imx_tmu_regs_v3 regs_v3;
 };
 
 struct imx_tmu_plat {
@@ -112,7 +135,10 @@ static int read_temperature(struct udevice *dev, int *temp)
mdelay(100);
retry--;
 
-   if (drv_data & FLAGS_VER2) {
+   if (drv_data & FLAGS_VER3) {
+   val = readl(>regs->regs_v3.tritsr);
+   valid = val & (1 << (30 + pdata->id));
+   } else if (drv_data & FLAGS_VER2) {
val = readl(>regs->regs_v2.tritsr);
/*
 * Check if TEMP is in valid range, the V bit in TRITSR
@@ -125,10 +151,23 @@ static int read_temperature(struct udevice *dev, int 
*temp)
}
} while (!valid && retry > 0);
 
-   if (retry > 0)
-   *temp = (val & 0xff) * 1000;
-   else
+   if (retry > 0) {
+   if (drv_data & FLAGS_VER3) {
+   val = (val >> (pdata->id * 16)) & 0xff;
+   if (val & 0x80) /* Negative */
+   val = (~(val & 0x7f) + 1);
+
+   *temp = val;
+   if (*temp < -40 || *temp > 125) /* Check the range */
+   return -EINVAL;
+
+   *temp *= 1000;
+   } else {
+   *temp = (val & 0xff) * 1000;
+   }
+   } else {
return -EINVAL;
+   }
 
return 0;
 }
@@ -171,7 +210,7 @@ static int imx_tmu_calibration(struct udevice *dev)
 
debug("%s\n", __func__);
 
-   if (drv_data & FLAGS_VER2)
+   if (drv_data & (FLAGS_VER2 | FLAGS_VER3))
return 0;
 
ret = dev_read_u32_array(dev, "fsl,tmu-range", range, 4);
@@ -213,7 +252,14 @@ static void imx_tmu_init(struct udevice *dev)
 
debug("%s\n", __func__);
 
-   if (drv_data & FLAGS_VER2) {
+   if (drv_data & FLAGS_VER3) {
+   /* Disable monitoring */
+   writel(0x0, >regs->regs_v3.ter);
+
+   /* Disable interrupt, using polling instead */
+   writel(0x0, >regs->regs_v3.tier);
+
+   } else if (drv_data & FLAGS_VER2) {
/* Disable monitoring */
writel(0x0, >regs->regs_v2.ter);
 
@@ -244,7 +290,22 @@ static int imx_tmu_enable_msite(struct udevice *dev)
if (!pdata->regs)
return -EIO;
 
-   if (drv_data & FLAGS_VER2) {
+   if (drv_data & FLAGS_VER3) {
+   reg = readl(>regs->regs_v3.ter);
+   reg &= ~TER_EN;
+   writel(reg, >regs->regs_v3.ter);
+
+   writel(pdata->id << 30, >regs->regs_v3.tps);
+
+   reg &= ~TER_ALPF;
+   reg |= 0x1;
+   reg &= ~TER_ADC_PD;
+   writel(reg, >regs->regs_v3.ter);
+
+   /* Enable monitor */
+   reg |= TER_EN;
+   writel(reg, >regs->regs_v3.ter);
+   } else if (drv_data & 

[PATCH 06/13] thermal: imx_tmu: Check the TEMP range for iMX8MM

[Peng Fan]

On iMX8MM, the V flag in TRISTR register only reflect the state of SNSR
value, not the calibrated TEMP value. So checking this flag is not
reliable. Per IC suggestion, change to read the TEMP/AVG_TEMP directly
and check whether it in valid range 10-125C.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/thermal/imx_tmu.c | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index 2a08d5085c..c577b0bd6c 100644
--- a/drivers/thermal/imx_tmu.c
+++ b/drivers/thermal/imx_tmu.c
@@ -106,16 +106,24 @@ static int read_temperature(struct udevice *dev, int 
*temp)
ulong drv_data = dev_get_driver_data(dev);
u32 val;
u32 retry = 10;
+   u32 valid = 0;
 
do {
mdelay(100);
retry--;
 
-   if (drv_data & FLAGS_VER2)
+   if (drv_data & FLAGS_VER2) {
val = readl(>regs->regs_v2.tritsr);
-   else
+   /*
+* Check if TEMP is in valid range, the V bit in TRITSR
+* only reflects the RAW uncalibrated data
+*/
+   valid =  ((val & 0xff) < 10 || (val & 0xff) > 125) ? 0 
: 1;
+   } else {
val = 
readl(>regs->regs_v1.site[pdata->id].tritsr);
-   } while (!(val & 0x8000) && retry > 0);
+   valid = val & 0x8000;
+   }
+   } while (!valid && retry > 0);
 
if (retry > 0)
*temp = (val & 0xff) * 1000;
-- 
2.16.4

[PATCH 04/13] thermal: imx_tmu: support TMU arch level initialization

[Peng Fan]

i.MX8MM TMU needs to load some registers from fuse, this is arch
dependent operation and may vary on different platforms. So add
a interface for arch level initialization.

Signed-off-by: Peng Fan 
---
 drivers/thermal/imx_tmu.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index df0b35b7ba..049f32c39e 100644
--- a/drivers/thermal/imx_tmu.c
+++ b/drivers/thermal/imx_tmu.c
@@ -187,6 +187,10 @@ static int imx_tmu_calibration(struct udevice *dev)
return 0;
 }
 
+void __weak imx_tmu_arch_init(void *reg_base)
+{
+}
+
 static void imx_tmu_init(struct udevice *dev)
 {
struct imx_tmu_plat *pdata = dev_get_platdata(dev);
@@ -210,6 +214,8 @@ static void imx_tmu_init(struct udevice *dev)
/* Set update_interval */
writel(TMTMIR_DEFAULT, >regs->regs_v1.tmtmir);
}
+
+   imx_tmu_arch_init((void *)pdata->regs);
 }
 
 static int imx_tmu_enable_msite(struct udevice *dev)
-- 
2.16.4

[PATCH 03/13] thermal: imx_tmu: Add support for thermal sensor on iMX8MM

[Peng Fan]

The analog sensors on iMX8MM are new, used for 14LPP process. So the
Temperature Sensor Monitoring Unit (TMU) has some change accordingly.
We use version 2 in TMU driver to represent the new TMU, so the one
driver can service for both i.MX8MQ/M.

Signed-off-by: Peng Fan 
---
 drivers/thermal/imx_tmu.c | 113 +++---
 1 file changed, 86 insertions(+), 27 deletions(-)

diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index f496ce03b6..df0b35b7ba 100644
--- a/drivers/thermal/imx_tmu.c
+++ b/drivers/thermal/imx_tmu.c
@@ -20,6 +20,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define SITES_MAX  16
+#define FLAGS_VER2 0x1
 
 #define TMR_DISABLE0x0
 #define TMR_ME 0x8000
@@ -27,6 +28,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define TMTMIR_DEFAULT 0x0002
 #define TIER_DISABLE   0x0
 
+#define TER_EN 0x8000
+#define TER_ADC_PD 0x4000
 /*
  * i.MX TMU Registers
  */
@@ -67,22 +70,47 @@ struct imx_tmu_regs {
u32 ttr3cr; /* Temperature Range 3 Control Register */
 };
 
+struct imx_tmu_regs_v2 {
+   u32 ter;/* TMU enable Register */
+   u32 tsr;/* Status Register */
+   u32 tier;   /* Interrupt enable register */
+   u32 tidr;   /* Interrupt detect  register */
+   u32 tmhtitr;/* Monitor high temperature immediate threshold 
register */
+   u32 tmhtatr;/* Monitor high temperature average threshold register 
*/
+   u32 tmhtactr;   /* TMU monitor high temperature average critical  
threshold register */
+   u32 tscr;   /* Sensor value capture register */
+   u32 tritsr; /* Report immediate temperature site register 0 */
+   u32 tratsr; /* Report average temperature site register 0 */
+   u32 tasr;   /* Amplifier setting register */
+   u32 ttmc;   /* Test MUX control */
+   u32 tcaliv;
+};
+
+union tmu_regs {
+   struct imx_tmu_regs regs_v1;
+   struct imx_tmu_regs_v2 regs_v2;
+};
+
 struct imx_tmu_plat {
int critical;
int alert;
int polling_delay;
int id;
bool zone_node;
-   struct imx_tmu_regs *regs;
+   union tmu_regs *regs;
 };
 
 static int read_temperature(struct udevice *dev, int *temp)
 {
struct imx_tmu_plat *pdata = dev_get_platdata(dev);
+   ulong drv_data = dev_get_driver_data(dev);
u32 val;
 
do {
-   val = readl(>regs->site[pdata->id].tritsr);
+   if (drv_data & FLAGS_VER2) {
+   val = readl(>regs->regs_v2.tritsr);
+   else
+   val = 
readl(>regs->regs_v1.site[pdata->id].tritsr);
} while (!(val & 0x8000));
 
*temp = (val & 0xff) * 1000;
@@ -124,9 +152,13 @@ static int imx_tmu_calibration(struct udevice *dev)
u32 range[4];
const fdt32_t *calibration;
struct imx_tmu_plat *pdata = dev_get_platdata(dev);
+   ulong drv_data = dev_get_driver_data(dev);
 
debug("%s\n", __func__);
 
+   if (drv_data & FLAGS_VER2)
+   return 0;
+
ret = dev_read_u32_array(dev, "fsl,tmu-range", range, 4);
if (ret) {
printf("TMU: missing calibration range, ret = %d.\n", ret);
@@ -134,10 +166,10 @@ static int imx_tmu_calibration(struct udevice *dev)
}
 
/* Init temperature range registers */
-   writel(range[0], >regs->ttr0cr);
-   writel(range[1], >regs->ttr1cr);
-   writel(range[2], >regs->ttr2cr);
-   writel(range[3], >regs->ttr3cr);
+   writel(range[0], >regs->regs_v1.ttr0cr);
+   writel(range[1], >regs->regs_v1.ttr1cr);
+   writel(range[2], >regs->regs_v1.ttr2cr);
+   writel(range[3], >regs->regs_v1.ttr3cr);
 
calibration = dev_read_prop(dev, "fsl,tmu-calibration", );
if (!calibration || len % 8) {
@@ -147,31 +179,43 @@ static int imx_tmu_calibration(struct udevice *dev)
 
for (i = 0; i < len; i += 8, calibration += 2) {
val = fdt32_to_cpu(*calibration);
-   writel(val, >regs->ttcfgr);
+   writel(val, >regs->regs_v1.ttcfgr);
val = fdt32_to_cpu(*(calibration + 1));
-   writel(val, >regs->tscfgr);
+   writel(val, >regs->regs_v1.tscfgr);
}
 
return 0;
 }
 
-static void imx_tmu_init(struct imx_tmu_plat *pdata)
+static void imx_tmu_init(struct udevice *dev)
 {
+   struct imx_tmu_plat *pdata = dev_get_platdata(dev);
+   ulong drv_data = dev_get_driver_data(dev);
+
debug("%s\n", __func__);
 
-   /* Disable monitoring */
-   writel(TMR_DISABLE, >regs->tmr);
+   if (drv_data & FLAGS_VER2) {
+   /* Disable monitoring */
+   writel(0x0, >regs->regs_v2.ter);
+
+   /* Disable interrupt, using polling instead */
+   writel(0x0, >regs->regs_v2.tier);
+   } else {
+   /* Disable monitoring */
+   

[PATCH 01/13] thermal: imx_scu_thermal: Update driver for i.MX8QM thermal sensor

[Peng Fan]

From: Ye Li 

Add iMX8QM thermal compatible string and its driver data.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/thermal/imx_scu_thermal.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/thermal/imx_scu_thermal.c 
b/drivers/thermal/imx_scu_thermal.c
index 7e17377b69..da13121a09 100644
--- a/drivers/thermal/imx_scu_thermal.c
+++ b/drivers/thermal/imx_scu_thermal.c
@@ -179,12 +179,20 @@ static int imx_sc_thermal_ofdata_to_platdata(struct 
udevice *dev)
return 0;
 }
 
+static const sc_rsrc_t imx8qm_sensor_rsrc[] = {
+   SC_R_A53, SC_R_A72, SC_R_GPU_0_PID0, SC_R_GPU_1_PID0,
+   SC_R_DRC_0, SC_R_DRC_1, SC_R_VPU_PID0, SC_R_PMIC_0,
+   SC_R_PMIC_1, SC_R_PMIC_2,
+};
+
 static const sc_rsrc_t imx8qxp_sensor_rsrc[] = {
SC_R_SYSTEM, SC_R_DRC_0, SC_R_PMIC_0,
SC_R_PMIC_1, SC_R_PMIC_2,
 };
 
 static const struct udevice_id imx_sc_thermal_ids[] = {
+   { .compatible = "nxp,imx8qm-sc-tsens", .data =
+   (ulong)_sensor_rsrc, },
{ .compatible = "nxp,imx8qxp-sc-tsens", .data =
(ulong)_sensor_rsrc, },
{ }
-- 
2.16.4

[PATCH 00/13] imx: tmu support and scu thermal update

[Peng Fan]

This patchset is to support TMU in i.MX8M family, including
i.MX8QM SCU thermal update.

Peng Fan (8):
  thermal: Add thermal driver for i.MX8M
  thermal: imx_tmu: Add support for thermal sensor on iMX8MM
  thermal: imx_tmu: support TMU arch level initialization
  thermal: imx_tmu: Fix for temperature out of range
  thermal: imx_tmu: Check the TEMP range for iMX8MM
  thermal: imx_tmu: support i.MX8MP
  imx: regs: add more fuse bank structure
  imx: cpu: support tmu

Ye Li (5):
  thermal: imx_scu_thermal: Update driver for i.MX8QM thermal sensor
  imx8mm: Load fuse for TMU TCALIV and TASR
  imx: i.MX8MN: Enable loading TASR and TCALIV from fuse
  imx: load calibration parameters from fuse for i.MX8MP
  imx8mp: Set default SNSR25C for TMU probe1

 arch/arm/include/asm/arch-imx8m/imx-regs.h |  41 ++-
 arch/arm/mach-imx/cpu.c|   4 +-
 arch/arm/mach-imx/imx8m/soc.c  |  75 -
 drivers/thermal/Kconfig|   9 +
 drivers/thermal/Makefile   |   1 +
 drivers/thermal/imx_scu_thermal.c  |   8 +
 drivers/thermal/imx_tmu.c  | 467 +
 7 files changed, 595 insertions(+), 10 deletions(-)
 create mode 100644 drivers/thermal/imx_tmu.c

-- 
2.16.4

Re: [PATCH v8 00/14] Add support for MediaTek xHCI host controller

[Marek Vasut]

On 5/3/20 8:33 AM, Frank Wunderlich wrote:
> 
> 
> Am 2. Mai 2020 12:32:56 MESZ schrieb Marek Vasut :
>> Applied, thanks.
>>
>> btw do you really need such a massive CC list ?
> 
> Thanks,
> 
> i took To/Cc from v7 (i guess coverletter) to prepare my coverletter and used 
> it for complete series.

But was such a massive CC really necessary ?

RE: [PATCH 2/3] net: tsec: Access eTSEC registers using virtual address

[Z.q. Hou]

Hi Vladimir,

Thanks a lot for your review and test!

Thanks,
Zhiqiang

> -Original Message-
> From: Vladimir Oltean 
> Sent: 2020年5月3日 19:36
> To: Z.q. Hou 
> Cc: u-boot ; Joe Hershberger
> ; Bin Meng ; Priyanka
> Jain 
> Subject: Re: [PATCH 2/3] net: tsec: Access eTSEC registers using virtual
> address
> 
> Hi Zhiqiang,
> 
> On Sun, 3 May 2020 at 09:28, Zhiqiang Hou 
> wrote:
> >
> > From: Hou Zhiqiang 
> >
> > The current code accesses eTSEC registers using physical address
> > directly, it's not correct, though no problem on current platforms. It
> > won't work on platforms, which does not support 1:1 virtual-physical
> > address map.
> >
> > Signed-off-by: Hou Zhiqiang 
> > ---
> 
> Reviewed-by: Vladimir Oltean 
> Tested-by: Vladimir Oltean 
> 
> (on LS1021A)
> 
> >  drivers/net/tsec.c | 9 ++---
> >  1 file changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index
> > f85cdcb97e..ce41aec5cf 100644
> > --- a/drivers/net/tsec.c
> > +++ b/drivers/net/tsec.c
> > @@ -798,7 +798,7 @@ int tsec_probe(struct udevice *dev)
> > int ret;
> >
> > pdata->iobase = (phys_addr_t)dev_read_addr(dev);
> > -   priv->regs = (struct tsec *)pdata->iobase;
> > +   priv->regs = dev_remap_addr(dev);
> >
> > if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> >_args)) { @@
> -817,8
> > +817,11 @@ int tsec_probe(struct udevice *dev)
> > }
> >
> > reg = ofnode_get_addr_index(parent, 0);
> > -   priv->phyregs_sgmii = (struct tsec_mii_mng *)
> > -   (reg + TSEC_MDIO_REGS_OFFSET);
> > +   if (reg == FDT_ADDR_T_NONE)
> > +   return -ENOENT;
> > +
> > +   priv->phyregs_sgmii = map_physmem(reg +
> TSEC_MDIO_REGS_OFFSET, 0,
> > + MAP_NOCACHE);
> >
> > ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0,
> 0,
> >  _args);
> > --
> > 2.17.1
> >

RE: [PATCH 3/3] net: tsec: Access TBI PHY through the corresponding MII

[Z.q. Hou]

Hi Vladimir,

Thanks a lot for your review and test!

> -Original Message-
> From: Vladimir Oltean 
> Sent: 2020年5月3日 19:35
> To: Z.q. Hou 
> Cc: u-boot ; Joe Hershberger
> ; Bin Meng ; Priyanka
> Jain 
> Subject: Re: [PATCH 3/3] net: tsec: Access TBI PHY through the
> corresponding MII
> 
> On Sun, 3 May 2020 at 09:28, Zhiqiang Hou 
> wrote:
> >
> > From: Hou Zhiqiang 
> >
> > When an eTSEC is configured to use TBI, configuration of the TBI is
> > done through the MIIM registers for that eTSEC.
> > For example, if a TBI interface is required on eTSEC2, then the MIIM
> > registers starting at offset 0x2_5520 are used to configure it.
> >
> > Fixes: 9a1d6af55ecd ("net: tsec: Add driver model ethernet support")
> > Signed-off-by: Hou Zhiqiang 
> > ---
> >  drivers/net/tsec.c | 17 ++---
> >  1 file changed, 14 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index
> > ce41aec5cf..31056f3117 100644
> > --- a/drivers/net/tsec.c
> > +++ b/drivers/net/tsec.c
> > @@ -789,6 +789,7 @@ int tsec_probe(struct udevice *dev)  {
> > struct eth_pdata *pdata = dev_get_platdata(dev);
> > struct tsec_private *priv = dev_get_priv(dev);
> > +   struct tsec_mii_mng __iomem *ext_phyregs_mii;
> > struct ofnode_phandle_args phandle_args;
> > u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
> > struct fsl_pq_mdio_info mdio_info; @@ -820,8 +821,8 @@ int
> > tsec_probe(struct udevice *dev)
> > if (reg == FDT_ADDR_T_NONE)
> > return -ENOENT;
> >
> > -   priv->phyregs_sgmii = map_physmem(reg +
> TSEC_MDIO_REGS_OFFSET, 0,
> > - MAP_NOCACHE);
> > +   ext_phyregs_mii = map_physmem(reg +
> TSEC_MDIO_REGS_OFFSET, 0,
> > + MAP_NOCACHE);
> >
> > ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0,
> 0,
> >  _args); @@
> -830,6
> > +831,16 @@ int tsec_probe(struct udevice *dev)
> >
> > priv->tbiaddr = tbiaddr;
> >
> > +   parent = ofnode_get_parent(phandle_args.node);
> > +   if (!ofnode_valid(parent)) {
> > +   printf("No parent node for TBI PHY?\n");
> > +   return -ENOENT;
> > +   }
> > +
> > +   reg = ofnode_get_addr_index(parent, 0);
> 
> Missing a check
> 
> if (reg == FDT_ADDR_T_NONE)
> return -ENOENT;
> 
> here?

Yes, will fix in v2.

Thanks,
Zhiqiang

> 
> > +   priv->phyregs_sgmii = map_physmem(reg +
> TSEC_MDIO_REGS_OFFSET, 0,
> > + MAP_NOCACHE);
> > +
> > phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
> > if (phy_mode)
> > pdata->phy_interface =
> > phy_get_interface_by_name(phy_mode);
> > @@ -844,7 +855,7 @@ int tsec_probe(struct udevice *dev)
> > if (priv->interface == PHY_INTERFACE_MODE_SGMII)
> > priv->flags |= TSEC_SGMII;
> >
> > -   mdio_info.regs = priv->phyregs_sgmii;
> > +   mdio_info.regs = ext_phyregs_mii;
> > mdio_info.name = (char *)dev->name;
> > ret = fsl_pq_mdio_init(NULL, _info);
> > if (ret)
> > --
> > 2.17.1
> >
> 
> With that:
> 
> Reviewed-by: Vladimir Oltean 
> Tested-by: Vladimir Oltean 
> 
> (on LS1021A)
> 
> Thanks!
> -Vladimir

RE: [PATCH 1/3] doc: dt-bindings: tsec: Correct the Ethernet port compatible string

[Z.q. Hou]

Hi Vladimir,

Thanks a lot for your ack!

> -Original Message-
> From: Vladimir Oltean 
> Sent: 2020年5月3日 19:13
> To: Z.q. Hou 
> Cc: u-boot ; Joe Hershberger
> ; Bin Meng ; Priyanka
> Jain ; mario@gdsys.cc
> Subject: Re: [PATCH 1/3] doc: dt-bindings: tsec: Correct the Ethernet port
> compatible string
> 
> On Sun, 3 May 2020 at 09:28, Zhiqiang Hou 
> wrote:
> >
> > From: Hou Zhiqiang 
> >
> > Change the compatible string to "fsl,etsec2" for the Ethernet ports,
> > which is used in the current driver's match table.
> >
> > Fixes: 69a00875e3db ("doc: dt-bindings: Describe Freescale TSEC
> > ethernet controller")
> > Signed-off-by: Hou Zhiqiang 
> > ---
> 
> Acked-by: Vladimir Oltean 
> 
> Although I am unclear how the G MPC8308 boards
> (arch/powerpc/dts/gdsys/mpc8308.dtsi) have ever probed their TSEC
> interfaces. Probably not based on DM, since the fsl,tsec compatible string
> has never been supported by the mainline tsec driver.

I agree with you, they seems using legacy driver. I'm working on the support
of compatible "gianfar", the MPC8308 boards can shift to the DM driver then.

Thanks,
Zhiqiang

> 
> >  doc/device-tree-bindings/net/fsl-tsec-phy.txt | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
> > b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
> > index 59989e3b09..8e8574bc97 100644
> > --- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
> > +++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
> > @@ -2,7 +2,7 @@
> >
> >  Properties:
> >
> > -  - compatible : Should be "fsl,tsec"
> > +  - compatible : Should be "fsl,etsec2"
> >- reg : Offset and length of the register set for the device
> >- phy-handle : See ethernet.txt file in the same directory.
> >- phy-connection-type : See ethernet.txt file in the same
> > directory. This @@ -12,7 +12,7 @@ Properties:
> >
> >  Example:
> > ethernet@24000 {
> > -   compatible = "fsl,tsec";
> > +   compatible = "fsl,etsec2";
> > reg = <0x24000 0x1000>;
> > phy-handle = <>;
> > phy-connection-type = "sgmii";
> > --
> > 2.17.1
> >

Re: [PATCH v2 8/8] rockchip: Enable PCIe/M.2 on rock960 board

[Manivannan Sadhasivam]

On Thu, Apr 30, 2020 at 12:34:12PM +0530, Jagan Teki wrote:
> Due to some on board limitation rock960 PCIe
> works only with 1.8V IO domain.
> 
> So, this patch enables grf io_sel explicitly
> to make PCIe/M.2 to work.
> 
> Cc: Tom Cubie 
> Cc: Manivannan Sadhasivam 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v2:
> - none
> 
>  board/vamrs/rock960_rk3399/rock960-rk3399.c | 20 
>  configs/rock960-rk3399_defconfig|  5 +
>  2 files changed, 25 insertions(+)
> 
> diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c 
> b/board/vamrs/rock960_rk3399/rock960-rk3399.c
> index 68a127b9ac..98d62e89ca 100644
> --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c
> +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c
> @@ -2,3 +2,23 @@
>  /*
>   * Copyright (C) 2018 Manivannan Sadhasivam 
> 
>   */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#ifdef CONFIG_MISC_INIT_R
> +int misc_init_r(void)
> +{
> + struct rk3399_grf_regs *grf =
> + syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +
> + /* BT565 is in 1.8v domain */

>From where this BT565 comes in?

Anyway, I don't have the PCI-E device with me to test this change but
it looks good to me.

Acked-by: Manivannan Sadhasivam 

PS: Added Peter to CC incase he is interested.

Thanks,
Mani

> + rk_setreg(>io_vsel, BIT(0));
> +
> + return 0;
> +}
> +#endif
> diff --git a/configs/rock960-rk3399_defconfig 
> b/configs/rock960-rk3399_defconfig
> index c4e954731a..cb1ec3c26b 100644
> --- a/configs/rock960-rk3399_defconfig
> +++ b/configs/rock960-rk3399_defconfig
> @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xFF1A
>  CONFIG_DEBUG_UART_CLOCK=2400
>  CONFIG_DEBUG_UART=y
>  CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
> +CONFIG_MISC_INIT_R=y
>  CONFIG_DISPLAY_BOARDINFO_LATE=y
>  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>  CONFIG_SPL_STACK_R=y
> @@ -19,6 +20,7 @@ CONFIG_CMD_BOOTZ=y
>  CONFIG_CMD_GPT=y
>  CONFIG_CMD_MMC=y
>  CONFIG_CMD_USB=y
> +CONFIG_CMD_PCI=y
>  # CONFIG_CMD_SETEXPR is not set
>  CONFIG_CMD_TIME=y
>  CONFIG_CMD_PMIC=y
> @@ -36,10 +38,13 @@ CONFIG_MMC_SDHCI=y
>  CONFIG_MMC_SDHCI_SDMA=y
>  CONFIG_MMC_SDHCI_ROCKCHIP=y
>  CONFIG_DM_ETH=y
> +CONFIG_NVME=y
> +CONFIG_PCI=y
>  CONFIG_PMIC_RK8XX=y
>  CONFIG_REGULATOR_PWM=y
>  CONFIG_REGULATOR_RK8XX=y
>  CONFIG_PWM_ROCKCHIP=y
> +CONFIG_DM_RESET=y
>  CONFIG_BAUDRATE=150
>  CONFIG_DEBUG_UART_SHIFT=2
>  CONFIG_SYSRESET=y
> -- 
> 2.17.1
> 

[PATCH V3 9/9] cpu: imx8: show RevC instead of Rev? at boot log

[Peng Fan]

From: Frank Li 

Add REVC informaiton.

Reviewed-by: Simon Glass 
Signed-off-by: Frank Li 
Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Add R-b tag

 arch/arm/include/asm/arch-imx/cpu.h | 1 +
 drivers/cpu/imx8_cpu.c  | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx/cpu.h 
b/arch/arm/include/asm/arch-imx/cpu.h
index 5ade63665a..06b8122e7c 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -57,6 +57,7 @@
 
 #define CHIP_REV_A 0x0
 #define CHIP_REV_B 0x1
+#define CHIP_REV_C 0x2
 
 #define BOARD_REV_1_0   0x0
 #define BOARD_REV_2_0   0x1
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 85ba7b7df2..95c14c98d8 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -43,6 +43,8 @@ const char *get_imx8_rev(u32 rev)
return "A";
case CHIP_REV_B:
return "B";
+   case CHIP_REV_C:
+   return "C";
default:
return "?";
}
-- 
2.16.4

[PATCH V3 8/9] cpu: imx_cpu: Print the CPU temperature for iMX8QM A72

[Peng Fan]

From: Ye Li 

iMX8QM registers two thermal devices for CPUs, get the temperature
from "cpu-thermal1" device for A72

Reviewed-by: Simon Glass 
Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
V3:
 None
V2:
 Per Simon's comments, use uclass_get_device

 drivers/cpu/imx8_cpu.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index cd11b78d06..85ba7b7df2 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -61,13 +61,15 @@ const char *get_core_name(struct udevice *dev)
 }
 
 #if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
-static int cpu_imx_get_temp(void)
+static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
 {
struct udevice *thermal_dev;
int cpu_tmp, ret;
 
-   ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0",
-   _dev);
+   if (!strcmp(plat->name, "A72"))
+   ret = uclass_get_device(UCLASS_THERMAL, 1, _dev);
+   else
+   ret = uclass_get_device(UCLASS_THERMAL, 0, _dev);
 
if (!ret) {
ret = thermal_get_temp(thermal_dev, _tmp);
@@ -80,7 +82,7 @@ static int cpu_imx_get_temp(void)
return cpu_tmp;
 }
 #else
-static int cpu_imx_get_temp(void)
+static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
 {
return 0;
 }
@@ -89,7 +91,7 @@ static int cpu_imx_get_temp(void)
 int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
 {
struct cpu_imx_platdata *plat = dev_get_platdata(dev);
-   int ret;
+   int ret, temp;
 
if (size < 100)
return -ENOSPC;
@@ -98,9 +100,13 @@ int cpu_imx_get_desc(struct udevice *dev, char *buf, int 
size)
   plat->type, plat->rev, plat->name, plat->freq_mhz);
 
if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
+   temp = cpu_imx_get_temp(plat);
buf = buf + ret;
size = size - ret;
-   ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
+   if (temp != 0xdeadbeef)
+   ret = snprintf(buf, size, " at %dC", temp);
+   else
+   ret = snprintf(buf, size, " - invalid sensor data");
}
 
snprintf(buf + ret, size - ret, "\n");
-- 
2.16.4

[PATCH V3 7/9] cpu: imx8: fix get core name and rate

[Peng Fan]

When current cpu is A53, using is_cortex_a53 could not detect A72
information, so check cpu device compatible property to get
the correct information.

Reviewed-by: Simon Glass 
Signed-off-by: Peng Fan 
---
V3:
 None
V2:
 Add R-b tag

 drivers/cpu/imx8_cpu.c | 27 +--
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index c4679e1642..cd11b78d06 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -48,13 +48,13 @@ const char *get_imx8_rev(u32 rev)
}
 }
 
-const char *get_core_name(void)
+const char *get_core_name(struct udevice *dev)
 {
-   if (is_cortex_a35())
+   if (!device_is_compatible(dev, "arm,cortex-a35"))
return "A35";
-   else if (is_cortex_a53())
+   else if (!device_is_compatible(dev, "arm,cortex-a53"))
return "A53";
-   else if (is_cortex_a72())
+   else if (!device_is_compatible(dev, "arm,cortex-a72"))
return "A72";
else
return "?";
@@ -170,12 +170,19 @@ static const struct udevice_id cpu_imx8_ids[] = {
{ }
 };
 
-static ulong imx8_get_cpu_rate(void)
+static ulong imx8_get_cpu_rate(struct udevice *dev)
 {
ulong rate;
-   int ret;
-   int type = is_cortex_a35() ? SC_R_A35 : is_cortex_a53() ?
-  SC_R_A53 : SC_R_A72;
+   int ret, type;
+
+   if (!device_is_compatible(dev, "arm,cortex-a35"))
+   type = SC_R_A35;
+   else if (!device_is_compatible(dev, "arm,cortex-a53"))
+   type = SC_R_A53;
+   else if (!device_is_compatible(dev, "arm,cortex-a72"))
+   type = SC_R_A72;
+   else
+   return 0;
 
ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU,
   (sc_pm_clock_rate_t *));
@@ -194,10 +201,10 @@ static int imx8_cpu_probe(struct udevice *dev)
 
cpurev = get_cpu_rev();
plat->cpurev = cpurev;
-   plat->name = get_core_name();
+   plat->name = get_core_name(dev);
plat->rev = get_imx8_rev(cpurev & 0xFFF);
plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
-   plat->freq_mhz = imx8_get_cpu_rate() / 100;
+   plat->freq_mhz = imx8_get_cpu_rate(dev) / 100;
plat->mpidr = dev_read_addr(dev);
if (plat->mpidr == FDT_ADDR_T_NONE) {
printf("%s: Failed to get CPU reg property\n", __func__);
-- 
2.16.4

[PATCH V3 6/9] cpu: imx8: support a72 as boot cpu

[Peng Fan]

Support booting i.MX8QM with A72 as boot cpu

Reviewed-by: Simon Glass 
Signed-off-by: Peng Fan 
---
V3:
 None
V2:
 Add R-b tag

 drivers/cpu/imx8_cpu.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 7c54c290b8..c4679e1642 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -20,6 +20,7 @@ struct cpu_imx_platdata {
const char *type;
u32 cpurev;
u32 freq_mhz;
+   u32 mpidr;
 };
 
 const char *get_imx8_type(u32 imxtype)
@@ -144,16 +145,28 @@ static int cpu_imx_get_vendor(struct udevice *dev,  char 
*buf, int size)
return 0;
 }
 
+static int cpu_imx_is_current(struct udevice *dev)
+{
+   struct cpu_imx_platdata *plat = dev_get_platdata(dev);
+
+   if (plat->mpidr == (read_mpidr() & 0x))
+   return 1;
+
+   return 0;
+}
+
 static const struct cpu_ops cpu_imx8_ops = {
.get_desc   = cpu_imx_get_desc,
.get_info   = cpu_imx_get_info,
.get_count  = cpu_imx_get_count,
.get_vendor = cpu_imx_get_vendor,
+   .is_current = cpu_imx_is_current,
 };
 
 static const struct udevice_id cpu_imx8_ids[] = {
{ .compatible = "arm,cortex-a35" },
{ .compatible = "arm,cortex-a53" },
+   { .compatible = "arm,cortex-a72" },
{ }
 };
 
@@ -185,6 +198,12 @@ static int imx8_cpu_probe(struct udevice *dev)
plat->rev = get_imx8_rev(cpurev & 0xFFF);
plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
plat->freq_mhz = imx8_get_cpu_rate() / 100;
+   plat->mpidr = dev_read_addr(dev);
+   if (plat->mpidr == FDT_ADDR_T_NONE) {
+   printf("%s: Failed to get CPU reg property\n", __func__);
+   return -EINVAL;
+   }
+
return 0;
 }
 
-- 
2.16.4

[PATCH V3 4/9] common: board_f: Use cpu_get_current_dev in print_cpuinfo

[Peng Fan]

From: Ye Li 

Current print_cpuinfo gets the first udevice in CPU class to return
the cpu info. This has problem if the boot CPU is not fixed.

Changing to use new API cpu_get_current_dev to fix the issue.

Reviewed-by: Simon Glass 
Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 None

 common/board_f.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/common/board_f.c b/common/board_f.c
index 5c650f046c..5223453511 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -183,11 +183,11 @@ static int print_cpuinfo(void)
char desc[512];
int ret;
 
-   ret = uclass_first_device_err(UCLASS_CPU, );
-   if (ret) {
-   debug("%s: Could not get CPU device (err = %d)\n",
- __func__, ret);
-   return ret;
+   dev = cpu_get_current_dev();
+   if (!dev) {
+   debug("%s: Could not get CPU device\n",
+ __func__);
+   return -ENODEV;
}
 
ret = cpu_get_desc(dev, desc, sizeof(desc));
-- 
2.16.4

[PATCH V3 3/9] test: cpu: test current cpu

[Peng Fan]

Add test whether the CPU is U-Boot is running from.

Reviewed-by: Simon Glass 
Signed-off-by: Peng Fan 
---
V3:
 Add R-b tag
V2:
 New

 test/dm/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/test/dm/cpu.c b/test/dm/cpu.c
index e6dc576ea3..def9b64a28 100644
--- a/test/dm/cpu.c
+++ b/test/dm/cpu.c
@@ -26,6 +26,8 @@ static int dm_test_cpu(struct unit_test_state *uts)
ut_assert(dev->flags & DM_FLAG_ACTIVATED);
 
ut_assertok(uclass_get_device_by_name(UCLASS_CPU, "cpu-test1", ));
+   ut_asserteq_ptr(cpu_get_current_dev(), dev);
+   ut_asserteq(cpu_is_current(dev), 1);
 
ut_assertok(cpu_get_desc(dev, text, sizeof(text)));
ut_assertok(strcmp(text, "LEG Inc. SuperMegaUltraTurbo CPU No. 1"));
-- 
2.16.4

[PATCH V3 5/9] cpu: imx8: reimplement get cpu count

[Peng Fan]

Return 4 is not correct on i.MX8DX/DXL/8QM and etc. we need to count
available cpu node with device_type "cpu".

Reviewed-by: Simon Glass 
Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Add R-b tag

 drivers/cpu/imx8_cpu.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 95653683ac..7c54c290b8 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -118,7 +118,24 @@ static int cpu_imx_get_info(struct udevice *dev, struct 
cpu_info *info)
 
 static int cpu_imx_get_count(struct udevice *dev)
 {
-   return 4;
+   ofnode node;
+   int num = 0;
+
+   ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+   const char *device_type;
+
+   if (!ofnode_is_available(node))
+   continue;
+
+   device_type = ofnode_read_string(node, "device_type");
+   if (!device_type)
+   continue;
+
+   if (!strcmp(device_type, "cpu"))
+   num++;
+   }
+
+   return num;
 }
 
 static int cpu_imx_get_vendor(struct udevice *dev,  char *buf, int size)
-- 
2.16.4

[PATCH V3 2/9] cpu: sandbox: support is_current

[Peng Fan]

Support querying whether U-Boot is running on current cpu

Reviewed-by: Simon Glass 
Signed-off-by: Peng Fan 
---
V3:
 Add R-b
V2:
 New

 drivers/cpu/cpu_sandbox.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c
index 05b384f6a4..30a12e5a53 100644
--- a/drivers/cpu/cpu_sandbox.c
+++ b/drivers/cpu/cpu_sandbox.c
@@ -36,11 +36,20 @@ int cpu_sandbox_get_vendor(struct udevice *dev, char *buf, 
int size)
return 0;
 }
 
+int cpu_sandbox_is_current(struct udevice *dev)
+{
+   if (!strcmp(dev->name, "cpu-test1"))
+   return 1;
+
+   return 0;
+}
+
 static const struct cpu_ops cpu_sandbox_ops = {
.get_desc = cpu_sandbox_get_desc,
.get_info = cpu_sandbox_get_info,
.get_count = cpu_sandbox_get_count,
.get_vendor = cpu_sandbox_get_vendor,
+   .is_current = cpu_sandbox_is_current,
 };
 
 int cpu_sandbox_probe(struct udevice *dev)
-- 
2.16.4

[PATCH V3 1/9] uclass: cpu: Add new API to get udevice for current CPU

[Peng Fan]

When running on SoC with multiple clusters, the boot CPU may
not be fixed, saying booting from cluster A or cluster B.
Add a API that can return the udevice for current boot CPU.
Cpu driver needs to implement is_current_cpu interface for this
feature, otherwise the API only returns the first udevice in
cpu uclass.

Reviewed-by: Simon Glass 
Signed-off-by: Peng Fan 
Signed-off-by: Ye Li 
---
V3:
 Drop ops check. Add R-b

V2:
 Per Simon's comment,
  - Add cpu_is_current
  - use uclass_foreach_dev_probe
  - Update code comment


 drivers/cpu/cpu-uclass.c | 34 ++
 include/cpu.h| 23 +++
 2 files changed, 57 insertions(+)

diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c
index 457f77b7c8..8352e2eb0b 100644
--- a/drivers/cpu/cpu-uclass.c
+++ b/drivers/cpu/cpu-uclass.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 int cpu_probe_all(void)
 {
@@ -34,6 +35,39 @@ int cpu_probe_all(void)
return 0;
 }
 
+int cpu_is_current(struct udevice *cpu)
+{
+   struct cpu_ops *ops = cpu_get_ops(cpu);
+
+   if (ops->is_current) {
+   if (ops->is_current(cpu))
+   return 1;
+   }
+
+   return -ENOSYS;
+}
+
+struct udevice *cpu_get_current_dev(void)
+{
+   struct udevice *cpu;
+   int ret;
+
+   uclass_foreach_dev_probe(UCLASS_CPU, cpu) {
+   if (cpu_is_current(cpu) > 0)
+   return cpu;
+   }
+
+   /* If can't find current cpu device, use the first dev instead */
+   ret = uclass_first_device_err(UCLASS_CPU, );
+   if (ret) {
+   debug("%s: Could not get CPU device (err = %d)\n",
+ __func__, ret);
+   return NULL;
+   }
+
+   return cpu;
+}
+
 int cpu_get_desc(struct udevice *dev, char *buf, int size)
 {
struct cpu_ops *ops = cpu_get_ops(dev);
diff --git a/include/cpu.h b/include/cpu.h
index 6b1b6b37b3..2f283fe244 100644
--- a/include/cpu.h
+++ b/include/cpu.h
@@ -89,6 +89,15 @@ struct cpu_ops {
 * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
 */
int (*get_vendor)(struct udevice *dev, char *buf, int size);
+
+   /**
+* is_current() - Check if the CPU that U-Boot is currently running from
+*
+* @dev:Device to check (UCLASS_CPU)
+* @return 1 if the CPU that U-Boot is currently running from, 0
+* if not.
+*/
+   int (*is_current)(struct udevice *dev);
 };
 
 #define cpu_get_ops(dev)((struct cpu_ops *)(dev)->driver->ops)
@@ -137,4 +146,18 @@ int cpu_get_vendor(struct udevice *dev, char *buf, int 
size);
  */
 int cpu_probe_all(void);
 
+/**
+ * cpu_is_current() - Check if the CPU that U-Boot is currently running from
+ *
+ * Return: 1 if yes, - 0 if not
+ */
+int cpu_is_current(struct udevice *cpu);
+
+/**
+ * cpu_get_current_dev() - Get CPU udevice for current CPU
+ *
+ * Return: udevice if OK, - NULL on error
+ */
+struct udevice *cpu_get_current_dev(void);
+
 #endif
-- 
2.16.4

RE: [PATCH V2 1/9] uclass: cpu: Add new API to get udevice for current CPU

[Peng Fan]

Hi Simon,

> Subject: Re: [PATCH V2 1/9] uclass: cpu: Add new API to get udevice for
> current CPU
> 
> Hi Peng,
> 
> On Fri, 1 May 2020 at 07:22, Peng Fan  wrote:
> >
> > When running on SoC with multiple clusters, the boot CPU may not be
> > fixed, saying booting from cluster A or cluster B.
> > Add a API that can return the udevice for current boot CPU.
> > Cpu driver needs to implement is_current_cpu interface for this
> > feature, otherwise the API only returns the first udevice in cpu
> > uclass.
> >
> > Signed-off-by: Peng Fan 
> > Signed-off-by: Ye Li 
> > ---
> >
> > V2:
> >  Per Simon's comment,
> >   - Add cpu_is_current
> >   - use uclass_foreach_dev_probe
> >   - Update code comment
> >
> >  drivers/cpu/cpu-uclass.c | 34 ++
> >  include/cpu.h| 23 +++
> >  2 files changed, 57 insertions(+)
> >
> 
> Reviewed-by: Simon Glass 
> 
> 
> > diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index
> > 457f77b7c8..33d38a0fde 100644
> > --- a/drivers/cpu/cpu-uclass.c
> > +++ b/drivers/cpu/cpu-uclass.c
> > @@ -10,6 +10,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> >  int cpu_probe_all(void)
> >  {
> > @@ -34,6 +35,39 @@ int cpu_probe_all(void)
> > return 0;
> >  }
> >
> > +int cpu_is_current(struct udevice *cpu) {
> > +   struct cpu_ops *ops = cpu_get_ops(cpu);
> > +
> > +   if (ops && ops->is_current) {
> > +   if (ops->is_current(cpu))
> > +   return 1;
> 
> return 0 here I think

I prefer to use 1 here, since is_current return 0 seems
werid to show it is the cpu that uboot is running from.

> 
> Also you should not check 'ops'.

I'll drop it.

Thanks,
Peng.

> 
> 
> > +   }
> > +
> > +   return -ENOSYS;
> > +}
> > +
> > +struct udevice *cpu_get_current_dev(void) {
> > +   struct udevice *cpu;
> > +   int ret;
> > +
> > +   uclass_foreach_dev_probe(UCLASS_CPU, cpu) {
> > +   if (cpu_is_current(cpu) > 0)
> > +   return cpu;
> > +   }
> > +
> > +   /* If can't find current cpu device, use the first dev instead */
> > +   ret = uclass_first_device_err(UCLASS_CPU, );
> > +   if (ret) {
> > +   debug("%s: Could not get CPU device (err = %d)\n",
> > + __func__, ret);
> > +   return NULL;
> > +   }
> > +
> > +   return cpu;
> > +}
> > +
> >  int cpu_get_desc(struct udevice *dev, char *buf, int size)  {
> > struct cpu_ops *ops = cpu_get_ops(dev); diff --git
> > a/include/cpu.h b/include/cpu.h index 6b1b6b37b3..2f283fe244 100644
> > --- a/include/cpu.h
> > +++ b/include/cpu.h
> > @@ -89,6 +89,15 @@ struct cpu_ops {
> >  * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on
> error
> >  */
> > int (*get_vendor)(struct udevice *dev, char *buf, int size);
> > +
> > +   /**
> > +* is_current() - Check if the CPU that U-Boot is currently running
> from
> > +*
> > +* @dev:Device to check (UCLASS_CPU)
> > +* @return 1 if the CPU that U-Boot is currently running from, 0
> > +* if not.
> > +*/
> > +   int (*is_current)(struct udevice *dev);
> >  };
> >
> >  #define cpu_get_ops(dev)((struct cpu_ops *)(dev)->driver->ops)
> > @@ -137,4 +146,18 @@ int cpu_get_vendor(struct udevice *dev, char *buf,
> int size);
> >   */
> >  int cpu_probe_all(void);
> >
> > +/**
> > + * cpu_is_current() - Check if the CPU that U-Boot is currently
> > +running from
> > + *
> > + * Return: 1 if yes, - 0 if not
> > + */
> > +int cpu_is_current(struct udevice *cpu);
> > +
> > +/**
> > + * cpu_get_current_dev() - Get CPU udevice for current CPU
> > + *
> > + * Return: udevice if OK, - NULL on error  */ struct udevice
> > +*cpu_get_current_dev(void);
> > +
> >  #endif
> > --
> > 2.16.4
> >

[PATCH V2] imx: Add support for i.MX8MM Beacon EmbeddedWorks devkit.

[Adam Ford]

Beacon EmbeddedWorks, formerly known as Logic PD, is releasing
a devkit based on the i.MX8M Mini SoC consisting of baseboard +
SOM.

It supports eMMC on the SOM, microSD on the baseboard, various
GPIO, the PINCTRL, and UART.

Signed-off-by: Adam Ford 
---
V2:  Remove do_reset from SPL and enable caches during SPL.
 Remove more remnants of un-related hardware.
 Add MAINTAINERS file.

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2c123bd6da..9c0fb8488d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -733,7 +733,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-verdin.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-evk.dtb \
-   imx8mp-evk.dtb
+   imx8mp-evk.dtb \
+   imx8mm-beacon-kit.dtb
 
 dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi 
b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
new file mode 100644
index 00..baa5f997d0
--- /dev/null
+++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/ {
+   leds {
+   compatible = "gpio-leds";
+
+   led0 {
+   label = "gen_led0";
+   gpios = <_1 4 GPIO_ACTIVE_HIGH>;
+   default-state = "none";
+   };
+
+   led1 {
+   label = "gen_led1";
+   gpios = <_1 5 GPIO_ACTIVE_HIGH>;
+   default-state = "none";
+   };
+
+   led2 {
+   label = "gen_led2";
+   gpios = <_1 6 GPIO_ACTIVE_HIGH>;
+   default-state = "none";
+   };
+
+   led3 {
+   pinctrl-names = "default";
+   pinctrl-0 = <_led3>;
+   label = "heartbeat";
+   gpios = < 28 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+
+   reg_audio: regulator-audio {
+   compatible = "regulator-fixed";
+   regulator-name = "3v3_aud";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <_1 11 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   reg_usdhc2_vmmc: regulator-usdhc2 {
+   compatible = "regulator-fixed";
+   regulator-name = "VSD_3V3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = < 19 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   sound {
+   compatible = "fsl,imx-audio-wm8962";
+   model = "wm8962-audio";
+   audio-cpu = <>;
+   audio-codec = <>;
+   audio-routing =
+   "Headphone Jack", "HPOUTL",
+   "Headphone Jack", "HPOUTR",
+   "Ext Spk", "SPKOUTL",
+   "Ext Spk", "SPKOUTR",
+   "AMIC", "MICBIAS",
+   "IN3R", "AMIC";
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_espi2>;
+   cs-gpios = < 9 0>;
+   status = "okay";
+
+   eeprom@0 {
+   compatible = "microchip,at25160bn", "atmel,at25";
+   reg = <0>;
+   spi-max-frequency = <500>;
+   spi-cpha;
+   spi-cpol;
+   pagesize = <32>;
+   size = <2048>;
+   address-width = <16>;
+   };
+};
+
+ {
+   clock-frequency = <40>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c2>;
+   status = "okay";
+};
+
+ {
+   clock-frequency = <40>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c4>;
+   status = "okay";
+
+   wm8962: audio-codec@1a {
+   compatible = "wlf,wm8962";
+   reg = <0x1a>;
+   clocks = < IMX8MM_CLK_SAI3_ROOT>;
+   clock-names = "xclk";
+   DCVDD-supply = <_audio>;
+   DBVDD-supply = <_audio>;
+   AVDD-supply = <_audio>;
+   CPVDD-supply = <_audio>;
+   MICVDD-supply = <_audio>;
+   PLLVDD-supply = <_audio>;
+   SPKVDD1-supply = <_audio>;
+   SPKVDD2-supply = <_audio>;
+   gpio-cfg = <
+   0x /* 0:Default */
+   0x /* 1:Default */
+   0x /* 2:FN_DMICCLK */
+   0x /* 3:Default */
+   0x /* 4:FN_DMICCDAT */
+   0x /* 5:Default */
+   >;
+   };
+
+   pca6416_0: gpio@20 {
+   compatible = "nxp,pcal6416";
+   reg = 

[PATCH] dm: serial: introduce puts hook

[Peng Fan]

Introduce puts hook for dm serial driver.

Signed-off-by: Peng Fan 
---
 drivers/serial/serial-uclass.c | 13 +++--
 include/serial.h   |  8 
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 7703c67492..b6a7502ac8 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -189,8 +189,17 @@ static void _serial_putc(struct udevice *dev, char ch)
 
 static void _serial_puts(struct udevice *dev, const char *str)
 {
-   while (*str)
-   _serial_putc(dev, *str++);
+   struct dm_serial_ops *ops = serial_get_ops(dev);
+   int err;
+
+   if (ops->puts) {
+   do {
+   err = ops->puts(dev, str);
+   } while (err == -EAGAIN);
+   } else {
+   while (*str)
+   _serial_putc(dev, *str++);
+   }
 }
 
 static int __serial_getc(struct udevice *dev)
diff --git a/include/serial.h b/include/serial.h
index 54b21a0470..0b40b27526 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -186,6 +186,14 @@ struct dm_serial_ops {
 * @return character (0..255), -ve on error
 */
int (*getc)(struct udevice *dev);
+   /**
+* puts() - puts a string
+*
+* @dev: Device pointer
+* @str: string to write
+* @return 0 if OK, -ve on error
+*/
+   int (*puts)(struct udevice *dev, const char *str);
/**
 * putc() - Write a character
 *
-- 
2.16.4

[PATCH] sf: Add Macronix MX25R6435F SPI NOR flash to flash parameters array

[Peng Fan]

From: Ye Li 

On i.mx7ulp EVK board, we use MX25R6435F NOR flash, add its parameters
and IDs to flash parameter array. Otherwise, the flash probe will fails.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/mtd/spi/spi-nor-ids.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index abdf560e02..b80b25650b 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -159,6 +159,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx66u2g45g",  0xc2253c, 0, 64 * 1024, 4096, SECT_4K | 
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66l1g45g",  0xc2201b, 0, 64 * 1024, 2048, SECT_4K | 
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | 
SPI_NOR_4B_OPCODES | SECT_4K) },
+   { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
 #endif
 
 #ifdef CONFIG_SPI_FLASH_STMICRO/* STMICRO */
-- 
2.16.4

[PATCH] pinctrl: nxp: scu: Check the pad partition before set pinmux

[Peng Fan]

From: Ye Li 

If a pad is not owned by current partition we should not set its
pinmux.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/pinctrl/nxp/pinctrl-scu.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/nxp/pinctrl-scu.c 
b/drivers/pinctrl/nxp/pinctrl-scu.c
index aa11075e0a..c032be782a 100644
--- a/drivers/pinctrl/nxp/pinctrl-scu.c
+++ b/drivers/pinctrl/nxp/pinctrl-scu.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2019 NXP
  */
 
 #include 
@@ -29,6 +29,11 @@ static int imx_pinconf_scu_set(struct imx_pinctrl_soc_info 
*info, u32 pad,
 * to handle that in scfw, so config it in pad conf func
 */
 
+   if (!sc_rm_is_pad_owned(-1, pad)) {
+   debug("Pad[%u] is not owned by curr partition\n", pad);
+   return -EPERM;
+   }
+
val |= PADRING_IFMUX_EN_MASK;
val |= PADRING_GP_EN_MASK;
val |= (mux << PADRING_IFMUX_SHIFT) & PADRING_IFMUX_MASK;
@@ -57,7 +62,7 @@ int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info 
*info, u32 *pin_data,
config_val = pin_data[j++];
 
ret = imx_pinconf_scu_set(info, pin_id, mux, config_val);
-   if (ret)
+   if (ret && ret != -EPERM)
printf("Set pin %d, mux %d, val %d, error\n", pin_id,
   mux, config_val);
}
-- 
2.16.4

[PATCH 2/4] clk: clk-imx8mn: Update clock tree and support set parent

[Peng Fan]

From: Ye Li 

Add set clock parent support.
Add ENET and flexspi related clocks to support assigned clocks

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/clk/imx/clk-imx8mn.c | 56 
 1 file changed, 56 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index eb43971ae6..64aea15a40 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -80,6 +80,17 @@ static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", 
"sys_pll1_133m", "sys_p
 static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", 
"sys_pll1_800m", "sys_pll2_250m",
 "sys_pll2_200m", "audio_pll1_out", 
"video_pll1_out", "sys_pll3_out", };
 
+#ifndef CONFIG_SPL_BUILD
+static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", 
"sys_pll2_50m", "sys_pll2_100m",
+"sys_pll1_160m", "audio_pll1_out", 
"video_pll1_out", "clk_ext4", };
+
+static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", 
"sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
+  "clk_ext3", "clk_ext4", 
"video_pll1_out", };
+
+static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", 
"sys_pll2_125m", "sys_pll2_200m",
+"sys_pll2_500m", "video_pll1_out", 
"audio_pll2_out", };
+#endif
+
 static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", 
"sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
   "sys_pll1_133m", "sys_pll3_out", 
"sys_pll2_250m", "audio_pll1_out", };
 
@@ -107,6 +118,9 @@ static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", 
"sys_pll1_133m", "sys_
 static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll1_800m", "sys_pll2_500m",
   "sys_pll3_out", "sys_pll1_266m", 
"audio_pll2_clk", "sys_pll1_100m", };
 
+static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll2_333m", "sys_pll2_500m",
+  "audio_pll2_out", "sys_pll1_266m", 
"sys_pll3_out", "sys_pll1_100m", };
+
 static ulong imx8mn_clk_get_rate(struct clk *clk)
 {
struct clk *c;
@@ -164,11 +178,33 @@ static int imx8mn_clk_enable(struct clk *clk)
return __imx8mn_clk_enable(clk, 1);
 }
 
+static int imx8mn_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+   struct clk *c, *cp;
+   int ret;
+
+   debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+   ret = clk_get_by_id(clk->id, );
+   if (ret)
+   return ret;
+
+   ret = clk_get_by_id(parent->id, );
+   if (ret)
+   return ret;
+
+   ret = clk_set_parent(c, cp);
+   c->dev->parent = cp->dev;
+
+   return ret;
+}
+
 static struct clk_ops imx8mn_clk_ops = {
.set_rate = imx8mn_clk_set_rate,
.get_rate = imx8mn_clk_get_rate,
.enable = imx8mn_clk_enable,
.disable = imx8mn_clk_disable,
+   .set_parent = imx8mn_clk_set_parent,
 };
 
 static int imx8mn_clk_probe(struct udevice *dev)
@@ -339,6 +375,8 @@ static int imx8mn_clk_probe(struct udevice *dev)
clk_dm(IMX8MN_CLK_USDHC3,
   imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
   base + 0xbc80));
+   clk_dm(IMX8MN_CLK_QSPI,
+  imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
 
clk_dm(IMX8MN_CLK_I2C1_ROOT,
   imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
@@ -362,6 +400,24 @@ static int imx8mn_clk_probe(struct udevice *dev)
   imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
clk_dm(IMX8MN_CLK_USDHC3_ROOT,
   imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+   clk_dm(IMX8MN_CLK_QSPI_ROOT,
+  imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+
+   /* clks not needed in SPL stage */
+#ifndef CONFIG_SPL_BUILD
+   clk_dm(IMX8MN_CLK_ENET_REF,
+  imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
+  base + 0xa980));
+   clk_dm(IMX8MN_CLK_ENET_TIMER,
+  imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
+  base + 0xaa00));
+   clk_dm(IMX8MN_CLK_ENET_PHY_REF,
+  imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
+  base + 0xaa80));
+   clk_dm(IMX8MN_CLK_ENET1_ROOT,
+  imx_clk_gate4("enet1_root_clk", "enet_axi",
+  base + 0x40a0, 0));
+#endif
 
 #ifdef CONFIG_SPL_BUILD
struct clk *clkp, *clkp1;
-- 
2.16.4

[PATCH 3/4] clk: imx8mm/8mn: Add USB clocks

[Peng Fan]

From: Ye Li 

Add USB relevant clocks to support usb clock settings for both
DM USB host and gadget drivers

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/clk/imx/clk-imx8mm.c | 17 +
 drivers/clk/imx/clk-imx8mn.c | 20 
 2 files changed, 37 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 95069e7395..1db615c355 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -94,6 +94,9 @@ static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", 
"sys_pll2_50m", "s
 static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", 
"sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
   "sys_pll1_133m", "sys_pll3_out", 
"sys_pll2_250m", "audio_pll1_out", };
 
+static const char *imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", 
"sys_pll1_800m", "sys_pll2_100m",
+   "sys_pll2_200m", "clk_ext2", 
"clk_ext4", "audio_pll2_out", };
+
 static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll1_800m", "sys_pll2_500m",
   "sys_pll3_out", "sys_pll1_266m", 
"audio_pll2_out", "sys_pll1_100m", };
 
@@ -121,6 +124,12 @@ static const char *imx8mm_usdhc3_sels[] = 
{"clock-osc-24m", "sys_pll1_400m", "sy
 static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll2_333m", "sys_pll2_500m",
   "audio_pll2_out", "sys_pll1_266m", 
"sys_pll3_out", "sys_pll1_100m", };
 
+static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", 
"sys_pll1_40m", "sys_pll2_100m",
+"sys_pll2_200m", "clk_ext2", 
"clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", 
"sys_pll1_40m", "sys_pll2_100m",
+"sys_pll2_200m", "clk_ext2", 
"clk_ext3", "audio_pll2_out", };
+
 static ulong imx8mm_clk_get_rate(struct clk *clk)
 {
struct clk *c;
@@ -354,6 +363,8 @@ static int imx8mm_clk_probe(struct udevice *dev)
   imx8m_clk_composite_critical("nand_usdhc_bus",
imx8mm_nand_usdhc_sels,
base + 0x8900));
+   clk_dm(IMX8MM_CLK_USB_BUS,
+   imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 
0x8b80));
 
/* IP */
clk_dm(IMX8MM_CLK_USDHC1,
@@ -377,6 +388,10 @@ static int imx8mm_clk_probe(struct udevice *dev)
   base + 0xbc80));
clk_dm(IMX8MM_CLK_QSPI,
   imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
+   clk_dm(IMX8MM_CLK_USB_CORE_REF,
+   imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base 
+ 0xb100));
+   clk_dm(IMX8MM_CLK_USB_PHY_REF,
+   imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 
0xb180));
 
clk_dm(IMX8MM_CLK_I2C1_ROOT,
   imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
@@ -402,6 +417,8 @@ static int imx8mm_clk_probe(struct udevice *dev)
   imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
clk_dm(IMX8MM_CLK_QSPI_ROOT,
   imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+   clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
+   imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 
0));
 
/* clks not needed in SPL stage */
 #ifndef CONFIG_SPL_BUILD
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 64aea15a40..c805da1ca3 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -94,6 +94,10 @@ static const char *imx8mn_enet_phy_sels[] = 
{"clock-osc-24m", "sys_pll2_50m", "s
 static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", 
"sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
   "sys_pll1_133m", "sys_pll3_out", 
"sys_pll2_250m", "audio_pll1_out", };
 
+static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", 
"sys_pll2_500m", "sys_pll1_800m",
+   "sys_pll2_100m", 
"sys_pll2_200m", "clk_ext2",
+   "clk_ext4", "audio_pll2_out", };
+
 static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll1_800m", "sys_pll2_500m",
   "sys_pll3_out", "sys_pll1_266m", 
"audio_pll2_out", "sys_pll1_100m", };
 
@@ -121,6 +125,14 @@ static const char *imx8mn_usdhc3_sels[] = 
{"clock-osc-24m", "sys_pll1_400m", "sy
 static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll2_333m", "sys_pll2_500m",
   "audio_pll2_out", "sys_pll1_266m", 
"sys_pll3_out", "sys_pll1_100m", };
 
+static 

[PATCH 1/4] clk: clk-imx8mm: Add flexspi clock and fix set parent

[Peng Fan]

From: Ye Li 

Add flexspi relevant clocks, and fix set parent clock,  so we can
assign clocks through DTB

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/clk/imx/clk-imx8mm.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index fc41a028f6..95069e7395 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -118,6 +118,9 @@ static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", 
"sys_pll1_133m", "sys_
 static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll1_800m", "sys_pll2_500m",
   "sys_pll3_out", "sys_pll1_266m", 
"audio_pll2_clk", "sys_pll1_100m", };
 
+static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll2_333m", "sys_pll2_500m",
+  "audio_pll2_out", "sys_pll1_266m", 
"sys_pll3_out", "sys_pll1_100m", };
+
 static ulong imx8mm_clk_get_rate(struct clk *clk)
 {
struct clk *c;
@@ -190,7 +193,10 @@ static int imx8mm_clk_set_parent(struct clk *clk, struct 
clk *parent)
if (ret)
return ret;
 
-   return clk_set_parent(c, cp);
+   ret = clk_set_parent(c, cp);
+   c->dev->parent = cp->dev;
+
+   return ret;
 }
 
 static struct clk_ops imx8mm_clk_ops = {
@@ -369,6 +375,8 @@ static int imx8mm_clk_probe(struct udevice *dev)
clk_dm(IMX8MM_CLK_USDHC3,
   imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
   base + 0xbc80));
+   clk_dm(IMX8MM_CLK_QSPI,
+  imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
 
clk_dm(IMX8MM_CLK_I2C1_ROOT,
   imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
@@ -392,6 +400,8 @@ static int imx8mm_clk_probe(struct udevice *dev)
   imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
clk_dm(IMX8MM_CLK_USDHC3_ROOT,
   imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+   clk_dm(IMX8MM_CLK_QSPI_ROOT,
+  imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
 
/* clks not needed in SPL stage */
 #ifndef CONFIG_SPL_BUILD
-- 
2.16.4

[PATCH 4/4] clk: imx8mp: Update imx8mp ccf clock driver

[Peng Fan]

From: Ye Li 

Add clocks for FEC and flexspi, and add set parent clock callback,
so DTS can assign clocks

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/clk/imx/clk-imx8mp.c | 52 
 1 file changed, 52 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index a2693d2f7a..787b5750ce 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -79,6 +79,10 @@ static const char *imx8mp_main_axi_sels[] = 
{"clock-osc-24m", "sys_pll2_333m", "
 "sys_pll2_250m", "sys_pll2_1000m", 
"audio_pll1_out",
 "video_pll1_out", 
"sys_pll1_100m",};
 
+static const char *imx8mp_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", 
"sys_pll1_800m",
+"sys_pll2_250m", "sys_pll2_200m", 
"audio_pll1_out",
+"video_pll1_out", "sys_pll3_out", 
};
+
 static const char *imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", 
"sys_pll1_266m", "sys_pll1_800m",
   "sys_pll2_200m", 
"sys_pll1_133m", "sys_pll3_out",
   "sys_pll2_250m", 
"audio_pll1_out", };
@@ -159,10 +163,26 @@ static const char *imx8mp_wdog_sels[] = {"clock-osc-24m", 
"sys_pll1_133m", "sys_
 "vpu_pll_out", "sys_pll2_125m", 
"sys_pll3_out",
 "sys_pll1_80m", "sys_pll2_166m" };
 
+static const char *imx8mp_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll2_333m",
+"sys_pll2_500m", "audio_pll2_out", 
"sys_pll1_266m",
+"sys_pll3_out", "sys_pll1_100m", };
+
 static const char *imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll1_800m",
   "sys_pll2_500m", "sys_pll3_out", 
"sys_pll1_266m",
   "audio_pll2_out", "sys_pll1_100m", };
 
+static const char *imx8mp_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", 
"sys_pll2_50m",
+"sys_pll2_100m", "sys_pll1_160m", 
"audio_pll1_out",
+"video_pll1_out", "clk_ext4", };
+
+static const char *imx8mp_enet_timer_sels[] = {"clock-osc-24m", 
"sys_pll2_100m", "audio_pll1_out",
+  "clk_ext1", "clk_ext2", 
"clk_ext3",
+  "clk_ext4", "video_pll1_out", };
+
+static const char *imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", 
"sys_pll2_50m", "sys_pll2_125m",
+"sys_pll2_200m", 
"sys_pll2_500m", "audio_pll1_out",
+"video_pll1_out", 
"audio_pll2_out", };
+
 static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", 
};
 
 
@@ -223,11 +243,34 @@ static int imx8mp_clk_enable(struct clk *clk)
return __imx8mp_clk_enable(clk, 1);
 }
 
+static int imx8mp_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+   struct clk *c, *cp;
+   int ret;
+
+   debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+   ret = clk_get_by_id(clk->id, );
+   if (ret)
+   return ret;
+
+   ret = clk_get_by_id(parent->id, );
+   if (ret)
+   return ret;
+
+   ret = clk_set_parent(c, cp);
+
+   c->dev->parent = cp->dev;
+
+   return ret;
+}
+
 static struct clk_ops imx8mp_clk_ops = {
.set_rate = imx8mp_clk_set_rate,
.get_rate = imx8mp_clk_get_rate,
.enable = imx8mp_clk_enable,
.disable = imx8mp_clk_disable,
+   .set_parent = imx8mp_clk_set_parent,
 };
 
 static int imx8mp_clk_probe(struct udevice *dev)
@@ -289,6 +332,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", 
"arm_a53_cg", base + 0x8000, 0, 3));
 
clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", 
imx8mp_main_axi_sels, base + 0x8800));
+   clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", 
imx8mp_enet_axi_sels, base + 0x8880));
clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, 
imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 
0x8900));
clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", 
imx8mp_noc_sels, base + 0x8d00));
clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", 
imx8mp_noc_io_sels, base + 0x8d80));
@@ -301,6 +345,10 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", 
imx8mp_dram_apb_sels, base + 0xa080));
clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, 
base + 0xa480));
clk_dm(IMX8MP_CLK_I2C6, 

Re: [PATCH] rsa: fix alignment issue when getting public exponent

[Philipp Tomsich]

> On 03.05.2020, at 13:26, Heiko Stuebner  wrote:
> 
> From: Heiko Stuebner 
> 
> To fill the exponent field of the rsa_public_key struct, rsa_mod_exp_sw
> did a cast to uint64_t of the key_prop->public_exponent field.
> But that alignment is not guaranteed in all cases.
> 
> This came to light when in my spl-fit-signature the key-name exceeded
> a certain length and with it the verification then started failing.
> (naming it "integrity" worked fine, "integrity-uboot" failed)
> 
> key_prop.public_exponent itself is actually a void-pointer, fdt_getprop()
> also just returns such a void-pointer and inside the devicetree the 64bit
> exponent is represented as 2 32bit numbers, so assuming a 64bit alignment
> can lead to false reads.
> 
> So just use the already existing rsa_convert_big_endian() to do the actual
> conversion from the dt's big-endian to the needed uint64 value.
> 
> Fixes: fc2f4246b4b3 ("rsa: Split the rsa-verify to separate the modular 
> exponentiation")
> Signed-off-by: Heiko Stuebner 

Reviewed-by: Philipp Tomsich 

Re: [PATCH 2/3] net: tsec: Access eTSEC registers using virtual address

[Vladimir Oltean]

Hi Zhiqiang,

On Sun, 3 May 2020 at 09:28, Zhiqiang Hou  wrote:
>
> From: Hou Zhiqiang 
>
> The current code accesses eTSEC registers using physical
> address directly, it's not correct, though no problem on
> current platforms. It won't work on platforms, which does
> not support 1:1 virtual-physical address map.
>
> Signed-off-by: Hou Zhiqiang 
> ---

Reviewed-by: Vladimir Oltean 
Tested-by: Vladimir Oltean 

(on LS1021A)

>  drivers/net/tsec.c | 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
> index f85cdcb97e..ce41aec5cf 100644
> --- a/drivers/net/tsec.c
> +++ b/drivers/net/tsec.c
> @@ -798,7 +798,7 @@ int tsec_probe(struct udevice *dev)
> int ret;
>
> pdata->iobase = (phys_addr_t)dev_read_addr(dev);
> -   priv->regs = (struct tsec *)pdata->iobase;
> +   priv->regs = dev_remap_addr(dev);
>
> if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
>_args)) {
> @@ -817,8 +817,11 @@ int tsec_probe(struct udevice *dev)
> }
>
> reg = ofnode_get_addr_index(parent, 0);
> -   priv->phyregs_sgmii = (struct tsec_mii_mng *)
> -   (reg + TSEC_MDIO_REGS_OFFSET);
> +   if (reg == FDT_ADDR_T_NONE)
> +   return -ENOENT;
> +
> +   priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
> + MAP_NOCACHE);
>
> ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
>  _args);
> --
> 2.17.1
>

Re: [PATCH 3/3] net: tsec: Access TBI PHY through the corresponding MII

[Vladimir Oltean]

On Sun, 3 May 2020 at 09:28, Zhiqiang Hou  wrote:
>
> From: Hou Zhiqiang 
>
> When an eTSEC is configured to use TBI, configuration of the
> TBI is done through the MIIM registers for that eTSEC.
> For example, if a TBI interface is required on eTSEC2, then
> the MIIM registers starting at offset 0x2_5520 are used to
> configure it.
>
> Fixes: 9a1d6af55ecd ("net: tsec: Add driver model ethernet support")
> Signed-off-by: Hou Zhiqiang 
> ---
>  drivers/net/tsec.c | 17 ++---
>  1 file changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
> index ce41aec5cf..31056f3117 100644
> --- a/drivers/net/tsec.c
> +++ b/drivers/net/tsec.c
> @@ -789,6 +789,7 @@ int tsec_probe(struct udevice *dev)
>  {
> struct eth_pdata *pdata = dev_get_platdata(dev);
> struct tsec_private *priv = dev_get_priv(dev);
> +   struct tsec_mii_mng __iomem *ext_phyregs_mii;
> struct ofnode_phandle_args phandle_args;
> u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
> struct fsl_pq_mdio_info mdio_info;
> @@ -820,8 +821,8 @@ int tsec_probe(struct udevice *dev)
> if (reg == FDT_ADDR_T_NONE)
> return -ENOENT;
>
> -   priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
> - MAP_NOCACHE);
> +   ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
> + MAP_NOCACHE);
>
> ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
>  _args);
> @@ -830,6 +831,16 @@ int tsec_probe(struct udevice *dev)
>
> priv->tbiaddr = tbiaddr;
>
> +   parent = ofnode_get_parent(phandle_args.node);
> +   if (!ofnode_valid(parent)) {
> +   printf("No parent node for TBI PHY?\n");
> +   return -ENOENT;
> +   }
> +
> +   reg = ofnode_get_addr_index(parent, 0);

Missing a check

if (reg == FDT_ADDR_T_NONE)
return -ENOENT;

here?

> +   priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
> + MAP_NOCACHE);
> +
> phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
> if (phy_mode)
> pdata->phy_interface = phy_get_interface_by_name(phy_mode);
> @@ -844,7 +855,7 @@ int tsec_probe(struct udevice *dev)
> if (priv->interface == PHY_INTERFACE_MODE_SGMII)
> priv->flags |= TSEC_SGMII;
>
> -   mdio_info.regs = priv->phyregs_sgmii;
> +   mdio_info.regs = ext_phyregs_mii;
> mdio_info.name = (char *)dev->name;
> ret = fsl_pq_mdio_init(NULL, _info);
> if (ret)
> --
> 2.17.1
>

With that:

Reviewed-by: Vladimir Oltean 
Tested-by: Vladimir Oltean 

(on LS1021A)

Thanks!
-Vladimir

Re: libfdt issue - key verification fails with longer key-name

[Heiko Stuebner]

Hi Simon,

Am Dienstag, 28. April 2020, 00:25:06 CEST schrieb Simon Glass:
> On Sun, 26 Apr 2020 at 17:55, Heiko Stuebner
>  wrote:
> > I've encountered a strange issue that happens depending on the
> > length of the used key-name. Naming it "integrity" works,
> > "integrity-uboot" or even "integrity-ub" does not.
> > With the resulting key-node of course then being "key-integrity-uboot".
> >
> >
> > On the upper levels everything looks great, it finds the signatures and
> > correct key-node,  but when the spl reaches the
> > rsa_verify_with_keynode() function it falls apart and libfdt seems to read
> > strange values from the fdt.
> >
> > Single values seem to be read back correctly, as can be seen with
> > rsa,n0-inverse and rsa,num-bits values that are correct with both
> > key-names (for the same base key).
> >
> > But it's different with the public exponent rsa,exponent:
> > Where it reads back in the correct case as 0x  0001 0001
> > with the longer keyname the result is i.e. 0x44b2 0100  
> > (or similar, depending on the length of the keyname it seems).
> > The 0x0100 part stays the same always, but the 0x44b2 can also be
> > a 0xecb1
> >
> >
> > Is this some alignment issue somewhere, or do you have a hint
> > what I should poke?
> 
> Not really, but can you repeat it with sandbox? It sounds like it
> could be a bug?

it really seems to be an alignment-bug ... the rsa-mod-exp code
assumes an u64-alignment when that is not guaranteed.

See the patch titled
"rsa: fix alignment issue when getting public exponent"
I sent just now.

Heiko