[U-Boot] [PATCH] powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so
that it knows
which PCI device tree node to look for. The calls to these macros are using a
hard-coded string,
but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the
same string, so we
should use that.
Signed-off-by: Timur Tabi ti...@freescale.com
---
We don't update p3060_ids.c because support for that SOC is going away.
arch/powerpc/cpu/mpc85xx/p2041_ids.c |6 +++---
arch/powerpc/cpu/mpc85xx/p3041_ids.c |8
arch/powerpc/cpu/mpc85xx/p4080_ids.c |6 +++---
arch/powerpc/cpu/mpc85xx/p5020_ids.c |8
4 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c
b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
index b99b54d..91d9cac 100644
--- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
@@ -62,9 +62,9 @@ struct liodn_id_table liodn_tbl[] = {
SET_SATA_LIODN(1, 127),
SET_SATA_LIODN(2, 128),
- SET_PCI_LIODN(fsl,qoriq-pcie-v2.2, 1, 193),
- SET_PCI_LIODN(fsl,qoriq-pcie-v2.2, 2, 194),
- SET_PCI_LIODN(fsl,qoriq-pcie-v2.2, 3, 195),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c
b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
index c50b442..e46a714 100644
--- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
@@ -62,10 +62,10 @@ struct liodn_id_table liodn_tbl[] = {
SET_SATA_LIODN(1, 127),
SET_SATA_LIODN(2, 128),
- SET_PCI_LIODN(fsl,qoriq-pcie-v2.2, 1, 193),
- SET_PCI_LIODN(fsl,qoriq-pcie-v2.2, 2, 194),
- SET_PCI_LIODN(fsl,qoriq-pcie-v2.2, 3, 195),
- SET_PCI_LIODN(fsl,qoriq-pcie-v2.2, 4, 196),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196),
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c
b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
index a6ea6af..5c287fb 100644
--- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
@@ -52,9 +52,9 @@ struct liodn_id_table liodn_tbl[] = {
SET_SDHC_LIODN(1, 156),
- SET_PCI_LIODN(fsl,p4080-pcie, 1, 193),
- SET_PCI_LIODN(fsl,p4080-pcie, 2, 194),
- SET_PCI_LIODN(fsl,p4080-pcie, 3, 195),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_DMA_LIODN(1, 196),
SET_DMA_LIODN(2, 197),
diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c
b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
index ff57a19..e8c26bf 100644
--- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
@@ -62,10 +62,10 @@ struct liodn_id_table liodn_tbl[] = {
SET_SATA_LIODN(1, 127),
SET_SATA_LIODN(2, 128),
- SET_PCI_LIODN(fsl,qoriq-pcie-v2.2, 1, 193),
- SET_PCI_LIODN(fsl,qoriq-pcie-v2.2, 2, 194),
- SET_PCI_LIODN(fsl,qoriq-pcie-v2.2, 3, 195),
- SET_PCI_LIODN(fsl,qoriq-pcie-v2.2, 4, 196),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196),
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
--
1.7.3.4
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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location
Wolfgang Denk wrote: In case you have an EEPROM with correct layout (CRC at 0xFC) but incorrect CRC, you will access random data and interpret this as CRC. This is provoking undefined behaviour. True, but it doesn't matter. The EEPROM is not that important, and the odds of screwing this up is one in four billion. If you want, then rather provide an update tool that theuser can use (manually!) to update, but this should be done once, and with explicit confirmation from the user, never automagically. Considering how unimportant the EEPROM really is, I don't see the point in making it so complicated. We already automagically upgrade the board from NXID v0 to NXID v1. Now we automagically fix boards that have the CRC in the wrong place. Anyway, I don't see why it's so controversial. This code is only used on a small number of Freescale reference boards. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location
Wolfgang Denk wrote: Well, if it's really so unimportant and used in only a small number of boards, then just omit this broken code that provokes the undefined behaviour. As I said before, we need to support situations where people upgrade their U-Boot. When the EEPROM is read, the CRC is checked in both locations. If it's valid in either, then we assume the data is valid and continue. When the user wants to write back the EEPROM (via the mac save command), the CRC is written only at the proper location (0xFC). This fixes the EEPROM, and the code will never read the CRC from the wrong location (0xCC). -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location
Scott Wood wrote: Timur, I know you said you don't control the format, but could you ask for a version number bump so that going forward there's a way to unambiguously mark the contents as good (the spec wouldn't change, but there would be no known implementations of v2 with this bug)? I'm not sure what you mean. The specification for v1 has always said that the CRC is at address 0xFC. I just wrote the code wrong. I was always under the impression that I was writing the CRC at 0xFC, until York pointed that out to me last year. As far as the specification is concerned, nothing has changed. If not, and Wolfgang still refuses to accept this, what about checking the old location on a CRC fail, and if the old CRC passes, don't automatically use it but print a message telling the user that they probably need to run the migration command? I honestly don't see what's wrong with checking the CRC in the old location, and using it if it's valid. Like I said, we already automagically update EEPROMs from version 0 to version 1. The existing code already checks a version number to determine where the CRC is: /* * If we've read an NXID v0 EEPROM, then we need to set the CRC offset * to where it is in v0. */ if (e.version == 0) crc_offset = 0x72; So here we're reading the 'version' field before we validate the data, because we need to check the version to know where the CRC is. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location
Scott Wood wrote:
I know the spec wouldn't change, except the version number. But as I
said above, there would be no known v2 implementations with the bug.
You would only check the bad CRC location if you see v1 data, because
there are known buggy v1 implementations.
I already have that:
if ((e.version == NXID_VERSION) (crc != be32_to_cpup(crcp))) {
NXID_VERSION is equal to 1, so we only do the check for the old CRC if we
have a v1 EEPROM.
--
Timur Tabi
Linux kernel developer at Freescale
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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location
Scott Wood wrote: But you continue to generate v1 EEPROMs. If we get the people who define the format to accept v2, then we can generate v2 after the fix is applied, and the (very small) risk of a real CRC failure combined with a spurious CRC success in the old location would only apply on EEPROMs which haven't been saved since the update. Again, I'm confused. Why would we bump the version to v2? What is different in V2 compared to V1? It's highly unlikely that there will ever be a V2. The only reason we went from V0 to V1 is to allow for more than 8 MAC addresses. Now the entire EEPROM is filled with MAC addresses, and so we've reached the hard limit of 31. We would need to switch to a new EEPROM device in order to handle more, and none of the other information in the EEPROM is used by U-Boot. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location
The NXID v1 EEPROM format has the CRC at offset 0xFC, but for some reason it
was placed at address 0xCC instead. To retain compatibility with existing
boards, we check the CRC in the old location if necessary.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/common/sys_eeprom.c | 28 ++--
1 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/board/freescale/common/sys_eeprom.c
b/board/freescale/common/sys_eeprom.c
index d2ed036..2541dd2 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -34,8 +34,16 @@
#endif
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
-#define MAX_NUM_PORTS 23
+#define MAX_NUM_PORTS 31
#define NXID_VERSION 1
+
+/*
+ * Older versions of this code incorrectly placed the CRC at offset 0xCC,
+ * when it should have been at 0xFC. To maintain compatibility with boards
+ * that have the CRC at 0xCC, we check for the CRC at 0xCC if it's not in
+ * 0xFC.
+ */
+#define BROKEN_CRC_OFFSET 0xCC
#endif
/**
@@ -71,7 +79,7 @@ static struct __attribute__ ((__packed__)) eeprom {
u8 mac_count; /* 0x40Number of MAC addresses */
u8 mac_flag; /* 0x41MAC table flags */
u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
- u32 crc; /* x+1 CRC32 checksum */
+ u32 crc; /* 0xFCCRC32 checksum */
#endif
} e;
@@ -457,6 +465,22 @@ int mac_read_from_eeprom(void)
crc = crc32(0, (void *)e, crc_offset);
crcp = (void *)e + crc_offset;
+#ifdef BROKEN_CRC_OFFSET
+ /*
+* If the CRC is wrong, then check the old location. If it contains a
+* valid CRC, then assume that this is an older EEPROM. We update the
+* real CRC so that the EEPROM looks valid.
+*/
+ if ((e.version == NXID_VERSION) (crc != be32_to_cpup(crcp))) {
+ u32 crc2 = crc32(0, (void *)e, BROKEN_CRC_OFFSET);
+ void *crcp2 = (void *)e + BROKEN_CRC_OFFSET;
+
+ if (crc2 == be32_to_cpup(crcp2)) {
+ debug(Broken NXID v1 CRC found and corrected\n);
+ update_crc();
+ }
+ }
+#endif
if (crc != be32_to_cpu(*crcp)) {
printf(CRC mismatch (%08x != %08x)\n, crc,
be32_to_cpu(e.crc));
return -1;
--
1.7.3.4
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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location
Scott Wood wrote: That patch itself is OK. But the comment is incorrect. We keep adding more mac addresses to this data structure. The CRC was at the end. The offset 0xCC was correct. Is there anything in the data structure to indicate that this growth has happened? The version number indicates whether it's 8 addresses (v0) or more than 8 (v1). The problem is that I think I just made a math error when I calculated the number of MAC addresses that would fit in the EEPROM. I was supposed to do (0xFC - 0x72) / 6 == 31, but instead I ended up with 23, and never validated it. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location
Scott Wood wrote: If the 0xCC version is already in real use, then this change should bump the version number. I can't, because I don't control the spec. Like I said, it was just wrong before. No one has more than 23 MAC addresses anyway. My patch provides transparent updates to handle it. It will read broken EEPROMs and verify the CRC in the old location, and if you have re-save the EEPROM, it will put the CRC in the right place. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] [v3] net: abort network initialization if the PHY driver fails
Joe Hershberger wrote:
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index eee41d7..5700552 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -510,7 +510,13 @@ static int fec_open(struct eth_device *edev)
fec_eth_phy_config(edev);
if (fec-phydev) {
/* Start up the PHY */
- phy_startup(fec-phydev);
+ int ret = phy_startup(fec-phydev);
+
Why a blank line here when it isn't in the rest of the implementations?
The coding standard requires blank lines after variable declarations.
+ if (ret) {
+ printf(Could not initialize PHY %s\n,
+ fec-phydev-dev-name);
+ return ret;
+ }
speed = fec-phydev-speed;
} else {
speed = _100BASET;
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index f34f4db..2b616ad 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -363,6 +363,9 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
{
struct fm_eth *fm_eth;
struct fsl_enet_mac *mac;
+#ifdef CONFIG_PHYLIB
+ int ret;
+#endif
fm_eth = (struct fm_eth *)dev-priv;
mac = fm_eth-mac;
@@ -384,7 +387,11 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
fmc_tx_port_graceful_stop_disable(fm_eth);
#ifdef CONFIG_PHYLIB
- phy_startup(fm_eth-phydev);
+ ret = phy_startup(fm_eth-phydev);
+ if (ret) {
+ printf(%s: Could not initialize\n,
fm_eth-phydev-dev-name);
Why is this string different from the others? Consistency?
Yes. I tried to keep the messages consistent with the other messages in
the function.
+ return ret;
+ }
#else
fm_eth-phydev-speed = SPEED_1000;
fm_eth-phydev-link = 1;
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index bb57e4d..268d884 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -415,7 +415,11 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t
*bd)
goto err_phy_cfg;
}
phy = port_info-phydev;
- phy_startup(phy);
+ ret = phy_startup(phy);
+ if (ret) {
+ printf(SHETHER_NAME : phy startup failure\n);
Why is this string different from the others? Consistency?
Yes, it looks like the other messages in sh_eth_config().
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 7854a04..d777144 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -272,7 +272,11 @@ static int setup_phy(struct eth_device *dev)
phydev-advertising = phydev-supported;
priv-phydev = phydev;
phy_config(phydev);
- phy_startup(phydev);
+ if (phy_startup(phydev)) {
+ printf(axiemac: could not initialize PHY %s\n,
Lower-case could in string? Consistency?
Yes, consistency. :-)
+ phydev-dev-name);
+ return 0;
Why are you returning 0 here and not the return value from phy_startup()?
I answered that in another email. This is what setup_phy() is supposed to
return on failure.
--
Timur Tabi
Linux kernel developer at Freescale
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Re: [U-Boot] [PATCH 2/2] [v3] net: abort network initialization if the PHY driver fails
Joe Hershberger wrote:
@@ -384,7 +387,11 @@ static int fm_eth_open(struct eth_device *dev, bd_t
*bd)
fmc_tx_port_graceful_stop_disable(fm_eth);
#ifdef CONFIG_PHYLIB
- phy_startup(fm_eth-phydev);
+ ret = phy_startup(fm_eth-phydev);
+ if (ret) {
+ printf(%s: Could not initialize\n,
fm_eth-phydev-dev-name);
Why is this string different from the others? Consistency?
Yes. I tried to keep the messages consistent with the other messages in
the function.
Should you not at least keep the core message the same? Could not
initialize PHY
Well, I suppose I could add the word PHY here.
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index bb57e4d..268d884 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -415,7 +415,11 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t
*bd)
goto err_phy_cfg;
}
phy = port_info-phydev;
- phy_startup(phy);
+ ret = phy_startup(phy);
+ if (ret) {
+ printf(SHETHER_NAME : phy startup failure\n);
Why is this string different from the others? Consistency?
Yes, it looks like the other messages in sh_eth_config().
Same here, at least the core message Could not initialize PHY
I am saying that, just in a different way. phy startup failure means
the same as Could not initialize PHY, but the wording matches the rest
of the function.
--
Timur Tabi
Linux kernel developer at Freescale
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[U-Boot] [PATCH 2/2] [v3] net: abort network initialization if the PHY driver fails
Now that phy_startup() can return an actual error code, check for that error
code and abort network initialization if the PHY fails.
Signed-off-by: Timur Tabi ti...@freescale.com
Acked-by: Nobuhiro Iwamamatsu nobuhiro.iwamatsu...@renesas.com (sh_eth part)
Acked-by: Stephan Linz l...@li-pro.net (Xilinx part, xilinx_axi_emac and
xilinx_ll_temac)
Reviewed-by: Marek Vasut ma...@denx.de (FEC part)
---
drivers/net/fec_mxc.c |8 +++-
drivers/net/fm/eth.c |9 -
drivers/net/sh_eth.c |6 +-
drivers/net/tsec.c|8 +++-
drivers/net/xilinx_axi_emac.c |6 +-
drivers/net/xilinx_ll_temac.c |8 +++-
6 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index eee41d7..5700552 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -510,7 +510,13 @@ static int fec_open(struct eth_device *edev)
fec_eth_phy_config(edev);
if (fec-phydev) {
/* Start up the PHY */
- phy_startup(fec-phydev);
+ int ret = phy_startup(fec-phydev);
+
+ if (ret) {
+ printf(Could not initialize PHY %s\n,
+ fec-phydev-dev-name);
+ return ret;
+ }
speed = fec-phydev-speed;
} else {
speed = _100BASET;
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index f34f4db..2b616ad 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -363,6 +363,9 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
{
struct fm_eth *fm_eth;
struct fsl_enet_mac *mac;
+#ifdef CONFIG_PHYLIB
+ int ret;
+#endif
fm_eth = (struct fm_eth *)dev-priv;
mac = fm_eth-mac;
@@ -384,7 +387,11 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
fmc_tx_port_graceful_stop_disable(fm_eth);
#ifdef CONFIG_PHYLIB
- phy_startup(fm_eth-phydev);
+ ret = phy_startup(fm_eth-phydev);
+ if (ret) {
+ printf(%s: Could not initialize\n, fm_eth-phydev-dev-name);
+ return ret;
+ }
#else
fm_eth-phydev-speed = SPEED_1000;
fm_eth-phydev-link = 1;
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index bb57e4d..268d884 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -415,7 +415,11 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
goto err_phy_cfg;
}
phy = port_info-phydev;
- phy_startup(phy);
+ ret = phy_startup(phy);
+ if (ret) {
+ printf(SHETHER_NAME : phy startup failure\n);
+ return ret;
+ }
val = 0;
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 3c1c8f0..f5e314b 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -480,6 +480,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
int i;
struct tsec_private *priv = (struct tsec_private *)dev-priv;
tsec_t *regs = priv-regs;
+ int ret;
/* Make sure the controller is stopped */
tsec_halt(dev);
@@ -511,7 +512,12 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
startup_tsec(dev);
/* Start up the PHY */
- phy_startup(priv-phydev);
+ ret = phy_startup(priv-phydev);
+ if (ret) {
+ printf(Could not initialize PHY %s\n,
+ priv-phydev-dev-name);
+ return ret;
+ }
adjust_link(priv, priv-phydev);
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 7854a04..d777144 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -272,7 +272,11 @@ static int setup_phy(struct eth_device *dev)
phydev-advertising = phydev-supported;
priv-phydev = phydev;
phy_config(phydev);
- phy_startup(phydev);
+ if (phy_startup(phydev)) {
+ printf(axiemac: could not initialize PHY %s\n,
+ phydev-dev-name);
+ return 0;
+ }
switch (phydev-speed) {
case 1000:
diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c
index 27dafc1..b67153b 100644
--- a/drivers/net/xilinx_ll_temac.c
+++ b/drivers/net/xilinx_ll_temac.c
@@ -232,6 +232,7 @@ static void ll_temac_halt(struct eth_device *dev)
static int ll_temac_init(struct eth_device *dev, bd_t *bis)
{
struct ll_temac *ll_temac = dev-priv;
+ int ret;
printf(%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n,
dev-name, dev-index, dev-iobase);
@@ -240,7 +241,12 @@ static int ll_temac_init(struct eth_device *dev, bd_t *bis)
return -1;
/* Start up the PHY */
- phy_startup(ll_temac-phydev);
+ ret = phy_startup(ll_temac-phydev);
+ if (ret) {
+ printf(%s: Could
[U-Boot] [PATCH] powerpc/85xx: improve definition of BR_PHYS_ADDR macro
The BR_PHYS_ADDR(x) macro was missing parentheses around x in the macro definition, so callers had to supply their own parenthesis. Signed-off-by: Timur Tabi ti...@freescale.com --- arch/powerpc/include/asm/fsl_lbc.h |6 +++--- include/configs/MPC8536DS.h|9 - include/configs/MPC8548CDS.h |3 +-- include/configs/MPC8572DS.h|9 - include/configs/P1022DS.h |2 +- include/configs/P2020DS.h |9 + include/configs/corenet_ds.h |2 +- include/configs/p1_p2_rdb_pc.h |4 ++-- 8 files changed, 21 insertions(+), 23 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 2a23d84..d1def75 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -82,10 +82,10 @@ void lbc_sdram_init(void); /* Convert an address into the right format for the BR registers */ #if defined(CONFIG_PHYS_64BIT) !defined(CONFIG_FSL_ELBC) -#define BR_PHYS_ADDR(x)((unsigned long)((x 0x08000ULL) | \ -((x 0x3ULL) 19))) +#define BR_PHYS_ADDR(x)\ + ((u32)(((x) 0x08000ULL) | (((x) 0x3ULL) 19))) #else -#define BR_PHYS_ADDR(x) (x 0x8000) +#define BR_PHYS_ADDR(x) ((u32)(x) 0x8000) #endif /* OR - Option Registers diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index c26cb63..4a6b64f 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -217,8 +217,7 @@ #endif #define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800)) \ -| BR_PS_16 | BR_V) + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800) | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 #define CONFIG_SYS_BR1_PRELIM \ @@ -380,14 +379,14 @@ #endif #define CONFIG_SYS_BR4_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x4)) \ + (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x4) \ | (2BR_DECC_SHIFT)/* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR5_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x8)) \ + (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x8) \ | (2BR_DECC_SHIFT)/* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ @@ -395,7 +394,7 @@ #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR6_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc)) \ + (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc) \ | (2BR_DECC_SHIFT)/* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 1a6ba69..82bbb3e 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -189,8 +189,7 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_SYS_BR0_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x80)) \ - | BR_PS_16 | BR_V) + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x80) | BR_PS_16 | BR_V) #define CONFIG_SYS_BR1_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index d7910e1..eeb9a8d 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -205,8 +205,7 @@ #define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800)) \ - | BR_PS_16 | BR_V) + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800) | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) @@ -376,20 +375,20 @@ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #endif -#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x4))\ +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x4) \ | (2BR_DECC_SHIFT)/* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR4_PRELIM
[U-Boot] [PATCH 2/2] [v2] net: abort network initialization if the PHY driver fails
Now that phy_startup() can return an actual error code, check for that error
code and abort network initialization if the PHY fails.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/fec_mxc.c |7 ++-
drivers/net/fm/eth.c |9 -
drivers/net/sh_eth.c |6 +-
drivers/net/tsec.c|8 +++-
drivers/net/xilinx_axi_emac.c |6 +-
drivers/net/xilinx_ll_temac.c |8 +++-
6 files changed, 38 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index eee41d7..e62ae61 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -510,7 +510,12 @@ static int fec_open(struct eth_device *edev)
fec_eth_phy_config(edev);
if (fec-phydev) {
/* Start up the PHY */
- phy_startup(fec-phydev);
+ int ret = phy_startup(fec-phydev);
+ if (ret) {
+ printf(Could not initialize PHY %s\n,
+ fec-phydev-dev-name);
+ return ret;
+ }
speed = fec-phydev-speed;
} else {
speed = _100BASET;
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index f34f4db..2b616ad 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -363,6 +363,9 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
{
struct fm_eth *fm_eth;
struct fsl_enet_mac *mac;
+#ifdef CONFIG_PHYLIB
+ int ret;
+#endif
fm_eth = (struct fm_eth *)dev-priv;
mac = fm_eth-mac;
@@ -384,7 +387,11 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
fmc_tx_port_graceful_stop_disable(fm_eth);
#ifdef CONFIG_PHYLIB
- phy_startup(fm_eth-phydev);
+ ret = phy_startup(fm_eth-phydev);
+ if (ret) {
+ printf(%s: Could not initialize\n, fm_eth-phydev-dev-name);
+ return ret;
+ }
#else
fm_eth-phydev-speed = SPEED_1000;
fm_eth-phydev-link = 1;
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index bb57e4d..268d884 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -415,7 +415,11 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
goto err_phy_cfg;
}
phy = port_info-phydev;
- phy_startup(phy);
+ ret = phy_startup(phy);
+ if (ret) {
+ printf(SHETHER_NAME : phy startup failure\n);
+ return ret;
+ }
val = 0;
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 3c1c8f0..f5e314b 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -480,6 +480,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
int i;
struct tsec_private *priv = (struct tsec_private *)dev-priv;
tsec_t *regs = priv-regs;
+ int ret;
/* Make sure the controller is stopped */
tsec_halt(dev);
@@ -511,7 +512,12 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
startup_tsec(dev);
/* Start up the PHY */
- phy_startup(priv-phydev);
+ ret = phy_startup(priv-phydev);
+ if (ret) {
+ printf(Could not initialize PHY %s\n,
+ priv-phydev-dev-name);
+ return ret;
+ }
adjust_link(priv, priv-phydev);
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 7854a04..d777144 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -272,7 +272,11 @@ static int setup_phy(struct eth_device *dev)
phydev-advertising = phydev-supported;
priv-phydev = phydev;
phy_config(phydev);
- phy_startup(phydev);
+ if (phy_startup(phydev)) {
+ printf(axiemac: could not initialize PHY %s\n,
+ phydev-dev-name);
+ return 0;
+ }
switch (phydev-speed) {
case 1000:
diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c
index 27dafc1..b67153b 100644
--- a/drivers/net/xilinx_ll_temac.c
+++ b/drivers/net/xilinx_ll_temac.c
@@ -232,6 +232,7 @@ static void ll_temac_halt(struct eth_device *dev)
static int ll_temac_init(struct eth_device *dev, bd_t *bis)
{
struct ll_temac *ll_temac = dev-priv;
+ int ret;
printf(%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n,
dev-name, dev-index, dev-iobase);
@@ -240,7 +241,12 @@ static int ll_temac_init(struct eth_device *dev, bd_t *bis)
return -1;
/* Start up the PHY */
- phy_startup(ll_temac-phydev);
+ ret = phy_startup(ll_temac-phydev);
+ if (ret) {
+ printf(%s: Could not initialize PHY %s\n,
+ dev-name, ll_temac-phydev-dev-name);
+ return ret;
+ }
if (!ll_temac_adjust_link(dev)) {
ll_temac_halt(dev);
--
1.7.3.4
Re: [U-Boot] [PATCH 2/2] [v2] net: abort network initialization if the PHY driver fails
Wolfgang Denk wrote: Blank line after variable declarations, please. Oops. I'll wait to see if there are any other comments before I respin. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] phylib: phy_startup() should return an error code on failure
phy_startup() calls the PHY driver's startup function, but it ignores the
return code from that function, and so it never returns any failures.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/phy/phy.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 7d327f7..baef60f 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -723,10 +723,13 @@ struct phy_device *phy_connect(struct mii_dev *bus, int
addr,
return phydev;
}
+/*
+ * Start the PHY. Returns 0 on success, or a negative error code.
+ */
int phy_startup(struct phy_device *phydev)
{
if (phydev-drv-startup)
- phydev-drv-startup(phydev);
+ return phydev-drv-startup(phydev);
return 0;
}
--
1.7.3.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] net: abort network initialization if the PHY driver fails
Now that phy_startup() can return an actual error code, check for that error
code and abort network initialization if the PHY fails.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/fec_mxc.c |7 ++-
drivers/net/fm/eth.c |9 -
drivers/net/sh_eth.c |6 +-
drivers/net/tsec.c|8 +++-
drivers/net/xilinx_axi_emac.c |6 +-
drivers/net/xilinx_ll_temac.c |8 +++-
6 files changed, 38 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index eee41d7..7a3d16b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -510,7 +510,12 @@ static int fec_open(struct eth_device *edev)
fec_eth_phy_config(edev);
if (fec-phydev) {
/* Start up the PHY */
- phy_startup(fec-phydev);
+ int ret = phy_startup(fec-phydev);
+ if (ret) {
+ printf(Could not initialize PHY %s\n,
+ fm_eth-phydev-dev-name);
+ return ret;
+ }
speed = fec-phydev-speed;
} else {
speed = _100BASET;
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index f34f4db..2b616ad 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -363,6 +363,9 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
{
struct fm_eth *fm_eth;
struct fsl_enet_mac *mac;
+#ifdef CONFIG_PHYLIB
+ int ret;
+#endif
fm_eth = (struct fm_eth *)dev-priv;
mac = fm_eth-mac;
@@ -384,7 +387,11 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
fmc_tx_port_graceful_stop_disable(fm_eth);
#ifdef CONFIG_PHYLIB
- phy_startup(fm_eth-phydev);
+ ret = phy_startup(fm_eth-phydev);
+ if (ret) {
+ printf(%s: Could not initialize\n, fm_eth-phydev-dev-name);
+ return ret;
+ }
#else
fm_eth-phydev-speed = SPEED_1000;
fm_eth-phydev-link = 1;
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index bb57e4d..268d884 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -415,7 +415,11 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
goto err_phy_cfg;
}
phy = port_info-phydev;
- phy_startup(phy);
+ ret = phy_startup(phy);
+ if (ret) {
+ printf(SHETHER_NAME : phy startup failure\n);
+ return ret;
+ }
val = 0;
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 3c1c8f0..f5e314b 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -480,6 +480,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
int i;
struct tsec_private *priv = (struct tsec_private *)dev-priv;
tsec_t *regs = priv-regs;
+ int ret;
/* Make sure the controller is stopped */
tsec_halt(dev);
@@ -511,7 +512,12 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
startup_tsec(dev);
/* Start up the PHY */
- phy_startup(priv-phydev);
+ ret = phy_startup(priv-phydev);
+ if (ret) {
+ printf(Could not initialize PHY %s\n,
+ priv-phydev-dev-name);
+ return ret;
+ }
adjust_link(priv, priv-phydev);
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 7854a04..d777144 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -272,7 +272,11 @@ static int setup_phy(struct eth_device *dev)
phydev-advertising = phydev-supported;
priv-phydev = phydev;
phy_config(phydev);
- phy_startup(phydev);
+ if (phy_startup(phydev)) {
+ printf(axiemac: could not initialize PHY %s\n,
+ phydev-dev-name);
+ return 0;
+ }
switch (phydev-speed) {
case 1000:
diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c
index 27dafc1..b67153b 100644
--- a/drivers/net/xilinx_ll_temac.c
+++ b/drivers/net/xilinx_ll_temac.c
@@ -232,6 +232,7 @@ static void ll_temac_halt(struct eth_device *dev)
static int ll_temac_init(struct eth_device *dev, bd_t *bis)
{
struct ll_temac *ll_temac = dev-priv;
+ int ret;
printf(%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n,
dev-name, dev-index, dev-iobase);
@@ -240,7 +241,12 @@ static int ll_temac_init(struct eth_device *dev, bd_t *bis)
return -1;
/* Start up the PHY */
- phy_startup(ll_temac-phydev);
+ ret = phy_startup(ll_temac-phydev);
+ if (ret) {
+ printf(%s: Could not initialize PHY %s\n,
+ dev-name, ll_temac-phydev-dev-name);
+ return ret;
+ }
if (!ll_temac_adjust_link(dev)) {
ll_temac_halt(dev);
--
1.7.3.4
[U-Boot] [PATCH] powerpc/mpc83xx: fix copyright string in serdes.c
The misspelling of semiconductor causes some internal copyright analysis tools to complain. Signed-off-by: Timur Tabi ti...@freescale.com --- arch/powerpc/cpu/mpc83xx/serdes.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c index a88fab9..2d5ee03 100644 --- a/arch/powerpc/cpu/mpc83xx/serdes.c +++ b/arch/powerpc/cpu/mpc83xx/serdes.c @@ -1,7 +1,7 @@ /* * Freescale SerDes initialization routine * - * Copyright (C) 2007,2011 Freescale Semicondutor, Inc. + * Copyright 2007,2011 Freescale Semiconductor, Inc. * Copyright (C) 2008 MontaVista Software, Inc. * * Author: Li Yang le...@freescale.com -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/6] cmd_nvedit.c: allow board-specific code before/after saving the environment
Wolfgang Denk wrote: This is already streching the code to the limits, and the only reason you ever got this thrugh is that it's FSL specific code, you you have to deal yourself with this ugliness. I don;t think you will find good arguments to convince me adding such stuff into common code, though. Well, I guess we'll just have to agree to disagree. I didn't think Mike's idea was a bad one, but if you don't like it, then I'll drop it. Unfortunately, it only covers NOR flash. The new design covers NOR and NAND. Well, your code does not really cover NOR flash. I think it covers only a small subset of the use cases, but horribly fails else. For example, what happens when I just use md or itest *addr or similar trying to read NOR flash while the display is on? The reason I make a big deal about saveenv is because I use an environment variable (video-mode) to enable video support. Once the console is switched to the video display, the only way to switch it back to the serial port is to delete the environment variable, save the environment, and reboot. If we had a command that switched the console back to the serial port, I wouldn't need any of this. You _do_ have a broken hardware design, and if you cannot access NOR flash with display running, and vice versa, than just accept this fact. Feel free to provide commands to switch mode, but don't lard the code with hooks here and there trying to fix what cannot be fixed. Is there a way to switch the console Well, you try again to fix just a single use-case, leaving all the others unsolved. It makes zero sense to fix saveenv while not fixing all other access modes to the same storage device. Yes, it is a pain if you have to run something like = busmux flash;saveenv;busmux diu Hmmm... that's not a bad idea. I'll think about it. but the ugliness comes from the hardware design, so we have no reasoin to camouflage it. Let people see what is going on under the hood - if this is done in a clean way, you don't have to be ashamed. LOL. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/6] cmd_nvedit.c: allow board-specific code before/after saving the environment
Scott Wood wrote: There's no NAND support at all. Of course there's NAND support. I was asking what, besides the mux, makes that existing support not work on this board. No, there is no NAND support for the P1022DS upstream. [b04825@efes u-boot.0]$ grep -i nand include/configs/P1022DS.h [b04825@efes u-boot.0]$ However, I just tried the two SDK patches that add it, and they apply cleanly, so that's an easy fix. Which patches are those? powerpc/85xx: add SPI and SD builds for P1022DS powerpc/p1022ds: Add support for NAND and NAND boot -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] powerpc/p1022ds: add support for SPI and SD boot
From: Matthew McClintock m...@freescale.com
Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.
Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to
00b for them.
Configure the PX_BRDCFG0[0~1] to 10b which is connected to
SPI devices as SPI_CS(0:3)_B.
Signed-off-by: Matthew McClintock m...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Jiang Yutang b14...@freescale.com
---
board/freescale/p1022ds/p1022ds.c |4 +++
board/freescale/p1022ds/tlb.c | 14 ++
boards.cfg|4 +++
include/configs/P1022DS.h | 51 ++--
4 files changed, 70 insertions(+), 3 deletions(-)
diff --git a/board/freescale/p1022ds/p1022ds.c
b/board/freescale/p1022ds/p1022ds.c
index aca30f3..37531b4 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -39,6 +39,10 @@ int board_early_init_f(void)
/* Set pmuxcr to allow both i2c1 and i2c2 */
setbits_be32(gur-pmuxcr, 0x1000);
+#ifdef CONFIG_SYS_RAMBOOT
+ setbits_be32(gur-pmuxcr,
+ in_be32(gur-pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+#endif
/* Read back the register to synchronize the write. */
in_be32(gur-pmuxcr);
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
index e620112..71e71f7 100644
--- a/board/freescale/p1022ds/tlb.c
+++ b/board/freescale/p1022ds/tlb.c
@@ -71,6 +71,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_SYS_RAMBOOT
+ /* *I*G - eSDHC/eSPI/NAND boot */
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+
+ /* map the second 1G */
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x4000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_1G, 1),
+#endif
+#
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 7194e08..42e5ae0 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -699,6 +699,10 @@ P1021RDB-PC_NAND powerpc mpc85xx
p1_p2_rdb_pcfreesca
P1021RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc
freescale - p1_p2_rdb_pc:P1021RDB,SDCARD
P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc
freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH
P1022DS powerpc mpc85xx p1022ds
freescale
+P1022DS_SPIFLASH powerpc mpc85xx p1022ds
freescale - P1022DS:SPIFLASH
+P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds
freescale - P1022DS:36BIT,SPIFLASH
+P1022DS_SDCARD powerpc mpc85xx p1022ds
freescale - P1022DS:SDCARD
+P1022DS_36BIT_SDCARD powerpc mpc85xx p1022ds
freescale - P1022DS:36BIT,SDCARD
P1022DS_36BITpowerpc mpc85xx p1022ds
freescale - P1022DS:36BIT
P1023RDS powerpc mpc85xx p1023rds
freescale - P1023RDS
P1023RDS_NANDpowerpc mpc85xx p1023rds
freescale - P1023RDS:NAND
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 89e8663..ea1d19f 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -18,6 +18,22 @@
#define CONFIG_PHYS_64BIT
#endif
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE 0x1100
+#define CONFIG_RESET_VECTOR_ADDRESS0x1107fffc
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE 0x1100
+#define CONFIG_RESET_VECTOR_ADDRESS0x1107fffc
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500/* BOOKE e500 family */
@@ -397,11 +413,40 @@
/*
* Environment
*/
+#ifdef CONFIG_SYS_RAMBOOT
+#ifdef CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 1000
+#define CONFIG_ENV_SPI_MODE0
+#define CONFIG_ENV_SIZE0x2000 /* 8KB
[U-Boot] [PATCH 2/2] powerpc/p1022ds: Add support for NAND and NAND boot
From: Matthew McClintock m...@freescale.com
Add defines needed to access NAND, remove second flash bank that is
actually connected to NAND.
Add nand booting support for P1022DS with hardcoded DDR config
Signed-off-by: Matthew McClintock m...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Jiang Yutang b14...@freescale.com
---
board/freescale/p1022ds/law.c|3 +
board/freescale/p1022ds/tlb.c| 25 +++--
boards.cfg |2 +
include/configs/P1022DS.h| 121 +--
nand_spl/board/freescale/p1022ds/Makefile| 137 ++
nand_spl/board/freescale/p1022ds/nand_boot.c | 132 +
6 files changed, 401 insertions(+), 19 deletions(-)
create mode 100644 nand_spl/board/freescale/p1022ds/Makefile
create mode 100644 nand_spl/board/freescale/p1022ds/nand_boot.c
diff --git a/board/freescale/p1022ds/law.c b/board/freescale/p1022ds/law.c
index b23b8f9..476069c 100644
--- a/board/freescale/p1022ds/law.c
+++ b/board/freescale/p1022ds/law.c
@@ -16,6 +16,9 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
index 71e71f7..1301c78 100644
--- a/board/freescale/p1022ds/tlb.c
+++ b/board/freescale/p1022ds/tlb.c
@@ -41,6 +41,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
+#ifdef CONFIG_SYS_NAND_BASE
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_1M, 1),
+#endif
+
+ SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_4K, 1),
+
+#ifndef CONFIG_NAND_SPL
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
@@ -67,24 +79,19 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
-
- SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_4K, 1),
+#endif
#ifdef CONFIG_SYS_RAMBOOT
/* *I*G - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
-
- /* map the second 1G */
+ /* *I*G - eSDHC/eSPI/NAND boot - second 1GB of memory */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x4000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+CONFIG_SYS_DDR_SDRAM_BASE + 0x4000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif
-#
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 42e5ae0..418e5fe 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -699,6 +699,8 @@ P1021RDB-PC_NAND powerpc mpc85xx
p1_p2_rdb_pcfreesca
P1021RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc
freescale - p1_p2_rdb_pc:P1021RDB,SDCARD
P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc
freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH
P1022DS powerpc mpc85xx p1022ds
freescale
+P1022DS_NAND powerpc mpc85xx p1022ds
freescale - P1022DS:NAND
+P1022DS_36BIT_NAND powerpc mpc85xx p1022ds
freescale - P1022DS:36BIT,NAND
P1022DS_SPIFLASH powerpc mpc85xx p1022ds
freescale - P1022DS:SPIFLASH
P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds
freescale - P1022DS:36BIT,SPIFLASH
P1022DS_SDCARD powerpc mpc85xx p1022ds
freescale - P1022DS:SDCARD
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index ea1d19f..de48e55 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -34,6
Re: [U-Boot] [PATCH 5/6] cmd_nvedit.c: allow board-specific code before/after saving the environment
Scott Wood wrote: That's the equivalent of saying Linux doesn't support something because nobody bothered to enable it in a certain defconfig. Well, that's exactly what I meant. When you boot an upstream U-boot on a P1022DS, there is no support for NAND chips. The 'nand' command does not exist. You cannot build a u-boot.bin that will boot from NAND. That pretty much means there is no NAND support. However, I just tried the two SDK patches that add it, and they apply cleanly, so that's an easy fix. Which patches are those? powerpc/85xx: add SPI and SD builds for P1022DS powerpc/p1022ds: Add support for NAND and NAND boot I'm not sure what SPI and SD have to do with it... The 2nd patch applies on top of the first. Most of the latter patch is concerned with NAND boot, which is a different issue from NAND support, but still pretty important if you're going NAND-only. It looks like the patches were actually initially separate, but Kumar oh-so-helpfully squashed them together. It's a good thing we don't do that any more. One thing I would like to see fixed in at upstream version of p1022ds NAND boot support is for it to use SPD like a normal p1022ds boot. This will likely require reviving the three-stage boot discussion (TPL). I just posted those two patches for upstream. I don't want the TPL work to hold up these patches. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] powerpc/p1022ds: Add support for NAND and NAND boot
Scott Wood wrote: NACK, please use SPD. Also please use the new SPL infrastructure. I'm just taking the patches as they are on the SDK and posting them. I have no idea how the new SPL infrastructure works. If you're going to NACK this patch set, then I'm just going to drop them and work on something else. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/6] cmd_nvedit.c: allow board-specific code before/after saving the environment
Scott Wood wrote: It was over a year ago that I made that request internally. And still the answer is I need this now now now!. Who's going to do that work, if not you? NACK any non-SPD NAND boot for a board that otherwise uses SPD, particularly if it has socketed RAM. It's not as if we don't know how to make this work. Well, *I* don't know how to do that. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/p1022ds: fix DIU/LBC switching with NAND enabled
In order for indirect mode on the PIXIS to work properly, both chip selects
need to be set to GPCM mode, otherwise writes to the chip select base
addresses will not actually post to the local bus -- they'll go to the
NAND controller instead. Therefore, we need to set BR0 and BR1 to GPCM
mode before switching to indirect mode.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/p1022ds/diu.c | 82 +
1 files changed, 74 insertions(+), 8 deletions(-)
diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c
index d5428ea..898f4c7 100644
--- a/board/freescale/p1022ds/diu.c
+++ b/board/freescale/p1022ds/diu.c
@@ -63,6 +63,8 @@ static u8 px_brdcfg0;
static u32 pmuxcr;
static void *lbc_lcs0_ba;
static void *lbc_lcs1_ba;
+static u32 old_br0, old_or0, old_br1, old_or1;
+static u32 new_br0, new_or0, new_br1, new_or1;
void diu_set_pixel_clock(unsigned int pixclock)
{
@@ -88,10 +90,63 @@ int platform_diu_init(unsigned int xres, unsigned int yres,
const char *port)
const char *name;
u32 pixel_format;
u8 temp;
+ phys_addr_t phys0, phys1; /* BR0/BR1 physical addresses */
- /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
- lbc_lcs0_ba = (void *)(get_lbc_br(0) get_lbc_or(0) 0x8000);
- lbc_lcs1_ba = (void *)(get_lbc_br(1) get_lbc_or(1) 0x8000);
+ /*
+* Indirect mode requires both BR0 and BR1 to be set to GPCM,
+* otherwise writes to these addresses won't actually appear on the
+* local bus, and so the PIXIS won't see them.
+*
+* In FCM mode, writes go to the NAND controller, which does not pass
+* them to the localbus directly. So we force BR0 and BR1 into GPCM
+* mode, since we don't care about what's behind the localbus any
+* more. However, we save those registers first, so that we can
+* restore them when necessary.
+*/
+ new_br0 = old_br0 = get_lbc_br(0);
+ new_br1 = old_br1 = get_lbc_br(1);
+ new_or0 = old_or0 = get_lbc_or(0);
+ new_or1 = old_or1 = get_lbc_or(1);
+
+ /*
+* Use the existing BRx/ORx values if it's already GPCM. Otherwise,
+* force the values to simple 32KB GPCM windows with the most
+* conservative timing.
+*/
+ if ((old_br0 BR_MSEL) != BR_MS_GPCM) {
+ new_br0 = (get_lbc_br(0) BR_BA) | BR_V;
+ new_or0 = OR_AM_32KB | 0xFF7;
+ set_lbc_br(0, new_br0);
+ set_lbc_or(0, new_or0);
+ }
+ if ((old_br1 BR_MSEL) != BR_MS_GPCM) {
+ new_br1 = (get_lbc_br(1) BR_BA) | BR_V;
+ new_or1 = OR_AM_32KB | 0xFF7;
+ set_lbc_br(1, new_br1);
+ set_lbc_or(1, new_or1);
+ }
+
+ /*
+* Determine the physical addresses for Chip Selects 0 and 1. The
+* BR0/BR1 registers contain the truncated physical addresses for the
+* chip selects, mapped via the localbus LAW. Since the BRx registers
+* only contain the lower 32 bits of the address, we have to determine
+* the upper 4 bits some other way. The proper way is to scan the LAW
+* table looking for a matching localbus address. Instead, we cheat.
+* We know that the upper bits are 0 for 32-bit addressing, or 0xF for
+* 36-bit addressing.
+*/
+#ifdef CONFIG_PHYS_64BIT
+ phys0 = 0xfULL | (old_br0 old_or0 BR_BA);
+ phys1 = 0xfULL | (old_br1 old_or1 BR_BA);
+#else
+ phys0 = old_br0 old_or0 BR_BA;
+ phys1 = old_br1 old_or1 BR_BA;
+#endif
+
+/* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
+ lbc_lcs0_ba = map_physmem(phys0, 1, 0);
+ lbc_lcs1_ba = map_physmem(phys1, 1, 0);
pixel_format = cpu_to_le32(AD_BYTE_F | (3 AD_ALPHA_C_SHIFT) |
(0 AD_BLUE_C_SHIFT) | (1 AD_GREEN_C_SHIFT) |
@@ -134,6 +189,7 @@ int platform_diu_init(unsigned int xres, unsigned int yres,
const char *port)
out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
px_brdcfg0 = in_8(lbc_lcs1_ba);
out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
+ in_8(lbc_lcs1_ba);
/* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
clrsetbits_be32(gur-pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
@@ -168,12 +224,10 @@ static int set_mux_to_lbc(void)
* In DIU mode, the PIXIS can only be accessed indirectly
* since we can't read/write the LBC directly.
*/
-
/* Set the board mux to LBC. This will disable the display. */
out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
- px_brdcfg0 = in_8(lbc_lcs1_ba);
- out_8(lbc_lcs1_ba, (px_brdcfg0 ~(PX_BRDCFG0_ELBC_SPI_MASK
- | PX_BRDCFG0_ELBC_DIU
Re: [U-Boot] [PATCH 5/6] cmd_nvedit.c: allow board-specific code before/after saving the environment
Mike Frysinger wrote:
this is less bloat:
int board_saveenv(void) __attribute__((weak, alias(saveenv)));
int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf(Saving Environment to %s...\n, env_name_spec);
return board_saveenv() ? 1 : 0;
}
I don't think this can work:
cmd_nvedit.c:599:5: error: 'board_saveenv' aliased to undefined symbol
'saveenv'
cmd_nvedit.c:599:5: error: 'board_saveenv' aliased to undefined symbol
'saveenv'
make[1]: *** [/home/b04825/git/u-boot.0/1022/common/cmd_nvedit.o] Error 1
It looks like weak functions can't be in another source file?
If I change it to this, then it works:
static int __saveenv(void)
{
return saveenv();
}
int board_saveenv(void) __attribute__((weak, alias(__saveenv)));
int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf(Saving Environment to %s...\n, env_name_spec);
return board_saveenv() ? 1 : 0;
}
--
Timur Tabi
Linux kernel developer at Freescale
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Re: [U-Boot] [PATCH 5/6] cmd_nvedit.c: allow board-specific code before/after saving the environment
Wolfgang Denk wrote:
I think whoever told you this was right. Let it break.
Come on, Wolfgang. That's not acceptable.
We cannot add pre- and post-hooks all ever the place for brain-dead
designs that need to do this and that before and after doing perfectly
things.
Well, I already have code in U-boot that does this. If you look at
board/freescale/p1022ds/diu.c, you'll see that I override each of the NOR
flash accessors. This is horribly inefficient, but it works.
Unfortunately, it only covers NOR flash. The new design covers NOR and NAND.
The last two patches of this patchset are a vast improvement, but they
require a board hook (and using Mike's idea, only one hook is necessary,
not two).
As for 'all over the place, I think it's unfair to say my one board hook
function is going to result in all over the place hacks.
It makes no sense adding this to saveenv, because there will be othe
rplaces in the code that need to to the same - like if it's NAND
flash, you will probabaly need to do the same for all NAND related
commands.
Actually, the same code works for saving the environment to NAND flash.
This is how the board code will look:
/*
* While the DIU is active, the localbus is not available. Therefore, in
* order to support the saveenv command to localbus devices, we need to
* temporarily disable the DIU and enable the localbus. To do this, we
* provide our own implementation of board_saveenv(). This function is called
* by do_env_save().
*/
#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_FLASH)
int board_saveenv(void)
{
int switched, ret;
switched = set_mux_to_lbc();
ret = saveenv();
if (switched)
set_mux_to_diu();
return ret;
}
#endif
cmd_nvedit.c is definitely the wrong place for this.
If you have a better idea, then I'm all ears. I could implement my own
version of saveenv(), but the current design of U-boot does not allow me
to have two functions called saveenv().
--
Timur Tabi
Linux kernel developer at Freescale
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Re: [U-Boot] [PATCH 5/6] cmd_nvedit.c: allow board-specific code before/after saving the environment
Scott Wood wrote: NAND doesn't need it because NAND goes through an API rather than direct memory-mapped access, and has more coarse-grained operations. NAND should be able to take care of this entirely in the driver using the select_chip() callback. Fair enough. How do I enable that feature? Do I create my own board_nand_init() and then do this: this-select_chip = p1022ds_nand_select_chip; Timur, is there any reason to use NOR rather than NAND with this chip? Well, as with most of our boards, NOR is the default configuration. Also, there's no NAND support upstream yet. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/6] cmd_nvedit.c: allow board-specific code before/after saving the environment
Mike Frysinger wrote:
On Friday 04 May 2012 18:21:31 Timur Tabi wrote:
Introduce board_start_saveenv() and board_finish_saveenv(), two weak
functions that are called before and after saving the environment. This
allows for board-specific functions that prepare the board for saving
the environment. This is useful if, for some reason, the non-volatile
storage is normally unavailable (e.g. blocked via a mux).
all these board hooks are paper-cutting us to death with unused bloat
I know, and I don't like it either. I hate how our hardware designers are
always breaking the rules, forcing us software developers to hack up our
software more and more. The muxing on this chip is a like a cruel joke
being played on me. I've even been told that I'm trying too hard to make
it work.
this is less bloat:
int board_start_saveenv(void) __attribute__((weak, alias(saveenv)));
int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf(Saving Environment to %s...\n, env_name_spec);
return board_saveenv() ? 1 : 0;
}
Ah, I see. This forces the board-specific function to call saveenv().
That gives us more flexibility in the board code.
However, I was trying to mimic what we have in the NAND layer, with
nand_get_device() and nand_release_device(). That is, before we save the
environment, we have to get it, and then after we save it, we can
release it.
Your approach, although it eliminates two weak functions, is not as
architecturally clean as mine, IMHO.
I'm happy to do it your way if that's the consensus. I just want everyone
to understand my approach first.
--
Timur Tabi
Linux kernel developer at Freescale
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[U-Boot] nand_get_device() and nand_release_device()
Scott,
As you know, the P1022 has this weird LBC/DIU muxing problem. I'd like to
add support for the 'nand' command while the DIU is active. Looking at
the NAND code, I see functions nand_get_device() and
nand_release_device(). What is the idea behind these functions? Would it
make sense to do something like this:
static int __board_start_nand(void)
{
return 0;
}
int board_start_nand(void) __attribute__((weak, alias(__board_start_nand)));
static void __board_finish_nand(void)
{
}
void board_finish_nand(void) __attribute__((weak,
alias(__board_finish_nand)));
static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
int new_state)
{
chip-state = new_state;
return board_start_nand();
}
static void nand_release_device(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd-priv;
board_finish_nand();
/* De-select the NAND device */
chip-select_chip(mtd, -1);
}
--
Timur Tabi
Linux kernel developer at Freescale
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Re: [U-Boot] [PATCH v3] powerpc/p1022ds: Add sdcard and spi boot support to P1022DS
Dirk Eibach wrote:
Signed-off-by: Dirk Eibach eib...@gdsys.de
Cc: Timur Tabi ti...@freescale.com
---
Can you give me some instructions on how to test this? I'm working on
adding NAND boot support to the P1022, so I need to make sure I don't
conflict with your patch.
Changes in v2:
- add Cc
- split up original patch series
Changes in v3:
- use clrsetbits() instead of clrbits()/setbits()
- remove dead code
- remove unnecessary #undef
board/freescale/p1022ds/p1022ds.c |3 ++
board/freescale/p1022ds/tlb.c | 10 ++
boards.cfg|4 ++
include/configs/P1022DS.h | 56 +---
4 files changed, 68 insertions(+), 5 deletions(-)
diff --git a/board/freescale/p1022ds/p1022ds.c
b/board/freescale/p1022ds/p1022ds.c
index 456d9b0..fd4193d 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -37,6 +37,9 @@ int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ /* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */
+ clrsetbits_be32(gur-pmuxcr, 0x0060, 0x8000);
+
Should there be an #ifdef around this, like maybe:
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
/* Reset eLBC_DIU and SPI_eLBC when we are booting from SD */
clrsetbits_be32(gur-pmuxcr, 0x0060, 0x8000);
#endif
/* Set pmuxcr to allow both i2c1 and i2c2 */
setbits_be32(gur-pmuxcr, 0x1000);
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
index e620112..1e9969f 100644
--- a/board/freescale/p1022ds/tlb.c
+++ b/board/freescale/p1022ds/tlb.c
@@ -71,6 +71,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4K, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT)
Please use #ifdef instead of #if defined where possible.
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x4000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_1G, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 24c5879..8de4235 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -700,6 +700,10 @@ P1021RDB-PC_SDCARD powerpc mpc85xx
p1_p2_rdb_pcfreesca
P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc
freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH
P1022DS powerpc mpc85xx p1022ds
freescale
P1022DS_36BITpowerpc mpc85xx p1022ds
freescale - P1022DS:36BIT
+P1022DS_36BIT_SDCARD powerpc mpc85xx p1022ds
freescale - P1022DS:36BIT,SDCARD
+P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds
freescale - P1022DS:36BIT,SPIFLASH
+P1022DS_SDCARD powerpc mpc85xx p1022ds
freescale - P1022DS:SDCARD
+P1022DS_SPIFLASH powerpc mpc85xx p1022ds
freescale - P1022DS:SPIFLASH
P1023RDS powerpc mpc85xx p1023rds
freescale - P1023RDS
P1023RDS_NANDpowerpc mpc85xx p1023rds
freescale - P1023RDS:NAND
P1024RDB powerpc mpc85xx p1_p2_rdb_pc
freescale - p1_p2_rdb_pc:P1024RDB
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 70d751d..213c5e3 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -26,6 +26,18 @@
#define CONFIG_P1022DS
#define CONFIG_MP/* support multiple processors */
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD1
+#define CONFIG_SYS_TEXT_BASE 0x1100
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH 1
+#define CONFIG_SYS_TEXT_BASE 0x1100
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff8
#endif
@@ -54,6 +66,7 @@
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+
#define CONFIG_ICS307_REFCLK_HZ 3000 /* ICS307 clock chip ref freq
*/
Unrelated whitespace change, please remove.
/*
@@ -138,6 +151,12 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE/*
start
[U-Boot] [PATCH 1/6] powerpc/85xx: minor clean-ups to the P2020DS board header file
Remove some unused macros and remove all #undef macros.
The RTL8139 network adapter is not shipped with the board nor commonly
used, so don't define it by default. The E1000 is still defined.
Add 57,600 baud as an option. For some reason, this baud rate is missing
from many boards.
Signed-off-by: Timur Tabi ti...@freescale.com
---
include/configs/P2020DS.h | 22 +-
1 files changed, 1 insertions(+), 21 deletions(-)
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index f0eb029..183d70a 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -128,7 +128,6 @@
#else
#define CONFIG_FSL_DDR31
#endif
-#undef CONFIG_FSL_DDR_INTERACTIVE
/* ECC will be enabled based on perf_mode environment variable */
/* #define CONFIG_DDR_ECC */
@@ -207,8 +206,6 @@
*
*/
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Memory map
*
@@ -251,7 +248,6 @@
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024/* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT6 /* Flash Erase Timeout
(ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Flash Write Timeout
(ms) */
@@ -373,7 +369,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2(CONFIG_SYS_CCSRBAR+0x4600)
@@ -394,7 +390,6 @@
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C/* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 40 /* I2C speed and slave address
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
@@ -529,17 +524,6 @@
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x2000 /* 512M */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-#define CONFIG_RTL8139
-
-#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDRCONFIG_SYS_PCIE3_IO_BUS
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
- #define PCI_IDSEL_NUMBER0x11/* IDSEL = AD11 */
-#endif
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#define CONFIG_SCSI_AHCI
@@ -566,7 +550,6 @@
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME eTSEC3
-#define CONFIG_PIXIS_SGMII_CMD
#define CONFIG_FSL_SGMII_RISER 1
#define SGMII_RISER_PHY_OFFSET 0x1b
@@ -655,8 +638,6 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
/*
* SDHC/MMC
*/
@@ -732,7 +713,6 @@
#define CONFIG_LOADADDR100
#define CONFIG_BOOTDELAY 10/* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS/* the boot command will set bootargs */
#define CONFIG_BAUDRATE115200
--
1.7.3.4
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[U-Boot] [PATCH 2/6] powerpc/85xx: fdt_set_phy_handle() should return an error code
fdt_set_phy_handle() makes several FDT calls that could fail, so it should
not be hiding these errors.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/common/fman.c | 36 +++-
board/freescale/common/fman.h |2 +-
2 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
index 8a55fde..6ddf816 100644
--- a/board/freescale/common/fman.c
+++ b/board/freescale/common/fman.c
@@ -37,31 +37,33 @@
* ... update that Ethernet node's phy-handle property to point to the
* ethernet-phy node. This is how we link an Ethernet node to its PHY, so each
* PHY in a virtual MDIO node must have an alias.
+ *
+ * Returns 0 on success, or a negative FDT error code on error.
*/
-void fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
+int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
const char *alias)
{
- int offset, ph;
+ int offset;
+ unsigned int ph;
const char *path;
/* Get a path to the node that 'alias' points to */
path = fdt_get_alias(fdt, alias);
- if (path) {
- /* Get the offset of that node */
- int off = fdt_path_offset(fdt, path);
- if (off 0)
- ph = fdt_create_phandle(fdt, off);
- else
- return;
- } else {
- return ;
- }
+ if (!path)
+ return -FDT_ERR_BADPATH;
+
+ /* Get the offset of that node */
+ offset = fdt_path_offset(fdt, path);
+ if (offset 0)
+ return offset;
- /* failed to create a phandle */
- if (ph = 0)
- return ;
+ ph = fdt_create_phandle(fdt, offset);
+ if (!ph)
+ return -FDT_ERR_BADPHANDLE;
offset = fdt_node_offset_by_compat_reg(fdt, compat, addr);
- if (offset 0)
- fdt_setprop(fdt, offset, phy-handle, ph, sizeof(ph));
+ if (offset 0)
+ return offset;
+
+ return fdt_setprop(fdt, offset, phy-handle, ph, sizeof(ph));
}
diff --git a/board/freescale/common/fman.h b/board/freescale/common/fman.h
index 19ef7c4..d39ef08 100644
--- a/board/freescale/common/fman.h
+++ b/board/freescale/common/fman.h
@@ -20,7 +20,7 @@
#ifndef __FMAN_BOARD_HELPER__
#define __FMAN_BOARD_HELPER__
-void fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
+int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
const char *alias);
#endif
--
1.7.3.4
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[U-Boot] [PATCH 3/6] powerpc/85xx: clean up P1022DS board configuration header file
Remove some unused default environment variables (memctl_intlv_ctl, perf_mode, diuregs, dium, and diuerr), update 'tftpflash' variable, and add videobootargs as a Linux command line variable (so that we can easily pass video= to the kernel). Signed-off-by: Timur Tabi ti...@freescale.com --- include/configs/P1022DS.h | 43 +++ 1 files changed, 19 insertions(+), 24 deletions(-) diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 70d751d..9d2f8ea 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -488,35 +488,30 @@ #define CONFIG_LOADADDR100 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#define CONFIG_BOOTARGS #define CONFIG_BAUDRATE115200 -#defineCONFIG_EXTRA_ENV_SETTINGS \ - perf_mode=stable\0\ - memctl_intlv_ctl=2\0 \ - netdev=eth0\0 \ - uboot= MK_STR(CONFIG_UBOOTPATH) \0 \ - tftpflash=tftpboot $loadaddr $uboot; \ - protect off MK_STR(CONFIG_SYS_TEXT_BASE) +$filesize; \ - erase MK_STR(CONFIG_SYS_TEXT_BASE) +$filesize; \ - cp.b $loadaddr MK_STR(CONFIG_SYS_TEXT_BASE) $filesize; \ - protect on MK_STR(CONFIG_SYS_TEXT_BASE) +$filesize; \ - cmp.b $loadaddr MK_STR(CONFIG_SYS_TEXT_BASE) $filesize\0 \ - consoledev=ttyS0\0\ - ramdiskaddr=200\0 \ - ramdiskfile=uramdisk\0\ - fdtaddr=c0\0 \ - fdtfile=p1022ds.dtb\0 \ - bdev=sda3\0 \ - diuregs=md e002c000 1d\0 \ - dium=mw e002c01c\0\ - diuerr=md e002c014 1\0\ +#defineCONFIG_EXTRA_ENV_SETTINGS \ + netdev=eth0\0 \ + uboot= MK_STR(CONFIG_UBOOTPATH) \0 \ + ubootaddr= MK_STR(CONFIG_SYS_TEXT_BASE) \0 \ + tftpflash=tftpboot $loadaddr $uboot \ + protect off $ubootaddr +$filesize \ + erase $ubootaddr +$filesize \ + cp.b $loadaddr $ubootaddr $filesize \ + protect on $ubootaddr +$filesize\ + cmp.b $loadaddr $ubootaddr $filesize\0\ + consoledev=ttyS0\0\ + ramdiskaddr=200\0 \ + ramdiskfile=rootfs.ext2.gz.uboot\0\ + fdtaddr=c0\0 \ + fdtfile=p1022ds.dtb\0 \ + bdev=sda3\0 \ hwconfig=esdhc;audclk:12\0 #define CONFIG_HDBOOT \ setenv bootargs root=/dev/$bdev rw\ - console=$consoledev,$baudrate $othbootargs; \ + console=$consoledev,$baudrate $othbootargs $videobootargs;\ tftp $loadaddr $bootfile; \ tftp $fdtaddr $fdtfile; \ bootm $loadaddr - $fdtaddr @@ -525,14 +520,14 @@ setenv bootargs root=/dev/nfs rw \ nfsroot=$serverip:$rootpath \ ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off \ - console=$consoledev,$baudrate $othbootargs; \ + console=$consoledev,$baudrate $othbootargs $videobootargs;\ tftp $loadaddr $bootfile; \ tftp $fdtaddr $fdtfile; \ bootm $loadaddr - $fdtaddr #define CONFIG_RAMBOOTCOMMAND \ setenv bootargs root=/dev/ram rw \ - console=$consoledev,$baudrate $othbootargs; \ + console=$consoledev,$baudrate $othbootargs $videobootargs;\ tftp $ramdiskaddr $ramdiskfile; \ tftp $loadaddr $bootfile; \ tftp $fdtaddr $fdtfile; \ -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/6] cmd_nvedit.c: allow board-specific code before/after saving the environment
Introduce board_start_saveenv() and board_finish_saveenv(), two weak
functions that are called before and after saving the environment. This
allows for board-specific functions that prepare the board for saving
the environment. This is useful if, for some reason, the non-volatile
storage is normally unavailable (e.g. blocked via a mux).
Signed-off-by: Timur Tabi ti...@freescale.com
---
common/cmd_nvedit.c | 24 +++-
1 files changed, 23 insertions(+), 1 deletions(-)
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index e1ccdd8..9637682 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -595,11 +595,33 @@ ulong getenv_ulong(const char *name, int base, ulong
default_val)
}
#if defined(CONFIG_CMD_SAVEENV) !defined(CONFIG_ENV_IS_NOWHERE)
+
+static int __board_start_saveenv(void)
+{
+ return 0;
+}
+int board_start_saveenv(void) __attribute__((weak,
alias(__board_start_saveenv)));
+
+static void __board_finish_saveenv(void)
+{
+}
+void board_finish_saveenv(void) __attribute__((weak,
alias(__board_finish_saveenv)));
+
int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+ int ret;
+
printf(Saving Environment to %s...\n, env_name_spec);
- return saveenv() ? 1 : 0;
+ ret = board_start_saveenv();
+ if (ret)
+ return 0;
+
+ ret = saveenv() ? 1 : 0;
+
+ board_finish_saveenv();
+
+ return ret;
}
U_BOOT_CMD(
--
1.7.3.4
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[U-Boot] [PATCH 4/6] lib/powerpc: addrmap_phys_to_virt() should return a pointer
addrmap_phys_to_virt() converts a physical address (phys_addr_t) to a
virtual address, so it should return a pointer instead of an unsigned long.
Its counterpart, addrmap_virt_to_phys(), takes a pointer, so now they're
orthogonal.
The only caller of addrmap_phys_to_virt() converts the return value to
a pointer anyway.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/include/asm/io.h |2 +-
include/addr_map.h|2 +-
lib/addr_map.c| 19 +++
3 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 56ac9fe..6b52a94 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -295,7 +295,7 @@ static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
#ifdef CONFIG_ADDR_MAP
- return (void *)(addrmap_phys_to_virt(paddr));
+ return addrmap_phys_to_virt(paddr);
#else
return (void *)((unsigned long)paddr);
#endif
diff --git a/include/addr_map.h b/include/addr_map.h
index d55f5f6..36da256 100644
--- a/include/addr_map.h
+++ b/include/addr_map.h
@@ -22,7 +22,7 @@
#include asm/types.h
extern phys_addr_t addrmap_virt_to_phys(void *vaddr);
-extern unsigned long addrmap_phys_to_virt(phys_addr_t paddr);
+void *addrmap_phys_to_virt(phys_addr_t paddr);
extern void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr,
phys_size_t size, int idx);
diff --git a/lib/addr_map.c b/lib/addr_map.c
index ff8532c..31384d1 100644
--- a/lib/addr_map.c
+++ b/lib/addr_map.c
@@ -47,26 +47,29 @@ phys_addr_t addrmap_virt_to_phys(void * vaddr)
return (phys_addr_t)(~0);
}
-unsigned long addrmap_phys_to_virt(phys_addr_t paddr)
+void *addrmap_phys_to_virt(phys_addr_t paddr)
{
int i;
for (i = 0; i CONFIG_SYS_NUM_ADDR_MAP; i++) {
- u64 base, upper, addr;
+ phys_addr_t base, upper;
if (address_map[i].size == 0)
continue;
- addr = (u64)paddr;
- base = (u64)(address_map[i].paddr);
- upper = (u64)(address_map[i].size) + base - 1;
+ base = address_map[i].paddr;
+ upper = address_map[i].size + base - 1;
- if (addr = base addr = upper) {
- return paddr - address_map[i].paddr +
address_map[i].vaddr;
+ if (paddr = base paddr = upper) {
+ phys_addr_t offset;
+
+ offset = address_map[i].paddr - address_map[i].vaddr;
+
+ return (void *)(unsigned long)(paddr - offset);
}
}
- return (unsigned long)(~0);
+ return (void *)(~0);
}
void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr,
--
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[U-Boot] [PATCH 6/6] powerpc/85xx: p1022ds: use the saveenv board preparation functions
On the P1022, the DIU video signals are muxed with the localbus, so when
the DIU is active, the localbus is unavailable. The saveenv command
now supports board-specific functions that allow the DIU/LBC mux to
be switched while saving the environment.
This is much more efficient than switching the mux for each NOR flash
transaction (which is what the current code does), and it also allows
us to support any localbus device, not just NOR flash.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/p1022ds/diu.c | 173 +++--
include/configs/P1022DS.h |6 --
2 files changed, 28 insertions(+), 151 deletions(-)
diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c
index d5428ea..1dd0e1f 100644
--- a/board/freescale/p1022ds/diu.c
+++ b/board/freescale/p1022ds/diu.c
@@ -147,10 +147,7 @@ int platform_diu_init(unsigned int xres, unsigned int
yres, const char *port)
*
* On the Freescale P1022, the DIU video signal and the LBC address/data lines
* share the same pins, which means that when the DIU is active (e.g. the
- * console is on the DVI display), NOR flash cannot be accessed. So we use the
- * weak accessor feature of the CFI flash code to temporarily switch the pin
- * mux from DIU to LBC whenever we want to read or write flash. This has a
- * significant performance penalty, but it's the only way to make it work.
+ * console is on the DVI display), NOR flash cannot be accessed.
*
* There are two muxes: one on the chip, and one on the board. The chip mux
* controls whether the pins are used for the DIU or the LBC, and it is
@@ -213,6 +210,33 @@ static void set_mux_to_diu(void)
}
/*
+ * While the DIU is active, the localbus is not available. Therefore, in
+ * order to support the saveenv command, we need to temporarily disable the
+ * DIU and enable the localbus. To do this, we provide our own
+ * implementations of the board_start_saveenv() and board_finish_saveenv()
+ * weak functions. These functions are called by do_env_save() before and
+ * after the environment is saved.
+ */
+
+/* Remember if we switched the MUX, so that we know to switch it back */
+static int switched;
+
+int board_start_saveenv(void)
+{
+ switched = set_mux_to_lbc();
+
+ return 0;
+}
+
+void board_finish_saveenv(void)
+{
+ if (switched)
+ set_mux_to_diu();
+
+ switched = 0;
+}
+
+/*
* pixis_read - board-specific function to read from the PIXIS
*
* This function overrides the generic pixis_read() function, so that it can
@@ -271,144 +295,3 @@ void pixis_bank_reset(void)
while (1);
}
-
-#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-
-void flash_write8(u8 value, void *addr)
-{
- int sw = set_mux_to_lbc();
-
- __raw_writeb(value, addr);
- if (sw) {
- /*
-* To ensure the post-write is completed to eLBC, software must
-* perform a dummy read from one valid address from eLBC space
-* before changing the eLBC_DIU from NOR mode to DIU mode.
-* set_mux_to_diu() includes a sync that will ensure the
-* __raw_readb() completes before it switches the mux.
-*/
- __raw_readb(addr);
- set_mux_to_diu();
- }
-}
-
-void flash_write16(u16 value, void *addr)
-{
- int sw = set_mux_to_lbc();
-
- __raw_writew(value, addr);
- if (sw) {
- /*
-* To ensure the post-write is completed to eLBC, software must
-* perform a dummy read from one valid address from eLBC space
-* before changing the eLBC_DIU from NOR mode to DIU mode.
-* set_mux_to_diu() includes a sync that will ensure the
-* __raw_readb() completes before it switches the mux.
-*/
- __raw_readb(addr);
- set_mux_to_diu();
- }
-}
-
-void flash_write32(u32 value, void *addr)
-{
- int sw = set_mux_to_lbc();
-
- __raw_writel(value, addr);
- if (sw) {
- /*
-* To ensure the post-write is completed to eLBC, software must
-* perform a dummy read from one valid address from eLBC space
-* before changing the eLBC_DIU from NOR mode to DIU mode.
-* set_mux_to_diu() includes a sync that will ensure the
-* __raw_readb() completes before it switches the mux.
-*/
- __raw_readb(addr);
- set_mux_to_diu();
- }
-}
-
-void flash_write64(u64 value, void *addr)
-{
- int sw = set_mux_to_lbc();
- uint32_t *p = addr;
-
- /*
-* There is no __raw_writeq(), so do the write manually. We don't trust
-* the compiler, so we use inline assembly.
-*/
- __asm__ __volatile__(
- stw%U0%X0 %2,%0;\n
- stw%U1%X1 %3,%1;\n
Re: [U-Boot] BIOS EMULATOR driver
Marek Vasut wrote: Sure, but I see no point in keeping such dead code in U-Boot code base. Aka. why keep functions in U-Boot that are never used? I think what Wolfgang is trying to say is that no one has proven that there actually IS any unused code. The ATI driver needs the BIOS emulator, so you need to enable support for the ATI driver to see what is and is not actually used. Just because it's not enabled currently in any board, that doesn't mean that the code is useless. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] BIOS EMULATOR driver
Marek Vasut wrote: Agreed, but I expected there was some dead code and that was the point I was trying to express ;-) Well, until you do a thorough analysis, you really have no idea if there is any dead code at all. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] BIOS EMULATOR driver
Viktor Křivák wrote: I think here may be a little misunderstanding. I don't want to remove whole driver. I only want to remove support of bios emulator form that 2 board because I think they don't use it. I try compile it without this driver and everything seems to be ok. I think it's okay to remove it from the P1022DS board. I think the only reason it is enabled because of some misunderstanding of the BSP requirement, and no one ever noticed. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but that register does not exist on e500v1. Signed-off-by: Timur Tabi ti...@freescale.com --- arch/powerpc/cpu/mpc85xx/start.S |8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 4d37d6e..d0872cf 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -434,13 +434,15 @@ create_ccsr_new_tlb: ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l +#ifdef CONFIG_ENABLE_36BIT_PHYS lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + mtspr MAS7, r7 +#endif mtspr MAS0, r0 mtspr MAS1, r1 mtspr MAS2, r2 mtspr MAS3, r3 - mtspr MAS7, r7 isync msync tlbwe @@ -456,12 +458,14 @@ create_ccsr_old_tlb: ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l +#ifdef CONFIG_ENABLE_36BIT_PHYS li r7, 0 /* The default CCSR address is always a 32-bit number */ + mtspr MAS7, r7 +#endif mtspr MAS0, r0 /* MAS1 is the same as above */ mtspr MAS2, r2 mtspr MAS3, r3 - mtspr MAS7, r7 isync msync tlbwe -- 1.7.10.rc1.8.ga99c5.dirty ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4][v2] powerpc/85xx:Make debug exception vector accessible
Scott Wood wrote: Either it's needed, or we should get rid of CONFIG_ENABLE_36BIT_PHYS entirely. Either way, we should test the results on e500v1 hardware. That macro conditionally enables support for MAS7: #if defined(CONFIG_ENABLE_36BIT_PHYS) ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ #endif So I don't think we can get rid of it, otherwise I suspect an e500v1 operating system will not work on an e500v2 part. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4][v2] powerpc/85xx:Make debug exception vector accessible
Scott Wood wrote: For your kind information : in start.S, label label create_ccsr_new_tlb, create_ccsr_old_tlb uses MAS7 without CONFIG_ENABLE_36BIT_PHYS #define. It should be fixed ?? Yes, it should be fixed. That was a fairly recent change and perhaps e500v1 has not been tested since then -- Timur, could you look at this? On e500v1 parts, CONFIG_SYS_CCSRBAR_PHYS_HIGH will always be 0, so it will only write 0 to MAS7. Is that still considered a bad thing? The tlbwe will ignore MAS7. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/83xx: increment malloc heap size for the MPC832x MDS boards
The malloc buffer is not large enough to hold a flash sector (0x2 bytes) in addition to whatever else it normally holds, so double its size. This fixes a failure trying to save the environment: = save Saving Environment to Flash... Unable to save the rest of sector (122880) . done Protected 1 sectors This problem probably surfaced from some other change that significantly increased the normal memory usage, thereby not leaving enough room for the saveenv command. Signed-off-by: Timur Tabi ti...@freescale.com --- include/configs/MPC832XEMDS.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 4ed5a97..6f8622c 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -181,7 +181,7 @@ /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ #define CONFIG_SYS_MONITOR_LEN (384 * 1024)/* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024)/* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024)/* Reserved for malloc */ /* * Initial RAM Base Address Setup -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] [v3] powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes
displays which of these is actually built, but it's inconsistent. This is
especially problematic since the default build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used. Not only that, but each board includes code that displays
the message, so there is duplication.
The 'bdinfo' command has been updated to display this information, so
we don't need to display it at boot time. The board-specific code is
deleted.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/corenet_ds/corenet_ds.c |4
board/freescale/mpc8536ds/mpc8536ds.c |7 +--
board/freescale/mpc8572ds/mpc8572ds.c |6 +-
board/freescale/p1010rdb/p1010rdb.c |6 +-
board/freescale/p1022ds/p1022ds.c |8 ++--
board/freescale/p1_p2_rdb/p1_p2_rdb.c |4 +---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c |8 +---
board/freescale/p2020ds/p2020ds.c |8 ++--
board/freescale/p2041rdb/p2041rdb.c |4
board/freescale/p3060qds/p3060qds.c |3 ---
10 files changed, 9 insertions(+), 49 deletions(-)
diff --git a/board/freescale/corenet_ds/corenet_ds.c
b/board/freescale/corenet_ds/corenet_ds.c
index b1eecc4..a33c936 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -62,10 +62,6 @@ int checkboard (void)
else
printf(invalid setting of SW%u\n, PIXIS_LBMAP_SWITCH);
-#ifdef CONFIG_PHYS_64BIT
- puts(36-bit Addressing\n);
-#endif
-
/* Display the RCW, so that no one gets confused as to what RCW
* we're actually using for this boot.
*/
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c
b/board/freescale/mpc8536ds/mpc8536ds.c
index c9f85c8..6d0bfde 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -68,12 +68,7 @@ int checkboard (void)
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
- puts(Board: MPC8536DS );
-#ifdef CONFIG_PHYS_64BIT
- puts((36-bit addrmap) );
-#endif
-
- printf (Sys ID: 0x%02x,
+ printf(Board: MPC8536DS Sys ID: 0x%02x,
Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ,
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c
b/board/freescale/mpc8572ds/mpc8572ds.c
index b20299e..33a02ba 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -45,11 +45,7 @@ int checkboard (void)
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
- puts (Board: MPC8572DS );
-#ifdef CONFIG_PHYS_64BIT
- puts ((36-bit addrmap) );
-#endif
- printf (Sys ID: 0x%02x,
+ printf(Board: MPC8572DS Sys ID: 0x%02x,
Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ,
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
diff --git a/board/freescale/p1010rdb/p1010rdb.c
b/board/freescale/p1010rdb/p1010rdb.c
index b9e66f7..79a6ead 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -165,11 +165,7 @@ int checkboard(void)
struct cpu_type *cpu;
cpu = gd-cpu;
- printf(Board: %sRDB , cpu-name);
-#ifdef CONFIG_PHYS_64BIT
- puts((36-bit addrmap));
-#endif
- puts(\n);
+ printf(Board: %sRDB\n, cpu-name);
return 0;
}
diff --git a/board/freescale/p1022ds/p1022ds.c
b/board/freescale/p1022ds/p1022ds.c
index 456d9b0..aca30f3 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -56,12 +56,8 @@ int checkboard(void)
{
u8 sw;
- puts(Board: P1022DS );
-#ifdef CONFIG_PHYS_64BIT
- puts((36-bit addrmap) );
-#endif
-
- printf(Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ,
+ printf(Board: P1022DS Sys ID: 0x%02x,
+ Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ,
in_8(pixis-id), in_8(pixis-arch), in_8(pixis-scver));
sw = in_8(PIXIS_SW(PIXIS_LBMAP_SWITCH));
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index cfbae69..437eaf0 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -110,9 +110,7 @@ int checkboard (void)
cpu = gd-cpu;
printf (Board: %sRDB Rev%c\n, cpu-name, board_rev);
-#ifdef CONFIG_PHYS_64BIT
- puts ((36-bit addrmap) \n);
-#endif
+
setbits_be32(pgpio-gpdir, GPIO_DIR);
/*
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index a60c5a2..aa39260 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -225,13 +225,7
[U-Boot] [PATCH 1/2] cmd_bdinfo: display the address map size (32-bit vs. 36-bit)
Some Freescale SOCs support 32-bit and 36-bit physical addressing, and U-Boot must be built to enable one or the other. Add this information to the bdinfo command. Signed-off-by: Timur Tabi ti...@freescale.com --- This patch set replaces the following patches: http://patchwork.ozlabs.org/patch/118367/ http://patchwork.ozlabs.org/patch/129590/ common/cmd_bdinfo.c |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 5359a47..3ab285b 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -119,6 +119,14 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_mhz(pevfreq,bd-bi_pevfreq); #endif +#ifdef CONFIG_ENABLE_36BIT_PHYS +#ifdef CONFIG_PHYS_64BIT + puts(addressing = 36-bit\n); +#else + puts(addressing = 32-bit\n); +#endif +#endif + print_eth(0); #if defined(CONFIG_HAS_ETH1) print_eth(1); -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] i2c: add i2c_core and prepare for new multibus support
Wolfgang Denk wrote: As mentioned before, this is what we currently have as device model in U-Boot - not only I2C: we have the same current device concept with IDE, USB, ... The difference is that I2C operations are typically done internally by other code, whereas IDE, USB, etc are done by the user on the command line. It's not unusual for boot code to access multiple I2C devices on different buses, so we're switching I2C buses a lot. People generally don't try to access two networks or two USB devices back-to-back, but that's exactly what we do with I2C. The other problem is that I2C operations are necessary prior to relocation, but IDE, USB, etc generally are not. That's why we have this: static unsigned int i2c_bus_num __attribute__ ((section (.data))) = CONFIG_SYS_SPD_BUS_NUM; We need to initialize i2c_bus_num to the I2C bus that SPD is on, because i2c_bus_num is not writable until after relocation, and DDR initialization requires I2C. A board that has SPD on two different I2C buses could not be supported by U-Boot today. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] i2c: add i2c_core and prepare for new multibus support
Mike Frysinger wrote: that's only needed if you expect the pointer to stay valid across calls. i don't think it does for most (all?) drivers. True, but it's hard to know sometimes when it's needed. I do it in my code just to be sure. Regardless, I still think the idea of a current i2c bus is flawed. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] i2c: add i2c_core and prepare for new multibus support
Simon Glass wrote: I agree completely, it was one of the things I was going to ask for. We should add a new parameter to calls instead IMO. I would be in favor of a patch that replaces all of the I2C calls. It would be a massive patch, but it solve a lot of problems in one shot. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] i2c: add i2c_core and prepare for new multibus support
Simon Glass wrote: I agree. Do you know of such a patch? :-) No, but it wouldn't be heard to create -- mostly a global search-and-replace. I wouldn't even attempt it without getting pre-approved by Wolfgang first, though. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [GIT PULL] please pull u-boot-mpc85xx
wrote: The reason I ask is that you're missing some of my patches. http://patchwork.ozlabs.org/project/uboot/list/?submitter=timur Ok, technically you're only missing ONE of my patches. http://patchwork.ozlabs.org/patch/118367/ -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] [v2] powerpc/85xx: move the Fman microcode from ef000000 to eff40000
On some Freescale reference boards for SOCs with Fman devices, the Fman microcode is located at address 0xEF00 in NOR flash. Unfortunately, this address is in the middle of nowhere and makes it difficult to partition flash space for other images. So we change the expected address to 0xEFF4, which is the flash sector adjacent to the environment. Signed-off-by: Timur Tabi ti...@freescale.com --- include/configs/P1023RDS.h |2 +- include/configs/P2041RDB.h |2 +- include/configs/corenet_ds.h |2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index e057b1f..54f4dd4 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -527,7 +527,7 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF00 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF4 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f0 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index a48055e..bc177d0 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -429,7 +429,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF00 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF4 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x1 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 7925b95..e03d318 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -493,7 +493,7 @@ #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF00 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF4 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x1 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] [v2] powerpc/85xx: move the Fman microcode from ef000000 to eff40000
Wolfgang Denk wrote: Instead of hard-coding magic addresses which then need to be changed again and again, would it not make more sense to read the value from an environment variable so it can be easily changed without having to modify the source, rebuild, reinstall all the time? (Adding Haiying) Well, I tried that a while back and it didn't work, but I can't remember why. That was before I implemented a unified approach to Fman ucode identification, so maybe it will work better now. Part of the problem is that the meaning of the address depends on where the ucode actually is stored -- NOR flash, NAND flash, SPI flash, etc. I suppose we could do something like this: ucode_loc=nor:eff4 And then at runtime parse the 'nor' and the 'eff4'. I just wish I could remember why I rejected the env variable approach back then. Haiying, is there ever a situation where we need to upload the QE ucode *before* the environment variables are available? -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] [v2] powerpc/85xx: move the Fman microcode from ef000000 to eff40000
Timur Tabi wrote: Well, I tried that a while back and it didn't work, but I can't remember why. That was before I implemented a unified approach to Fman ucode identification, so maybe it will work better now. Ok, I remember now. The problem was that using the environment variable was messy. On some systems, we have two code sections: 1) loads the ucode into RAM early during boot, and 2) that same ucode is needed to when booting Linux. We used an environment variable to pass the address of the ucode from 1) to 2). That was deemed to be too fragile, so we switched to macros. I suppose if we get #2 to reload the ucode, that will make it work. Then #1 won't need to store the ucode permanently in memory. It's not a trivial fix, though. All of the existing code works on the assumption that the ucode is only located in one place. I still have a nagging feeling that I'm missing something, though. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] net/fm: check the old and new Fman microcode locations in NOR flash
Kumar Gala wrote: I see no reason for this patch, if you're flashing a new u-boot flash the microcode to the new address as well. This is useful for people who have not moved the microcode. Are we going to ensure that everyone who updates U-Boot will also move their microcode to the new location? We can always revert this patch after everyone has migrated, if that's really necessary. You know as well as I do that if don't provide backwards compatibility, someone is going to break and won't know why. Don't we already have a warning if we don't find the ucode at the expected address. No. The warning just says that microcode is invalid, not that that it's at the wrong address. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] powerpc/85xx: move the Fman microcode from ef000000 to eff40000
On some Freescale reference boards for SOCs with Fman devices, the Fman microcode is located at address 0xEF00 in NOR flash. Unfortunately, this address is in the middle of nowhere and makes it difficult to partition flash space for other images. So we change the expected address to 0xEFF4, which is the flash sector adjacent to the environment. To support older boards, we use macro CONFIG_SYS_QE_FMAN_FW_ADDR_OLD to look for the microcode in the old location if it cannot be found in the new one. Signed-off-by: Timur Tabi ti...@freescale.com --- include/configs/P1023RDS.h |4 +++- include/configs/P2041RDB.h |4 +++- include/configs/corenet_ds.h |4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index e057b1f..734dc89 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -527,7 +527,9 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF00 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF4 +/* We may need to check the old location in NOR flash as well */ +#define CONFIG_SYS_QE_FMAN_FW_ADDR_OLD 0xEF00 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f0 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index a48055e..e6b70fc 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -429,7 +429,9 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF00 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF4 +/* We may need to check the old location in NOR flash as well */ +#define CONFIG_SYS_QE_FMAN_FW_ADDR_OLD 0xEF00 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x1 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 7925b95..9d1aea7 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -493,7 +493,9 @@ #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF00 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF4 +/* We may need to check the old location in NOR flash as well */ +#define CONFIG_SYS_QE_FMAN_FW_ADDR_OLD 0xEF00 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x1 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] net/fm: check the old and new Fman microcode locations in NOR flash
On some Freescale reference boards for SOCs with Fman devices, the Fman
microcode is located at address 0xEF00 in NOR flash. Unfortunately,
this address is in the middle of nowhere and makes it difficult to
partition flash space for other images.
So we change the expected address to 0xEFF4, which is the flash
sector adjacent to the environment. To support older boards, we use macro
CONFIG_SYS_QE_FMAN_FW_ADDR_OLD to look for the microcode in the old location
if it cannot be found in the new one.
The code which uploads the microcode checks the new default location, and
if the microcode is not found, then it checks the old location. This allows
newer U-Boots to work on older boards. However, during boot, the error
messages are a bit confusing:
Net: Fman1: Data at eff4 is not a firmware
Fman1: Uploading microcode version 101.8.0
Fman2: Data at eff4 is not a firmware
Fman2: Uploading microcode version 101.8.0
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/fm/fm.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 0b8c33f..f148608 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -412,6 +412,13 @@ int fm_init_common(int index, struct ccsr_fman *reg)
/* Upload the Fman microcode if it's present */
rc = fman_upload_firmware(index, reg-fm_imem, addr);
+#ifdef CONFIG_SYS_QE_FMAN_FW_ADDR_OLD
+ /* Check the old location in NOR flash */
+ if (rc) {
+ addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR_OLD;
+ rc = fman_upload_firmware(index, reg-fm_imem, addr);
+ }
+#endif
if (rc)
return rc;
sprintf(env_addr, 0x%lx, (long unsigned int)addr);
--
1.7.3.4
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/85xx: clean up and document the QE/FMAN microcode macros
Kumar Gala wrote: Can your respin against current upstream HEAD. For some reason this doesn't apply cleanly there. This patch broke it: drivers/net/fm/fm.c: Fix GCC 4.6 build warning I'll post a v2 in just a few minutes. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] [v2] powerpc/85xx: clean up and document the QE/FMAN microcode macros
Several macros are used to identify and locate the microcode binary image
that U-boot needs to upload to the QE or Fman. Both the QE and the Fman
use the QE Firmware binary format to package their respective microcode data,
which is why the same macros are used for both. A given SOC will only have
a QE or an Fman, so this is safe.
Unfortunately, the current macro definition and usage has inconsistencies.
For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
of NAND. There's no way to know by looking at a variable how it's supposed
to be used.
In the future, the code which uploads QE firmware and Fman firmware will
be merged.
Signed-off-by: Timur Tabi ti...@freescale.com
---
README | 38 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 12 +-
arch/powerpc/cpu/mpc85xx/fdt.c |2 +-
drivers/net/fm/fm.c | 32 ++--
drivers/qe/qe.c |4 +-
include/configs/MPC8569MDS.h|3 +-
include/configs/P1023RDS.h | 10 +---
include/configs/P2041RDB.h | 16 +-
include/configs/corenet_ds.h| 16 +-
include/configs/p1_p2_rdb_pc.h |5 ++-
10 files changed, 94 insertions(+), 44 deletions(-)
diff --git a/README b/README
index 73ca042..24bcad8 100644
--- a/README
+++ b/README
@@ -3268,6 +3268,44 @@ Low Level (hardware related) configuration options:
be used if available. These functions may be faster under some
conditions but may increase the binary size.
+Freescale QE/FMAN Firmware Support:
+---
+
+The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the
+loading of firmware, which is encoded in the QE firmware binary format.
+This firmware often needs to be loaded during U-Boot booting, so macros
+are used to identify the storage device (NOR flash, SPI, etc) and the address
+within that device.
+
+- CONFIG_SYS_QE_FMAN_FW_ADDR
+ The address in the storage device where the firmware is located. The
+ meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+ is also specified.
+
+- CONFIG_SYS_QE_FMAN_FW_LENGTH
+ The maximum possible size of the firmware. The firmware binary format
+ has a field that specifies the actual size of the firmware, but it
+ might not be possible to read any part of the firmware unless some
+ local storage is allocated to hold the entire firmware first.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_NOR
+ Specifies that QE/FMAN firmware is located in NOR flash, mapped as
+ normal addressable memory via the LBC. CONFIG_SYS_FMAN_FW_ADDR is the
+ virtual address in NOR flash.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_NAND
+ Specifies that QE/FMAN firmware is located in NAND flash.
+ CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_MMC
+ Specifies that QE/FMAN firmware is located on the primary SD/MMC
+ device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
+ Specifies that QE/FMAN firmware is located on the primary SPI
+ device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
+
Building the Software:
==
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b9a8193..1ff83a4 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -38,7 +38,7 @@
#include asm/fsl_law.h
#include asm/fsl_serdes.h
#include mp.h
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include nand.h
#include errno.h
#endif
@@ -523,17 +523,17 @@ void cpu_secondary_init_r(void)
{
#ifdef CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
int ret;
- size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
+ size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
/* load QE firmware from NAND flash to DDR first */
- ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
- fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+ ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
+ fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
if (ret ret == -EUCLEAN) {
printf (NAND read for QE firmware at offset %x failed %d\n,
- CONFIG_SYS_QE_FW_IN_NAND, ret);
+ CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
}
#endif
qe_init(qe_base);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 9d31568..435bd1a 100644
--- a/arch/powerpc/cpu/mpc85xx
[U-Boot] [PATCH 1/2] powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA controller, so it should be defined in config_mpc85xx.h instead of the various board header files. So now CONFIG_FSL_SATA_V2 is always defined on the P1013, P1022, P2041, P3041, P5010, and P5020. It was already defined for the P1010 and P1014. Signed-off-by: Timur Tabi ti...@freescale.com --- arch/powerpc/include/asm/config_mpc85xx.h |6 ++ include/configs/P1022DS.h |1 - include/configs/P2041RDB.h|5 ++--- include/configs/P3041DS.h |1 - include/configs/P5020DS.h |1 - 5 files changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 981d639..2ee1389 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -150,6 +150,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -237,6 +238,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -319,6 +321,7 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -337,6 +340,7 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -409,6 +413,7 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -427,6 +432,7 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 1158fec..70d751d 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -345,7 +345,6 @@ /* SATA */ #define CONFIG_LIBATA #define CONFIG_FSL_SATA -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 6d45bb1..f9fe3cf 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -446,10 +446,9 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_PCI */ /* SATA */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA #define CONFIG_FSL_SATA +#ifdef CONFIG_FSL_SATA +#define CONFIG_LIBATA #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index 57d5de5..98e7a42 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -32,7 +32,6 @@ #define CONFIG_MMC #define CONFIG_NAND_FSL_ELBC -#define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index a9cee23..4afc4f1 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -32,7 +32,6 @@ #define CONFIG_MMC #define CONFIG_NAND_FSL_ELBC -#define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_SYS_FSL_RAID_ENGINE -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] powerpc/85xx: always implement the work-around for Erratum SATA_A001
On the P1022/P1013, the work-around for erratum SATA_A001 was implemented
only if U-Boot initializes SATA, but SATA is not initialized by default. So
move the work-around to the CPU initialization function, so that it's always
executed on the SOCs that need it.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 37 +++---
drivers/block/fsl_sata.c| 21 ---
drivers/block/fsl_sata.h|1 +
3 files changed, 34 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b9a8193..27aa038 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -37,12 +37,15 @@
#include asm/mmu.h
#include asm/fsl_law.h
#include asm/fsl_serdes.h
+#include linux/compiler.h
#include mp.h
#ifdef CONFIG_SYS_QE_FW_IN_NAND
#include nand.h
#include errno.h
#endif
+#include ../../../../drivers/block/fsl_sata.h
+
DECLARE_GLOBAL_DATA_PTR;
extern void srio_init(void);
@@ -301,6 +304,7 @@ __attribute__((weak, alias(__fsl_serdes__init))) void
fsl_serdes_init(void);
*/
int cpu_init_r(void)
{
+ __maybe_unused u32 svr = get_svr();
#ifdef CONFIG_SYS_LBC_LCRR
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
@@ -316,10 +320,9 @@ int cpu_init_r(void)
#if defined(CONFIG_L2_CACHE)
volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
volatile uint cache_ctl;
- uint svr, ver;
+ uint ver;
u32 l2siz_field;
- svr = get_svr();
ver = SVR_SOC_VER(svr);
asm(msync;isync);
@@ -401,8 +404,8 @@ int cpu_init_r(void)
puts(enabled\n);
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
- if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
- (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
+ if ((SVR_SOC_VER(svr) == SVR_P2040) ||
+ (SVR_SOC_VER(svr) == SVR_P2040_E)) {
puts(N/A\n);
goto skip_l2;
}
@@ -488,6 +491,32 @@ skip_l2:
fman_enet_init();
#endif
+#if defined(CONFIG_FSL_SATA_V2) defined(CONFIG_FSL_SATA_ERRATUM_A001)
+ /*
+* For P1022/1013 Rev1.0 silicon, after power on SATA host
+* controller is configured in legacy mode instead of the
+* expected enterprise mode. Software needs to clear bit[28]
+* of HControl register to change to enterprise mode from
+* legacy mode. We assume that the controller is offline.
+*/
+ if (IS_SVR_REV(svr, 1, 0)
+ ((SVR_SOC_VER(svr) == SVR_P1022) ||
+(SVR_SOC_VER(svr) == SVR_P1022_E) ||
+(SVR_SOC_VER(svr) == SVR_P1013) ||
+(SVR_SOC_VER(svr) == SVR_P1013_E))) {
+ fsl_sata_reg_t *reg;
+
+ /* first SATA controller */
+ reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
+ clrbits_le32(reg-hcontrol, HCONTROL_ENTERPRISE_EN);
+
+ /* second SATA controller */
+ reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
+ clrbits_le32(reg-hcontrol, HCONTROL_ENTERPRISE_EN);
+ }
+#endif
+
+
return 0;
}
diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c
index 6b35173..3026ade 100644
--- a/drivers/block/fsl_sata.c
+++ b/drivers/block/fsl_sata.c
@@ -197,27 +197,6 @@ int init_sata(int dev)
/* Wait the controller offline */
ata_wait_register(reg-hstatus, HSTATUS_ONOFF, 0, 1000);
-#if defined(CONFIG_FSL_SATA_V2) defined(CONFIG_FSL_SATA_ERRATUM_A001)
- /*
-* For P1022/1013 Rev1.0 silicon, after power on SATA host
-* controller is configured in legacy mode instead of the
-* expected enterprise mode. software needs to clear bit[28]
-* of HControl register to change to enterprise mode from
-* legacy mode.
-*/
- {
- u32 svr = get_svr();
- if (IS_SVR_REV(svr, 1, 0)
- ((SVR_SOC_VER(svr) == SVR_P1022) ||
-(SVR_SOC_VER(svr) == SVR_P1022_E) ||
-(SVR_SOC_VER(svr) == SVR_P1013) ||
-(SVR_SOC_VER(svr) == SVR_P1013_E))) {
- out_le32(reg-hstatus, 0x2000);
- out_le32(reg-hcontrol, 0x0100);
- }
- }
-#endif
-
/* Set the command header base address to CHBA register to tell DMA */
out_le32(reg-chba, (u32)cmd_hdr ~0x3);
diff --git a/drivers/block/fsl_sata.h b/drivers/block/fsl_sata.h
index 576efaf..cecff68 100644
--- a/drivers/block/fsl_sata.h
+++ b/drivers/block/fsl_sata.h
@@ -103,6 +103,7 @@ typedef struct fsl_sata_reg {
*/
#define HCONTROL_ONOFF 0x8000 /* Online or offline request
*/
#define HCONTROL_FORCE_OFFLINE 0x4000 /* Force offline request */
+#define HCONTROL_ENTERPRISE_EN 0x1000 /* Enterprise mode enabled */
#define
[U-Boot] [PATCH] powerpc/85xx: verify the localbus device tree address before booting the OS
The localbus controller node in the device tree is typically a root node,
even though the controller is part of CCSR. If we were to put the lbc
node under the SOC node, then the 'ranges' property in the lbc node would
translate through the 'ranges' property of the parent SOC node, and we
don't want that.
Since the lbc is a separate node, it's possible for the 'reg' property to
be wrong. This happened with the original version of p1022ds.dts, which
used a 32-bit value in the 'reg' address, instead of a 36-bit address.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/fdt.c | 48 ---
1 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 9d31568..2fcd8c3 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -677,6 +677,12 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#define CCSR_VIRT_TO_PHYS(x) \
(CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
+static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
+{
+ printf(Warning: U-Boot configured %s at address %llx,\n
+ but the device tree has it at %llx\n, name, uaddr, daddr);
+}
+
/*
* Verify the device tree
*
@@ -692,33 +698,32 @@ void ft_cpu_setup(void *blob, bd_t *bd)
*/
int ft_verify_fdt(void *fdt)
{
- uint64_t ccsr = 0;
+ uint64_t addr = 0;
int aliases;
int off;
/* First check the CCSR base address */
off = fdt_node_offset_by_prop_value(fdt, -1, device_type, soc, 4);
if (off 0)
- ccsr = fdt_get_base_address(fdt, off);
+ addr = fdt_get_base_address(fdt, off);
- if (!ccsr) {
+ if (!addr) {
printf(Warning: could not determine base CCSR address in
device tree\n);
/* No point in checking anything else */
return 0;
}
- if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) {
- printf(Warning: U-Boot configured CCSR at address %llx,\n
- but the device tree has it at %llx\n,
- (uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr);
+ if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
+ msg(CCSR, CONFIG_SYS_CCSRBAR_PHYS, addr);
/* No point in checking anything else */
return 0;
}
/*
-* Get the 'aliases' node. If there isn't one, then there's nothing
-* left to do.
+* Check some nodes via aliases. We assume that U-Boot and the device
+* tree enumerate the devices equally. E.g. the first serial port in
+* U-Boot is the same as serial0 in the device tree.
*/
aliases = fdt_path_offset(fdt, /aliases);
if (aliases 0) {
@@ -735,5 +740,30 @@ int ft_verify_fdt(void *fdt)
#endif
}
+ /*
+* The localbus node is typically a root node, even though the lbc
+* controller is part of CCSR. If we were to put the lbc node under
+* the SOC node, then the 'ranges' property in the lbc node would
+* translate through the 'ranges' property of the parent SOC node, and
+* we don't want that. Since it's a separate node, it's possible for
+* the 'reg' property to be wrong, so check it here. For now, we
+* only check for fsl,elbc nodes.
+*/
+#ifdef CONFIG_SYS_LBC_ADDR
+ off = fdt_node_offset_by_compatible(fdt, -1, fsl,elbc);
+ if (off 0) {
+ const u32 *reg = fdt_getprop(fdt, off, reg, NULL);
+ if (reg) {
+ uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
+
+ addr = fdt_translate_address(fdt, off, reg);
+ if (uaddr != addr) {
+ msg(the localbus, uaddr, addr);
+ return 0;
+ }
+ }
+ }
+#endif
+
return 1;
}
--
1.7.3.4
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Re: [U-Boot] [u-boot-release] [PATCH] powerpc/85xx: verify the localbus device tree address before booting the OS
Swarthout Edward L-SWARTHOU wrote: ... it's possible for the 'reg' property to be wrong. Instead of all this, why doesn't u-boot just fix it? I have the same annoyance with ccsrbar. U-boot controls the ccsrbar address via a user configured #define. So instead of having different dts's based on the u-boot ccsrbar, why can't u-boot update the device tree? Because we can't just relocate the devices that we know about and ignore the rest. If CCSR is at the wrong address, then maybe the PCI memory ranges are wrong, too? Who's to say what else is wrong? -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Is CCSRBAR relocation broken on P2020?
Ira W. Snyder wrote: Hello Timur, Kumar, U-Boot List, I'm working on porting U-Boot to the Freescale P2020 COM-Express board. See the ML post from 2011-09-27 titled [PATCH 0/2] mpc85xx: support for Freescale COM Express P2020. I see that you are using a NAND boot, which is a multi-stage boot. There are some problems with that that have been fixed in recent patches posted by me and Kumar to the U-boot mailing list. In particular, one patches puts U-boot into an infinite loop if CCSR is relocated in the wrong step. When it was posted, the port was working on the top of tree U-Boot. This included relocation of the CCSRBAR from the power on location of 0xff70 to 0xffe0. Is there a reason why you want to relocate CCSR at all? Everything would be a lot easier if you just left it at the default location. I have a suspicion that many boards relocate CCSR just for the heck of it. However, Kumar's recent rework of the device trees may force all P2020 boards to have the same CCSR, so you might be stuck. Today I updated U-Boot to top of tree to address the comments in the initial mailing list posting. Upon attempting to boot the board, I get no console output. I have traced this to commit 6ca88b0958 (powerpc/85xx: relocate CCSR before creating the initial RAM area). This patch requires that only the last stage of U-Boot (i.e. the real U-Boot) relocate CCSR. All previous stages must not relocate CCSR. This is a change from the way we were doing things in the past. Indeed, making sure that the code does not run by adding the following to my board config file causes U-Boot to start correctly. Though the CCSRBAR is not relocated, as expected. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE If you set this macro and your DTS puts CCSR at 0xffe0, then you won't be able to boot Linux (or any OS that uses the device tree). As an alternative, reverting the commit causes my board to work again. The CCSRBAR is relocated correctly. The new CCSR relocation method is needed to standardize the way we handle that task and to support future SOCs that require CCSR to be relocated earlier in the boot process. I admit that it can sneak up on people, like it did for you, but the new approach is necessary. In the end, it will make everything a lot easier. The P2020DS board is very similar to the board I am using. It performs the same relocation of the CCSRBAR that I want to use as well. Does anyone have a P2020DS that they can test with the current top of tree U-Boot? Does it boot? Can you send the output of md ffe0 1? Kumar recently posted a patch that fixes the relocation on multi-stage U-Boots (e.g. NAND booting, SPI booting, etc). I also posted a patchset last week that fixes a few problems with -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Is CCSRBAR relocation broken on P2020?
Ira W. Snyder wrote: On Thu, Nov 10, 2011 at 11:12:41AM -0600, Timur Tabi wrote: Ira W. Snyder wrote: Hello Timur, Kumar, U-Boot List, I'm working on porting U-Boot to the Freescale P2020 COM-Express board. See the ML post from 2011-09-27 titled [PATCH 0/2] mpc85xx: support for Freescale COM Express P2020. I see that you are using a NAND boot, which is a multi-stage boot. There are some problems with that that have been fixed in recent patches posted by me and Kumar to the U-boot mailing list. In particular, one patches puts U-boot into an infinite loop if CCSR is relocated in the wrong step. I don't use NAND, nor any multi-stage boot (as far as I know). I see NAND here: +P2020COME_NAND powerpc mpc85xx p2020come freescale - P2020COME:NAND I boot off of SDCARD (P2020COME_SDCARD_config). To write the U-Boot image to the microSD card, I use a tool provided with the BSP called boot_format-1.0.0. Maybe you are familiar with it? I think that qualifies as multi-stage booting. The SD card is not mapped at address fff0 at POR time, which is needed to boot a single-stage U-Boot. Therefore, you must have a multi-stage U-Boot. I'm not familiar with boot_format-1.0.0, but my guess is that it creates the pre-boot loader. When it was posted, the port was working on the top of tree U-Boot. This included relocation of the CCSRBAR from the power on location of 0xff70 to 0xffe0. Is there a reason why you want to relocate CCSR at all? Everything would be a lot easier if you just left it at the default location. I have a suspicion that many boards relocate CCSR just for the heck of it. However, Kumar's recent rework of the device trees may force all P2020 boards to have the same CCSR, so you might be stuck. I relocate the CCSR because my device tree requires it. I wanted to use the Linux arch/powerpc/boot/dts/p2020si.dtsi as a base, and override the few things that are specific to this board. It requires the CCSR be relocated to 0xffe0. CCSR relocation is required for a 36-bit build, but if you don't need to support that, then I recommend you avoid relocation. If your device tree isn't set in stone, now would be a great time to change it. I'll look at Kumar's DTS changes. I saw them on the Linux PPC ML. Kumar just posted a bunch more a few minutes ago. Today I updated U-Boot to top of tree to address the comments in the initial mailing list posting. Upon attempting to boot the board, I get no console output. I have traced this to commit 6ca88b0958 (powerpc/85xx: relocate CCSR before creating the initial RAM area). This patch requires that only the last stage of U-Boot (i.e. the real U-Boot) relocate CCSR. All previous stages must not relocate CCSR. This is a change from the way we were doing things in the past. I understand that. I only use one U-Boot. To the best of my knowledge, boot on this platform works like this: - power on - the P2020 looks for the magic BOOT written by the boot_format tool on the SD card You need to figure out what this boot utility does. It might create a 4GB TLB, or it might relocate CCSR. I have a fix for the 4GB TLB problem that was posted recently. If that boot relocates CCSR, then the boot_format tool needs to be fixed. - the P2020 executes the instructions written by boot_format to setup RAM correctly, load the U-Boot from the SD card to RAM, and then jumps to it - U-Boot runs, including relocating CCSR Well, THAT is a multi-stage boot. A single-stage boot is when the first instruction that the core executes on POR is in your u-boot.bin, and that u-boot.bin is the only version of U-Boot that is loaded. This is true only when booting from NOR flash. Only one U-Boot is ever executed. But it isn't the first code to be executed. That's what I'm talking about. I understand that. Has the current top of tree been tested on P2020DS? Well, I didn't test EVERY board, and I did find some problems with some boards that I fixed recently. If you add all the patches that Kumar and I posted, everything should work (assuming boot_format doesn't relocate CCSR). I'm looking for some assurance that the code I'm trying to use actually works on a !CONFIG_FSL_CORENET platform which relocates the CCSR. One in-tree example is the P2020DS. I tested my code on the P1022DS, which is similar. The P2020DS board is very similar to the board I am using. It performs the same relocation of the CCSRBAR that I want to use as well. Does anyone have a P2020DS that they can test with the current top of tree U-Boot? Does it boot? Can you send the output of md ffe0 1? Kumar recently posted a patch that fixes the relocation on multi-stage U-Boots (e.g. NAND booting, SPI booting, etc). I also posted a patchset last week that fixes a few problems with Can you tell me the subject lines of these patches? Even though I don't use
Re: [U-Boot] Is CCSRBAR relocation broken on P2020?
McClintock Matthew-B29882 wrote: Did you test your CCSRBAR changes with a board that uses the on chip rom as well as L2SRAM to boot? No, just the on-chip ROM. Kumar later noticed that NAND booting was broken, so I fixed that too. That's why I'm saying the latest set of patches should fix it for everyone. I didn't consider the combination of multi-stage with SRAM, but since normal U-Boot runs from SRAM first, I expect that to work as well. Does the COME board load from SDCARD to DDR or to L2SRAM? I suspect it's L2SRAM since this board has 512kB which is large enough for a stock u-boot image. Ira says that early boot loader sets of DDR, so I presume it's running from that, not SRAM. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Is CCSRBAR relocation broken on P2020?
Ira W. Snyder wrote: I boot using the on-chip ROM, loading U-Boot from SD card to DDR. The on-chip creates a 4GB TLB, which breaks the CCSR code. My five-patch patchset fixes this. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/85xx: clean up and document the QE/FMAN microcode macros
Several macros are used to identify and locate the microcode binary image
that U-boot needs to upload to the QE or Fman. Both the QE and the Fman
use the QE Firmware binary format to package their respective microcode data,
which is why the same macros are used for both. A given SOC will only have
a QE or an Fman, so this is safe.
Unfortunately, the current macro definition and usage has inconsistencies.
For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
of NAND. There's no way to know by looking at a variable how it's supposed
to be used.
In the future, the code which uploads QE firmware and Fman firmware will
be merged.
Signed-off-by: Timur Tabi ti...@freescale.com
---
README | 38 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 12 +-
arch/powerpc/cpu/mpc85xx/fdt.c |2 +-
drivers/net/fm/fm.c | 32 ++--
drivers/qe/qe.c |4 +-
include/configs/MPC8569MDS.h|3 +-
include/configs/P1023RDS.h | 10 +---
include/configs/P2041RDB.h | 13 +++
include/configs/corenet_ds.h| 16 +-
include/configs/p1_p2_rdb_pc.h |5 ++-
10 files changed, 92 insertions(+), 43 deletions(-)
diff --git a/README b/README
index c05c40a..33cd678 100644
--- a/README
+++ b/README
@@ -3263,6 +3263,44 @@ Low Level (hardware related) configuration options:
be used if available. These functions may be faster under some
conditions but may increase the binary size.
+Freescale QE/FMAN Firmware Support:
+---
+
+The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the
+loading of firmware, which is encoded in the QE firmware binary format.
+This firmware often needs to be loaded during U-Boot booting, so macros
+are used to identify the storage device (NOR flash, SPI, etc) and the address
+within that device.
+
+- CONFIG_SYS_QE_FMAN_FW_ADDR
+ The address in the storage device where the firmware is located. The
+ meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+ is also specified.
+
+- CONFIG_SYS_QE_FMAN_FW_LENGTH
+ The maximum possible size of the firmware. The firmware binary format
+ has a field that specifies the actual size of the firmware, but it
+ might not be possible to read any part of the firmware unless some
+ local storage is allocated to hold the entire firmware first.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_NOR
+ Specifies that QE/FMAN firmware is located in NOR flash, mapped as
+ normal addressable memory via the LBC. CONFIG_SYS_FMAN_FW_ADDR is the
+ virtual address in NOR flash.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_NAND
+ Specifies that QE/FMAN firmware is located in NAND flash.
+ CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_MMC
+ Specifies that QE/FMAN firmware is located on the primary SD/MMC
+ device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
+- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
+ Specifies that QE/FMAN firmware is located on the primary SPI
+ device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
+
Building the Software:
==
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 0a4ce53..5e42955 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -38,7 +38,7 @@
#include asm/fsl_law.h
#include asm/fsl_serdes.h
#include mp.h
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include nand.h
#include errno.h
#endif
@@ -524,17 +524,17 @@ void cpu_secondary_init_r(void)
{
#ifdef CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
int ret;
- size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
+ size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
/* load QE firmware from NAND flash to DDR first */
- ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
- fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+ ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
+ fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
if (ret ret == -EUCLEAN) {
printf (NAND read for QE firmware at offset %x failed %d\n,
- CONFIG_SYS_QE_FW_IN_NAND, ret);
+ CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
}
#endif
qe_init(qe_base);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 9d31568..435bd1a 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
Re: [U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support
Kim Phillips wrote: 4. no need to clear BATs before writing them either. FYI, take a look at Becky's BAT patch from a month ago: http://patchwork.ozlabs.org/patch/117523/ The patch is for 86xx, so I have no idea if it's relevant to this discussion. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] e1000: remove duplicate macros in e1000.h
Some of the EEPROM Word Offset macros, and a few others, are defined
twice in e1000.h.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/e1000.h | 11 ---
1 files changed, 0 insertions(+), 11 deletions(-)
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index d8400d4..fd1d8f8 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -1678,14 +1678,6 @@ struct e1000_hw {
#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
-/* EEPROM Word Offsets */
-#define EEPROM_COMPAT 0x0003
-#define EEPROM_ID_LED_SETTINGS0x0004
-#define EEPROM_INIT_CONTROL1_REG 0x000A
-#define EEPROM_INIT_CONTROL2_REG 0x000F
-#define EEPROM_FLASH_VERSION 0x0032
-#define EEPROM_CHECKSUM_REG 0x003F
-
/* Word definitions for ID LED Settings */
#define ID_LED_RESERVED_ 0x
#define ID_LED_RESERVED_ 0x
@@ -2479,7 +2471,6 @@ struct e1000_hw {
#define ADVERTISE_100_FULL 0x0008
#define ADVERTISE_1000_HALF0x0010
#define ADVERTISE_1000_FULL0x0020
-#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
#define ICH_FLASH_GFPREG 0x
#define ICH_FLASH_HSFSTS 0x0004
@@ -2504,7 +2495,6 @@ struct e1000_hw {
#define ICH_GFPREG_BASE_MASK 0x1FFF
#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FF
-#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
/* SPI EEPROM Status Register */
@@ -2599,7 +2589,6 @@ struct e1000_hw {
#define PHY_CFG_TIMEOUT 100
#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x0009
#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x0008
-#define E1000_TXDMAC_DPP 0x0001
#define AUTO_ALL_MODES 0
#ifndef E1000_MASTER_SLAVE
--
1.7.3.4
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[U-Boot] [PATCH 1/5] powerpc/85xx: fix definition of MAS register macros
Some of the MAS register macros do not protect the parameter with parentheses, which could cause wrong values if the parameter includes operators. Also fix the definition of TSIZE_TO_BYTES() so that it actually uses the parameter. This hasn't caused any problems to date because the parameter was always been 'tsize'. Signed-off-by: Timur Tabi ti...@freescale.com --- arch/powerpc/include/asm/mmu.h | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index ef5076b..209103e 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -392,17 +392,17 @@ extern void print_bats(void); */ #define MAS0_TLBSEL_MSK0x3000 -#define MAS0_TLBSEL(x) ((x 28) MAS0_TLBSEL_MSK) +#define MAS0_TLBSEL(x) (((x) 28) MAS0_TLBSEL_MSK) #define MAS0_ESEL_MSK 0x0FFF -#define MAS0_ESEL(x) ((x 16) MAS0_ESEL_MSK) +#define MAS0_ESEL(x) (((x) 16) MAS0_ESEL_MSK) #define MAS0_NV(x) ((x) 0x0FFF) #define MAS1_VALID 0x8000 #define MAS1_IPROT 0x4000 -#define MAS1_TID(x)((x 16) 0x3FFF) +#define MAS1_TID(x)(((x) 16) 0x3FFF) #define MAS1_TS0x1000 -#define MAS1_TSIZE(x) ((x 8) 0x0F00) -#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL ((tsize * 2) + 10))) +#define MAS1_TSIZE(x) (((x) 8) 0x0F00) +#define TSIZE_TO_BYTES(x) (1ULL (((x) * 2) + 10)) #define MAS2_EPN 0xF000 #define MAS2_X00x0040 -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] powerpc/85xx: add some missing sync instructions in the CCSR relocation code
Calls to tlbwe and tlbsx should be preceded with an isync/msync pair. Signed-off-by: Timur Tabi ti...@freescale.com --- arch/powerpc/cpu/mpc85xx/start.S |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index b5bf1fa..ccb331a 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -363,6 +363,8 @@ purge_old_ccsr_tlb: li r1, 0 mtspr MAS6, r1/* Search the current address space and PID */ + isync + msync tlbsx 0, r8 mfspr r1, MAS1 andis. r2, r1, MAS1_VALID@h/* Check for the Valid bit */ @@ -370,6 +372,8 @@ purge_old_ccsr_tlb: rlwinm r1, r1, 0, 1, 31/* Clear Valid bit */ mtspr MAS1, r1 + isync + msync tlbwe 1: -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5] powerpc/85xx: resize the boot page TLB before relocating CCSR
On some Freescale systems (e.g. those booted from the on-chip ROM), the TLB that covers the boot page can also cover CCSR, which breaks the CCSR relocation code. To fix this, we resize the boot page TLB so that it only covers the 4KB boot page. Signed-off-by: Timur Tabi ti...@freescale.com --- arch/powerpc/cpu/mpc85xx/start.S | 49 ++ 1 files changed, 49 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 6de8765..39f1438 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -330,6 +330,55 @@ l2_disabled: #endif /* CONFIG_MPC8569 */ /* + * Search for the TLB that covers the code we're executing, and shrink it + * so that it covers only this 4K page. That will ensure that any other + * TLB we create won't interfere with it. We assume that the TLB exists, + * which is why we don't check the Valid bit of MAS1. + * + * This is necessary, for example, when booting from the on-chip ROM, + * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. + * If we don't shrink this TLB now, then we'll accidentally delete it + * in purge_old_ccsr_tlb below. + */ + bl nexti /* Find our address */ +nexti: mflrr1 /* R1 = our PC */ + li r2, 0 + mtspr MAS6, r2/* Assume the current PID and AS are 0 */ + isync + msync + tlbsx 0, r1 /* This must succeed */ + + /* Set the size of the TLB to 4KB */ + mfspr r3, MAS1 + li r2, 0xF00 + andcr3, r3, r2 /* Clear the TSIZE bits */ + ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l + mtspr MAS1, r3 + + /* +* Set the base address of the TLB to our PC. We assume that +* virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. +*/ + lis r3, MAS2_EPN@h + ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ + + and r1, r1, r3 /* Our PC, rounded down to the nearest page */ + + mfspr r2, MAS2 + andcr2, r2, r3 + or r2, r2, r1 + mtspr MAS2, r2/* Set the EPN to our PC base address */ + + mfspr r2, MAS3 + andcr2, r2, r3 + or r2, r2, r1 + mtspr MAS3, r2/* Set the RPN to our PC base address */ + + isync + msync + tlbwe + +/* * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default * location is not where we want it. This typically happens on a 36-bit * system, where we want to move CCSR to near the top of 36-bit address space. -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/5] powerpc/85xx: verify the current address of CCSR before relocating it
Verify that CCSR is actually located where it is supposed to be before we relocate it. This is useful in detecting U-Boot configurations that are broken (e.g. an incorrect value for CONFIG_SYS_CCSRBAR_DEFAULT). If the current value is wrong, we enter an infinite loop, which is handy for debuggers. Signed-off-by: Timur Tabi ti...@freescale.com --- arch/powerpc/cpu/mpc85xx/start.S | 27 +++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index ccb331a..6de8765 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -422,6 +422,33 @@ create_ccsr_old_tlb: msync tlbwe + /* +* We have a TLB for what we think is the current (old) CCSR. Let's +* verify that, otherwise we won't be able to move it. +* CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only +* need to compare the lower 32 bits of CCSRBAR on CoreNet systems. +*/ +verify_old_ccsr: + lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h + ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l +#ifdef CONFIG_FSL_CORENET + lwz r1, 4(r9) /* CCSRBARL */ +#else + lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ + slwir1, r1, 12 +#endif + + cmpl0, r0, r1 + + /* +* If the value we read from CCSRBARL is not what we expect, then +* enter an infinite loop. This will at least allow a debugger to +* halt execution and examine TLBs, etc. There's no point in going +* on. +*/ +infinite_debug_loop: + bne infinite_debug_loop + #ifdef CONFIG_FSL_CORENET #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/5] powerpc/85xx: fix some comments in the CCSR relocation code
Signed-off-by: Timur Tabi ti...@freescale.com --- arch/powerpc/cpu/mpc85xx/start.S |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 528abc9..b5bf1fa 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -398,7 +398,7 @@ create_ccsr_new_tlb: tlbwe /* -* Create a TLB for the old location of CCSR. Register R9 is reserved +* Create a TLB for the current location of CCSR. Register R9 is reserved * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). */ create_ccsr_old_tlb: @@ -457,7 +457,7 @@ create_temp_law: */ read_old_ccsrbar: lwz r0, 0(r9) /* CCSRBARH */ - lwz r0, 4(r9) /* CCSRBARH */ + lwz r0, 4(r9) /* CCSRBARL */ isync /* -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [GIT PULL] Pull request u-boot-85xx.git
Kumar Gala wrote: Need Wolfgang's Ack on that. Why? It just fixes a bug in our board code. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [GIT PULL] Pull request u-boot-85xx.git
Kumar Gala wrote: But it touches common/cmd_mac.c I've never understand why that file is in common/, since it applies only to Freescale SOCs. There's only one implementation of do_mac, and it's ours. I could have sworn York posted a patch to move do_mac into sys_eeprom.c. I don't see it anywhere, though. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3
The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the
P3060 and should always be set to zero.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/p3060_serdes.c | 20
arch/powerpc/include/asm/immap_85xx.h | 10 --
drivers/net/fm/p3060.c | 17 -
3 files changed, 0 insertions(+), 47 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/p3060_serdes.c
b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c
index 6387276..e720dcf 100644
--- a/arch/powerpc/cpu/mpc85xx/p3060_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c
@@ -83,8 +83,6 @@ void soc_serdes_init(void)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(gur-devdisr2);
u32 rcwsr11 = in_be32(gur-rcwsr[11]);
- u32 rcwsr13 = in_be32(gur-rcwsr[13]);
- u32 ec1_ext, ec2_ext;
/* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */
@@ -116,23 +114,5 @@ void soc_serdes_init(void)
devdisr2 = ~FSL_CORENET_DEVDISR2_DTSEC2_1;
}
- ec1_ext = rcwsr13 FSL_CORENET_RCWSR13_EC1_EXT;
- if (ec1_ext) {
- if ((ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII) ||
- (ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII))
- devdisr2 = ~FSL_CORENET_DEVDISR2_DTSEC1_4;
- }
-
- ec2_ext = rcwsr13 FSL_CORENET_RCWSR13_EC2_EXT;
- if (ec2_ext) {
- if ((ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII) ||
- (ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII))
- devdisr2 = ~FSL_CORENET_DEVDISR2_DTSEC2_4;
- }
-
- if ((rcwsr13 FSL_CORENET_RCWSR13_EC3) ==
- FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII)
- devdisr2 = ~FSL_CORENET_DEVDISR2_DTSEC2_4;
-
out_be32(gur-devdisr2, devdisr2);
}
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index a29fe35..1bbf986 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1708,16 +1708,6 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x0008
#define FSL_CORENET_RCWSR11_EC2_USB2 0x0010
#endif
-#if defined(CONFIG_PPC_P3060)
-#define FSL_CORENET_RCWSR13_EC1_EXT0x1c00
-#define FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII 0x0400
-#define FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII 0x0800
-#define FSL_CORENET_RCWSR13_EC2_EXT0x01c0
-#define FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII 0x0040
-#define FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII 0x0080
-#define FSL_CORENET_RCWSR13_EC30x0038
-#define FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII 0x0010
-#endif
#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \
|| defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x
diff --git a/drivers/net/fm/p3060.c b/drivers/net/fm/p3060.c
index b25bca7..176e1d2 100644
--- a/drivers/net/fm/p3060.c
+++ b/drivers/net/fm/p3060.c
@@ -52,7 +52,6 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(gur-rcwsr[11]);
- u32 rcwsr13 = in_be32(gur-rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
@@ -70,22 +69,6 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
return PHY_INTERFACE_MODE_RGMII;
- if ((port == FM1_DTSEC4) ((rcwsr13 FSL_CORENET_RCWSR13_EC1_EXT) ==
- FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII))
- return PHY_INTERFACE_MODE_RGMII;
-
- if ((port == FM1_DTSEC4) ((rcwsr13 FSL_CORENET_RCWSR13_EC1_EXT) ==
- FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII))
- return PHY_INTERFACE_MODE_MII;
-
- if ((port == FM2_DTSEC4) ((rcwsr13 FSL_CORENET_RCWSR13_EC2_EXT) ==
- FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII))
- return PHY_INTERFACE_MODE_RGMII;
-
- if ((port == FM2_DTSEC4) ((rcwsr13 FSL_CORENET_RCWSR13_EC2_EXT) ==
- FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII))
- return PHY_INTERFACE_MODE_MII;
-
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
--
1.7.3.4
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Re: [U-Boot] [PATCH V2 05/13] i2c: Create common default i2c_set_bus_num() function
Mike Frysinger wrote: i think that'd require a much larger rework of the framework and thus would be better to do in addition to Stefano's work rather than in place of ? Hmmm... I guess it would be easier to do the rework eventually if i2c_set_bus_num() is universal, instead of just for PowerPC. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] [v2] powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes
displays which of these is actually built, but it's inconsistent. This is
especially problematic since the default build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used. Not only that, but each board includes code that displays
the message, so there is duplication.
So instead of displaying this message at boot time, the address map size
information is moved into the 'bdinfo' command. The board-specific code is
deleted.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/corenet_ds/corenet_ds.c |4
board/freescale/mpc8536ds/mpc8536ds.c |7 +--
board/freescale/mpc8572ds/mpc8572ds.c |6 +-
board/freescale/p1010rdb/p1010rdb.c |6 +-
board/freescale/p1022ds/p1022ds.c |8 ++--
board/freescale/p1_p2_rdb/p1_p2_rdb.c |4 +---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c |8 +---
board/freescale/p2020ds/p2020ds.c |8 ++--
board/freescale/p2041rdb/p2041rdb.c |4
common/cmd_bdinfo.c |8
10 files changed, 17 insertions(+), 46 deletions(-)
diff --git a/board/freescale/corenet_ds/corenet_ds.c
b/board/freescale/corenet_ds/corenet_ds.c
index b1eecc4..a33c936 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -62,10 +62,6 @@ int checkboard (void)
else
printf(invalid setting of SW%u\n, PIXIS_LBMAP_SWITCH);
-#ifdef CONFIG_PHYS_64BIT
- puts(36-bit Addressing\n);
-#endif
-
/* Display the RCW, so that no one gets confused as to what RCW
* we're actually using for this boot.
*/
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c
b/board/freescale/mpc8536ds/mpc8536ds.c
index c9f85c8..6d0bfde 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -68,12 +68,7 @@ int checkboard (void)
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
- puts(Board: MPC8536DS );
-#ifdef CONFIG_PHYS_64BIT
- puts((36-bit addrmap) );
-#endif
-
- printf (Sys ID: 0x%02x,
+ printf(Board: MPC8536DS Sys ID: 0x%02x,
Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ,
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c
b/board/freescale/mpc8572ds/mpc8572ds.c
index b20299e..33a02ba 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -45,11 +45,7 @@ int checkboard (void)
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
- puts (Board: MPC8572DS );
-#ifdef CONFIG_PHYS_64BIT
- puts ((36-bit addrmap) );
-#endif
- printf (Sys ID: 0x%02x,
+ printf(Board: MPC8572DS Sys ID: 0x%02x,
Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ,
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
diff --git a/board/freescale/p1010rdb/p1010rdb.c
b/board/freescale/p1010rdb/p1010rdb.c
index 03e9da1..7aa2117 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -165,11 +165,7 @@ int checkboard(void)
struct cpu_type *cpu;
cpu = gd-cpu;
- printf(Board: %sRDB , cpu-name);
-#ifdef CONFIG_PHYS_64BIT
- puts((36-bit addrmap));
-#endif
- puts(\n);
+ printf(Board: %sRDB\n, cpu-name);
return 0;
}
diff --git a/board/freescale/p1022ds/p1022ds.c
b/board/freescale/p1022ds/p1022ds.c
index 456d9b0..aca30f3 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -56,12 +56,8 @@ int checkboard(void)
{
u8 sw;
- puts(Board: P1022DS );
-#ifdef CONFIG_PHYS_64BIT
- puts((36-bit addrmap) );
-#endif
-
- printf(Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ,
+ printf(Board: P1022DS Sys ID: 0x%02x,
+ Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ,
in_8(pixis-id), in_8(pixis-arch), in_8(pixis-scver));
sw = in_8(PIXIS_SW(PIXIS_LBMAP_SWITCH));
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 864b3ce..6418710 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -110,9 +110,7 @@ int checkboard (void)
cpu = gd-cpu;
printf (Board: %sRDB Rev%c\n, cpu-name, board_rev);
-#ifdef CONFIG_PHYS_64BIT
- puts ((36-bit addrmap) \n);
-#endif
+
setbits_be32(pgpio-gpdir, GPIO_DIR);
/*
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 4671128..abe087b 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
[U-Boot] [PATCH 2/3] [v2] phylib: wait for TN2020 to achieve SERDES lane alignment at startup
Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be
aligned, so wait for lane alignment before completing the startup sequence.
Note that this process can take up to three seconds.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/phy/teranetics.c | 33 +
1 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c
index a13b48c..9d9397a 100644
--- a/drivers/net/phy/teranetics.c
+++ b/drivers/net/phy/teranetics.c
@@ -21,6 +21,7 @@
*
*/
#include config.h
+#include common.h
#include phy.h
#ifndef CONFIG_PHYLIB_10G
@@ -43,6 +44,38 @@ int tn2020_config(struct phy_device *phydev)
int tn2020_startup(struct phy_device *phydev)
{
+ unsigned int timeout = 5 * 1000; /* 5 second timeout */
+
+#define MDIO_PHYXS_LANE_READY (MDIO_PHYXS_LNSTAT_SYNC0 | \
+ MDIO_PHYXS_LNSTAT_SYNC1 | \
+ MDIO_PHYXS_LNSTAT_SYNC2 | \
+ MDIO_PHYXS_LNSTAT_SYNC3 | \
+ MDIO_PHYXS_LNSTAT_ALIGN)
+
+ /*
+* Wait for the XAUI-SERDES lanes to align first. Under normal
+* circumstances, this can take up to three seconds.
+*/
+ while (--timeout) {
+ int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT);
+ if (reg 0) {
+ printf(TN2020: Error reading from PHY at
+ address %u\n, phydev-addr);
+ break;
+ }
+ if ((reg MDIO_PHYXS_LANE_READY) == MDIO_PHYXS_LANE_READY)
+ break;
+ udelay(1000);
+ }
+ if (!timeout) {
+ /*
+* A timeout is bad, but it may not be fatal, so don't
+* return an error. Display a warning instead.
+*/
+ printf(TN2020: Timeout waiting for PHY at address %u to
+ align.\n, phydev-addr);
+ }
+
if (phydev-port != PORT_FIBRE)
return gen10g_startup(phydev);
--
1.7.3.4
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[U-Boot] [PATCH 3/3] [v2] powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes
should be reset after the XAUI starts tranmitting alignment signals.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 10 --
board/freescale/corenet_ds/eth_p4080.c| 42 -
drivers/net/phy/teranetics.h |1 +
3 files changed, 35 insertions(+), 18 deletions(-)
create mode 100644 drivers/net/phy/teranetics.h
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 07e58ed..89ed5b4 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -504,9 +504,6 @@ void fsl_serdes_init(void)
const char *srds_lpd_arg;
size_t arglen;
#endif
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
- enum srds_prtcl device;
-#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */
#endif
@@ -787,11 +784,4 @@ void fsl_serdes_init(void)
SRDS_RSTCTL_SDPD);
}
#endif
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
- for (device = XAUI_FM1; device = XAUI_FM2; device++) {
- if (is_serdes_configured(device))
- __serdes_reset_rx(srds_regs, cfg, device);
- }
-#endif
}
diff --git a/board/freescale/corenet_ds/eth_p4080.c
b/board/freescale/corenet_ds/eth_p4080.c
index d4657f7..1c22a4d 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -42,6 +42,10 @@
#include ../common/fman.h
#include asm/fsl_dtsec.h
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) defined(CONFIG_PHY_TERANETICS)
+#include ../../../drivers/net/phy/teranetics.h /* for tn2020_driver.uid */
+#endif
+
#define EMI_NONE 0x
#define EMI_MASK 0xf000
#define EMI1_RGMII 0x0
@@ -93,21 +97,43 @@ struct mii_dev *mii_dev_for_muxval(u32 muxval)
return bus;
}
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) defined(CONFIG_PHY_TERANETICS)
int board_phy_config(struct phy_device *phydev)
{
- /*
-* If this is the 10G PHY, and we switched it to fiber,
-* we need to reset the serdes link for SERDES9
-*/
- if ((phydev-port == PORT_FIBRE) (phydev-drv-uid == 0x00a19410)) {
+ if (phydev-drv-uid == tn2020_driver.uid) {
+ unsigned long timeout = 1 * 1000; /* 1 seconds */
enum srds_prtcl device;
+ /*
+* Wait for the XAUI to come out of reset. This is when it
+* starts transmitting alignment signals.
+*/
+ while (--timeout) {
+ int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
+ if (reg 0) {
+ printf(TN2020: Error reading from PHY at
+ address %u\n, phydev-addr);
+ break;
+ }
+ /*
+* Note that we've never actually seen
+* MDIO_CTRL1_RESET set to 1.
+*/
+ if ((reg MDIO_CTRL1_RESET) == 0)
+ break;
+ udelay(1000);
+ }
+
+ if (!timeout) {
+ printf(TN2020: Timeout waiting for PHY at address %u
+ to reset.\n, phydev-addr);
+ }
+
switch (phydev-addr) {
- case 4:
+ case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
device = XAUI_FM1;
break;
- case 0:
+ case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
device = XAUI_FM2;
break;
default:
diff --git a/drivers/net/phy/teranetics.h b/drivers/net/phy/teranetics.h
new file mode 100644
index 000..1d983de
--- /dev/null
+++ b/drivers/net/phy/teranetics.h
@@ -0,0 +1 @@
+extern struct phy_driver tn2020_driver;
--
1.7.3.4
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Re: [U-Boot] [PATCH 3/3] powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
Wolfgang Denk wrote: WARNING: externs should be avoided in .c files #114: FILE: board/freescale/corenet_ds/eth_p4080.c:100: + extern struct phy_driver tn2020_driver; This is intentional. There's no header file for the teranetics driver, and referencing the structure allows me to avoid a hard-coded number. Are you suggesting that I create a header file just to contain this line: extern struct phy_driver tn2020_driver; because that seems silly. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] powerpc/85xx: Fix the work-arounds for errata SERDES-8 SERDES-A001 on p4080
Wolfgang Denk wrote: WARNING: line over 80 characters #127: FILE: arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:43: +#error CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8 Lines like these would be accepted into the Linux kernel. Are the standards for U-boot stricter than for Linux? It appears that you are requiring exact conformance to checkpatch, even when it complains about something that isn't really that bad. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] phylib: Work around bug in Teranetics PHY
From: Andy Fleming aflem...@freescale.com
The Teranetics PHY does not properly report the link state
for fiber connections. The new PHY code actually checked the link,
and so the FM driver would refuse to talk over a linkless PHY.
But the link may actually be up, so now we always report it as up
for fiber connections on the tn2020.
Signed-off-by: Andy Fleming aflem...@freescale.com
---
drivers/net/phy/teranetics.c | 23 +--
1 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c
index a771791..5932bf0 100644
--- a/drivers/net/phy/teranetics.c
+++ b/drivers/net/phy/teranetics.c
@@ -20,7 +20,7 @@
* author Andy Fleming
*
*/
-#include config.h
+#include common.h
#include phy.h
#ifndef CONFIG_PHYLIB_10G
@@ -41,6 +41,25 @@ int tn2020_config(struct phy_device *phydev)
return 0;
}
+int tn2020_startup(struct phy_device *phydev)
+{
+ if (phydev-port != PORT_FIBRE)
+ return gen10g_startup(phydev);
+
+ /*
+* The TN2020 only pretends to support fiber.
+* It works, but it doesn't look like it works,
+* so the link status reports no link.
+*/
+ phydev-link = 1;
+
+ /* For now just lie and say it's 10G all the time */
+ phydev-speed = SPEED_1;
+ phydev-duplex = DUPLEX_FULL;
+
+ return 0;
+}
+
struct phy_driver tn2020_driver = {
.name = Teranetics TN2020,
.uid = 0x00a19410,
@@ -50,7 +69,7 @@ struct phy_driver tn2020_driver = {
MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
.config = tn2020_config,
- .startup = gen10g_startup,
+ .startup = tn2020_startup,
.shutdown = gen10g_shutdown,
};
--
1.7.3.4
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[U-Boot] [PATCH 3/3] powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes
should be reset after the XAUI starts tranmitting alignment signals.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 10 --
board/freescale/corenet_ds/eth_p4080.c| 40
2 files changed, 33 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 07e58ed..89ed5b4 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -504,9 +504,6 @@ void fsl_serdes_init(void)
const char *srds_lpd_arg;
size_t arglen;
#endif
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
- enum srds_prtcl device;
-#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */
#endif
@@ -787,11 +784,4 @@ void fsl_serdes_init(void)
SRDS_RSTCTL_SDPD);
}
#endif
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
- for (device = XAUI_FM1; device = XAUI_FM2; device++) {
- if (is_serdes_configured(device))
- __serdes_reset_rx(srds_regs, cfg, device);
- }
-#endif
}
diff --git a/board/freescale/corenet_ds/eth_p4080.c
b/board/freescale/corenet_ds/eth_p4080.c
index d4657f7..a724ffc 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -96,18 +96,43 @@ struct mii_dev *mii_dev_for_muxval(u32 muxval)
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
int board_phy_config(struct phy_device *phydev)
{
- /*
-* If this is the 10G PHY, and we switched it to fiber,
-* we need to reset the serdes link for SERDES9
-*/
- if ((phydev-port == PORT_FIBRE) (phydev-drv-uid == 0x00a19410)) {
+#ifdef CONFIG_PHY_TERANETICS
+ extern struct phy_driver tn2020_driver;
+
+ if (phydev-drv-uid == tn2020_driver.uid) {
+ unsigned long timeout = 1 * 1000; /* 1 seconds */
enum srds_prtcl device;
+ /*
+* Wait for the XAUI to come out of reset. This is when it
+* starts transmitting alignment signals.
+*/
+ while (--timeout) {
+ int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
+ if (reg 0) {
+ printf(TN2020: Error reading from PHY at
+ address %u\n, phydev-addr);
+ break;
+ }
+ /*
+* Note that we've never actually seen
+* MDIO_CTRL1_RESET set to 1.
+*/
+ if ((reg MDIO_CTRL1_RESET) == 0)
+ break;
+ udelay(1000);
+ }
+
+ if (!timeout) {
+ printf(TN2020: Timeout waiting for PHY at address %u
+ to reset.\n, phydev-addr);
+ }
+
switch (phydev-addr) {
- case 4:
+ case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
device = XAUI_FM1;
break;
- case 0:
+ case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
device = XAUI_FM2;
break;
default:
@@ -116,6 +141,7 @@ int board_phy_config(struct phy_device *phydev)
serdes_reset_rx(device);
}
+#endif
return 0;
}
--
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[U-Boot] [PATCH 2/3] phylib: wait for TN2020 to achieve SERDES lane alignment at startup
Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be
aligned, so wait for lane alignment before completing the startup sequence.
Note that this process can take up to three seconds.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/phy/teranetics.c | 32
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c
index 5932bf0..97fe5f4 100644
--- a/drivers/net/phy/teranetics.c
+++ b/drivers/net/phy/teranetics.c
@@ -43,6 +43,38 @@ int tn2020_config(struct phy_device *phydev)
int tn2020_startup(struct phy_device *phydev)
{
+ unsigned int timeout = 5 * 1000; /* 5 second timeout */
+
+#define MDIO_PHYXS_LANE_READY (MDIO_PHYXS_LNSTAT_SYNC0 | \
+ MDIO_PHYXS_LNSTAT_SYNC1 | \
+ MDIO_PHYXS_LNSTAT_SYNC2 | \
+ MDIO_PHYXS_LNSTAT_SYNC3 | \
+ MDIO_PHYXS_LNSTAT_ALIGN)
+
+ /*
+* Wait for the XAUI-SERDES lanes to align first. Under normal
+* circumstances, this can take up to three seconds.
+*/
+ while (--timeout) {
+ int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT);
+ if (reg 0) {
+ printf(TN2020: Error reading from PHY at
+ address %u\n, phydev-addr);
+ break;
+ }
+ if ((reg MDIO_PHYXS_LANE_READY) == MDIO_PHYXS_LANE_READY)
+ break;
+ udelay(1000);
+ }
+ if (!timeout) {
+ /*
+* A timeout is bad, but it may not be fatal, so don't
+* return an error. Display a warning instead.
+*/
+ printf(TN2020: Timeout waiting for PHY at address %u to
+ align.\n, phydev-addr);
+ }
+
if (phydev-port != PORT_FIBRE)
return gen10g_startup(phydev);
--
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[U-Boot] [PATCH] cmd_bdinfo: replace print_str() with print_mhz()
The print_str() helper function for cmd_bdinfo can print any string, but it
is only used to print MHz values. Replace it with print_mhz() that takes
a number and converts it to a string internally.
Signed-off-by: Timur Tabi ti...@freescale.com
---
This patch applies on top of powerpc/85xx: don't display address map size
(32-bit vs. 36-bit) during boot.
I've only tested this on PowerPC.
common/cmd_bdinfo.c | 72 --
1 files changed, 35 insertions(+), 37 deletions(-)
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 12863f2..3f7f6e6 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -40,12 +40,11 @@ static void print_lnum(const char *, u64);
#endif
#if defined(CONFIG_PPC)
-static void print_str(const char *, const char *);
+static void print_mhz(const char *, unsigned long);
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd-bd;
- char buf[32];
#ifdef DEBUG
print_num(bd address, (ulong)bd);
@@ -68,32 +67,32 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_XILINX_405)
- print_str(procfreq, strmhz(buf, bd-bi_procfreq));
- print_str(plb_busfreq,strmhz(buf, bd-bi_plb_busfreq));
+ print_mhz(procfreq, bd-bi_procfreq);
+ print_mhz(plb_busfreq,bd-bi_plb_busfreq);
#ifdefined(CONFIG_405EP) || defined(CONFIG_405GP) || \
defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SPE) || defined(CONFIG_XILINX_405)
- print_str(pci_busfreq,strmhz(buf, bd-bi_pci_busfreq));
+ print_mhz(pci_busfreq,bd-bi_pci_busfreq);
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405,
CONFIG_440EP CONFIG_440GR */
#if defined(CONFIG_CPM2)
- print_str(vco,strmhz(buf, bd-bi_vco));
- print_str(sccfreq,strmhz(buf, bd-bi_sccfreq));
- print_str(brgfreq,strmhz(buf, bd-bi_brgfreq));
+ print_mhz(vco,bd-bi_vco);
+ print_mhz(sccfreq,bd-bi_sccfreq);
+ print_mhz(brgfreq,bd-bi_brgfreq);
#endif
- print_str(intfreq,strmhz(buf, bd-bi_intfreq));
+ print_mhz(intfreq,bd-bi_intfreq);
#if defined(CONFIG_CPM2)
- print_str(cpmfreq,strmhz(buf, bd-bi_cpmfreq));
+ print_mhz(cpmfreq,bd-bi_cpmfreq);
#endif
- print_str(busfreq,strmhz(buf, bd-bi_busfreq));
+ print_mhz(busfreq,bd-bi_busfreq);
#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405,
CONFIG_440EP CONFIG_440GR */
#if defined(CONFIG_MPC8220)
- print_str(inpfreq,strmhz(buf, bd-bi_inpfreq));
- print_str(flbfreq,strmhz(buf, bd-bi_flbfreq));
- print_str(pcifreq,strmhz(buf, bd-bi_pcifreq));
- print_str(vcofreq,strmhz(buf, bd-bi_vcofreq));
- print_str(pevfreq,strmhz(buf, bd-bi_pevfreq));
+ print_mhz(inpfreq,bd-bi_inpfreq);
+ print_mhz(flbfreq,bd-bi_flbfreq);
+ print_mhz(pcifreq,bd-bi_pcifreq);
+ print_mhz(vcofreq,bd-bi_vcofreq);
+ print_mhz(pevfreq,bd-bi_pevfreq);
#endif
#ifdef CONFIG_ENABLE_36BIT_PHYS
@@ -122,7 +121,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
#endif
#ifdef CONFIG_HERMES
- print_str(ethspeed, strmhz(buf, bd-bi_ethspeed));
+ print_mhz(ethspeed, bd-bi_ethspeed);
#endif
printf(IP addr = %pI4\n, bd-bi_ip_addr);
printf(baudrate= %6ld bps\n, bd-bi_baudrate);
@@ -214,12 +213,11 @@ int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char
* const argv[])
#elif defined(CONFIG_M68K)
-static void print_str(const char *, const char *);
+static void print_mhz(const char *, unsigned long);
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd-bd;
- char buf[32];
print_num(memstart, (ulong)bd-bi_memstart);
print_lnum(memsize, (u64)bd-bi_memsize);
@@ -233,15 +231,15 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char
* const argv[])
#if defined(CONFIG_SYS_MBAR)
print_num(mbar, bd-bi_mbar_base);
#endif
- print_str(cpufreq,strmhz(buf, bd-bi_intfreq));
- print_str(busfreq,strmhz(buf, bd-bi_busfreq));
+ print_mhz(cpufreq,bd-bi_intfreq);
+ print_mhz(busfreq,bd-bi_busfreq);
#ifdef CONFIG_PCI
- print_str(pcifreq,strmhz(buf, bd-bi_pcifreq));
+ print_mhz
[U-Boot] [PATCH] powerpc/85xx: fix null pointer dereference when initializing the SGMII TBI PHY
Function dtsec_configure_serdes() needs to know where the TBI PHY registers
are in order to configure SGMII for proper SerDes operation.
During SGMII initialzation, fm_eth_init_mac() passing NULL for 'phyregs' when
it called init_dtsec(), because it was believed that phyregs was not used.
In fact, it is used by dtsec_configure_serdes() to configure the TBI PHY
registers.
We also need to define the PHY registers in struct fm_mdio.
Signed-off-by: Timur Tabi ti...@freescale.com
---
Note: I'm not sure of my change to struct fm_mdio. It works, but it doesn't
smell right.
arch/powerpc/include/asm/fsl_fman.h |9 -
drivers/net/fm/dtsec.c |2 +-
drivers/net/fm/eth.c|3 ++-
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_fman.h
b/arch/powerpc/include/asm/fsl_fman.h
index fddc0cc..2c0c9bc 100644
--- a/arch/powerpc/include/asm/fsl_fman.h
+++ b/arch/powerpc/include/asm/fsl_fman.h
@@ -405,7 +405,14 @@ typedef struct fm_dtesc {
} fm_dtsec_t;
typedef struct fm_mdio {
- u8 res[4*1024];
+ u8 res0[0x120];
+ u32 miimcfg;/* MII management configuration reg */
+ u32 miimcom;/* MII management command reg */
+ u32 miimadd;/* MII management address reg */
+ u32 miimcon;/* MII management control reg */
+ u32 miimstat; /* MII management status reg */
+ u32 miimind;/* MII management indication reg */
+ u8 res1[0x1000 - 0x138];
} fm_mdio_t;
typedef struct fm_10gec {
diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c
index a77ee20..7dd78f2 100644
--- a/drivers/net/fm/dtsec.c
+++ b/drivers/net/fm/dtsec.c
@@ -171,7 +171,7 @@ void init_dtsec(struct fsl_enet_mac *mac, void *base,
void *phyregs, int max_rx_len)
{
mac-base = base;
- mac-phyregs = NULL;
+ mac-phyregs = phyregs;
mac-max_rx_len = max_rx_len;
mac-init_mac = dtsec_init_mac;
mac-enable_mac = dtsec_enable_mac;
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 308d610..f7ed850 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -537,6 +537,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct
ccsr_fman *reg)
/* Get the mac registers base address */
if (fm_eth-type == FM_ETH_1G_E) {
base = reg-mac_1g[num].fm_dtesc;
+ phyregs = reg-mac_1g[num].fm_mdio.miimcfg;
} else {
base = reg-mac_10g[num].fm_10gec;
phyregs = reg-mac_10g[num].fm_10gec_mdio;
@@ -552,7 +553,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct
ccsr_fman *reg)
fm_eth-mac = mac;
if (fm_eth-type == FM_ETH_1G_E)
- init_dtsec(mac, base, NULL, MAX_RXBUF_LEN);
+ init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
else
init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
--
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[U-Boot] [PATCH 2/3] fdt: update fdt_alloc_phandle to use fdt_get_phandle
The device tree compiler, dtc, can use phandle and/or linux,phandle
properties to specify the phandle for any node. By default, it uses
both, but linux,phandle is deprecated. One day, we'd like to stop using
linux,phandle, but U-boot needs to support both properties equally
first.
fdt_alloc_phandle() generates a unique phandle, but it was only checking
the linux,phandle properties. Instead, we use fdt_get_phandle(),
which checks both properties automatically. This ensures that we
support dtbs that only use phandle.
The side-effect is that fdt_alloc_phandle() now takes twice as long, since
it has to check for two properties instead of one in each node that it
searches.
Signed-off-by: Timur Tabi ti...@freescale.com
---
common/fdt_support.c |7 ++-
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 698abf7..abf6d53 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -1182,14 +1182,11 @@ int fdt_node_offset_by_compat_reg(void *blob, const
char *compat,
*/
int fdt_alloc_phandle(void *blob)
{
- int offset, len, phandle = 0;
- const u32 *val;
+ int offset, phandle = 0;
for (offset = fdt_next_node(blob, -1, NULL); offset = 0;
offset = fdt_next_node(blob, offset, NULL)) {
- val = fdt_getprop(blob, offset, linux,phandle, len);
- if (val)
- phandle = max(*val, phandle);
+ phandle = max(phandle, fdt_get_phandle(blob, offset));
}
return phandle + 1;
--
1.7.4.4
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[U-Boot] [PATCH 3/3] powerpc/85xx: use fdt_create_phandle() to create the Fman firmware phandles
Function fdt_create_phandle() conveniently creates new phandle properties
using both linux,phandle and phandle, so it should be used by all code
that wants to create a phandle.
The Fman firmware code, which embeds an Fman firmware into the device tree,
was creating the phandle properties manually. Instead, change it to use
fdt_create_phandle().
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/fdt.c |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index d20c94c..9d2d769 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -504,9 +504,8 @@ void fdt_fixup_fman_firmware(void *blob)
fdt_strerror(rc));
return;
}
- phandle = fdt_alloc_phandle(blob);
- rc = fdt_setprop_cell(blob, fwnode, linux,phandle, phandle);
- if (rc 0) {
+ phandle = fdt_create_phandle(blob, fwnode);
+ if (!phandle) {
char s[64];
fdt_get_path(blob, fwnode, s, sizeof(s));
printf(Could not add phandle property to node %s: %s\n, s,
--
1.7.4.4
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[U-Boot] [PATCH 1/3] fdt: check for fdt errors in fdt_create_phandle
fdt_create_phandle() was ignoring errors from fdt_set_phandle(). If an
error occurs, print an error message and return 0, which is an invalid
phandle. We also need to change the return type for fdt_create_phandle()
to indicate that it cannot return an error code.
Signed-off-by: Timur Tabi ti...@freescale.com
---
common/fdt_support.c | 11 +--
include/fdt_support.h |2 +-
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 46aa842..698abf7 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -1241,15 +1241,22 @@ int fdt_set_phandle(void *fdt, int nodeoffset, uint32_t
phandle)
* @fdt: ptr to device tree
* @nodeoffset: node to update
*/
-int fdt_create_phandle(void *fdt, int nodeoffset)
+unsigned int fdt_create_phandle(void *fdt, int nodeoffset)
{
/* see if there is a phandle already */
int phandle = fdt_get_phandle(fdt, nodeoffset);
/* if we got 0, means no phandle so create one */
if (phandle == 0) {
+ int ret;
+
phandle = fdt_alloc_phandle(fdt);
- fdt_set_phandle(fdt, nodeoffset, phandle);
+ ret = fdt_set_phandle(fdt, nodeoffset, phandle);
+ if (ret 0) {
+ printf(Can't set phandle %u: %s\n, phandle,
+ fdt_strerror(ret));
+ return 0;
+ }
}
return phandle;
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 8f06aac..7206c56 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -90,7 +90,7 @@ int fdt_node_offset_by_compat_reg(void *blob, const char
*compat,
phys_addr_t compat_off);
int fdt_alloc_phandle(void *blob);
int fdt_set_phandle(void *fdt, int nodeoffset, uint32_t phandle);
-int fdt_create_phandle(void *fdt, int nodeoffset);
+unsigned int fdt_create_phandle(void *fdt, int nodeoffset);
int fdt_add_edid(void *blob, const char *compat, unsigned char *buf);
int fdt_verify_alias_address(void *fdt, int anode, const char *alias,
--
1.7.4.4
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Re: [U-Boot] [u-boot-release] [Patch v3 7/7] powerpc/8xxx: Add support for interactive DDR programming interface
York Sun wrote: +Interactive DDR debugging +=== + +For DDR parameter tuning up and debugging, the interactive DDR debugging can +be activated by saving an environment variable ddr_interactive. The value +doesn't matter. Once activated, U-boot prompts FSL DDR before enabling DDR +controller. The available commands can be seen by typing help. + +The example flow of using interactive debugging is +type command compute to calculate the parameters from the default +type command print with arguments to show SPD, options, registers +type command edit with arguments to change any if desired +type command go to continue calculation and enable DDR controller + +Note, check next_step to show the flow. For example, after editing registers, +DDR controller will be enabled with current setting without further +calculation. This is pretty skimpy for such a powerful feature. How about some examples and a detailed description of each command? -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot-release] [Patch v3 7/7] powerpc/8xxx: Add support for interactive DDR programming interface
York Sun wrote: I think the interactive command is self-explained. Why do people say things like that? If I say that it needs to be better documented, then obviously it isn't self-explanatory. I can add some examples if needed. But I am afraid the example will be either too short or too long. For example, I can add the following First step, run compute command, it returns with the DIMM part number FSL DDRcompute Detected UDIMM UG51U6400N8SU-ACF Second step, users can run 'print' command with arguments. Without argument, a help message will print out This is not an example. This is a walk-through. An example shows how individual commands can be used, and what the output could look like. I can further show the examples of print/edit dimmparams, commonparams, opts, regs. It will be too long. It is not difficult to use the self-guided interface. Agree? How could it be too long? Is there not enough room on the git server to store a text file? This file could be 200KB is size, and that would be okay. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI speed
Scott Wood wrote: There's no way it can be 3000, 6600, etc. based on the board's crystal? There is earlier code that sets pci1_speed to if the speed is unknown. So the actual value of pci1_speed is limited to those two numbers. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI speed
Scott Wood wrote: So you'll set the speed to if the actual speed is 6600? I think so. Even if it's 3300, why force it to ? That's a good question. Since the patch doesn't explain why it's making the change, there's no way for anyone to know. That makes it very difficult for people to review the patch, but I'm sure that Chenhui already knows that. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes
displays which of these is actually built, but it's inconsistent. This is
especially problematic since the default build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used. Not only that, but each board includes code that displays
the message, so there is duplication.
So instead of displaying this message at boot time, the address map size
information is moved into the 'bdinfo' command. The board-specific code is
deleted.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/corenet_ds/corenet_ds.c |4
board/freescale/mpc8536ds/mpc8536ds.c |7 +--
board/freescale/mpc8572ds/mpc8572ds.c |6 +-
board/freescale/p1010rdb/p1010rdb.c |6 +-
board/freescale/p1022ds/p1022ds.c |8 ++--
board/freescale/p1_p2_rdb/p1_p2_rdb.c |4 +---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c |8 +---
board/freescale/p2020ds/p2020ds.c |8 ++--
board/freescale/p2041rdb/p2041rdb.c |4
common/cmd_bdinfo.c |8
10 files changed, 17 insertions(+), 46 deletions(-)
diff --git a/board/freescale/corenet_ds/corenet_ds.c
b/board/freescale/corenet_ds/corenet_ds.c
index b1eecc4..a33c936 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -62,10 +62,6 @@ int checkboard (void)
else
printf(invalid setting of SW%u\n, PIXIS_LBMAP_SWITCH);
-#ifdef CONFIG_PHYS_64BIT
- puts(36-bit Addressing\n);
-#endif
-
/* Display the RCW, so that no one gets confused as to what RCW
* we're actually using for this boot.
*/
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c
b/board/freescale/mpc8536ds/mpc8536ds.c
index b292e13..b407f1d 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -62,12 +62,7 @@ int checkboard (void)
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
- puts(Board: MPC8536DS );
-#ifdef CONFIG_PHYS_64BIT
- puts((36-bit addrmap) );
-#endif
-
- printf (Sys ID: 0x%02x,
+ printf (Board: MPC8536DS Sys ID: 0x%02x,
Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ,
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c
b/board/freescale/mpc8572ds/mpc8572ds.c
index b20299e..38eafe0 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -45,11 +45,7 @@ int checkboard (void)
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
- puts (Board: MPC8572DS );
-#ifdef CONFIG_PHYS_64BIT
- puts ((36-bit addrmap) );
-#endif
- printf (Sys ID: 0x%02x,
+ printf (Board: MPC8572DS Sys ID: 0x%02x,
Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ,
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
diff --git a/board/freescale/p1010rdb/p1010rdb.c
b/board/freescale/p1010rdb/p1010rdb.c
index 03e9da1..7aa2117 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -165,11 +165,7 @@ int checkboard(void)
struct cpu_type *cpu;
cpu = gd-cpu;
- printf(Board: %sRDB , cpu-name);
-#ifdef CONFIG_PHYS_64BIT
- puts((36-bit addrmap));
-#endif
- puts(\n);
+ printf(Board: %sRDB\n, cpu-name);
return 0;
}
diff --git a/board/freescale/p1022ds/p1022ds.c
b/board/freescale/p1022ds/p1022ds.c
index 456d9b0..aca30f3 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -56,12 +56,8 @@ int checkboard(void)
{
u8 sw;
- puts(Board: P1022DS );
-#ifdef CONFIG_PHYS_64BIT
- puts((36-bit addrmap) );
-#endif
-
- printf(Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ,
+ printf(Board: P1022DS Sys ID: 0x%02x,
+ Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ,
in_8(pixis-id), in_8(pixis-arch), in_8(pixis-scver));
sw = in_8(PIXIS_SW(PIXIS_LBMAP_SWITCH));
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 864b3ce..6418710 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -110,9 +110,7 @@ int checkboard (void)
cpu = gd-cpu;
printf (Board: %sRDB Rev%c\n, cpu-name, board_rev);
-#ifdef CONFIG_PHYS_64BIT
- puts ((36-bit addrmap) \n);
-#endif
+
setbits_be32(pgpio-gpdir, GPIO_DIR);
/*
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 4671128..abe087b 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
[U-Boot] [PATCH 1/2] powerpc/85xx: CONFIG_ENABLE_36BIT_PHYS does not depend on CONFIG_PHYS_64BIT
The macro CONFIG_ENABLE_36BIT_PHYS is used to indicate that the given SOC is capable of 36-bit physical addresses, even if such large addresses are not used. On two boards, this macro was enabled only when building a 36-bit image. Signed-off-by: Timur Tabi ti...@freescale.com --- include/configs/P1022DS.h |3 ++- include/configs/p1_p2_rdb_pc.h |3 +-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index a3cccf4..28848bd 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -43,8 +43,9 @@ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#ifdef CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP16 /* number of TLB1 entries */ #endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index b9b89cf..df1925f 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -204,9 +204,8 @@ #define CONFIG_BTB #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ -#ifdef CONFIG_PHYS_64BIT + #define CONFIG_ENABLE_36BIT_PHYS -#endif #ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP1 -- 1.7.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] powerpc/85xx: standardize display of address map size (32-bit vs. 36-bit)
Kumar Gala wrote: Both. I'm think for your patch we'd add some general config option for extra print info. So you want to see this instead: /* * Display whether this is a 32-bit build or a 36-bit build. */ #ifdef CONFIG_DISPLAY_ADDR_SIZE #ifdef CONFIG_PHYS_64BIT puts(ADDR: 36-bit address map\n); #else puts(ADDR: 32-bit address map\n); #endif #endif I still like my way better. It eliminates the need to think about another CONFIG option. I think adding another CONFIG option is worse than adding another line of text. It think it's silly to complain about adding one line of text that is only displayed on e500 systems that support 36-bit addressing, especially since we display this information on most of our boards anyway. Surely we can find some other line of text that we can shorten or eliminate to make up for it. For instance, we can combine these two lines into one: CPU0: P1022E, Version: 1.0, (0x80ee0010) Core: E500, Version: 5.0, (0x80211050) or these two lines: L1:D-cache 32 kB enabled I-cache 32 kB enabled -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
