[USRP-users] Building rfnoc image
Hi everyone I want to build my custom rfnoc image in vivado , and based on some tutorial did this with running uhd_image_builder.py .But after sometime I got the below error : Could not read script '../usrp3/tools/scripts/viv_generate_hls_ip.tcl' Does anyone know about this? ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
Hi Jerrid/Brian, I wanted to follow up and let you know that the fix for this issue is now available on the UHD-3.15.LTS branch. Thank you for posting and for your patience. Regards, Michael On Thu, Jan 2, 2020 at 8:57 AM Jerrid Plymale via USRP-users < usrp-users@lists.ettus.com> wrote: > Yes, I have just been following the guide on the getting started with > RFNoC page. > > > > Best Regards, > > > > Jerrid > > > > *From:* Brian Padalino > *Sent:* Thursday, January 2, 2020 8:52 AM > *To:* Jerrid Plymale > *Cc:* usrp-users@lists.ettus.com > *Subject:* Re: [USRP-users] Building RFNoC image with default blocks > fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers > > > > On Thu, Jan 2, 2020 at 11:48 AM Jerrid Plymale < > jerrid.plym...@canyon-us.com> wrote: > > I am trying to generate a custom RFNoC FPGA Image using this version of > UHD. > > > > OK. So you've checked out fde2a94eb7231af859653db8caaf777ae2b66199 and > you're trying to build a regular image with Vivado 2018.3. Correct? > > > > Brian > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
Felix, thanks for the catch. That looks like a problem I may have
introduced by accident a few months ago. This PR should fix it, hopefully:
https://github.com/EttusResearch/fpga/pull/47/files
Note I expect this would get merged into master and potentially not
backported to whatever version of uhd-fpga you're using, so I'd recommend
keeping what you have locally if it works for you :D
EJ
On Wed, Jan 8, 2020 at 8:00 AM Felix Greiwe via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi EJ,
>
> thank you for your answer! To make my error more traceable, I created a
> new OOT Module and added the default gain block from rfnoc getting
> started.
>
> I also took your advice and looked at the uhd_image_builder.py script. I
> noticed very strange behaviour, because my print statements suggested,
> that the script did not include my makefile.srcs because it first edited
> the path
>
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/ to
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc and a bit later to
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc/rfnoc/fpga-src/ .
>
> As you can see two rfnoc's here hence it did not find the makefile.src in
> /fpga-src. The changes (marked with fgr) in the create_oot_include
> here seem to resolve the issue, hopefully helpful for other people too and
> maybe even a major bug?:
>
> def create_oot_include(device, include_dirs):
> """
> Create the include file for OOT RFNoC sources
> """
> oot_dir_list = []
> target_dir = device_dict(device.lower())
> dest_srcs_file = os.path.join(get_scriptpath(), '..', '..', 'top',\
> target_dir, 'Makefile.OOT.inc')
> incfile = open(dest_srcs_file, 'w')
> incfile.write(OOT_SRCS_FILE_HDR)
> if include_dirs is not None:
> for dirs in include_dirs:
> currpath = os.path.abspath(str(dirs))
> if os.path.isdir(currpath) & (os.path.basename(currpath) ==
> "rfnoc"):
> # Case 1: Pointed directly to rfnoc directory
> oot_path = currpath
> elif os.path.isdir(os.path.join(currpath, 'rfnoc')):
> # Case 2: Pointed to top level rfnoc module directory
> oot_path = os.path.join(currpath, 'rfnoc')
> elif os.path.isfile(os.path.join(currpath, 'Makefile.inc')):
> # Case 3: Pointed to a random directory with a Makefile.inc
> oot_path = currpath
> else:
> print('No RFNoC module found at ' +
> os.path.abspath(currpath))
> continue
> if oot_path not in oot_dir_list:
> oot_dir_list.append(oot_path)
> named_path = os.path.join('$(BASE_DIR)',
> get_relative_path(get_basedir(), oot_path))
> incfile.write(OOT_DIR_TMPL.format(oot_dir=named_path))
> if os.path.isfile(os.path.join(oot_path, 'Makefile.inc')):
> # Check for Makefile.inc
> incfile.write(OOT_INC_TMPL)
> elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
> 'Makefile.inc')):
> # Check for Makefile.inc
> incfile.write(OOT_INC_TMPL)
> #elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
> 'fpga-src', 'Makefile.srcs')): # Original
> elif os.path.isfile(os.path.join(oot_path, 'fpga-src',
> 'Makefile.srcs')): # Anders fgr
> # Legacy: Check for fpga-src/Makefile.srcs
> # Read, then append to file
> # curr_srcs = open(os.path.join(oot_path, 'rfnoc',
> 'fpga-src', 'Makefile.srcs'), 'r').read() # Original
> curr_srcs = open(os.path.join(oot_path, 'fpga-src',
> 'Makefile.srcs'), 'r').read() # Anders fgr
> # curr_srcs = curr_srcs.replace('SOURCES_PATH',
> os.path.join(oot_path, 'rfnoc', 'fpga-src', '')) #
> Original
> curr_srcs = curr_srcs.replace('SOURCES_PATH',
> os.path.join(oot_path, 'fpga-src', '')) # Anders fgr
> print('Searching for Makefile.srcs: ' + curr_srcs) #fgr
> incfile.write(OOT_SRCS_TMPL.format(sources=curr_srcs))
> else:
> print('No valid makefile found at ' +
> os.path.abspath(currpath))
> continue
>
> However 30 minutes later in the build I got the next errror and again have
> no idea what to do. My command was:
>
> ./uhd_image_builder.py gain ddc fft -I
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/ -d x310 -t X310_RFNOC_HG -m 6
> --fill-with-fifos
>
> Using Vivado 2018.3 and UHD 3.15.0.0-124-geb448043
>
>
> Erros are:
>
> ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4
> has multiple drivers: radio_clk_gen/inst/clkout1_buf/O, and
> bus_clk_gen/inst/clkout4_buf/O.
> ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
> radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 has
> multiple drivers:
>
> ce_reset_sync/reset_double_syn
Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
Hi Brian, thank you for the answer, with your help I was able to successfully build an Image! One last question: Do I need to worry about all those critical warnings that popped up during the build? Seems like a lot to me. Example: CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more evaluation cores that will cease to function after a certain period of time. This design should NOT be used in production systems. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[0].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL
Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
On Wed, Jan 8, 2020 at 8:00 AM Felix Greiwe via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi EJ,
>
> thank you for your answer! To make my error more traceable, I created a
> new OOT Module and added the default gain block from rfnoc getting
> started.
>
> I also took your advice and looked at the uhd_image_builder.py script. I
> noticed very strange behaviour, because my print statements suggested,
> that the script did not include my makefile.srcs because it first edited
> the path
>
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/ to
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc and a bit later to
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc/rfnoc/fpga-src/ .
>
> As you can see two rfnoc's here hence it did not find the makefile.src in
> /fpga-src. The changes (marked with fgr) in the create_oot_include
> here seem to resolve the issue, hopefully helpful for other people too and
> maybe even a major bug?:
>
> def create_oot_include(device, include_dirs):
> """
> Create the include file for OOT RFNoC sources
> """
> oot_dir_list = []
> target_dir = device_dict(device.lower())
> dest_srcs_file = os.path.join(get_scriptpath(), '..', '..', 'top',\
> target_dir, 'Makefile.OOT.inc')
> incfile = open(dest_srcs_file, 'w')
> incfile.write(OOT_SRCS_FILE_HDR)
> if include_dirs is not None:
> for dirs in include_dirs:
> currpath = os.path.abspath(str(dirs))
> if os.path.isdir(currpath) & (os.path.basename(currpath) ==
> "rfnoc"):
> # Case 1: Pointed directly to rfnoc directory
> oot_path = currpath
> elif os.path.isdir(os.path.join(currpath, 'rfnoc')):
> # Case 2: Pointed to top level rfnoc module directory
> oot_path = os.path.join(currpath, 'rfnoc')
> elif os.path.isfile(os.path.join(currpath, 'Makefile.inc')):
> # Case 3: Pointed to a random directory with a Makefile.inc
> oot_path = currpath
> else:
> print('No RFNoC module found at ' +
> os.path.abspath(currpath))
> continue
> if oot_path not in oot_dir_list:
> oot_dir_list.append(oot_path)
> named_path = os.path.join('$(BASE_DIR)',
> get_relative_path(get_basedir(), oot_path))
> incfile.write(OOT_DIR_TMPL.format(oot_dir=named_path))
> if os.path.isfile(os.path.join(oot_path, 'Makefile.inc')):
> # Check for Makefile.inc
> incfile.write(OOT_INC_TMPL)
> elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
> 'Makefile.inc')):
> # Check for Makefile.inc
> incfile.write(OOT_INC_TMPL)
> #elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
> 'fpga-src', 'Makefile.srcs')): # Original
> elif os.path.isfile(os.path.join(oot_path, 'fpga-src',
> 'Makefile.srcs')): # Anders fgr
> # Legacy: Check for fpga-src/Makefile.srcs
> # Read, then append to file
> # curr_srcs = open(os.path.join(oot_path, 'rfnoc',
> 'fpga-src', 'Makefile.srcs'), 'r').read() # Original
> curr_srcs = open(os.path.join(oot_path, 'fpga-src',
> 'Makefile.srcs'), 'r').read() # Anders fgr
> # curr_srcs = curr_srcs.replace('SOURCES_PATH',
> os.path.join(oot_path, 'rfnoc', 'fpga-src', '')) #
> Original
> curr_srcs = curr_srcs.replace('SOURCES_PATH',
> os.path.join(oot_path, 'fpga-src', '')) # Anders fgr
> print('Searching for Makefile.srcs: ' + curr_srcs) #fgr
> incfile.write(OOT_SRCS_TMPL.format(sources=curr_srcs))
> else:
> print('No valid makefile found at ' +
> os.path.abspath(currpath))
> continue
>
> However 30 minutes later in the build I got the next errror and again have
> no idea what to do. My command was:
>
> ./uhd_image_builder.py gain ddc fft -I
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/ -d x310 -t X310_RFNOC_HG -m 6
> --fill-with-fifos
>
> Using Vivado 2018.3 and UHD 3.15.0.0-124-geb448043
>
>
> Erros are:
>
> ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4
> has multiple drivers: radio_clk_gen/inst/clkout1_buf/O, and
> bus_clk_gen/inst/clkout4_buf/O.
> ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
> radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 has
> multiple drivers:
>
> ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q,
> and
>
> radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q.
> ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
> ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
> [00:24:46] Current task: DRC +++ Current Phase: Starting
> [00:24:46] Current task: DRC +++ Curren
Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
Hi EJ,
thank you for your answer! To make my error more traceable, I created a
new OOT Module and added the default gain block from rfnoc getting
started.
I also took your advice and looked at the uhd_image_builder.py script. I
noticed very strange behaviour, because my print statements suggested,
that the script did not include my makefile.srcs because it first edited
the path
/home/lskt/rfnoc/src/rfnoc-blocks_lskt/ to
/home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc and a bit later to
/home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc/rfnoc/fpga-src/ .
As you can see two rfnoc's here hence it did not find the makefile.src in
/fpga-src. The changes (marked with fgr) in the create_oot_include
here seem to resolve the issue, hopefully helpful for other people too and
maybe even a major bug?:
def create_oot_include(device, include_dirs):
"""
Create the include file for OOT RFNoC sources
"""
oot_dir_list = []
target_dir = device_dict(device.lower())
dest_srcs_file = os.path.join(get_scriptpath(), '..', '..', 'top',\
target_dir, 'Makefile.OOT.inc')
incfile = open(dest_srcs_file, 'w')
incfile.write(OOT_SRCS_FILE_HDR)
if include_dirs is not None:
for dirs in include_dirs:
currpath = os.path.abspath(str(dirs))
if os.path.isdir(currpath) & (os.path.basename(currpath) ==
"rfnoc"):
# Case 1: Pointed directly to rfnoc directory
oot_path = currpath
elif os.path.isdir(os.path.join(currpath, 'rfnoc')):
# Case 2: Pointed to top level rfnoc module directory
oot_path = os.path.join(currpath, 'rfnoc')
elif os.path.isfile(os.path.join(currpath, 'Makefile.inc')):
# Case 3: Pointed to a random directory with a Makefile.inc
oot_path = currpath
else:
print('No RFNoC module found at ' +
os.path.abspath(currpath))
continue
if oot_path not in oot_dir_list:
oot_dir_list.append(oot_path)
named_path = os.path.join('$(BASE_DIR)',
get_relative_path(get_basedir(), oot_path))
incfile.write(OOT_DIR_TMPL.format(oot_dir=named_path))
if os.path.isfile(os.path.join(oot_path, 'Makefile.inc')):
# Check for Makefile.inc
incfile.write(OOT_INC_TMPL)
elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
'Makefile.inc')):
# Check for Makefile.inc
incfile.write(OOT_INC_TMPL)
#elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
'fpga-src', 'Makefile.srcs')): # Original
elif os.path.isfile(os.path.join(oot_path, 'fpga-src',
'Makefile.srcs')): # Anders fgr
# Legacy: Check for fpga-src/Makefile.srcs
# Read, then append to file
# curr_srcs = open(os.path.join(oot_path, 'rfnoc',
'fpga-src', 'Makefile.srcs'), 'r').read() # Original
curr_srcs = open(os.path.join(oot_path, 'fpga-src',
'Makefile.srcs'), 'r').read() # Anders fgr
# curr_srcs = curr_srcs.replace('SOURCES_PATH',
os.path.join(oot_path, 'rfnoc', 'fpga-src', '')) #
Original
curr_srcs = curr_srcs.replace('SOURCES_PATH',
os.path.join(oot_path, 'fpga-src', '')) # Anders fgr
print('Searching for Makefile.srcs: ' + curr_srcs) #fgr
incfile.write(OOT_SRCS_TMPL.format(sources=curr_srcs))
else:
print('No valid makefile found at ' +
os.path.abspath(currpath))
continue
However 30 minutes later in the build I got the next errror and again have
no idea what to do. My command was:
./uhd_image_builder.py gain ddc fft -I
/home/lskt/rfnoc/src/rfnoc-blocks_lskt/ -d x310 -t X310_RFNOC_HG -m 6
--fill-with-fifos
Using Vivado 2018.3 and UHD 3.15.0.0-124-geb448043
Erros are:
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4
has multiple drivers: radio_clk_gen/inst/clkout1_buf/O, and
bus_clk_gen/inst/clkout4_buf/O.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 has
multiple drivers:
ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q,
and
radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
[00:24:46] Current task: DRC +++ Current Phase: Starting
[00:24:46] Current task: DRC +++ Current Phase: Finished
[00:24:46] Process terminated. Status: Failure
Warnings: 1304
Critical Warnings: 40
Errors: 4
Makefile.x300.inc:106: recipe for target 'bin' failed
make[1]: *** [bin] Error 1
make[1]: Verzeichnis /home
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
Hello Cherif and Brian, I did find the clock signal re-definitions you were talking about in *rfnoc_ce_auto_inst_x310.v*, and I did notice that the file is generated by the *uhd_image_builder.py file*, so I looked in the *uhd_image_builder.py* file to find the code that generates *rfnoc_ce_auto_inst_x310.v*. I was able to find the signal re-definitions in the image builder file, lines 43 and 44 I believe, and I changed them there. So far that seems to have fixed the issue and I have successfully been able to build a custom FPGA image. The one thing I have yet to try is building one with a custom RFNoC block. Anyways, thank you for the help and I will post again if I run into any other issues. Best Regards, Jerrid ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
Hi Felix, It's tough to debug your specific issues without seeing the whole OOT repo structure, including makefiles, etc. However I regularly use rfnoc with OOT folders successfully and have an example here you might be able to refer to for some hints: github.com/ejk43/rfnoc-ootexample I might suggest trying to check that out and see if you can build with one of those blocks first, then modify for your purposes? Also, one other thing to mention is you might have some luck debugging the uhd_image_builder.py to see where it's going wrong in your case (it's just a python file so it's pretty easy to add debug markers or print statements if you want)... EJ On Sat, Jan 4, 2020, 5:10 AM Felix Greiwe via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello again, > > has no one an idea? I have still not managed to get it working.. > I would take any advice! > > Best regards, > > Felix > > > > Hello together, > > > > recently I installed the whole UHD/GNU-Radio Toolchain on a fresh install > > of Kubuntu 18.04 LTS. I followed the instructions from > > https://kb.ettus.com/Getting_Started_with_RFNoC_Development > > and used the Pybombs install. > > > > (I ran into a lot of problems there and had to install a lot of stuff > > manually because most of the commands were not working properly. Maybe > the > > Pybombs Tutorial Section needs an update?) > > > > Finally I managed to install it successfully and the command > > uhd_config_version -- info prints: UHD 3.15.0.0-124-geb448043 > > (I also installed Vivado 2018.3 and added the License which seems to > > work.) > > > > After the install I wanted to validate it by creating an OOT Module and > > OOT Block named noc_block_checkdevprocess.v. I did not edit the Verilog > > Code because I only wanted to know if I was able to build an Image > > properly. > > (I ran the default Testbench too, which worked without errors.) > > > > The command to build my image is: > > > > ./uhd_image_builder.py checkdevprocess digital_gain -t X310_RFNOC_HG -d > > X310 -I /home/lskt/rfnoc-blocks_lskt/rfnoc > > > > with "rfnoc-blocks_lskt" beeing my OOT Module and "checkdevprocess" > beeing > > my custom block. > > (I also tried the paths home/lskt/rfnoc-blocks_lskt/rfnoc/; > > home/lskt/rfnoc-blocks_lskt/; home/lskt/rfnoc-blocks_lskt/rfnoc/fpga-src > ) > > > > Every single time I get the same error message: > > ERROR: [Synth 8-439] module 'noc_block_checkdevprocess' not found > > > [/home/lskt/rfnoc/src/uhd-fpga/usrp3/top/x300/rfnoc_ce_auto_inst_x310.v:22] > > > > and I don't know why. > > > > I also tried the the uhd_image_builder_gui.py which did not even pop up > > until I uncommented the Line at row 149. I can see my OOT Block here > after > > adding the Module in the gui, but it prints the same error message as the > > non-gui version. > > > > If you need further information to help please ask. > > > > Any help is appreciated. > > > > Felix > > > > > > > > > > > > ___ > > USRP-users mailing list > > USRP-users@lists.ettus.com > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
Hello again, has no one an idea? I have still not managed to get it working.. I would take any advice! Best regards, Felix > Hello together, > > recently I installed the whole UHD/GNU-Radio Toolchain on a fresh install > of Kubuntu 18.04 LTS. I followed the instructions from > https://kb.ettus.com/Getting_Started_with_RFNoC_Development > and used the Pybombs install. > > (I ran into a lot of problems there and had to install a lot of stuff > manually because most of the commands were not working properly. Maybe the > Pybombs Tutorial Section needs an update?) > > Finally I managed to install it successfully and the command > uhd_config_version -- info prints: UHD 3.15.0.0-124-geb448043 > (I also installed Vivado 2018.3 and added the License which seems to > work.) > > After the install I wanted to validate it by creating an OOT Module and > OOT Block named noc_block_checkdevprocess.v. I did not edit the Verilog > Code because I only wanted to know if I was able to build an Image > properly. > (I ran the default Testbench too, which worked without errors.) > > The command to build my image is: > > ./uhd_image_builder.py checkdevprocess digital_gain -t X310_RFNOC_HG -d > X310 -I /home/lskt/rfnoc-blocks_lskt/rfnoc > > with "rfnoc-blocks_lskt" beeing my OOT Module and "checkdevprocess" beeing > my custom block. > (I also tried the paths home/lskt/rfnoc-blocks_lskt/rfnoc/; > home/lskt/rfnoc-blocks_lskt/; home/lskt/rfnoc-blocks_lskt/rfnoc/fpga-src ) > > Every single time I get the same error message: > ERROR: [Synth 8-439] module 'noc_block_checkdevprocess' not found > [/home/lskt/rfnoc/src/uhd-fpga/usrp3/top/x300/rfnoc_ce_auto_inst_x310.v:22] > > and I don't know why. > > I also tried the the uhd_image_builder_gui.py which did not even pop up > until I uncommented the Line at row 149. I can see my OOT Block here after > adding the Module in the gui, but it prints the same error message as the > non-gui version. > > If you need further information to help please ask. > > Any help is appreciated. > > Felix > > > > > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
On Fri, Jan 3, 2020 at 1:41 PM Cherif Diouf wrote: > I have this version UHD 3.15.0.git-84-g164d76dc > > but the lines are there whenever you use the ./uhd_image_builder.py > scripts. > Ah, I see it now: https://github.com/EttusResearch/fpga/blob/fde2a94eb7231af859653db8caaf777ae2b66199/usrp3/tools/scripts/uhd_image_builder.py#L44 Someone at Ettus should probably stop assigning those clocks. Brian > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
I have this version UHD 3.15.0.git-84-g164d76dc but the lines are there whenever you use the ./uhd_image_builder.py scripts. Best Regards Cherif From: Brian Padalino Sent: Friday, January 3, 2020 7:25:00 PM To: Cherif Diouf Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers On Fri, Jan 3, 2020 at 1:14 PM Cherif Diouf via USRP-users mailto:usrp-users@lists.ettus.com>> wrote: Hi Jerrid, Some hints, for info, I am working with the X310 device, but you can take the big picture. I previously met such issues, those were related to signal re-definitions. The file *rfnoc_ce_auto_inst_x310.v* at lines 19/20 is re-defining the ce_clk/ce_rst signals by assigning to them radio_clk/radio_rst signals. The issue here is that ce_clk is a clock of its own and is already defined in the top block file *x300.v* at lines 259 and 290. My filepath is rfnoc/src/uhd-fpga/usrp3/top/x300/. In the 3.15.0.0 code on github I don't see what you're talking about: https://github.com/EttusResearch/fpga/blob/fde2a94eb7231af859653db8caaf777ae2b66199/usrp3/top/x300/rfnoc_ce_auto_inst_x300.v<https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_EttusResearch_fpga_blob_fde2a94eb7231af859653db8caaf777ae2b66199_usrp3_top_x300_rfnoc-5Fce-5Fauto-5Finst-5Fx300.v&d=DwMFaQ&c=XYzUhXBD2cD-CornpT4QE19xOJBbRy-TBPLK0X9U2o8&r=xIsHdXnCRYoK3O7I17CLaka29UJ1VwI3mC9u8FAc7Ss&m=uyt3D3vrCo1sD1ffyQEPYhBW4X1kPu-ydtQoXIbEFIA&s=oWOA1dV-heZzHDmVnnGT9vrXUo3FwHl3BxJ3Eq3s6q0&e=> Looking at the history of the file, it looked like that might have been removed way back in 2016 in commit c98bc14fe0ea2c27a5629a24d47915eb7e0b6700. Jerrid - do you have those lines that Cherif is describing? Brian ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
On Fri, Jan 3, 2020 at 1:14 PM Cherif Diouf via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi Jerrid, > > > > Some hints, for info, I am working with the X310 device, but you can > take the big picture. > > > I previously met such issues, those were related to signal re-definitions. > > > The file *rfnoc_ce_auto_inst_x310.v* at lines 19/20 is re-defining the > ce_clk/ce_rst signals by assigning to them radio_clk/radio_rst signals. > The issue here is that ce_clk is a clock of its own and is already defined > in the top block file *x300.v* at lines 259 and 290. My filepath is > rfnoc/src/uhd-fpga/usrp3/top/x300/. > In the 3.15.0.0 code on github I don't see what you're talking about: https://github.com/EttusResearch/fpga/blob/fde2a94eb7231af859653db8caaf777ae2b66199/usrp3/top/x300/rfnoc_ce_auto_inst_x300.v Looking at the history of the file, it looked like that might have been removed way back in 2016 in commit c98bc14fe0ea2c27a5629a24d47915eb7e0b6700. Jerrid - do you have those lines that Cherif is describing? Brian ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
Hi Jerrid, Some hints, for info, I am working with the X310 device, but you can take the big picture. I previously met such issues, those were related to signal re-definitions. The file *rfnoc_ce_auto_inst_x310.v* at lines 19/20 is re-defining the ce_clk/ce_rst signals by assigning to them radio_clk/radio_rst signals. The issue here is that ce_clk is a clock of its own and is already defined in the top block file *x300.v* at lines 259 and 290. My filepath is rfnoc/src/uhd-fpga/usrp3/top/x300/. Vivado 2017.4 would just let this pass but when I moved to Vivado 2018.4 the build would each time fail, popping Net having multiple drivers errors. Changing the ce_clk/ce_rst signals names in the *rfnoc_ce_auto_inst_x310.v* and modifying this instantiation file accordingly will make the build work. The solution is ok If you are using a different custom instantiation file,. However, I am not sure that in your case it will help, because your *rfnoc_ce_auto_inst_x310.v* file is re-created at each build command. So likely anything you update in the file will be dumped at the next build. Best Regards Cherif ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
Yes, I have just been following the guide on the getting started with RFNoC page. Best Regards, Jerrid From: Brian Padalino Sent: Thursday, January 2, 2020 8:52 AM To: Jerrid Plymale Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers On Thu, Jan 2, 2020 at 11:48 AM Jerrid Plymale mailto:jerrid.plym...@canyon-us.com>> wrote: I am trying to generate a custom RFNoC FPGA Image using this version of UHD. OK. So you've checked out fde2a94eb7231af859653db8caaf777ae2b66199 and you're trying to build a regular image with Vivado 2018.3. Correct? Brian ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
On Thu, Jan 2, 2020 at 11:48 AM Jerrid Plymale wrote: > I am trying to generate a custom RFNoC FPGA Image using this version of > UHD. > OK. So you've checked out fde2a94eb7231af859653db8caaf777ae2b66199 and you're trying to build a regular image with Vivado 2018.3. Correct? Brian > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
I am trying to generate a custom RFNoC FPGA Image using this version of UHD. Best Regards, Jerrid From: Brian Padalino Sent: Thursday, January 2, 2020 8:44 AM To: Jerrid Plymale Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers On Thu, Jan 2, 2020 at 11:42 AM Jerrid Plymale mailto:jerrid.plym...@canyon-us.com>> wrote: Hello Brian, I have installed UHD 3.15.0.0-124-geb448043 And this is what you're trying to build? Brian ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
On Thu, Jan 2, 2020 at 11:42 AM Jerrid Plymale wrote: > Hello Brian, > > > > I have installed UHD 3.15.0.0-124-geb448043 > And this is what you're trying to build? Brian > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
Hello Brian, I have installed UHD 3.15.0.0-124-geb448043 Best Regards, Jerrid ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
On Thu, Jan 2, 2020 at 11:24 AM Jerrid Plymale via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello Marcus, > > So I tried cleaning the uhd-fpga folder as you suggested, however I ended > up getting the same errors and the image still failed to build. I have > attached the build log again in case there was a change within it. > What version of UHD are you trying to build? Brian ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
Hello Jerrid, huh, a cursory glance tells me this is in the generated IP cores, i.e. not even in UHD code itself. I've not encountered that before; maybe there's a half-built IP core still present in the source tree? You can get that really pristine by cd uhd-fpga; git clean -xdf Best regards, Marcus On Fri, 2019-12-27 at 23:54 +, Jerrid Plymale via USRP-users wrote: > Hello all, > > So I have been attempting to build an X310 HG FPGA image following > the steps in the getting started guide for RFNoC for a while now, and > I have been getting the following error: > > Starting DRC Task > INFO: [DRC 23-27] Running DRC with 8 threads > ERROR: [DRC MDRV-1] Multiple Driver Nets: Net > bus_clk_gen/inst/CLK_OUT4 has multiple drivers: > bus_clk_gen/inst/clkout4_buf/O, and radio_clk_gen/inst/clkout1_buf/O. > ERROR: [DRC MDRV-1] Multiple Driver Nets: Net > radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 > has multiple drivers: > radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9]. > value_reg[9][0]/Q, and > ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].val > ue_reg[9][0]/Q. > INFO: [Project 1-461] DRC finished with 2 Errors > INFO: [Project 1-462] Please refer to the DRC report (report_drc) for > more information. > ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not > run. > > Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = > 13791.785 ; gain = 1.887 ; free physical = 109997 ; free virtual = > 117079 > INFO: [Common 17-83] Releasing license: Implementation > 7 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered. > opt_design failed > ERROR: [Common 17-39] 'opt_design' failed due to earlier errors. > > > I have attached the build log for those who may want to look at it > for more info. Can someone direct me in what I need to do to resolve > this issue so I can build an FPGA image successfully? any help would > be greatly appreciated. > > Best Regards, > > Jerrid > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
Hello all,
So I have been attempting to build an X310 HG FPGA image following the steps in
the getting started guide for RFNoC for a while now, and I have been getting
the following error:
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4 has
multiple drivers: bus_clk_gen/inst/clkout4_buf/O, and
radio_clk_gen/inst/clkout1_buf/O.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 has
multiple drivers:
radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q,
and
ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q.
INFO: [Project 1-461] DRC finished with 2 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more
information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 13791.785 ;
gain = 1.887 ; free physical = 109997 ; free virtual = 117079
INFO: [Common 17-83] Releasing license: Implementation
7 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
opt_design failed
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
I have attached the build log for those who may want to look at it for more
info. Can someone direct me in what I need to do to resolve this issue so I can
build an FPGA image successfully? any help would be greatly appreciated.
Best Regards,
Jerrid
#---
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Dec 27 15:38:56 2019
# Process ID: 29400
# Current directory: /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG
# Command line: vivado -mode gui -source /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build_x300.tcl -log build.log -journal x300.jou
# Log file: /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/build.log
# Journal file: /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/x300.jou
#---
start_gui
source /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build_x300.tcl
# source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl
## namespace eval ::vivado_utils {
## # Export commands
## namespace export \
## initialize_project \
## synthesize_design \
## check_design \
## generate_post_synth_reports \
## generate_post_place_reports \
## generate_post_route_reports \
## write_implementation_outputs \
## get_top_module \
## get_part_name \
## get_vivado_mode
##
## # Required environment variables
## variable g_tools_dir$::env(VIV_TOOLS_DIR)
## variable g_top_module $::env(VIV_TOP_MODULE)
## variable g_part_name$::env(VIV_PART_NAME)
## variable g_output_dir $::env(VIV_OUTPUT_DIR)
## variable g_source_files $::env(VIV_DESIGN_SRCS)
## variable g_vivado_mode $::env(VIV_MODE)
##
## # Optional environment variables
## variable g_verilog_defs ""
## if { [info exists ::env(VIV_VERILOG_DEFS) ] } {
## set g_verilog_defs $::env(VIV_VERILOG_DEFS)
## }
## variable g_include_dirs ""
## if { [info exists ::env(VIV_INCLUDE_DIRS) ] } {
## set g_include_dirs $::env(VIV_INCLUDE_DIRS)
## }
## }
## proc ::vivado_utils::initialize_project { {save_to_disk 0} } {
## variable g_top_module
## variable g_part_name
## variable g_output_dir
## variable g_source_files
##
## variable bd_files ""
##
## file delete -force $g_output_dir/build.rpt
##
## if {$save_to_disk == 1} {
## puts "BUILDER: Creating Vivado project ${g_top_module}_project.xpr for part $g_part_name"
## create_project -part $g_part_name ${g_top_module}_project
## } else {
## puts "BUILDER: Creating Vivado project in memory for part $g_part_name"
## create_project -in_memory -part $g_part_name
## }
##
## foreach src_file $g_source_files {
## set src_ext [file extension $src_file ]
## if [expr [lsearch {.vhd .vhdl} $src_ext] >= 0] {
## puts "BUILDER: Adding VHDL: $src_file"
## read_vhdl -library work $src_file
## } elseif [expr [lsearch {.v .vh .sv .svh} $src_ext] >= 0] {
## puts "BUILDER: Adding Verilog : $src_file"
## read_verilog $src_file
## } elseif [expr [lsearch {.xdc} $src_ext] >= 0] {
## puts "BUILDER: Adding XDC : $src_file"
## read_xdc $src_file
## } elseif [expr [lsearch {.xci} $src_ext] >= 0] {
## puts "BUILDER: Adding IP : $src_file"
## read_ip $src_file
## set_prop
[USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
Hello together, recently I installed the whole UHD/GNU-Radio Toolchain on a fresh install of Kubuntu 18.04 LTS. I followed the instructions from https://kb.ettus.com/Getting_Started_with_RFNoC_Development and used the Pybombs install. (I ran into a lot of problems there and had to install a lot of stuff manually because most of the commands were not working properly. Maybe the Pybombs Tutorial Section needs an update?) Finally I managed to install it successfully and the command uhd_config_version -- info prints: UHD 3.15.0.0-124-geb448043 (I also installed Vivado 2018.3 and added the License which seems to work.) After the install I wanted to validate it by creating an OOT Module and OOT Block named noc_block_checkdevprocess.v. I did not edit the Verilog Code because I only wanted to know if I was able to build an Image properly. (I ran the default Testbench too, which worked without errors.) The command to build my image is: ./uhd_image_builder.py checkdevprocess digital_gain -t X310_RFNOC_HG -d X310 -I /home/lskt/rfnoc-blocks_lskt/rfnoc with "rfnoc-blocks_lskt" beeing my OOT Module and "checkdevprocess" beeing my custom block. (I also tried the paths home/lskt/rfnoc-blocks_lskt/rfnoc/; home/lskt/rfnoc-blocks_lskt/; home/lskt/rfnoc-blocks_lskt/rfnoc/fpga-src ) Every single time I get the same error message: ERROR: [Synth 8-439] module 'noc_block_checkdevprocess' not found [/home/lskt/rfnoc/src/uhd-fpga/usrp3/top/x300/rfnoc_ce_auto_inst_x310.v:22] and I don't know why. I also tried the the uhd_image_builder_gui.py which did not even pop up until I uncommented the Line at row 149. I can see my OOT Block here after adding the Module in the gui, but it prints the same error message as the non-gui version. If you need further information to help please ask. Any help is appreciated. Felix ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
