Looks like JES2 to me
Keven Hall
JES2?
On Fri, Feb 16, 2018 at 3:50 PM -0600, "Dave Wade" wrote:
Folks,
Perhaps apposite to
It looks like macros from JES2
On Fri, Feb 16, 2018 at 3:50 PM -0600, "Dave Wade" wrote:
Folks,
Perhaps apposite to the recent conversation. I enjoy f
Maybe drop the REUSE directive on the alloc call?
Keven Hall
On Mon, Feb 19, 2018 at 7:19 AM -0600, "Gary Freestone"
wrote:
Sorry guys. W
TRT as in TRanslate and Test? Alas the assembler doesn’t
execute in-line assembly language but it does have an external function
facility that can call assembler code.
Assuming this is a program that gets called via JCL then it’s
trivial to call it from your own code.
As previously noted, you will likely need to set R1 to point to a valid PARM
construct (zero-length if no parameters).
If you’re
Don’t forget about any ABEND Reason Code.If bit SDWARCF is on
in SDWACMPF then there’s a valid Reason Code in SDWACRC. SDWACRC is in the
SDWARC1 Extension, the address of which is in SDWASVRP. SDWASVRP is in the
SDWAPTRS area
After UNPK you may need an OI to fix the sign nibble of the
resultant zoned decimal valuE (i.e., ensure that all the zoned digits are 0xf0
to 0xff) if you want to use a 16-byte translation table.
K3n
o: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: SDWA - SDWACMPC conversion
On Thu, 5 Apr 2018 14:45:15 +, Keven wrote:
>After UNPK you may need an OI to fix the sign nibble of the resultant
>zoned decimal valuE (i.e., ensure that all the zoned digits are 0xf0 to
>0xff) if you want to use a 16-byte translation table.
No. You need to unpack one more byte on the right.
--
Tom Marchant
does mean no reading past the last byte of the value to be
converted which may be desirable for a generalized implementation.
Keven
On Fri, Apr 6, 2018 at 9:22 AM -0500, "J R" wrote:
As you're concerned with
du/~smetz3
From: IBM Mainframe Assembler List on behalf of Keven
Sent: Wednesday, April 11, 2018 4:15 PM
To: ASSEMBLER-LIST@listserv.uga.edu
Subject: Re: SDWA - SDWACMPC conversion
Good point; I should have stuck with HEXTBL-240 but I decided
last minute that hexadecimal nota
tserv.uga.edu> wrote:
On Wed, 11 Apr 2018 20:15:12 +, Keven wrote:
>Using the UNPK/OI does mean no reading past the last byte of the value to be
>converted which may be desirable for a generalized implementation.
Sure, you could do something like this to convert two by
talents back into income-generating use once more.
Sorry for any confusion y’all Keven
On Fri, Apr 13, 2018 at 9:17 AM -0500, "Seymour J Metz" wrote:
Of course; the standard way to convert binary to hex is the UNPK/TR with a one
byte pad.
Hi David,
Could you not code it as =X’01000203’ instead?
Keven
On Fri, May 4, 2018 at 6:12 PM -0500, "Charles Mills" wrote:
I don
I think the technical answer in this context is:1 x 16-letter
word2 x 8-letter words 4 x 4-letter words8 x 2-letter words16 x 1-letter
words
This assumes single-byte character encoding.
Sorry if this sounds facile; I found my
instructions although it seems appropriate to label instructions that
are the target of Execute.
PERTURBED_BY_THIS CLC THIS,THAT
PREFER DS 0H CLC THIS,THAT
My tuppence-ha’penny worth Keven
On Wed, Aug 1, 2018 at 8:33 PM -0500
CLC THIS,THAT
PREFER DS 0H CLC THIS,THAT
On Wed, Aug 1, 2018 at 10:18 PM -0500, "Keven" wrote:
Chris, I share your dislike for labeled in
Ditto for
EX R0,*
except that you get a 0C3 program interrupt instead, which is usually a sign of
code scuttling itself and can be treated as such in recovery routines.
z
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Assembler List on behalf of Keven
Sent: Monday, August 6, 2018 11:23 AM
To: ASSEMBLER-LIST@listserv.uga.edu
Subject: Re: EX
Ditto for
EX R0,*
except that you get a 0C3 program interrupt instead, wh
I haven’t tried this; it’s an off the cuff suggestion but anyways...
Maybe define an alias for IEFJFCBN in MACLIB and have your #OCEWA macro either
invoke the alias name or generate the 176-byte area depending on the value in
&SYSNEST
Respectfully Keven
saved me way more time than I
spent posting my overthought solution so I have no regrets ;-)
Keven
On Fri, Dec 14, 2018 at 5:25 AM -0600, "David Cole" wrote:
Yep. Sure does.
Thanks!
At 12/14/2018 05:27 AM, Binyamin Dissen wrote:
>
Shouldn’t that be:Protection for readers is only necessary when the
storage in question doesn’t cross a doubleword boundary?
Keven
On Mon, Jan 14, 2019 at 4:17 PM -0600, "Ngan, Robert" wrote:
Protection for reade
does.
Regards,Keven
On Sun, Mar 3, 2019 at 8:15 PM -0600, "Jon Perryman"
wrote:
To me the easiest method is with global variables using a prefix to avoid
variable name collisions. It's been a long time, so you may not be corre
The OP’s table is built with multiple macro invocations so a global
SETC variable is required in order for the table to persist from one invocation
to the next.
Keven
On Mon, Mar 4, 2019 at 7:51 PM -0600, "Jon Perryman&quo
cause the instruction
cache line to be flushed which isn’t great.There’s almost no reason to use
self-modifying code that makes sense anymore...
Keven
On Mon, Apr 22, 2019 at 10:06 AM -0500, "Joseph Reichman"
wrote:
Had second th
bring it to the attention of
those seeking talent for hire. Thank you to those that have already helped;
y’all know who you are.
Keven
An IF SLIP Trap is probably the simplest sure-fire way of determining
if an exit is driven. You could modify the exit code or add another program to
the exit point to trace calls. It might help if you were more specific about
the exit you’re interested in.
Keven
HLASM has extended mnemonic codes for the Load On Condition
instructions and I think in this case you can use: LOCHINZ. R5,20 i
Keven
On Mon, Jun 3, 2019 at 11:07 AM -0500, "John McKown"
wrote:
I just wrote
LOCHINZ R5,20
On Mon, Jun 3, 2019 at 11:25 AM -0500, "Keven" wrote:
HLASM has extended mnemonic codes for the Load On Condition
instructions and I think in this case you can use: LOCHINZ
are you au fait with how an
AX and an EAX are used and when one or the other is required? Setting up and
using an EAX considerably more convoluted than setting up/using an AX.
Keven
On Wed, Nov 6, 2019 at 11:15 AM -0600, "esst...@juno.com&quo
Programs can view storage at absolute address zero by viewing the real
storage addressed by the prefix register for the processor executing the code.
I’m pretty sure the IPL text is in the first few bytes.
On Wed, Nov 6, 2019 at 1:01
Just curious; are we being made party to some sort of feud and/or
ongoing disgruntlement between subscribers DG and SM? If so please cease
forthwith and desist any further public airing of your grievances on this forum.
KH
On Fri, No
The paucity of detail makes answering your inquiry a matter of
inductive supposition. Maybe you should post additional information such as:
Source code?Assembly listing?ABEND code?SysLog?
Keven
On Thu, Nov 21, 2019 at 9:26 PM -0600
The “dead zone” is an OS-specific restriction. Processes running under
Linux on z/Architecture see the whole 64-bit address space, for example.
Keven
On Fri, Nov 22, 2019 at 4:23 PM -0600, "Paul Gilmartin"
<0014e
I’ve developed code that executed LURA and STURA instructions and I saw
a few S0C5s along the way. I remember thinking at the time that I had finally
filled in my S0Cx card (I.e., I had at that point written code that had
non-deliberately ABENDed with a S0C1 through S0C9.
Just wanted to add that ABEND S0C5 can occur either in DAT-on or
DAT-off mode. Moreover, Z/Architecture added a Real-space control mode
whereby real storage access is designated via access registers which means that
any storage-referencing instruction can result in ABEND
I believe it’s completely possible for Problem State code to raise a
Program Interrupt with code 5 in z/Architecture but not under z/OS.In AR ASC
mode an ALET can identify a Real-space designator that results in access to
real storage . z/OS (along with VM, VSE etc.) requ
about z/TPF or z/VSE,
but certainly neither z/OS nor z/VM gives an unprivileged user that sort of
access.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Assembler List on behalf of Keven
Sent: Thursday, January 30,
The generated code is:DC CL8’’
The assembler is supposed to generate character spaces if a character-type DC
statement Has a null nominal value.
Keven
On Mon, Apr 20, 2020 at 2:22 AM -0500, wrote:
There is nothing wrong with CL8'
I think the fix for APAR PH08424 is the one that corrects this issue.
The fix for APAR PH06572 addressed an issue with truncation of constants and
introduced the padding issue being discussed here.
Keven
On Mon, Apr 20, 2020 at 8
Are you suggesting the use SPM/IPM as an alternative to setting the
actual condition code?
K3n
On Tue, Jun 2, 2020 at 4:45 PM -0500, "Paul Gilmartin"
<0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote:
On 2020-06-02, at
Yes, z/Architecture has a number of SIMD instructions that operate on
distinct data types. They are called vector instructions in mainframeze and
accordingly have mnemonics that all begin with V.
On Thu, Jun 4, 2020 at 11:57 PM -0500,
Firstly please provide the generated assembly listing so we can see the
object code and secondly have you compared the RLD and object code to that
produced by HLASM (l suspect they will be identical).
Keven
On Thu, Jul 2, 2020 at 6:44
Pretty sure that a 2-byte RLD entry results from a Q-Type AdCon and
often represents a CXD or PRV offset. That’s to say, they have their uses
still.Keven
On Sat, Jul 4, 2020 at 7:11 PM -0500, "Seymour J Metz" wrote:
> And o
frame Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Keven [k...@k3n.us]
Sent: Saturday, July 4, 2020 8:35 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: z390 RLD Entries ... Bug or Feature?
Pretty sure that a 2-byte RLD entry results from a Q-Type AdCon and
often represen
some of it up and down a few times for extra fuzzies?
Keven
planning for security before
coding begins.
Keven
On Sat, Aug 8, 2020 at 12:28 PM -0500, "Paul Gilmartin"
<0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote:
On 2020-08-08, at 11:20:25, Robert Netzlof wrote:
>
> But do remembe
front-end that handles magic
instructions like 0x00FBAD.
Keven
On Sat, Aug 8, 2020 at 6:03 PM -0500, "Bernd Oppolzer"
wrote:
I know of at least one event where a site specific SVC which allowed to
store into write protected storage
stopp
I believe that options 1 & 2 are ‘hardware optimized’ for that
operation.
I personally I prefer the exclusive OR method.
Keven
On Mon, Aug 10, 2020 at 2:13 PM -0500, "Schmitt, Michael"
wrote:
There are many
There’s also LA/LAY which are probably as fast as the XR & SR options.
Keven
On Mon, Aug 10, 2020 at 2:36 PM -0500, "Gary Weinhold" wrote:
I'll make a stab at some principles behind the answer(s):
compatibility between (what would have been) 32-bit 390/ESA and 63-bit
z/Architecture in a manner analogous to how compatibility between 24-bit S/370
and 31-bit 370/XA systems was implemented? Would (24, 32, 63) have been a
better bit-size expansion sequence than was (24, 31, 64)?
Keven
decision to go with 63 or 64 bit addressing.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Assembler List on behalf of Keven
Sent: Thursday, September 3, 2020 5:19 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sub
For the 0.75 seconds it would take to differentiate an eye catching
string in program storage from an instance of it in in use to nominate a
control block, I have to wonder if this is a solution looking for a problem to
solve.
Keven
I’d say you were both correct.
Keven
On Tue, Oct 20, 2020 at 5:01 PM -0500, "Paul Gilmartin"
<0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote:
On 2020-10-20, at 14:58:52, Steve Smith wrote:
>
>
marks.
If you work in a CAPS ON universe (does anyone?) then maybe not but I think
it’s a option worthy of mention if only for its relative simplicity.
Keven
On Wed, Oct 21, 2020 at 12:45 PM -0500, "Tom Harper"
wrote:
As promised:
I think you'll need to specify a QNAME of SYSVSAM for your purposes;. SYSDSN
might not work for VSAM. You might want to experiment a little to make sure.
Keven
> On Feb 15, 2016, at 07:52, esst...@juno.com wrote:
>
> Thanks Mars looks like a good starting point.
>
&g
You could possibly page-protect the storage and use a recovery routine to drive
the table storage monitoring and/or read/write functionality. Easier than
rewiring PER or rolling your own OS.
Keven
> On Mar 5, 2016, at 07:39, Peter Relson wrote:
>
> It is not possible to monitor
that page-protected areas are backed by fixed frames. Is that so?
Keven
On Mar 6, 2016, at 07:20, Peter Relson wrote:
>> You could possibly page-protect the storage and use a recovery routine
>> to drive the table storage monitoring and/or read/write functionality.
>
> '
Peter,
If the END assembler directive is one that can be redefined, you could write
your own END macro that inserts any required data areas and generates an _END
(or whatever it is that END was redefined as).
Keven
> On Mar 17, 2017, at 12:29, Farley, Peter x23353
> wrote:
>
>
Taking no chances with the second Program Return, eh?
K3n
> On Apr 11, 2017, at 02:38, aldo.cro...@csebo.it wrote:
>
>
> example Cobol program that calls a routine.
> the routine returns a field containing two subfields (binary of 64 bits)
> that contain the seconds since 01.01.1972 (the fir
antic. For sure I'm dragging this thread ever further
from its original subject.
Keven
> On May 12, 2017, at 11:57, Paul Gilmartin
> <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote:
>
>> On 2017-05-12, at 09:56, somitcw wrote:
>>
>> My favourite w
I think the OP's data is unsorted, so regardless of the answer, the question
may be moot here
Keven
> On Jun 18, 2017, at 18:32, Richard Kuebbing wrote:
>
> Is a binary search ever appropriate on machines like the Z where the penalty
> for not being in the
Pretty sure Jeffrey is referring to storage patterns defined by invoking the
REFPAT macro (or HLL equivalent)
Keven
> On Jun 21, 2017, at 08:14, Tom Marchant
> <00a69b48f3bb-dmarc-requ...@listserv.uga.edu> wrote:
>
>> On Wed, 21 Jun 2017 06:11:23 -0500, Jeffrey Cela
Even if an instruction is interruptible, it's on interruptible on the CPU it's
executing on.
Other CPUs can be executing and modifying the same area of storage. Some
instructions guarantee block-concurrent access to operands, but for those that
do not, it's possible, if not likely, that concurr
Other than for SIGP I can't off the top of my head think of a suituation where
one processor interrupts another explicitly during instruction execution. Can
you provide some specific details as to what "interruptible" means here?
Keven
> On Jul 31, 2017, at 21:45, Ch
of emploring me to not engage in such an
undertaking.
You do not know me and are, I assume, ignorant of my skills and qualifications.
I find your comments to be disrespectful and do not welcome them here.
Keven
> On Jul 31, 2017, at 23:18, Charles Mills wrote:
>
> Nope. I give up. Y
code statements.No doubt Sisyphus would have been compelled to use
sequence numbers if he maintained code instead of a rock.
Keven
Get Outlook for iOS
On Mon, Dec 11, 2017 at 3:31 PM -0600, "Gibney, Dave" wrote:
I fin
that regard z/OS is like any other system out there. Ultimately Your
arguments fail to convince me of the existence of any actual vulnerabilities in
z/OS itself.
Keven
Get Outlook for iOS
On Sat, Dec 23, 2017 at 1:11 PM -0600, "J
.
Keven
Get Outlook for iOS
On Sun, Dec 24, 2017 at 1:11 AM -0600, "Farley, Peter x23353"
wrote:
Jon,
Dynalloc is not an exposure in a properly configured z/OS SAF environment.
Most large shops I have worked at d
I noticed this benign cyst of codein the SNAPX macro. Obviously this
has no effect on code generation but executing it a few million times
per day could really chew up some cycles. YMMV
.CKLFORM ANOP
AIF ('&MF' NE 'L').ARND
AIF ('&STORAGE' EQ '&#
Would not L/ST be faster than 4-MVIs? Most every control-block I’ve seen
bearing an eye-catcher is Fullword aligned in storage which makes for optimal
execution.
Keven
> On Oct 24, 2020, at 16:57, Tony Thigpen wrote:
>
> I was thinking that the MVI would be some sort o
from private to
common storage.
Keven
Sent from my iPhone
> On Nov 22, 2020, at 20:32, Joe Reichman wrote:
>
> Hi
>
>
>
> I have SRB code in my Assembly which I segregated with a CLASS via CATTR
>
>
>
> In that SRB routine I am calling CS
Any VCon or ACon moved along to CSA with the SRB code will refer to locations
in your private area and probably would not resolve satisfactorily in the
addres space the SRB is scheduled for execution
Keven
> On Nov 22, 2020, at 21:05, Joseph Reichman wrote:
>
> It would seem to m
Echoing Binyamin’s post, why is this not simply flagged by the assembler?
Assuming it’s valid code, Is the result of its execution to put the section
offset of MYLABEL in the low half of R3 (leaving the high half unaltered)?
Keven
> On Nov 24, 2020, at 00:06, Binyamin Dissen wr
Pretty sure that this constraint is related to cache-size and that your code
can cross a page boundary. Code of any length could potentially cross a page
boundary so if that were an actual constraint it would be explicitly stated
without associating it with a particular byte-length.
Keven
Do both routines use branch-entry linkage to WTO? Is there a particular reason
for using branch-entry in the function routine?
Keven
> On Mar 3, 2021, at 17:09, esst...@juno.com wrote:
>
> Hello,
> .
> I need to understand why messages written to the JOB LOG, are
> *NOT
Based on my reading of the description of the Interlocked Access Facility 2,
I'm led to assume that the following code paths are functionally equivalentt in
a multi-threaded/mutli-processing application. If I assume in error, please
feel at liberty to point out my folly.
Regards,
Hi Paul
Yes, anybody can call this PC and it will branch to the address in R1 with Psw
Key 0.
The target code probably is expected to issue a PR to return to the instruction
following the PC .
The System is basically compromised and unsecured
Regards,
Keven Hall
> On Oct 30, 2021, at
Maybe it’s the extra apostrophe on the $T attribute comparison?
Keven
> On Nov 15, 2021, at 09:28, Tony Thigpen wrote:
>
> I have a macro that works right when the the following code is actually
> 'executed':
>
> &LOPORTX SETC '&LOPORT
Simpler still: Just code the AHI instruction with a negated argument.
Keven
> On Dec 20, 2021, at 13:57, Alan Atkinson wrote:
>
> Which is just what we did - but turned it onto a macro.
>
> MACRO
> &NAMESHI &R,&I SUBTRACT HALFWORD
The second operand must end on or after the end (last byte) of the first
operand for correct results.
Regards
Keven
> On Jan 26, 2022, at 11:45, Frank M. Ramaekers
> wrote:
>
> Will this instruction work?
>
> ZAP WKPACK,WKPACK+(L'WKPACK-L'KDAYSQ
,
Keven
> On Mar 5, 2022, at 16:11, Tony Thigpen wrote:
>
> My thoughts.
>
> Since I support software that is called by any number of users, I would like
> to validate that they provided valid parms. As a called subsystem, I can't be
> messing with the callers error
Conceptually,the MVCL instruction could treat cases that specified the same
register pair
for source and target operands as a request to clean or fill the designated
storage area.
Keven
Sent from my iPhone
> On Apr 15, 2022, at 13:54, Mike Hochee wrote:
>
> I apparently stoppe
CLC DSNTOUSE,THATDSNDoes This DSN match That DSN?
BEANYPLACEYes, use This DSN
MVC DSNTOUSE,THATDSNOtherwise, use That DSN
ANYPLACE DS0H
AND ON,,, ...and on
Keven Hall
t least as much confusion as the original
un-sandwiched instruction.
Keven Hall | keh...@informatica.com
-Original Message-
From: IBM Mainframe Assembler List
[mailto:assembler-l...@listserv.uga.edu] On Behalf Of Mark Hammack
Sent: Monday, August 16, 2010 13:26
To: ASSEMBLER-LIST@LISTSE
n info I'm after is stuff like LPAR names; OS
name/version for each LPAR; total CPU capacity; CPU
allocation/weighting/capacity for each LPAR...
The data would be used for software licensing.
If this data can be obtained with existing z/OS facilities then using
them would be preferable.
K
Now I remember seeing a SHARE presentation on the BCPii. That looks
like the least treacherous path to take. I guess it's only available
from z/OS V1R10 onwards, huh?
Thank you responders and thank you HLASM community.
Keven Hall | keh...@informatica.com
Software Operative
Office: 512-795
ervals within the display space
(3270 screen, print page etc.) and that totally blows the flow.
Is there an exit for this?
Keven Hall | keh...@informatica.com
Software Operative
Office: 512-795-6959
-Original Message-
From: IBM Mainframe Assembler List
[mailto:assembler-l...@listserv.uga.
,228,194,211
&MDAT(1192) SETA 197,77,125,80,226,227,217,125
&MDAT(1200) SETA 93,0,1,215,228,213,195,200
&MDAT(1208) SETA 64,125,80,226,227,217,125,0
&MDAT(1216) SETA 80,226,227,217,64,64,64,64
&MDAT(1224) SETA 64,226,197,227,195,64,64,125
&MDAT(1232) SETA 125,0,75,212,193,195,227,247
&MDAT(1240
O .MACDAT
.*
.MACD99 ANOP ,
&I SETA 1
&STR SETC ''
.*
.MACTXT ANOP ,
AIF (&I GT N'&MDAT).MACT99
AIF (&MDAT(&I) EQ 0).MACT50
AIF (&MDAT(&I) EQ 1).MACT30
&STR SETC '&STR'.BYTE(&MDAT(&I))
AGO .MACT70
.MACT30 ANOP ,
&STR SETC '&STR'.(9)' '
AGO .MACT70
.MACT50 ANOP ,
&STR SETC DOUBLE('&STR')
PUNCH '&STR'
&STR SETC ''
.MACT70 ANOP ,
&I SETA &I+1
AGO .MACTXT
.*
.MACT99 ANOP ,
MEXIT ,
.*
.GENASM ANOP ,
MEND ,
Hints:
Assemble an invocation of the preceding macro (ignore &PARM, at least
for now).
Look at SYSLIN output.
Keven Hall | keh...@informatica.com
Software Operative
Office: 512-795-6959
You got it; it's a macro language "Quine" program. Sometimes you have
to let your geek flag fly and this is me doing just that. There's no
practical use for this macro, but the fact that it can be done says much
about the power inherent in HLASM's macro fa
More of the same, just less of it this time (this one is 44-lines
shorter than the original). Mostly this is due to the use of a table of
frequently occurring words/text-strings and single byte encoding of
multiple bytes of spaces. The code itself is considerably improved and
covers quite a lot o
I managed to mess up the formatting of the macro code in my prior
posting...
MACRO ,
MACQUINE ,
.*
.* Creates an EXACT copy of itself (Output in SYSLIN)
.*
LCLA &MDAT(1)
LCLC &KWD(1)
.*
&MDAT(1)SETA 75,92,0,9,14,1,125
&MDAT(8)SETA 9,212,193,195,2
A little off topic perhaps? Anyway, I think ISPCMDTB produces a list
sorted by command verb, and that ISPF searches tables sequentially, and
if that's actually the case then maybe a command is not being correctly
defined and/or aliased as a result.
Keven Hall | keh...@informatica.com
Sof
Are both the assembler and COBOL version invoked the same way (i.e., regardless
of which version of the program is chosen, are both either statically linked to
the main program or are they link-edited as discrete load modules)?
Keven Hall | keh...@informatica.com
Software Operative
Office: 512
If the C Programmer is allowed to cheat by using a pre-existent and
debugged set of code (in lieu of creating it from scratch), so can the
Assembler Programmer.
Interesting use of the verb "cheat"
Keven Hall | keh...@informatica.com
Software Operative
Office: 512-795-6959
-Origin
XC ECB,ECB or
ST Rx,ECB(assuming the value in Rx is zero)
This is safe even if multiple concurrent units of work exist that are
potential POSTers because the ECB is a word on a word boundary so
updates appear block concurrent to other CPUs).
Keven Hall | keh...@informatica.com
Sof
single access, block concurrent operation. Hopefully someone
in the know can confirm or refute this...
Keven Hall | keh...@informatica.com
Software Operative
Office: 512-795-6959
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Tony
There's probably a command I can send the listserv to confirm that the
list is just quiet and I really am still subscribed etc., but I'm too
lazy to go down that path and am instead going to send this to see if it
gets posted.
I think the z/Architecture FDH Optional Feature comprises most if not all of
the instructions mentioned recently.
Keven Hall | keh...@informatica.com
Software Operative
Office: 512-795-6959
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
I feel the same way about the ESEA instruction.
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Paul Gilmartin
Sent: Monday, November 21, 2011 7:25 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Conditional assembly for COBO
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