Re: [casper] Tips to speed up simulation

Hi Sebastian To add to what Dave has suggested. As you mention, significant time is taken to do the 'Update' before the actual simulation is run. To prevent having to do this every time a simulation runs, keep the design open rather than closing and re-opening. Parameter changes often do not

Re: [casper] Tips to speed up simulation

Hi, Sebastian, If you're only changing the inputs (i.e. NOT changing parameters of the CASPER blocks), you might want to consider building a test design that allows you to provide the inputs via a "Shared BRAM" block and reading the output from another "Shared BRAM" block. Then you could

[casper] Tips to speed up simulation

Hi, I am trying to simulate a model with a correlator using two pfbs+widebands ffts, and currently my biggest problem is the simulation time. For example for ~6000 cycles, the simulation takes up to 15 minutes and I would like to repeat it for like 4000 cases. I am using enabled subsystem with

Re: [casper] UFix/Fix data types and Fixed-Point Designer Toolbox

Hi Matheus, That's interesting! You might be right about the version difference. Or, maybe I was just wrong (though, as I recall, I tried compiling something relatively simple without the FP toolbox and it failed). I'd be interested to learn if you (or others) are able to compile anything more

[casper] UFix/Fix data types and Fixed-Point Designer Toolbox

Hi all, Recently, I came across an email by Jack Hickish on this list which dated back to early 2020, on which he stated that the Fixed-Point Designer was a basic minimum for compilations, given that it provided the UFix and Fix data types in Simulink (link here:

Re: [casper] Error when running SNAP tutorial

Hi Xin, Can you confirm for me your toolflow setup? Are you on ubuntu 16.04 or 18.04? Which versions of matlab and vivado are you using (2018a/2019.1)? Are you using the main casper-astro/mlib_devel or are you using the mlib_devel that is submoduled in the casper-astro/tutorials_devel

[casper] Error when running SNAP tutorial

Hello, I finished set up the tool flow, which seems to work properly. I can start the environment by running 'startsg' without any errors. But I had errors when I tried to simulate a SNAP tutorial -- snap_tut_intro.slx. Please see the error message below:

[casper] postdoctoral fellow opening at the University of New Mexico

Hi Everyone, We are advertising a postdoc position here at the University of New Mexico to work on developing and utilizing the Bifrost pipeline framework.  Since we are interested in making Bifrost into a more general purpose tool, applicants do not necessarily need a background in radio

Re: [casper] Error installing in python3 environment on SELinux7

I think your main issue is likely to be that the ROACH2 filesystem is so old the bundled version of tcpborphserver doesn't support the `upload_to_ram_and_program` infrastructure used by the latest casperfpga. Hopefully if this is the case updating your tcpborphserver (or the whole R2 filesystem)

Re: [casper] Error installing in python3 environment on SELinux7

I have not tried it so I would not like to make guarantees, but I'm not aware of any reason for it not to work. If you do try it out and run into issues, please let us know here / on the #casperfpga slack channel! On Fri, 27 Aug 2021 at 19:06, Jeb Bailey wrote: > What are your thoughts on it

Re: [casper] Error installing in python3 environment on SELinux7

What are your thoughts on it working well with ROACH2 boards from ~5 years ago? -Jeb —— Dr. J.I. Bailey, III (Jeb) / Project Scientist Mazin Lab / Department of Physics, UCSB jebbailey.com / +1 (734) 389-5143 / skype:spacecolonyone > On Aug 27, 2021, at

Re: [casper] Error installing in python3 environment on SELinux7

Hi Jeb, There are a couple of branches and forks of casperfpga that *mostly* work in python 3 - it's a work in progress, and hopefully we'll have the main branch of the repository updated soon. In the interim there is a py3 branch of casperfpga here:

[casper] Error installing in python3 environment on SELinux7

Hi Folks, We are using a lightly patched version of 0.4.3.1 (here ) related to #74 I opened. I’m trying to get our readout environment up to python 3 and in the process discovered that the change of imports (at a minimum)

RE: [casper] FW: casperfpga screenshots

Hello Indrajit, Thanks for reply. I ended up using "pip intstall ." per suggestion from Jonathon Kocz, and that worked for me. I've tried the setup.py method for casperfpga in the past and ran into problems, so maybe your suggestion will clear those problems if I ever have to try it again.

RE: [casper] FW: casperfpga screenshots

Jonathon, Thank you, “pip install .” worked, i.e. the installed casperfpga code is the same as the cloned casperfpga code. And I’m now able to write uint up to 2^32 – 1 to the software regs. It’s probably worth noting that version 0.1.1 installed when I did "pip install casperfpga", while

Re: [casper] FW: casperfpga screenshots

Hello Kobesky, Jeffrey Recently I installed casperfpga, I fixed the bug and reported it in Github, please do follow it and casperfpga will install. https://github.com/ska-sa/casperfpga/issues/105 --- Thanks and Regards Indrajit Vittal Barve On 2021-08-06 20:44, 'Kobesky, Jeffrey CIV USN

Re: [casper] FW: casperfpga screenshots

Hi Jeff, I'd have to check up on the write_int/_uint functionality, but in terms of versions, what I *think* might be happening is: If you follow the readthedocs instructions exactly, it's installing the required packages (requirements.txt) and then installing the version of casperfpga

[casper] Virtual VLA Tour: 40 Years of Science - 7 August 2021

Greetings Casperites, As the subject suggests, I've just come across a virtual VLA tour scheduled for this weekend. Information about the event and a registration link can be found here (it is free to attend). For your calendars

Re: [casper] Red Pitaya STEMlab 125-14-Z7020

Dear Mutsuo and Sebastian, Here is the CASPER hardware Red Pitaya board list - we only support 125-10 and the original 125-14. The rest will need to be added, but as Wesley said we are focusing on the Alveo boards right now. We will gladly assist you if you wish to target a new board. I would

Re: [casper] Red Pitaya STEMlab 125-14-Z7020

The old 7010 redpitaya also has sata ports, you could sync several of them using that port https://www.koheron.com/blog/2016/11/29/red-pitaya-cluster But the 7010 redpitaya ADCs uses a crystal as its main clock, so you have to move some resistances to feed another clock to the ADCs

Re: [casper] Red Pitaya STEMlab 125-14-Z7020

Hi Mutsuo, There was a small team that added support for the first 2 red pitaya boards to be used as cheap tutorial hardware for evaluation of the CASPER tools. The nature of CASPER is one of open-source and collaboration. Unfortunately many of us won't have the time to focus on making a port for

[casper] Red Pitaya STEMlab 125-14-Z7020

Dear Sirs, We are developing an InGaAs SWIR camera and hoping to use SOC-FPGA for related real-time processing in a user frendly manner. I wonder who prepared the elaborate tutorial for Casper project. It will be very nice to get the Casper module for STEMlab 125-14-Z7020 and its line by line

[casper] SKARAB and Red Pitaya Builds on Ubuntu 18.04LTS

Dear Casperities, I can't remember if I published anything officially, but I finally installed my desktop with OS Ubuntu 18.04LTS to work with the current toolflow and the planned new toolflow. I am about 6 months behind publishing this, but I can now say that the toolflow for SKARAB and the Red

Re: [casper] SNAP Fusion power chip configuration (overtemperature shutdown)

Hi Eamon, That third file is, I think, some rogue configuration from testing which should never have been committed to that repository. I suspect the 80C threshold was set (by me!) based on a sample configuration file from the KC705 development board and/or based on the data sheet's 85C max

Re: [EXT][casper] SNAP Fusion power chip configuration (overtemperature shutdown)

Eamon, Pardon me for butting in here, but it seems to me that you ought to solve over-temperature problems by redesigning the board cooling system, rather than raising the shutdown temperature in the configuration. I can offer some guidance offline, if you'd care to send me a few photos of the

[casper] SNAP Fusion power chip configuration (overtemperature shutdown)

Hello, We are having thermal shutdown problems we are pretty sure are coming from the fusion controllers, so I thought I'd have a look at the shutdown temperature thresholds to see if they could be raised. I went and loaded up the SNAP fusion power chip configuration files from

RE: [casper] SNAP error: no programming informs yet. Odd?

Hi Eamon, I hope Jack is getting some well deserved sleep. To the best of my knowledge there is no PMBus support in the FPGA. Sorry if you've already seen the Power and Schematic sections of the SNAP's wiki https://casper.ssl.berkeley.edu/wiki/SNAP but they have links to files with: PDF

RE: [casper] SNAP error: no programming informs yet. Odd?

@Jack, is there a list of which RPi GPIO pins are (un/)used in the standard SNAP board setup? They all seem to connect to the FPGA, but it’s not evident from the schematic whether they’re all used for something. Eamon From: Jack Hickish Sent: July 22, 2021 1:51 PM To: casper Subject: Re:

Re: [casper] SNAP error: no programming informs yet. Odd?

In my experience the first thing to go in the event of overheating will be the power regulators, which will trigger a shutdown of one (or more) voltage rails. I don't think there is an easy way to recover from this short of a hard power cycle. You might be able to wire one of your RPi GPIOs to a

RE: [casper] SNAP error: no programming informs yet. Odd?

Hi, After further testing, it seems that the problem is likely a symptom of the SNAP overheating inside the case. We were able to reproduce the error with the SNAP inside a thermally insulated cooler. Unfortunately, restarting the borphserver after cooling down the SNAP did not clear the

Re: [casper] System Verilog

I've been quite happy to be gaining these answers too. I'd be interested in joining a training pool if that foot note starts to snowball. Regards, Ross Donnachie On Fri, 25 Jun 2021, 13:54 Jack Hickish, wrote: > Thanks, Dave, Bob, Brian. Great suggestions all round. > > Cheers > Jack > >

[casper] Re: Cannot Join Casper List Server & Question about Error in Jasper Tutorial

Hi Kathryn, cc list Did emailing casper+subscr...@lists.berkeley.edu (as per https://casper.berkeley.edu/index.php/contact/) not work? In any case, I've added you manually, so you should be able to post directly to casper@lists.berkeley.edu from this JPL email address. Let me know if this doesn't

RE: [casper] System Verilog

Sorry, I missed the rest of a comment: >> there is “standard” way of doing things … The Mentor way, the Cadence way, the Aldec way, … you get the drift. Mentor’s Verification Academy has a lot of good resources for learning SystemVerilog, UVM, Code Coverage. On the subject of Code Coverage,

RE: [casper] System Verilog

Hi All, Cliff Cummings still does training. We have had him come to JPL to give classes in UVM. He has a good teaching style. I have his contact details if anyone is interested. (His company is now part of Paradigm-Works, another company I have used). Once you dig into UVM, you’ll find that

Re: [casper] System Verilog

If you are still looking and can afford to pay for a pro trainer check out: http://www.sunburst-design.com His website is a little out of date but if Cliff Cummings is still training he has a complete course and he has trained hundreds of people. Cliff may have something you can tag along on

[casper] Re: System Verilog

Hey Jack, A little late here but better late than never I suppose... Papers worth a read: - https://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf - http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf -

[casper] Fwd: GNU Radio conference

Howdy Casperites, See below, info about the upcoming GNU Radio conference. For those unfamiliar, GNU Radio is an open source software-defined radio project, and has a lot of crossover with CASPER's use cases and interests. As GPUs and CPUs get more powerful, there is an increasing amount of

Re: [casper] python version for casperfpga

Hi Jeff, Well done on sorting this out - looking forward to this dark energy sensor ;). Thanks for sharing these links. Just a reminder, that our toolflow supports Matlab R2018a. The GUI socket timeout issue is because you are using Matlab R2019a, I think? If you don't use Matlab R2018a, Vivado

RE: [casper] python version for casperfpga

Spiro, Adam, Thanks for the info. I’ve successfully programmed Red Pitaya_Tutorial 1, orange light is blinking, so now I can move onto dark energy sensors next (kidding). I think my main problem was I did not understand the different python environments and how they could be used with the

Re: [casper] python version for casperfpga

Hi Jeff, Please see my feedback in red below. Kind regards, Adam Isaacson South African Radio Astronomy Observatory (SARAO) Hardware Manager Cell: (+27) 825639602 Tel: (+27) 215067300 email: aisaac...@ska.ac.za On Tue, May 4, 2021 at 4:34 PM 'Kobesky, Jeffrey CIV USN NRL () Washington

RE: [casper] python version for casperfpga

Sorry, better formatting on this version: Hello CASPER, I thought I had the Python stuff figured out, but turns out I'm completely lost. I followed the instructions on this page: https://casper-toolflow.readthedocs.io/en/latest/src/How-to-install-casperfpga.html I did both the upper set of

RE: [casper] python version for casperfpga

Hello CASPER, I thought I had the Python stuff figured out, but turns out I'm completely lost. I followed the instructions on this page: https://casper-toolflow.readthedocs.io/en/latest/src/How-to-install-casperfpga.html I did both the upper set of instructions using pip, and the lower set of

RE: [casper] Computer Specs Recommendation

IMO System 76 makes nice Linux machines that are easy to specify in terms of # of cores, amount of RAM, size of NVMe, etc. Plus when you run into pesky Linux problem you can call tech support and speak with real live human Linux expert. -- jeff -Original Message- From: Michael

[casper] System Verilog

Hi CASPERites, Does anyone have any resources for learning System Verilog they've used and particularly like? Cheers Jack -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails

Re: [casper] Computer Specs Recommendation

Hi Mike, Thats great, thanks for your email. Cheers, Eoin. On 2021-04-28 12:54, Michael D'Cruze wrote: Lots of cores, lots of RAM, and an SSD primary! I worked with a six-core i7 running at 4.xxGHz and 64GB RAM, which seemed fine, but I was clearly bottlenecked by my HDDs. Definitely have an

RE: [casper] Computer Specs Recommendation

Lots of cores, lots of RAM, and an SSD primary! I worked with a six-core i7 running at 4.xxGHz and 64GB RAM, which seemed fine, but I was clearly bottlenecked by my HDDs. Definitely have an SSD... fortunately multi-TB NVMe drives are affordable now. Best, Mike -Original Message- From:

[casper] Computer Specs Recommendation

Hi Guys, Quick question. We're looking at purchasing a new computer for compiling our firmware and am wondering if anybody can recommend what specs are beneficial for speeding up compilation times? Cheers, Eoin. -- You received this message because you are subscribed to the Google Groups

[casper] Failed on SNAP tutorial 1 simulation

Hello Casper mailing list, I just installed the workflow, and I feel I installed the environment without any problem now. I have this conclusion because I can start the workflow and load the library correctly. Now I am running the tutorial 1 for SNAP by using the provided library for snap

[casper] ZCU111 Spectrum Analyzer

Hi Casperites, I’ve just released an application for the Xilinx ZCU111 FPGA board that allows you to quickly view signal spectrums, measure cable delays, measure filter magnitude/phase transfer functions and channel imbalance, view time waveforms, and generate test signals. It supports

Re: [casper] python version for casperfpga

Hi Jeff, This is great information. We had a recent "wheel" support request and it turns out it is not needed, but nice that you figured out how to install it. This should be added to our readthedocs. Thanks Jeff! Let me know how the SKARAB and Red Pitaya testing goes. Kind regards, Adam

Re: [casper] python version for casperfpga

Hi Jeff, Well done on solving your problem. I must say I missed the single underscore completely :). It is wonderful when casperites solve their own problems :). Yes, please keep me posted on Pop OS! or Pop!_OS. I had to look that up to be honest. I see it is indeed derived from Ubuntu 18.04LTS.

RE: [casper] python version for casperfpga

All good info, please keep hijacking ☺ I do want to add to the original post. I figured out the original error I got was because I used single underscores (casperfpga._version_) instead of double underscores (casperfpga.__version__) in ipython. It’s always the mundane details that get me.

Re: [casper] python version for casperfpga

Hi Jeff and everyone, While we are hacking Jeff's thread (apologies, but this will be useful info), please note that our toolflow only supports the following Red Pitaya devices: STEMlab125-10 (10 bit ADC and DAC) and STEMlab125-14 (14 bit ADC and DAC). There are another three Red Pitaya boards

Re: [casper] python version for casperfpga

Hi all, To add to Amish's info, for ease of access, the design files for said projects can be found here . Morag (Sorry Jeffrey!) On Wed, Apr 14, 2021 at 7:55 AM Amish Patel wrote: > Xin chào, Hien, > > CASPER's

Re: [casper] python version for casperfpga

Xin chào, Hien, CASPER's Tutorials have three small projects that use the Red Pitaya with the CASPER toolflow. First, you will need to do some general setup

Re: [casper] python version for casperfpga

Greeting Can any one point out the link to some small projects that use the Red Pitya board with the CASPER flow ? Regards Hien Vo Vietnamese German University On Tue, Apr 13, 2021 at 9:59 PM Adam Isaacson wrote: > Hi Jeff, > > The toolflow is normally used with a Python virtual environment

Re: [casper] python version for casperfpga

Hi Jeff, The toolflow is normally used with a Python virtual environment setup with Python 3. The casperfpga tool (provides comms to the board) uses just python 2.7. This is the way we use the toolflow and casperpfga at SARAO (South African Radio Astronomy Observatory). We support the SKARAB and

[casper] python version for casperfpga

Hello CASPER, I'm installing tool flow and am confused about which python version to use for casperfpga. I have both python 2.7 and 3.6 on my machine. For my equipment (red pitaya and skarab) this link https://casper-toolflow.readthedocs.io/en/latest/ says to use python3. But if I follow

[casper] Casper workshop-- abstracts due today

Dear all, This is just a reminder that today, April 12, is the last day to submit abstracts for the 2021 Casper workshop (the form will stay open until Tuesday morning Pacific time in case this reminder is arriving late in your time zone). The workshop will be held online May 17-20 and there is

Re: [casper] snap tutorial 3

On Fri, 9 Apr 2021 at 17:59, Guillermo Gancio wrote: > Hi Jack, > > Excellent! yes, with that I can read all the data with casperfpfa > 1024*8, and I can see a "proper" spectrum, but other issue appear > (that I didn't notice before) while configuring the synthesizer with > >

Re: [casper] snap tutorial 3

Hi Jack, Excellent! yes, with that I can read all the data with casperfpfa 1024*8, and I can see a "proper" spectrum, but other issue appear (that I didn't notice before) while configuring the synthesizer with adc.init(samplingRate=800, numChannel=1) it takes more than 20 secs, and on the

Re: [casper] snap tutorial 3

Hi Guillermo, Interesting. So, if I understood your last few emails, you can read the whole bram fine if you do so one word at a time. But if you read 512 bytes or more things break. The answer is somewhere in bulk_read in spifpga_user.c, I think. But I wonder, if you change MAX_BURST_SIZE

Re: [casper] snap tutorial 3

Hi Jack, I have been doing more tests, and I notice the following on the raspberry pi tcpborphserver3 Log When I do Casperfpga -> fpga.read('even',512,0) on the Rpi tcpb3 log I got: data added is 522, needed at least 10 + 513 Now if I do, fpga.read('even',1024*8,0), or any number of bytes

Re: [casper] ROACH-2: Identifying Spurs in FFT of Noise Spectrum

Hi Benjamin, I haven't read the full thread, so not sure if you detailed sampling frequencies, etc., but in our testing of ROACH and ROACH2, we found the biggest culprit to be a bus signal that never leaves the PowerPC, and (if memory serves) causes the biggest spur at 133 MHz (and of course

Re: [casper] ROACH-2: Identifying Spurs in FFT of Noise Spectrum

Well put Dan. fyi. IEEE 1241-2010 describes a few ways to test ADCs. https://ieeexplore.ieee.org/document/5692956 Online searches find the -2010 version at http://class.ece.iastate.edu/djchen/ee509/2018/IEEE1241-2011.pdf The older version, IEEE 1241-2000, is also easy to find on the WWW.

Re: [casper] snap tutorial 3

Hi, I'm using the prebuild fpg and a build by me fpg, both with the same result. I did try as you mention to see how much can I read with CasperFpga.read_uint increasing the offset and I can read up to 2048 values before the error appear, I think that's ok, as the u_int read 32 bits, and I have

Re: [casper] snap tutorial 3

On Wed, 7 Apr 2021, 2:57 pm Guillermo Gancio, wrote: > Hi, > > I'm using the tutorials from > https://github.com/casper-astro/tutorials_devel/tree/master/snap/tut_spec > I just clone them and I got the same result, could be an issue with > the katcp installation on the snap-raspberry? > You're

Re: [casper] snap tutorial 3

Hi, I'm using the tutorials from https://github.com/casper-astro/tutorials_devel/tree/master/snap/tut_spec I just clone them and I got the same result, could be an issue with the katcp installation on the snap-raspberry? I'm also checking the casperfpga installation... Cheers. El mié, 7

Re: [casper] snap tutorial 3

Hi Guillermo, If the values are 64 bits in the model, it is suspicious that the reads are 1024*4 Bytes. I notice that in the latest tutorials_devel the reads are 1024*8 bytes (

Re: [casper] snap tutorial 3

Hi Jack, What I understand from the tutorial, and correct me if I'm wrong, is: Size of PFB and FFT, 2^12 i.e Re+Im 4096 channels, that's 2048 frequency channels after obtaining power values from the complex values. Those 2048 channels end up in two registers 'even' and 'odd' of 2^10 i.e. 1024

Re: [casper] snap tutorial 3

Hi Guillermo, How many channels is that tutorial supposed to generate? It looks like the RAM is smaller than expected by the software. Is it possible that each even/odd RAM is supposed to be 512*4 (i.e., 512 words, each 32-bits wide) for 1024 channels total? Cheers Jack On Mon, 5 Apr 2021 at

[casper] Casper workshop: reminder abstract submission deadline April 12

Dear all, This is just a reminder to please submit abstracts for the Casper workshop by April 12. The 2021 Casper workshop will be held online May 17-20 and there is no fee. More details as well as registration and abstract submission are on the workshop webpage here:

[casper] snap tutorial 3

Hi Casperities (?) I'm going thru the tutorial 3 on a snap board, and I have some issue/error while reading the 'odd' and 'even' register, when reading with -> a_0=struct.unpack('>1024l',fpga.read('even',1024*4,0)) I end up with the error -> Request: ?read odd 0 4096 -> Reply: !read fail but if

Re: [casper] Failed to install `virtualenv`

Hi Xin, Thanks for letting us know - it is useful to have the feedback. I think the gratitude must go to Morag here :). Kind regards, Adam Isaacson South African Radio Astronomy Observatory (SARAO) Hardware Manager Cell: (+27) 825639602 Tel: (+27) 215067300 email: aisaac...@ska.ac.za On

RE: [casper] Failed to install `virtualenv`

Hi Morag, Adam, I would like to give you an update on my toolflow configuration. As Morag suggested, the errors message I posted in my previous email are not problems for the toolflow configuration. I finished all the configuration following the steps in the instruction, now I can start up the

Re: [casper] Failed to install `virtualenv`

Hi Xin, Morag explained it very well and has actually updated the readthedocs with all the necessary information - just checked my notes. The readthedocs section has actually been updated with the correct info, so my instructions won't help. I have been able to install without the wheel issue,

Re: [casper] Failed to install `virtualenv`

Hi Xin, Using virtualenv no longer works - people smarter and more knowledgeable than I way know why. As an alternative, you can use "*python3 -m venv*" to create a virtual environment. Sourcing the venv is the same (*source /path/to/venv/bin/activate*), and then install the requirements.txt

[casper] Failed to install `virtualenv`

Hello, I am trying to set up working environment to run SNAP. According to the instruction, I finished the installation of Matlab and Vivado on Ubuntu16.04. Now I am trying to create Python3 virtual environment. I failed to install the virtual environment by running `sudo pip3 install

Re: [casper] casperfpga on python3

Hi Guillermo, The branch that Danny sent you is the correct branch to use https://github.com/casper-astro/casperfpga/tree/py3-merge. The branch in the ska-sa repo is still a work in progress and needs to be fully tested. I have a feeling that both branches may not work for the SKARAB hardware -

Re: [casper] casperfpga on python3

Hi Danny, Thank you very much, it seems to be ok! What I did was... Clone the git, change the branch to py3-merge, pip install -r requirements, python setup.py install... Then from from Ipython I got: In [1]: import casperfpga In [2]: casperfpga.__version__ Out[2]:

Re: [casper] casperfpga on python3

Hi Guillermo, You could try this branch: https://github.com/casper-astro/casperfpga/tree/py3-merge This works for my purposes in Py3 (with the snap board), with the *huge* caveat that adc calibration doesnt work. (Ive heard that this has been solved by Aaron and Jonathon but not merged).

[casper] casperfpga on python3

Dear all, I'm trying the python3-port of casperfpga, from https://github.com/ska-sa/casperfpga/tree/python3-port I had to fix some minnor issues like "except KatcpClientError, e: " to "(except KatcpClientError, e): and "from thread" to "from _thread" which I'm not sure if they are ok And then

Re: [casper] quantum entanglement sensing using high-speed digital sampling and cross-multiplies

Hi Neil, Yes, we use Python 3 for our CASPER toolflow (with a virtual python environment) and our comms package casperfpga is written in Python 2.7. We are working on a Python 3 version. The tooflow consists of a frontend, middlend and backend. The frontend, middlend and backend all use Python.

Re: [casper] quantum entanglement sensing using high-speed digital sampling and cross-multiplies

Hi Neil, If you want to use the CASPER libraries, you will still need a Matlab/Simulink and toolbox (DSP system, Signal Processing and Fixed Point Designer) licenses. The hardware could be used without it and you will still be able to gain from the libraries, but it will be much more work. On the

Re: [casper] quantum entanglement sensing using high-speed digital sampling and cross-multiplies

hi neil, if you want to sample your band with breaking it up into sub-bands, there are a few samplers at 60 Gsps and beyond. vadatech has a pricy 8 bit 56 Gsps ADC board. jpl and jonathan kocz got one, but i don't think they've had a chance to play with it yet. intel recently demo'ed a 64 Gsps

RE: [casper] quantum entanglement sensing using high-speed digital sampling and cross-multiplies

Hi Dan, Thanks for those great options. Those sampling rates are the sort that I’m looking for. I can probably operate with a smaller RF band to start with, to make the task a little less difficult. Hi Francios, Thanks for helping out here. I don’t have academic licences but I could

Re: [casper] quantum entanglement sensing using high-speed digital sampling and cross-multiplies

hi neil, there's a quad 16 Gsps 4 bit ADC FMC board developed by CFA/Smithsonian that connects to a VCU128 FPGA board that might be useful for your work. the analog bandwidth of the ADC doesn't get up to 30 GHz, so you'd have to mix down your band before digitizing. you could break your 20 GHz

Re: [casper] quantum entanglement sensing using high-speed digital sampling and cross-multiplies

Hi Neil, Second question first - you can access CASPER technology from anywhere. The software licensing may be different if you do not get academic discounts from Mathworks, and Xilinx may also charge you something depending on your exact situation. Both companies are generous to academic users.

[casper] quantum entanglement sensing using high-speed digital sampling and cross-multiplies

Dear All, Would it be possible to access Casper technology for research into quantum entanglement sensing for the micro/mm-wave band? To explore some sensor concepts I'd be looking to make 4-bit sampling of radiation in the band 10 GHz to 30 GHz at something like 10 Gsps. I'd need to

[casper] Fwd: Postdoctoral position on VLA commensal science

Hi CASPERites, In case any of you are interested in SETI science with oodles of data from the VLA, please see the below job posting from Cherry Ng. Cheers Jack -- Forwarded message - From: Cherry Ng Date: Mon, 15 Mar 2021 at 19:44 Subject: Postdoctoral position on VLA commensal

[casper] Casper workshop May 17-20 2021: registration open

Dear all, The 2021 Casper workshop will be held online May 17-20 and will be free to attend. Registration is open now and abstracts are due by April 12. Please find more details and register on the workshop webpage here: https://casper.berkeley.edu/index.php/casper-workshop-2021/. The

Re: [casper] general SNAP toolflow setup guidance

Hi Eamon, 1. Is it likely to work with more recent versions of any of these components? System generator and Vivado are *very* finicky as to version compatibility. You could update Ubuntu if you were really keen (it will run on 18.04, but with caveats (e.g. you have to install kde-full,

[casper] general SNAP toolflow setup guidance

Hello, A colleague and I are just getting started setting up a build environment for SNAP. We have a few general questions. 1. Seeing the relatively old versions of Ubuntu, MATLAB and Vivado with which the toolflow has been tested, it's tempting to wonder if something more recent is

[casper] videos from CASPER W/S and BH PIRE DSP School 2019!

Dear CASPERites and 2019 Workshop/DSP School attendees, Sorry it took so long to post-produce and publish the video lectures and research presentations from CASPER 2019. I (Jonathan) massively underestimated the volume and difficulty (to one not trained) of the editing task. Things only

Re: [EXT]Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

hi colm, for slack discussion on RFSOC2x2, i suggest using the RFSOC slack channel for now, rather than the ZCU111 channel. if there is a lot of traffic, we could make a dedicated channel for the 2x2 board... bit streams for ZCU111 and RFSOC2x2 are likely not compatible, because FPGA pinouts

Re: [EXT]Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

That is what I was planning Dan, to use the 2 x USB 3.0 (as well as the 1G Ethernet), we should get just over 10Gbit/sec. I do not know much about zysygy data connectors. An FMC+ port would have been great! Placing order this week hopefully! Is there a need for a '2x2' channel on Slack, or is

Re: [EXT]Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

it's not easy to get high bandwidth ethernet data off this RFSOC2x2 board: there's a standard parallel zysygy data connector on the board (13 LVDS pairs or 26 single ended), and there are small commercial $300 fpga boards that have several zysygy connectors including high speed serdes zysygy

Re: [EXT]Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

Thanks! It seems that I did not guess the correct search words :-) Interesting... Cheers, Kaj On 09/03/2021 17:33, Forbes, David C - (dforbes) wrote: Kaj, A quick Google search reveals all... https://www.xilinx.com/support/university/boards-portfolio/xup-boards/RFSoC2x2.html

RE: [EXT]Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

Kaj, A quick Google search reveals all... https://www.xilinx.com/support/university/boards-portfolio/xup-boards/RFSoC2x2.html -Original Message- From: Kaj Wiik Sent: Tuesday, March 9, 2021 7:21 AM To: casper@lists.berkeley.edu Subject: [EXT]Re: [casper] low cost academic xilinx RFSOC

Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

Hi! Did the tutorial reveal any further info (spec sheet, availability) of this board? Thanks, Kaj On 16/02/2021 16:36, Francois Kapp wrote: Hi Colm, We discussed this and it appears that only two of the ADC's and DAC's will be routed to connectors, hence the 2x2.  Dan has already asked

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