Re: [casper] CASPER Advisory Board

Hi Francois: This is Homin from Taiwan. Hope all is well with you. I would like to nominate Mitch Burnett as a new member of the advisory board. Mitch has come up with a whole set of RFSoC stuff, it is a great contribution to the community. Grabbing him in the advisory board will make him

[casper] X engine green block

t -> latency -> change "convert latency" from 1 to 0. -- If you used directly, the output will not be exactly correct. best regards homin jiang -- You received this message because you are su

Re: [casper] casperites receive breakthough prize

breakthrough event by casperites. Best Regards. Homin Jiang On Fri, Sep 6, 2019 at 12:06 AM Dan Werthimer wrote: > > > casperites, > > several casper people received the breakthrough prize today for making the > first image of a black hole, > including jonathan weintroub, homi

Re: [casper] VCU118 Support

Hi Jack: I modified the vivado version from 2018.2 to 2018.1 in a file under cont_microblaze. The compilation is fine and completed. Bitcodes are generated. I have the UART output as following. My problem is the DHCP i guess. Looks like the DHCP didn't work. Usually, the led right next to the

Re: [casper] Vivado System Generator cannot find parts

Hi Arash and all : I tried Vivado 2018.1 with Matlab 2018a under scientific Linux 7.0, after struggling a while, it is fine now. Back to "hardware porting" workshop last summer, l had the issue of FPGA model name as Adam mentioned. It have to be exactly the same. best regards homin On Fri, Dec

Re: [casper] New Wideband Spectrometer Designs

eous upper and lower sidebands are >> required) >> >> Or we could move on to newer ADCs and processing boards, and get the full >> 4 GHz from each polarization in one go. I think this is preferable, for >> many reasons. >> >> The key here, I think, is the ADCs

[casper] position for digital expert for ALMA development in Mitaka

Hi all: There is job opportunity in Japan. https://www.nao.ac.jp/en/contents/job-vacancy/job-20180702-chile-en.pdf best homin jiang -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this grou

Re: [casper] packets lost of a packetized correlator

clock that goes through a massive splitter) or just a clock of the same >> frequency locked to the same reference (but not the exact same clock)? >> Things get more complicated once you run F and X at different rates, so I >> wouldn't recommend that path if you can avoid it. >>

Re: [casper] packets lost of a packetized correlator

plicated once you run F and X at different rates, so I >> wouldn't recommend that path if you can avoid it. >> >> HTH, >> Dave >> >> >> On Mar 12, 2018, at 22:01, Homin Jiang <ho...@asiaa.sinica.edu.tw> wrote: >> >> Hi Dave: >> >> Thanks of

Re: [casper] packets lost of a packetized correlator

ing and outgoing data rates are > on the various ports involved. > > Does your design have any way of capturing the overflow flags of the 10 > GbE cores? > > Dave > > On Mar 12, 2018, at 19:39, Homin Jiang <ho...@asiaa.sinica.edu.tw> wrote: > > Dear Casperite: &g

[casper] packets lost of a packetized correlator

yellow block. Any comments of suggestions are highly welcome. best homin jiang -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to caspe

Re: [casper] Writing calibrated data to QDR of ROACH2

s) so you'd have to > count the steps during calibration, and then save these somewhere ready to > be reloaded after reprogramming. > > Cheers > Jack > > On Sun, 21 Jan 2018 at 17:34 Homin Jiang <ho...@asiaa.sinica.edu.tw> > wrote: > >> Dear Folks: >> >>

[casper] Writing calibrated data to QDR of ROACH2

Dear Folks: This might be a trivial question. Is there a way to write the QDR calibrated data to ROACH2 ? It will save time if we don't have to do it every time. best homin jiang -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu&q

[casper] EMI test data of ROACH2

Hello: Did anyone carry out the EMI measurement for ROACH-2 ? Highly appreciate of sharing the information. regards homin jiang

[casper] 32 parallel input to fft_wideband_real

Dear all: I have trouble in the output order of the fft_wideband_real which i fed 32 parallel inputs. I marked the "unscramble output". The output sequence seems not in order as the 8 or 16 parallel inputs fft does. Has anyone tried the 32 input to the fft block ? Comments are highly appreciate.

Re: [casper] 32 parallel inputs to fft_wideband_real

at 12:38 AM, Jack Hickish <jackhick...@gmail.com> wrote: > Hi Homin, > > What total size of FFT are you trying to do? How does the FFT fail? > > Cheers, > Jack > > On Mon, 11 Jan 2016 at 00:35 Homin Jiang <ho...@asiaa.sinica.edu.tw> > wrote: > >> Hello:

[casper] QDR control of V14.7

Hello: Recently I upgraded my toolflow from V14.4 to V14.7. In V14.4, the QDR can work properly without any control from Python. In V14.7, the QDR didn't work that way, so i want to make sure that is there any activation command by Python code ? regards homin jiang

[casper] constraints for qdr2/ROACH2

in hand to share with ? regards homin jiang

Re: [casper] software register

, Homin Jiang ho...@asiaa.sinica.edu.tw wrote: Hello: I am upgrading my system to xilinx 14.7 with Matlab 2012a and up to date mlib_devel library. I encountered errors by the software register in XPS library. Any one can help ? thanks homin

[casper] software register

Hello: I am upgrading my system to xilinx 14.7 with Matlab 2012a and up to date mlib_devel library. I encountered errors by the software register in XPS library. Any one can help ? thanks homin

Re: [casper] casper Digest, Vol 65, Issue 38

Hi Haoxuan: There is a bug in Planahead V14. It works fine with the ngc files generated by the version older than 14. If the ngc files are generated by V14 itself, the planahead won't work. I opened a xilinx webcase CASE:966795, but no answer so far. cheers homin On Wed, May 1, 2013 at 3:14

Re: [casper] casper Digest, Vol 65, Issue 38

Hi : I should make my statement more precise. I have problems on Planahead V14.3 and V14.4. Couple of groups said that the V14.2 works fine. regards homin On Wed, May 1, 2013 at 3:14 AM, casper-requ...@lists.berkeley.edu wrote: Send casper mailing list submissions to

Re: [casper] No ADC clock signal in ROACH2 Rev. 2

the correct bitcode which provides that reset. Jonathan On Apr 18, 2013, at 10:27 PM, Homin Jiang wrote: Dear Rurik: I downloaded the library from github/ska-sa at Jan 21,2013. Could you specify where is the floating reset line ? that might give me some hints. Dear Mark and Glenn

[casper] No ADC clock signal in ROACH2 Rev. 2

homin jiang

Re: [casper] No ADC clock signal in ROACH2 Rev. 2

to rev2. Are you still running a design that was compiled for rev1? Regards Henno On Thu, Apr 18, 2013 at 2:22 PM, Homin Jiang ho...@asiaa.sinica.edu.twjavascript:_e({}, 'cvml', 'ho...@asiaa.sinica.edu.tw'); wrote: Hello: After couple of tests, we found that the ADC clock signal

Re: [casper] No ADC clock signal in ROACH2 Rev. 2

pins to the FPGA from rev1 to rev2. Are you still running a design that was compiled for rev1? Regards Henno On Thu, Apr 18, 2013 at 2:22 PM, Homin Jiang ho...@asiaa.sinica.edu.tw**javascript:_e({}, 'cvml', 'ho...@asiaa.sinica.edu.tw'); wrote: Hello: After couple of tests, we found

[casper] ADC 1x5000-8 1:2 boards

Dear Ross: I will check our inventory. I guess we still have some. I am interested to know why not 1:1 ? cheers homin

[casper] 16 ports of ADC

? cheers homin jiang

Re: [casper] F engine for Packetized correlator

a sense of packetized correlator. -- Regards, Homin Jiang(¦¿§»©ú)

Re: [casper] casper Digest, Vol 25, Issue 16

to the tgtap call. Jason On 22 Dec 2009, at 10:49, Homin Jiang wrote: Hi Jason: Are there stable model files for packetized correlator on ROACH ? I saw there are 2 model files in the /roach subdirectory, but with comments of lots of stuff here for debug . cheers homin jiang Today's Topics: 1

Re: [casper] casper Digest, Vol 25, Issue 16

Hi Jason: Are there stable model files for packetized correlator on ROACH ? I saw there are 2 model files in the /roach subdirectory, but with comments of lots of stuff here for debug . cheers homin jiang Today's Topics: 1. roach reference designs (Jason Manley

[casper] /3GB

' passed with computer time of 5:18:42. I compiled it again with computer time of 04:15:30. http://blogs.technet.com/askperf/archive/2007/03/23/memory-management-demystifying-3gb.aspx Cheers homin jiang

Re: [casper] /3GB

wrote: Hello, For me, I just put the /3GB option in boot.ini. Everything just works fine. Zhiwei On Tue, Nov 17, 2009 at 8:42 PM, Homin Jiang ho...@asiaa.sinica.edu.tw wrote: Hello: I am writing this email just for record. I met the same problem as ZhiWei had in OCt 13,2009 while compiling

[casper] ROACH pin assignment

the detail of each pin assignment ? for example : i would like to know where it goes of the zdok0_p_18. cheers homin -- Regards, Homin Jiang(¦¿§»©ú)

Re: [casper] ADC initiate software

a borph iadc driver exists, but it would be a good thing to have. Regards, David -- Regards, Homin Jiang(¦¿§»©ú)

[casper] ADC initiate software

. Homin Jiang(¦¿§»©ú), ho...@asiaa.sinica.edu.tw http://www.asiaa.sinica.edu.tw/~homin/

[casper] SPI driver

, that is why i am looking for the device driver. Anyone has suggestion of SPI programming on ROACH is highly welcome. -- Homin Jiang(¦¿§»©ú), ho...@asiaa.sinica.edu.tw http://www.asiaa.sinica.edu.tw/~homin/ Tel:(02)3365-2200 ext:788 Fax:(02)2367-7849 P.O. Box 23-141, Taipei, Taiwan, 106 Institute

[casper] USB and done bit not asserted

got the same problem as Wan Cheng had in May 14. SelectMap - Done pin has not been asserted. Is there something missed in my Linux setup ? -- Regards, Homin Jiang(¦¿§»©ú)

Re: [casper] USB and done bit not asserted

with LX110s and not the SX devices. Regards Alec Homin Jiang wrote: Hello: Couple of trials here shown that 2 GB USB works well in current configuration. I have tried 4 G, 8 G, both of them didn't work. Key in USB start in UBOOT didn't help. It would be a temporary solution. I tried to run one

[casper] bug report -- opb_adccontroller_v1_00_a -- user_logic.vhd

the compilation with error of ERROR:HDLParsers:715 - user_logic.vhd Line 179. Attribute on units are only allowed on current unit. Regards, Homin Jiang(¦¿§»©ú)

Re: [casper] Missing downsample

Hi Glenn: You are right. The problem is gone after i include the signal processing blockset . Thanks a lot homin G Jones wrote: I believe this is in the Simulink signal processing blockset or communications blockset. Glenn On Sun, Nov 9, 2008 at 5:28 PM, Homin Jiang ho