Word length. :)
> On Jun 9, 2024, at 10:40 AM, Murray McCullough via cctalk
> wrote:
>
> Intel introduced to the world the x86 processor: the CISC technology still
> with us. So what has changed other than speed and upward development?
>
> Happy computing,
>
> Murray 🙂
On 6/9/24 08:40, Murray McCullough via cctalk wrote:
> Intel introduced to the world the x86 processor: the CISC technology still
> with us. So what has changed other than speed and upward development?
The Internet?
Really, it's always been my view that computational technical progress
has long b
On 6/9/24 09:59, Milo Velimirović via cctalk wrote:
> Word length. :)
Scarcely innovative. 64 bit architectures predated the 64-bit x86 by
decades. Call it a natural evolution.
Don't forget cheap memory.
--Chuck
On 2024-06-09 10:59 a.m., Milo Velimirović via cctalk wrote:
Word length. :)
On Jun 9, 2024, at 10:40 AM, Murray McCullough via cctalk
wrote:
Intel introduced to the world the x86 processor: the CISC technology still
with us. So what has changed other than speed and upward development?
Happ
On 2024-06-09 11:01 a.m., Chuck Guzis via cctalk wrote:
On 6/9/24 08:40, Murray McCullough via cctalk wrote:
Intel introduced to the world the x86 processor: the CISC technology still
with us. So what has changed other than speed and upward development?
The Internet?
Really, it's always been
I think the biggest change is our compute resources stopped going faster
in terms of raw cycles per second, and started going wider in terms of
parallelism. It's now commonplace for me to run workloads that can actually
use many CPU cores, and I'm starting to occasionally run workloads that are
so
Highly parallel workloads are an important niche in computing.
On Mon, 10 June 2024, 8:48 am Scott Baker via cctalk,
wrote:
> I think the biggest change is our compute resources stopped going faster
> in terms of raw cycles per second, and started going wider in terms of
> parallelism. It's now
I agree that parallelism, or more accurately multiprocessing, has
contributed a great deal to the advancement of 8086 technology. So to has
speed: The first 8086 was clocked at 5Mhz.; now the speed is 6Ghz. The
shrinkage of computer components in ULSIC technology has made this
possible. But today I
On Sun, 9 Jun 2024, Murray McCullough via cctalk wrote:
I agree that parallelism, or more accurately multiprocessing, has
contributed a great deal to the advancement of 8086 technology. So to has
speed: The first 8086 was clocked at 5Mhz.; now the speed is 6Ghz. The
shrinkage of computer componen
No one is mentioning multiple processors on a single die and cache that is
bigger than most systems of that times complete RAM.
Clock speed was dealt with clever register reassignment, pipelining and
prediction.
Dwight
On 10/06/2024 00:28, ben via cctalk wrote:
The CPU Price it keeps going UP ... :(
8008 $25 1975
8080 $75 MITS kit 1975
8088 $125
386 $130 (286 $20)
Hardly, you can pick up a new CPU today for less than $50. It's not
going to be particularly fast, but it'll run circles round most decade
old CP
On 10/06/2024 05:54, dwight via cctalk wrote:
No one is mentioning multiple processors on a single die and cache that is
bigger than most systems of that times complete RAM.
Clock speed was dealt with clever register reassignment, pipelining and
prediction.
Dwight
Pipelining has always been a
It's interesting and probably indicative of some mindset where a
discussion of the evolution of a given architecture is being discussed
that specific technical aspects are most often mentioned, even though
most of those are holdovers from the 1960s, just made smaller.
My take is "why were these ad
> On Jun 10, 2024, at 12:18 PM, Joshua Rice via cctalk
> wrote:
>
> On 10/06/2024 05:54, dwight via cctalk wrote:
>> No one is mentioning multiple processors on a single die and cache that is
>> bigger than most systems of that times complete RAM.
>> Clock speed was dealt with clever registe
On 2024-06-10 10:18 a.m., Joshua Rice via cctalk wrote:
On 10/06/2024 05:54, dwight via cctalk wrote:
No one is mentioning multiple processors on a single die and cache
that is bigger than most systems of that times complete RAM.
Clock speed was dealt with clever register reassignment, pipelinin
On 2024-06-10 10:05 a.m., Joshua Rice via cctalk wrote:
On 10/06/2024 00:28, ben via cctalk wrote:
The CPU Price it keeps going UP ... :(
8008 $25 1975
8080 $75 MITS kit 1975
8088 $125
386 $130 (286 $20)
Hardly, you can pick up a new CPU today for less than $50. It's not
going to be particula
On Tue, 11 Jun 2024, ben via cctalk wrote:
Gates's law "The speed of software halves every 18 months"
Isn't it more similar to Boyle's law?
Software expands to require slightly more than the available memory.
On Mon, Jun 10, 2024 at 05:18:56PM +0100, Joshua Rice via cctalk wrote:
[...]
> DEC came across another issue with the PDP-11 vs the VAX. Although the
> pipelined architecture of the VAX was much faster than the PDP-11, the
> actual time for a single instruction cycle was much increased, which led
On 6/12/24 01:02, Peter Corlett via cctalk wrote:
> Fun factoid: despite modern x86 being clocked ~1000x faster than ye olde
> 6502, there's not much in it between them when it comes to interrupt
> response time. If all goes well, x86 takes "only" a hundred-ish cycles to do
> its book-keeping and
On 6/12/24 03:02, Peter Corlett via cctalk wrote:
Fun factoid: despite modern x86 being clocked ~1000x faster than ye olde
6502, there's not much in it between them when it comes to interrupt
response time. If all goes well, x86 takes "only" a hundred-ish cycles to do
its book-keeping and jump t
Even without things like system management mode, there are lots of speed-up
features on modern processors that result in variable execution times -
things like caching and pipelining. With sufficient care these can
sometimes be made predictable but there are certain common needs that
have always f
On 2024-06-13 9:40 a.m., Jon Elson via cctalk wrote:
AACK! Sorry, that was supposed to be F-16!
The divide bug strikes again.
Jon
What would one use today instead of the 586?
Ben.
On 6/13/24 10:32, Paul Koning via cctalk wrote:
> Huh? There is no direct connection between word length, register count, and
> pipeline length.
Indeed. There are architectures with NO user-addressable registers.
Some have memory-mapped registers, where a "register number" is merely
shorthand
> On Jun 11, 2024, at 11:52 PM, ben via cctalk wrote:
>
> On 2024-06-10 10:18 a.m., Joshua Rice via cctalk wrote:
>> On 10/06/2024 05:54, dwight via cctalk wrote:
>>> No one is mentioning multiple processors on a single die and cache that is
>>> bigger than most systems of that times complete
On 6/12/24 09:52, Jon Elson via cctalk wrote:
On 6/12/24 03:02, Peter Corlett via cctalk wrote:
Fun factoid: despite modern x86 being clocked ~1000x
faster than ye olde
6502, there's not much in it between them when it comes
to interrupt
response time. If all goes well, x86 takes "only" a
hu
Even earlier than the TPU on the 68332 is the communications
co-processor built into the 68302. This predate the entire CPU-32 family.
On 6/13/2024 10:56 AM, Adrian Godwin via cctalk wrote:
Even without things like system management mode, there are lots of speed-up
features on modern processor
> On Jun 13, 2024, at 2:00 PM, Chuck Guzis via cctalk
> wrote:
>
> On 6/13/24 10:32, Paul Koning via cctalk wrote:
>> Huh? There is no direct connection between word length, register count, and
>> pipeline length.
> Indeed. There are architectures with NO user-addressable registers.
> So
Chuck Guzis wrote:
> Scarcely innovative. 64 bit architectures predated the 64-bit x86 by
> decades. Call it a natural evolution.
I'm kinda surprised that nobody has mentioned this ...
But.. even less innovative than that! - the subject mentions "8086" and 46
years - the 8086 was only a 16 bi
On 2024-06-13 11:32 a.m., Paul Koning via cctalk wrote:
e up an entire chassis, 750-ish logic modules.
You never see a gate level delays on a spec sheet.
Our pipeline is X delays + N delays for a latch.
Gate level delays are not interesting for the machine user to know. What is interesting
On 2024-06-13 12:06 p.m., Paul Koning via cctalk wrote:
On Jun 13, 2024, at 2:00 PM, Chuck Guzis via cctalk
wrote:
On 6/13/24 10:32, Paul Koning via cctalk wrote:
Huh? There is no direct connection between word length, register count, and
pipeline length.
Indeed. There are architecture
On 2024-06-13 4:30 p.m., Dave Dunfield via cctalk wrote:
I think the 86 came at a good time/place because the 8080 series had become
quite popular in microcomputers
and designers were feeling the limits of a 8-bit architecture - the 86 provided
a fairly powerful (for the time) and
easy upgrade
On 6/14/24 08:13, Paul Koning via cctalk wrote:
> You compare machines by what they deliver. The purpose of computers is not
> to deliver logic circuits but to deliver computation, so comparing
> computational ability (speed and size) is meaningful, along with cost. How
> it's implemented und
> On Jun 13, 2024, at 7:31 PM, ben via cctalk wrote:
>
> On 2024-06-13 11:32 a.m., Paul Koning via cctalk wrote:
> e up an entire chassis, 750-ish logic modules.
>>
>>> You never see a gate level delays on a spec sheet.
>>> Our pipeline is X delays + N delays for a latch.
>> Gate level dela
ben wrote:
>> My own entry into the "microprocessor"
>> design fray was something I called the: C-FLEA
>> A very tiny/simple 16 bit CPU that was very optimal as a target for
>> my C compiler.
>> Never did see it to silicon, but did quite a few "virtual machines"
>> - this let me efficiently put C c
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