On Sat, Jul 09, 2011 at 05:04:43PM +0200, Florentin Demetrescu wrote:
>
> - my objective was to install coreboot on my new board MA785GMT-UDH2. I had
> bring with me a Phenom II 1055T CPU with 6 cores. Unfortunately I met big
> problems because:
[...]
> coreboot and give it a run, but I will do th
I've just seen these news about a new vehicle PC with
5 seconds boot time thanks to coreboot, but there is
no information on pricing, software (if any, maybe it
is sold without hard disks ?) or firmware (apparently
they would ship it with coreboot, but the datasheet
does only say "supports AMD
On Wed, Aug 24, 2011 at 03:37:58PM -0700, SAL-e wrote:
> Hi,
>
> I have old Asus M3A78-EM [1] board inside my HTPC. I'm looking to
> speed up the boot process of my HTPC. I have heard that coreboot can
> boot directly into Linux or GRUB. I checked the supported list and
> found out that my board i
On Tue, Sep 13, 2011 at 12:18:24PM +0200, Paul Menzel wrote:
> > src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE
> > /F10MicrocodePatch01bf.c
>
> 2. I do not understand the commit message. What do you mean with patch
> file? In this patch you are only adding a header file.
>
It
On Tue, Jan 10, 2012 at 10:41:49PM +0100, Paul Menzel wrote:
> Am Dienstag, den 10.01.2012, 19:50 +0100 schrieb Denis 'GNUtoo' Carikli:
> > Thanks a lot
>
> I second that! Thank you very much and congrats for finishing your
> thesis.
>
+1
--
coreboot mailing list: coreboot@coreboot.org
ht
Sorry for the rant, it's not aimed at any particular person,
just to blobs which I don't think should get into coreboot.
On Mon, Apr 16, 2012 at 08:53:56AM +0100, Andrew Goodbody wrote:
> To be honest I don't see the difference between having binary blobs
> in a separate repo and having them in t
On Thu, Feb 07, 2013 at 04:13:00PM +0100, "Kristóf, Csillag" wrote:
> It seems that you are right.
Yes, I'm afraid we lose. I'd love to hear about any success however,
I'd be interested in such a system. At least with regards to freedom
my requirements are the same, performance and features are m
On Thu, Feb 07, 2013 at 08:52:47PM +0100, Denis 'GNUtoo' Carikli wrote:
> on the radeon of the M4A785T-M (01:05.0 VGA compatible controller:
> Advanced Micro Devices [AMD] nee ATI RS880 [Radeon HD 4200]) it can:
> some time ago I commented the VGA option rom running but kept it in
> memory and it w
On Sat, Apr 06, 2013 at 02:47:06PM +0200, Denis 'GNUtoo' Carikli wrote:
> Is the inclusion of the microcode in GPLv2 source code compatible with
> the GPLv2?
I think the correct thing legally would be to load the microcode from
a file (or let the CPU work with the factory microcode and not update
Hello.
While trying the latest svn code I've seen curious results. It mostly
works better than before but still hangs at various places (it seems
random which one of the places reaches at each boot attempt). Since
I haven't finished fixes in fidvid.c it may well be that. But if
I turn on post to
Sorry, I'm asleep, this patch is better.
Signed-off-by: Xavi Drudis Ferran
Index: src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
===
--- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c (revision 5864)
+++ src/northbridge/amd/amdmct/mct_ddr3
Hello.
I'm looking at the fidvid code while trying to make it work
for more revisions and so on, and I don't understand its logic.
at src/cpu/amd/model_10xxx/fidvid.c line 260 (in prep_fid_change()) it
tests F3xA0[31] to tell whether it's in a dual power plane
configuration.
But according to
My .02 from an end user (wannabe) pov:
In general I agree with Warren Turkal:
I'd like a certification that ensures coreboot and free sofware work
with the hardware, irrelevant of what happens with non-free
software. I don't mind having other certification (tags) for non-free
software for whoev
On Wed, Oct 20, 2010 at 02:20:12PM -0500, Scott Duplichan wrote:
>movl $(log2(CONFIG_MMCONF_BUS_NUMBER) << 2), %eax
I have no idea of gas, but log2(x) for integer x > 0
is the position of the leftmost 1 in the binary representation
of x (position 0=rightmost).
int log2(unsigned int x) {
On Wed, Oct 20, 2010 at 02:20:12PM -0500, Scott Duplichan wrote:
> But gas has no base 2 log function and could not figure out how to
> write a macro that returns a constant.
>
Sorry, ignore my previous post . I misread and answered without thinking.
It was about gas, not about log2. I'm surpri
On Fri, Nov 05, 2010 at 08:11:28PM +0100, Patrick Georgi wrote:
> SET_FIDVID*:
> These have _very_ weird behaviour, being set to some defaults in the two
> init_cpus.c (and fidvid.c seems to expect to be included after that
> one?), and some other settings somewhere else.
> I tried to untangle that
On Sat, Nov 06, 2010 at 11:52:27PM +0200, Niklas Cholmkvist wrote:
> Hi,
>
> I would like a mainboard from a vendor that supports coreboot, but also
> has an Intel GMA(3D acceleration) on the same mainboard.(Intel GMA
> because of my percieved 'good 3D FLOSS drivers'...though irrelevant to
> coreb
On Sat, Nov 06, 2010 at 03:32:30PM +0100, xdrudis wrote:
>
> So I would suppose you don't really need to check all cores in
> a processor. If they share the northbridge how could they
> require different frequencies for it ?. But this is only with
> respect to the frecuenc
On Sat, Nov 06, 2010 at 01:56:45PM +0100, Patrick Georgi wrote:
> Hi,
>
> I moved the SET_FIDVID family of configuration options to Kconfig,
> adapting its use (CONFIG_ prefix), and tried to minimize the board
> specific settings.
>
> They get some defaults in src/cpu/amd/model_*xx/Kconfig, which
On Sun, Nov 07, 2010 at 08:37:00AM +0100, Patrick Georgi wrote:
> Am 07.11.2010 02:28, schrieb xdrudis:
> It is an option right now (just in romstage.c) - maybe we should drop
> some of these options on Fam10 completely (and their uses as well), but
> for now all I want to do is
On Sun, Nov 07, 2010 at 06:16:28PM +0100, HacKurx wrote:
> Please can someone help me know if I can install coreboot on my Laptop?
I haven't looked at the components, but I hear that in general laptops
are very difficult. I guess it has improved with usb console but still,
assuming that the chip
On Wed, Dec 15, 2010 at 10:07:50PM +0100, Patrick Georgi wrote:
> Am Mittwoch, 15. Dezember 2010, um 20:17:18 schrieb Xavi Drudis Ferran:
> > If the later I don't like the idea and at least I would like a huge
> > warning "BLOBS IN HERE !!!" at the end of the make output.
> I avoid the term "blob"
Warning: long, personal, philosophical, not even very original
or insightful. Read at your leisure or not at all.
On Thu, Dec 16, 2010 at 05:14:29AM +0100, Stefan Reinauer wrote:
>
> While that last conclusion might sound logical, loading something at
> runtime rather than onto a masked rom or F
On Wed, Jan 12, 2011 at 11:57:39PM +0100, Stefan Reinauer wrote:
>
> Looks like a piece of Kconfig patch went missing?
>
I don't know but I think I already saw this last august. I didn't
care because I didn't know what I wanted expert mode for, so I
just disabled it. I was never sure whether it
Hello.
This patch works for me but needs a small function calc_id_buffer for
each board/cpu/whatever. I only made one for amd quadcore because it
is what I have. My board does not get to ramstage, so it might not
work there. It works for my serial console but should work for net or
usb if I'm no
On Sat, Jan 29, 2011 at 11:09:05AM +0100, xdrudis wrote:
> is what I have. My board does not get to ramstage, so it might not
> work there. It works for my serial console but should work for net or
Ok, now I see it. It won't work with sprintf in ramstage.
I shouldn't have mo
On Sat, Jan 29, 2011 at 11:09:05AM +0100, xdrudis wrote:
> formats output. If someone has more than 16 cores does she really
> want to see ouput from all at a time? Redefining the weak function
> calc_id_buffer you can choose to have some of them mix into the same
> buffer or jus
On Sun, Jan 30, 2011 at 08:32:58PM +0100, Stefan Reinauer wrote:
> * xdrudis [110130 15:46]:
> > On Sat, Jan 29, 2011 at 11:09:05AM +0100, xdrudis wrote:
> > > is what I have. My board does not get to ramstage, so it might not
> > > work there. It works for my serial
On Sun, Jan 30, 2011 at 09:07:52PM +0100, Stefan Reinauer wrote:
> * xdrudis [110130 20:59]:
> > Yes, it'd be mostly unneeded, but anyway the patch I sent does not
> > disable it in ramstage. So it still causes sprintf to consume
> > the double of bytes maybe beyon
On Sun, Jan 30, 2011 at 01:05:54PM -0700, Marc Jones wrote:
>
> I think that the locking can be added via the BSPs cache. All
> multicore should use CAR and it is a matter of adding it where it
> won't get stepped on by the normal use of CAR. For AMD fam10, the
> sysinfo setup would need to be fix
My setup is similar to yours, I bought it trying to get easy coreboot
support (easy, not immediate, and also some features), I've spent
some 6 months trying to "install coreboot" and it still does not
boot. But I'm not experienced in low level programming and I don't
have that much spare time to
On Sat, Feb 12, 2011 at 05:33:44PM +0100, xdrudis wrote:
> http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=W25Q80BVDAIG-ND
>
Forgot to say: this is the one I bought (thanks to Rudolf Marek for
the advice) and it's working here with flashrom. The original chip in
m
see patchPrepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode). No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now
see patch
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. W
see patch
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches.
see patch
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. W
see patch
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We
see patch
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid. Factor out a little common code.
Also, our earlier config_clk_power_ctrl_reg0
was
see patch
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . Factor out the decision whether
to update northbridge frequency and voltage becau
see patch
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).
As suggested by a FIXME, factor out the common code in init_fidvid_ap
and init_fidvid_core and put it into a new function init_fidvid_core
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Bring F3xD4 (Clock/Power Control Register 0) more in line
with BKDG i more cases. It requires looking at the CPU package type
so I add a function for that (in the wr
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
I didn't understand quite why it did that iwth F3xA0 (Power
Control Misc Register) so I moved Pll Lock time to rules in defaults.h
and reimplemented F3xA0 programming.
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
BKDG says nbSynPtrAdj may also be 6 sometimes.
Signed-off-by: Xavi Drudis Ferran
--- src/cpu/amd/model_10xxx/fidvid.c 2011-02-13 19:30:42.0 +0100
+++ src/c
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Configuration of F3x[84:80] was hardcoded for rev B.
I change that for some code that checks for revision
and configures according to BKDG. Unfinished but
hopefully
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Contemplate the possibility of nbCofVidUpdate not being
defined, trying to get closer to BKDG
Signed-off-by: Xavi Drudis Ferran
--- src/cpu/amd/model_10xxx/fidvid
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Factor out some common expressions.
Add an error message when coreboots hangs waiting for a pstate
that never comes (it happened to me), and throw some
paranoia at it
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Looking at BKDG the process for updating
Pstate Nb vid after warn reset seemed
more similar to the codethat was there fo
pvi than the one for svi, so I called the
pv
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Add to init_fidvid_stage2 some step for my CPU (rev C3)
mentioned in BKDG 2.4.2.6 (5) that was missing
Signed-off-by: Xavi Drudis Ferran
--- src/cpu/amd/model_
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Add to init_fidvid_stage2 some step
mentioned in BKDG 2.4.2.7 that was missing . Some lines
are dead code now, but may handy if one day we support
revison E CPUs.
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Add an untested step in BKDG 2.4.2.8. I don't
have the hardware with Core Performance Boost and
I think it's only available in revision E that does
not even have a c
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Well, I understand it better like this, but maybe
it's only me, part of the changes are paranoic, and
the only effective change is for a factor depending on
mobile
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
bits 13 - 15 of F3xd4 (StutterScrubEn, CacheFlushImmOnAllHalt and MTC1eEn
are reserved for revisions D0 and earlier, so whe should not set them
to 0 in fidvid.c conf
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
In fact I changed coreDelay before deleting
the code in fidvid that called it. But there're
still a couple of calls from src/northbridge/amd/amdmct/wrappers/mcti_d.c
S
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?
Signed-off-by: Xavi Drudis Ferran
--- src/cpu/a
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
I remove an unused parameter and a duplicated constant.
Signed-off-by: Xavi Drudis Ferran
--- src/cpu/amd/model_10xxx/fidvid.c 2011-02-16 01:08:16.0 +0100
see patch
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Documentation only.
Adding a checklist to tell which function takes
care of which requirement of BKDG .
Signed-off-by: Xavi Drudis Ferran
--- src/cpu/amd/model_1
see patch
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On Fri, Feb 18, 2011 at 10:19:31AM -0500, Ward Vandewege wrote:
> Hi Xavi,
>
> On Wed, Feb 16, 2011 at 02:45:02PM +0100, Xavi Drudis Ferran wrote:
> > Should I send a patch making a Kconfig option to not upgrade microcode for
> > fam10? Is there any interest in that ?
>
> Yes, please. I would t
On Mon, Feb 21, 2011 at 08:44:35AM -0600, Scott Duplichan wrote:
>
> This really isn't relevant, but microcode patch source code
> certainly exists, as does source code for the main microcode
> that the patch modifies. A microcode assembler converts the
> source code into binary form.
>
I think i
On Thu, Feb 24, 2011 at 02:31:29PM +0100, Georgi, Patrick wrote:
> Am Donnerstag, den 17.02.2011, 07:35 +0100 schrieb xdrudis:
> > see patch
> Any opinion on these patches? Patch 1-8 seem to be refactorings only,
> and splitting functions into smaller logical units looks good to me,
This is the patch for option B.
You may not be able to test it without my next patch. At least for me
selectiong EXPERT in make menuconfig breaks the build. Next patch fixes it.
Make patching cpu microcode optional (for experts).
It's been requested to not link update_microcode.c in that case,
This patch tries to fix compilation when you select EXPERT in make menuconfig.
If I select Expert mode in make menuconfig I couldn't compile because
it complained of 2 missing configuration constants. I hope this is
the right solution, but haven't really checked that the related code
in src/nor
On Sat, Feb 26, 2011 at 03:53:43AM +0200, Alex G. wrote:
> On 02/26/2011 03:39 AM, xdrudis wrote:
> > This patch tries to fix compilation when you select EXPERT in make
> > menuconfig.
> >
> HT Frequencies are multiples of 200MHz AFAIK, so there are no 300MHz and
> 5
On Sat, Feb 26, 2011 at 04:01:56AM +0200, Alex G. wrote:
> On 02/26/2011 03:38 AM, xdrudis wrote:
> > This is the patch for option B.
> >
> > You may not be able to test it without my next patch. At least for me
> > selectiong EXPERT in make menuconfig breaks the
On Sat, Feb 26, 2011 at 07:17:46PM +0100, Peter Stuge wrote:
> xdrudis wrote:
> > > HT Frequencies are multiples of 200MHz AFAIK, so there are no
> > > 300MHz and 500MHz.
> ..
> > Oh! You may well be right. All others are multiples of 200 MHz .
> >
> >
On Sat, Feb 26, 2011 at 11:22:17PM +0200, Alex G. wrote:
> I look at the microcode as simply DIP switches used to configure the IRQ
> line on the hardware. If the manual (microcode updates) gives me
> erroneous information, then I put the switches back to their initial
> position (factory microcod
On Sun, Feb 27, 2011 at 01:30:19AM +0200, Alex G. wrote:
> On 02/27/2011 12:46 AM, xdrudis wrote:
> > On Sat, Feb 26, 2011 at 11:22:17PM +0200, Alex G. wrote:
>>> You will disagree and say that, as long as
>>> it can be updated, and source code exists for it, it is
On Fri, Mar 11, 2011 at 05:49:50PM +0200, Alex G. wrote:
> > 1. Does Coreboot work with Phenom II Thuban CPU ? I want 6-core CPU of
> > Phenom2
> >
> It's supported.
>
I didn't know this had been tested. It's a little difficult for me to
keep track of all mail in the list.
http://www.coreboot.o
On Sat, Mar 26, 2011 at 10:58:54PM +0800, Hamo wrote:
> Hi lists,
> This is a student from China who wants to apply for coreboot GSoC
> project. I am now studying Computer Science and Technology in Hebei
> University of Technology, which is a key university in China. I
> ardently love low-level dev
On Mon, Mar 21, 2011 at 01:49:49PM -0400, Leandro Dorileo wrote:
Excuse my ignorace, but you say :
>
> [1] - http://vps.dorilex.net/~dorileo/coreboot-spice-payload.txt
>
> 3. Coreboot Spice Payload
>
> Spice building blocks are Spice
On Mon, Mar 28, 2011 at 11:06:55AM +0800, Hamo wrote:
> All of the free bootloaders now are focus on embedded systems, but
> with the development of ARM architecture, it will not only be used on
> embedded systems but also servers and low power consumption PCs. So we
> need a full-function bootloa
Hello.
First things first: thank you all for working in coreboot, yet another
free software project I wouldn't think possible if you hadn't made it
real.
I've been reading the archives and browsing coreboot.org, but I have
little clue about firmware so I still have doubts I would like to
clear
On Tue, Apr 13, 2010 at 09:44:02AM -0600, Marc Jones wrote:
> Hi Xavi,
>
> Thanks for your interest in coreboot. This is a long email! :)
>
I'm bad at summarizing. Sorry.
>
> VGA BIOS is not required. You could have a headless system. Or a
> system with a framebuffer driver like Geode.
>
Hea
On Wed, Apr 14, 2010 at 10:18:50AM +0800, Qing Pei Wang wrote:
> the 780 mainboard which coreboot support now is mahogany. I am trying to
> porting a few more
> mainboard as GSOC project. the mainboard i choose at this moment is
> 1)Shine,2)Tilapia,3)Gigabyte GA-MA78GM-S2H,4)ASUS M4A78-VM 5)Colorf
On Fri, Apr 23, 2010 at 09:24:43AM +0800, Bao, Zheng wrote:
> DDR3 supporting is added.
>
Thank you very much. I would thank you more but I'm too busy looking
at what to buy from AMD...
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Thank you for your work on Dual BIOS.
What I don't understand is how is this supposed to work.
>From what you say and what I asked sales cotact staff at gigabyte (no
very useful insights) , there are two bios roms. One has the ability
to check the other and run it only if it detects it's ok. If i
On Sat, Apr 24, 2010 at 08:26:45PM +0200, Patrick Georgi wrote:
> Am 24.04.2010 19:43, schrieb xdrudis:
> They might just use a watchdog:
> - BIOS 1 sets a flag
> - BIOS 1 configures the watchdog to trigger when it's not touched within
> 2 seconds (or whatever). watchdog wou
On Sun, Apr 25, 2010 at 01:45:19PM +0200, Peter Stuge wrote:
> xdrudis wrote:
> > > They might just use a watchdog:
> >
> > Ok. I'm rereading the link Gigabyte gave me,
>
> Please read the US Patent.
>
I wasn't aware. I hadn't read your mail wh
On Tue, Apr 27, 2010 at 12:51:40AM +0200, xdrudis wrote:
> broad (they claim a computer, not merely a BIOS, a whatchdog, some
No, sorry, they claim "a selectable BIOS". I misread.
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On Tue, May 18, 2010 at 07:45:18PM -0400, Kevin O'Connor wrote:
>
> I think you're going to want SeaBIOS if you need to install Linux from
> a CD. I think filo has cd booting support, but I'd guess standard
> Linux distros wont work out of the box.
>
Mmmm... hadn't thought of that. Just a crazy
Hello.
I finally bought the hardware I told you and installed gnewsense 3 with a
custom linux-libre 2.6.34 :
mainboard Asus M4A77TD-PRO
http://www.asus.com/product.aspx?P_ID=0AvsBb7WBZe2i9zK
CPU AMD Phenom X4 910e stepping c3
AMD 770
AMD SB710
RAM 2 x 4Gb dual channel non-ECC G.Skill DDR3-133
I forgot to add that the mainboard did not boot when I built the PC.
It would only boot once when I cleared CMOS, and then never more until
I cleared it again.
I could fix it by downloading a BIOS image of a newer version
from asus and flashing it (with a tool called EZ flash, I think,
which was
ogs, do you
want
my .config, all files in the new mainboard dir ? the complete patch from the
base
revision, the diff between my m4a77td-pro and tilapia-fam10 dirs ?)
- quit and wait for someone more knowleadgeable to do the port if ever ?
Thanks for your time reading this.
Not that I like top postin
On Mon, Aug 02, 2010 at 11:54:15AM +0200, Rudolf Marek wrote:
> >When I boot with the propietary BIOS I can get GRUB2 and linux console
> >on the serial port, but only at 38400 bps. 118000 does not work. So
> >I've put 38400 in kconfig too.
>
>
> Hm this is strange. Maybe you can try with 9600 ?
On Mon, Aug 02, 2010 at 01:20:54PM +0200, Stefan Reinauer wrote:
>
> On 02.08.2010, at 12:43, xdrudis wrote:
>
> > On Mon, Aug 02, 2010 at 11:54:15AM +0200, Rudolf Marek wrote:
> >>> When I boot with the propietary BIOS I can get GRUB2 and linux console
> >&
On Mon, Aug 02, 2010 at 01:20:54PM +0200, Stefan Reinauer wrote:
>
> On 02.08.2010, at 12:43, xdrudis wrote:
>
> > On Mon, Aug 02, 2010 at 11:54:15AM +0200, Rudolf Marek wrote:
> >>> When I boot with the propietary BIOS I can get GRUB2 and linux console
> >&
On Mon, Aug 02, 2010 at 11:54:15AM +0200, Rudolf Marek wrote:
>
> I would suggest to try to make it work with serialICE first, then
> fix the coreboot console as second step. Go to www.serialice.com and
> download it.
>
> It is some kind of simple monitor which can execute various IO
> operations
On Tue, Aug 03, 2010 at 12:31:01AM +0200, Rudolf Marek wrote:
>
> Well please investigate because I put there already - it is the
> write to reg 0x72. There might be watchdog in SB700 datasheet says
> disabled by default but dunno if there is some possibility that it
> is enabled by default by s
Ok. Now I've got two lines of output in the serial port from coreboot.
Thank you very much.
The way I got it is a dodge but at least maybe I can now add debug messages
to find the proper way.
I just replaced sb700_lpc_init by the corresponding code by Rudolf Marek in
the serialICE mainboard .
I
On Tue, Aug 03, 2010 at 11:22:29AM +0200, xdrudis wrote:
>
> I could try to add code similar to that above to serialICE and see
> what happens.
>
Done. It now boots serialICE once and starts the shell. I haven't downloaded
qemu, patched it and tested with a coreboot image (
After I copied mainboard/amd/tilapia-fam10 dir for mainboard/asus/m4a77td-pro,
adapted it a litlle
and changed mainboard/asus/Kconfig and makemenuconfig, I had
to change a few small things because I got warnings treated as
erroes for unused symbols.
patch.warnerror
With only this patch applied
On Mon, Aug 16, 2010 at 06:21:31PM +0200, Xavi Drudis Ferran wrote:
> > Xavi Drudis Ferran wrote:
> >> 1.- In order to get sb700_lpc_init in sb700_early_setup.c to work
> >> I've got to modifiy pci_locate_device in order to refrain from
> >> scanning some functions in pci bus 0.
> >
> > Hm. Which f
Hello.
This is a patch for setting the processor names updated to the
same doc as the original but revision June 2010.
It applies to svn 5703 and I tested it with my previous patch.warnerrors
and patch.serial1 and it makes no difference. I can't tell whether
it works yet, but maybe someone else
Hi.
This is the rest of patches to get until fidvid or staring
ram stage, apparently at random. In fact once I've cleaned
up the other patches a little I can't seem to make it stop at fidvid
as it used to, but I guess with a dozen more tries it will...
It's including RB-C3 in AMD_FAM10_ALL
and
On Wed, Aug 18, 2010 at 03:07:04PM -0400, Corey Osgood wrote:
>
> Most of the code in these files is trivial and identical to every
> other super IO, with the exception of changing the model name/number.
> If we kept the copyright notices from every previous "author" of those
> files, it would pro
On Wed, Aug 18, 2010 at 05:53:19PM -0400, Corey Osgood wrote:
>
> Here's the problem: some time ago, someone wrote a superio chip.h that
> contained this:
>
[...]
Sorry, I didn't understand the problem. I thought it was triviality and
it was removal of the whole contribution of a previous auth
On Tue, Aug 17, 2010 at 08:44:10AM +0200, xdrudis wrote:
>
> I know I should split it to smaller pieces, I just haven't had
> the time yet, and there's some overlap, so I must take care...
>
> Signed off by: Xavi Drudis Ferran
>
I splitted the original patch in 8
My smallest patch ever
I've checked Revision Guide for AMD Family10h processors (#41322) rev
3.74 June 2010 for errata 351 and it agrees with the comment on
setting ForceFullT0= 000b but I believe the code didn't honor the
comment.
apply this after patch.rbc3infam10all
Index: src/cpu/amd/model_1
Signed off by: Xavi Drudis Ferran
diff -r -u src/cpu/amd/model_10xxx/defaults.h
../coreboot-p/src/cpu/amd/model_10xxx/defaults.h
--- src/cpu/amd/model_10xxx/defaults.h 2010-08-19 08:06:11.0 +0200
+++ ../coreboot-p/src/cpu/amd/model_10xxx/defaults.h2010-08-19
08:09:06.0 +02
Up to this patch, tests did the same as without the patches,
hang after setAMDMSR , but still I think they are useful,
since they get closer to documentation and don't make things worse.
Signed off by: Xavi Drudis Ferran
Complete code for errata 343. Revision Guide for AMD Family10h
processors (
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