[PATCH] Deal with prefixed loads/stores in tests, PR testsuite/100166
This patch updates the various tests in the testsuite to treat plxv
and pstxv as being vector loads/stores. This shows up if you run the
testsuite with a compiler configured with the option: --with-cpu=power10.
I have
[PATCH] Fix vec-splati-runnable.c test.
I noticed that the vec-splati-runnable.c did not have an abort after one
of the tests. If the test was run with optimization, the optimizer could
delete some of the tests and throw off the count. However, due to the
fact that the value being loaded in
[PATCH] Change rs6000_const_f32_to_i32 return type.
The function rs6000_const_f32_to_i32 called REAL_VALUE_TO_TARGET_SINGLE
with a long long type and returns it. This patch changes the type to long
which is the proper type for REAL_VALUE_TO_TARGET_SINGLE.
2021-07-07 Michael Meissner
gcc/
[PATCH] Fix long double tests when default long double is not IBM.
This patch adds 3 more selections to target-supports.exp to see if we can force
the compiler to use a particular long double format (IEEE 128-bit, IBM extended
double, 64-bit), and the library support will track the changes for
[PATCH] Generate 128-bit int divide/modulus on power10.
This patch adds support for the VDIVSQ, VDIVUQ, VMODSQ, and VMODUQ
instructions to do 128-bit arithmetic.
Ideally this patch can be approved in time to be back ported to GCC 11.2.
Can I check this into the master branch, and eventually
On Tue, Jun 29, 2021 at 07:06:14PM -0500, Segher Boessenkool wrote:
> On Thu, Jun 17, 2021 at 06:56:09PM -0400, Michael Meissner wrote:
> > The 'lp64' test
> > was needed because big endian 32-bit code cannot enable the IEEE 128-bit
> > floating point instructions.
>
> No, *does not* enable them.
On Wed, Jun 23, 2021 at 06:56:37PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Jun 17, 2021 at 03:18:48PM -0400, Michael Meissner wrote:
> > > The actual insns only check TARGET_POWER10 (so no TARGET_FLOAT128_HW).
> > > Which is right, this or that?
> >
> > It should include
On Fri, Jun 25, 2021 at 12:46:37PM -0500, Segher Boessenkool wrote:
> On Thu, Jun 17, 2021 at 04:11:40PM -0400, Michael Meissner wrote:
> > On Thu, Jun 17, 2021 at 01:11:58PM -0500, Segher Boessenkool wrote:
> > > > --- a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
> > > > +++
Note, as I mentioned previously, this patch needs to go into GCC 11.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
Note, this patch should go into GCC 11 after baking on the master branch.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
Ping this patch.
| Date: Tue, 8 Jun 2021 20:24:47 -0400
| Subject: [PATCH 3/3] Add IEEE 128-bit fp conditional move on PowerPC.
| Message-ID: <20210609002447.gc18...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email:
Ping this patch:
| Date: Thu, 17 Jun 2021 18:56:09 -0400
| Subject: [PATCH 2/3 V2] Fix IEEE 128-bit min/max test.
| Message-ID: <20210617225609.ga4...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email:
Ping this patch.
| Date: Fri, 4 Jun 2021 11:10:37 -0400
| Subject: Generate 128-bit divide/modulus
| Message-ID: <20210604151037.ga27...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1
Here is a replacement patch. Can I check this into the master branch, and
eventually backport it to GCC 11?
[PATCH] Fix IEEE 128-bit min/max test.
This patch fixes the float128-minmax.c test so that it can accommodate the
generation of xsmincqp and xsmaxcqp instructions on power10. I changed
On Thu, Jun 17, 2021 at 01:11:58PM -0500, Segher Boessenkool wrote:
> On Tue, Jun 08, 2021 at 08:22:40PM -0400, Michael Meissner wrote:
> >
> > * gcc.target/powerpc/float128-minmax.c: Adjust expected code for
> > power10.
> > * lib/target-supports.exp
On Thu, Jun 17, 2021 at 01:11:58PM -0500, Segher Boessenkool wrote:
> On Tue, Jun 08, 2021 at 08:22:40PM -0400, Michael Meissner wrote:
> >
> > * gcc.target/powerpc/float128-minmax.c: Adjust expected code for
> > power10.
> > * lib/target-supports.exp
On Thu, Jun 17, 2021 at 12:39:04PM -0500, Segher Boessenkool wrote:
> On Tue, Jun 08, 2021 at 08:21:25PM -0400, Michael Meissner wrote:
> > GCC will not convert ternary operations into using min/max instructions
> > provided in this patch unless the user uses -Ofast or similar switches due
> > to
Ping patch. In particular, we would like to get this to GCC 11.2 because it is
power10 enablement.
| Date: Fri, 4 Jun 2021 11:10:37 -0400
| Subject: Generate 128-bit divide/modulus
| Message-ID: <20210604151037.ga27...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550
Ping patch. In particular, we would like to get this patch into GCC 11.2 for
power10 enablement.
| Date: Tue, 8 Jun 2021 20:24:47 -0400
| Subject: [PATCH 3/3] Add IEEE 128-bit fp conditional move on PowerPC.
| Message-ID: <20210609002447.gc18...@ibm-toto.the-meissners.org>
--
Michael Meissner,
Ping patch. In particular, we like to get this into GCC 11.2 as part of
power10 enablement.
| Date: Tue, 8 Jun 2021 20:22:40 -0400
| Subject: [PATCH 2/3] Fix IEEE 128-bit min/max test.
| Message-ID: <20210609002240.gb18...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R,
Ping patch. In particular, we would like to get this into the GCC 11.2
backport as it is power10 enablement.
| Date: Tue, 8 Jun 2021 20:21:25 -0400
| Subject: [PATCH 1/3] Add IEEE 128-bit min/max support on PowerPC.
| Message-ID: <20210609002125.ga18...@ibm-toto.the-meissners.org>
--
Michael
[PATCH 3/3] Add IEEE 128-bit fp conditional move on PowerPC.
This patch adds the support for power10 IEEE 128-bit floating point conditional
move and for automatically generating min/max.
In this patch, I simplified things compared to previous patches. Instead of
allowing any four of the modes
[PATCH 2/3] Fix IEEE 128-bit min/max test.
This patch fixes the float128-minmax.c test so that it can accommodate the
generation of xsmincqp and xsmaxcqp instructions on power10. I changed
the effective target from 'float128' to 'ppc_float128_hw', since this
needs the IEEE 128-bit float hardware
[PATCH 1/3] Add IEEE 128-bit min/max support on PowerPC.
This patch adds the support for the IEEE 128-bit floating point C minimum and
maximum instructions. The next patch will add the support for using the
compare and set mask instruction to implement conditional moves.
This patch does not try
This is a revision of the patches I sent on May 18th.
I tested it on 3 platforms:
* Power9 little endian, --with-code=power9;
* Power8 big endian, --with-code=power8, both 32/64-bit tests done;
* Power10 little endian, --with-code=power10.
All systems bootstrapped and there
On Mon, Jun 07, 2021 at 05:31:50PM -0500, Segher Boessenkool wrote:
> On Tue, May 18, 2021 at 04:28:27PM -0400, Michael Meissner wrote:
> > In this patch, I simplified things compared to previous patches. Instead of
> > allowing any four of the modes to be used for the conditional move
> >
On Mon, Jun 07, 2021 at 03:25:06PM -0500, Segher Boessenkool wrote:
> On Tue, May 18, 2021 at 04:26:06PM -0400, Michael Meissner wrote:
> > This patch adds the support for the IEEE 128-bit floating point C minimum
> > and
> > maximum instructions.
>
> > gcc/
> > 2021-05-18 Michael Meissner
>
PR 99293: Optimize splat of vec_extract for V2DI/V2DF.
We had optimizations for splat of a vector extract for the other vector
types, but we missed having one for V2DI and V2DF. This patch adds a
combiner insn to do this optimization.
In looking at the source, we had similar optimizations for
Generate 128-bit divide/modulus.
This patch adds support for the VDIVSQ, VDIVUQ, VMODSQ, and VMODUQ
instructions to do 128-bit arithmetic.
I have tested this on 3 compilers:
* Power9 little endian, --with-cpu=power9
* Power8 big endian, --with-cpu=power8, both 32/64-bit tested
*
Ping patch again.
Original patch (Change rs6000_const_f32_to_i32 return type)
| Date: Tue, 18 May 2021 16:39:28 -0400
| Subject: [PATCH] Change rs6000_const_f32_to_i32 return type.
| Message-ID: <20210518203928.ga15...@ibm-toto.the-meissners.org>
|
Ping patch again.
Original patch (Fix tests when running on power10, PR testsuite/100166).
| Date: Tue, 18 May 2021 16:59:12 -0400
| Subject: [PATCH 2/2] Fix tests when running on power10, PR testsuite/100166
| Message-ID: <20210518205912.gb18...@ibm-toto.the-meissners.org>
|
Ping patch again.
Original patch (Deal with prefixed loads/stores in tests, PR testsuite/100166):
| Date: Tue, 18 May 2021 16:57:59 -0400
| Subject: [PATCH 1/2] Deal with prefixed loads/stores in tests, PR
testsuite/100166
| Message-ID: <20210518205759.ga18...@ibm-toto.the-meissners.org>
|
Ping patch again.
Original patch (Fix vec-splati-runnable.c test)
| Date: Tue, 18 May 2021 16:49:58 -0400
| Subject: [PATCH] Fix vec-splati-runnable.c test.
| Message-ID: <20210518204958.ga17...@ibm-toto.the-meissners.org>
| https://gcc.gnu.org/pipermail/gcc-patches/2021-May/570684.html
Note as
Ping patch again.
Original patch (fix xxevel predicates):
| Date: Tue, 18 May 2021 16:47:58 -0400
| Subject: [PATCH 2/2] Fix xxeval predicates.
| Message-ID: <20210518204758.gb16...@ibm-toto.the-meissners.org>
| https://gcc.gnu.org/pipermail/gcc-patches/2021-May/570683.html
--
Michael
Ping patch again.
Original patch (move xx* builtins to vsx.md)
| Date: Tue, 18 May 2021 16:46:47 -0400
| Subject: [PATCH 1/2] Move xx* builtins to vsx.md.
| Message-ID: <20210518204647.ga16...@ibm-toto.the-meissners.org>
| https://gcc.gnu.org/pipermail/gcc-patches/2021-May/570682.html
--
Ping patch again:
Original patch (Allow __ibm128 on older PowerPC systems):
| Date: Tue, 18 May 2021 16:36:32 -0400
| Subject: [PATCH] Allow __ibm128 on older PowerPC systems.
| Message-ID: <20210518203632.ga15...@ibm-toto.the-meissners.org>
|
Ping patch again.
| Date: Tue, 18 May 2021 16:32:33 -0400
| Subject: [PATCH] Fix long double tests when default long double is not IBM.
| Message-ID: <20210518203233.ga15...@ibm-toto.the-meissners.org>
| https://gcc.gnu.org/pipermail/gcc-patches/2021-May/570678.html
--
Michael Meissner, IBM
Ping patch again.
Original patch (Add IEEE 128-bit fp conditional move on PowerPC):
| Date: Tue, 18 May 2021 16:28:27 -0400
| Subject: [PATCH 2/2] Add IEEE 128-bit fp conditional move on PowerPC.
| Message-ID: <20210518202827.gb14...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM,
Ping again.
Original patch (Add IEEE 128-bit min/max support on PowerPC):
| Date: Tue, 18 May 2021 16:26:06 -0400
| Subject: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC.
| Message-ID: <20210518202606.ga14...@ibm-toto.the-meissners.org>
|
Ping patch.
| Date: Tue, 18 May 2021 16:59:12 -0400
| Subject: [PATCH 2/2] Fix tests when running on power10, PR testsuite/100166
| Message-ID: <20210518205912.gb18...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email:
Ping patch. This is independent of the other patches.
| Date: Tue, 18 May 2021 16:57:59 -0400
| Subject: [PATCH 1/2] Deal with prefixed loads/stores in tests, PR
testsuite/100166
| Message-ID: <20210518205759.ga18...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550
Ping patch.
| Date: Tue, 18 May 2021 16:47:58 -0400
| Subject: [PATCH 2/2] Fix xxeval predicates.
| Message-ID: <20210518204758.gb16...@ibm-toto.the-meissners.org>
This needs the following patch to have been applied:
| Date: Tue, 18 May 2021 16:46:47 -0400
| Subject: [PATCH 1/2] Move xx*
Ping patch. This patch is a set of 2 patches. The second patch will need this
patch applied. In addition, the next 3 patches that I will be submitting (to
add support for generating XXSPLTIW, XXSPLTIDP, and XXSPLTI32DX) will need this
patch applied (or else I would just have to reformulate the
Ping patch. This is independent of the other patches.
| Date: Tue, 18 May 2021 16:39:28 -0400
| Subject: [PATCH] Change rs6000_const_f32_to_i32 return type.
| Message-ID: <20210518203928.ga15...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA
Ping patch. This is independent of the other patches.
| Date: Tue, 18 May 2021 16:36:32 -0400
| Subject: [PATCH] Allow __ibm128 on older PowerPC systems.
| Message-ID: <20210518203632.ga15...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA
Ping patch. This is independent of the other patches.
| Date: Tue, 18 May 2021 16:32:33 -0400
| Subject: [PATCH] Fix long double tests when default long double is not IBM.
| Message-ID: <20210518203233.ga15...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King
Ping patch.
| Subject: [PATCH 2/2] Add IEEE 128-bit fp conditional move on PowerPC.
| Message-ID: <20210518202827.gb14...@ibm-toto.the-meissners.org>
Note this patch needs the following patch before it can be applied.
| Subject: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC.
|
Ping patch:
| Subject: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC.
| Message-ID: <20210518202606.ga14...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
On Thu, May 20, 2021 at 02:31:59PM -0500, will schmidt wrote:
> On Tue, 2021-05-18 at 16:49 -0400, Michael Meissner wrote:
> > [PATCH] Fix vec-splati-runnable.c test.
> >
>
> hi,
>
>
> > I noticed that the vec-splati-runnable.c did not have an abort after one
> > of the tests. If the test was
On Thu, May 20, 2021 at 02:31:08PM -0500, will schmidt wrote:
> On Tue, 2021-05-18 at 16:47 -0400, Michael Meissner wrote:
> > [PATCH 2/2] Fix xxeval predicates.
> >
> > In doing the patch to move the XX* built-in functions from altivec.md to
> > vsx.md, I noticed that the xxeval built-in
On Thu, May 20, 2021 at 02:30:24PM -0500, will schmidt wrote:
> > +;; XXPERMX built-in function support
> > +(define_expand "xxpermx"
> > + [(set (match_operand:V2DI 0 "register_operand" "+wa")
> > + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
> > +
On Thu, May 20, 2021 at 02:29:02PM -0500, will schmidt wrote:
> On Tue, 2021-05-18 at 16:36 -0400, Michael Meissner wrote:
> > [PATCH] Allow __ibm128 on older PowerPC systems.
> >
>
> Hi,
>
>
> > On January 8th, 2018, I added code to ibm-ldouble.c to use the built-in
> > function
On Thu, May 20, 2021 at 02:27:06PM -0500, will schmidt wrote:
> > diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
> > index fdaf12aeda0..ef1ebaaee05 100644
> > --- a/gcc/config/rs6000/rs6000.c
> > +++ b/gcc/config/rs6000/rs6000.c
> > @@ -15706,8 +15706,8 @@
On Thu, May 20, 2021 at 02:25:58PM -0500, will schmidt wrote:
> I'd throw the ternary term in there, easier to search for later.
> s/?: operations/ternary (?:) operations /
Thanks.
> So, presumably the float128-minmax-2.c test adds/replaces the power10
> code gen tests that were removed or
[PATCH 2/2] Fix tests when running on power10, PR testsuite/100166
This patch updates the various tests in the testsuite to adjust the test
if power10 code generation is used.
Some tests would not generate the expected instructions because power10
provides new instructions that the compiler now
[PATCH 1/2] Deal with prefixed loads/stores in tests, PR testsuite/100166
This patch updates the various tests in the testsuite to treat plxv
and pstxv as being vector loads/stores. This shows up if you run the
testsuite with a compiler configured with the option: --with-cpu=power10.
I have
I decided to do a run on our prototype power10 hardware, comparing using
--with-cpu=power9 and --with-cpu=power10. I noticed several tests were failing
with power10 code generation.
Most of the tests were failing because the regex's did not include prefixed
loads and stores. These are fixed in
[PATCH] Fix vec-splati-runnable.c test.
I noticed that the vec-splati-runnable.c did not have an abort after one
of the tests. If the test was run with optimization, the optimizer could
delete some of the tests and throw off the count.
I have bootstraped this on LE power9 and BE power8 systems.
[PATCH 2/2] Fix xxeval predicates.
In doing the patch to move the XX* built-in functions from altivec.md to
vsx.md, I noticed that the xxeval built-in function used the
altivec_register_operand predicate. Since it takes vsx registers, this
might force the register allocate to issue a move when
[PATCH 1/2] Move xx* builtins to vsx.md.
I noticed that the xx built-in functions (xxspltiw, xxspltidp, xxsplti32dx,
xxeval, xxblend, and xxpermx) were all defined in altivec.md. However, since
the XX instructions can take both traditional floating point and Altivec
registers, these built-in
[PATCH 0/2] Move xx* builtins to vsx.md.
I noticed that the xx built-in functions (xxspltiw, xxspltidp, xxsplti32dx,
xxeval, xxblend, and xxpermx) were all defined in altivec.md. However, since
the XX instructions can take both traditional floating point and Altivec
registers, these built-in
[PATCH] Change rs6000_const_f32_to_i32 return type.
The function rs6000_const_f32_to_i32 called REAL_VALUE_TO_TARGET_SINGLE
with a long long type and returns it. This patch changes the type to long
which is the proper type for REAL_VALUE_TO_TARGET_SINGLE.
I have done bootstraps on little endian
[PATCH] Allow __ibm128 on older PowerPC systems.
On January 8th, 2018, I added code to ibm-ldouble.c to use the built-in
function __builtin_pack_ibm128 if long double is IEEE 128-bit and continue to
use __builtin_pack_longdouble if long double is IBM extended double. This code
was needed because
[PATCH] Fix long double tests when default long double is not IBM.
This patch adds 3 more selections to target-supports.exp to see if we can force
the compiler to use a particular long double format (IEEE 128-bit, IBM extended
double, 64-bit), and the library support will track the changes for
[PATCH 2/2] Add IEEE 128-bit fp conditional move on PowerPC.
This patch adds the support for power10 IEEE 128-bit floating point conditional
move and for automatically generating min/max.
In this patch, I simplified things compared to previous patches. Instead of
allowing any four of the modes
[PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC.
This patch adds the support for the IEEE 128-bit floating point C minimum and
maximum instructions. The next patch will add the support for using the
compare and set mask instruction to implement conditional moves.
This patch does not try
The following two patches are new versions of the patches I've submitted in the
past to add support for the power10 IEEE 128-bit XSMAXCQP, XSMINCQP, XSCMPEQQ,
XSCMPGTQ, and XSCMPGEQ instructions.
This time I'm not trying to share code with the DFmode/SFmode min, max, or
conditional move support.
On Thu, Apr 29, 2021 at 05:50:03PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Apr 29, 2021 at 05:48:53PM -0400, Michael Meissner wrote:
> > This patch defines the constants needed for libgcc for the PowerPC
> > specific IEEE 128-bit floating point types (KFmode).
>
> It doesn't do that
[PATCH, V2] Define KFmode constants for libgcc.
This patch defines the constants needed for libgcc for the PowerPC
specific IEEE 128-bit floating point types (KFmode). The 4/28 changes to
libgcc need these constants defined.
We only define the KFmode constants if IEEE 128-bit floating point is
On Thu, Apr 29, 2021 at 04:48:07PM +, Joseph Myers wrote:
> On Thu, 29 Apr 2021, Michael Meissner via Gcc-patches wrote:
>
> > On Thu, Apr 29, 2021 at 04:31:50PM +, Joseph Myers wrote:
> > > On Thu, 29 Apr 2021, Michael Meissner via Gcc-patches wrote:
> >
On Thu, Apr 29, 2021 at 04:31:50PM +, Joseph Myers wrote:
> On Thu, 29 Apr 2021, Michael Meissner via Gcc-patches wrote:
>
> > Fix PR bootstrap/100327 (_divkf3.c) on PowerPC.
> >
> > This patch fixes the PowerPC _divkf3.c module to use the appropriate
> > F
Fix PR bootstrap/100327 (_divkf3.c) on PowerPC.
This patch fixes the PowerPC _divkf3.c module to use the appropriate
FLT128 constants if long double is not IEEE 128-bit.
I have tested this patch by doing a bootstrap on a little endian power9
system running Linux. Can I check this into the
On Thu, Apr 22, 2021 at 05:56:32PM -0500, Segher Boessenkool wrote:
> On Fri, Apr 09, 2021 at 05:09:07PM -0400, Michael Meissner wrote:
> > Fix logic error in 32-bit trampolines, PR target/98952.
> >
> > The test in the PowerPC 32-bit trampoline support is backwards. It aborts
> > if the
On Wed, Apr 21, 2021 at 10:10:07AM +0200, Tobias Burnus wrote:
> On 20.04.21 08:58, Richard Biener via Fortran wrote:
> >On Mon, Apr 19, 2021 at 9:40 PM Michael Meissner via Fortran
> > wrote:
> Is there any reason to not only send the email to fortran@ _and_
> gcc-patches@ but sending it to 13
Ping the patch for a logic error in setting up 32-bit trampolines.
| Subject: [PATCH] Fix logic error in 32-bit trampolines, PR target/98952
| Message-ID: <20210409210907.ga5...@ibm-toto.the-meissners.org>
| User-Agent: Mutt/1.5.21 (2010-09-15)
Fix Fortran rounding issues, PR fortran/96983.
I was looking at Fortran PR 96983, which fails on the PowerPC when trying to
run the test PR96711.F90. The compiler ICEs because the PowerPC does not have
a floating point type with a type precision of 128. The reason is that the
PowerPC has 3
[PATCH 2/2] Add IEEE 128-bit fp conditional move on PowerPC.
This patch adds the support for power10 IEEE 128-bit floating point conditional
move and for automatically generating min/max.
In this patch, I simplified things. Instead of allowing any four of the modes
to be used for the
[PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC.
This patch adds the support for the IEEE 128-bit floating point C minimum and
maximum instructions. The next patch will add the support for using the
compare and set mask instruction to implement conditional moves.
I removed the
These patches add support for the XSMAXCQP, XSMINCQP, XSCMPEQQP, XSCMPGTQP, and
XSCMPGEQP instructions that were added to the PowerPC ISA 3.1 (power10).
These patches address the comments raised from the last version of the patches.
In this iteration, I simplified the first patch, eliminating a
On Wed, Apr 14, 2021 at 02:15:47PM -0500, Segher Boessenkool wrote:
> On Wed, Apr 14, 2021 at 03:09:13PM -0400, Michael Meissner wrote:
> > On Tue, Apr 13, 2021 at 05:19:12PM -0500, Segher Boessenkool wrote:
> > > > * config/rs6000/rs6.h (FLOAT128_MIN_MAX_FPMASK_P): New
> > > > macro.
On Wed, Apr 14, 2021 at 02:38:47PM -0500, Segher Boessenkool wrote:
> On Fri, Apr 09, 2021 at 10:43:58AM -0400, Michael Meissner wrote:
> > (Fv mode attribute): Add KFmode and TFmode.
> > (movcc_fpmask): Replace
> > movcc_p9. Add IEEE 128-bit fp support.
> >
On Tue, Apr 13, 2021 at 05:19:12PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Fri, Apr 09, 2021 at 10:42:50AM -0400, Michael Meissner wrote:
> > Since then the patch seems to have gone into a limbo state.
>
> Patches I cannot immediately handle take time, and if they aren't
> pinged, they can
Fix logic error in 32-bit trampolines, PR target/98952.
The test in the PowerPC 32-bit trampoline support is backwards. It aborts
if the trampoline size is greater than the expected size. It should abort
when the trampoline size is less than the expected size.
I verified this by creating a
Add IEEE 128-bit fp conditional move on PowerPC.
This patch has been posted various times in the past. My memory is the last
time I changed the patch, I addressed the concerns posted at that time. Since
then the patch seems to have gone into a limbo state.
This patch adds the support for
Add IEEE 128-bit min/max support on PowerPC.
This patch has been posted various times in the past. My memory is the last
time I changed the patch, I addressed the concerns posted at that time. Since
then the patch seems to have gone into a limbo state.
This patch adds the support for the IEEE
These patches have been posted quite a few times before. My memory is I
addressed the concerns posted with the last set of changes in November.
These two patches add support for the ISA 3.1 (power10) instructions xsmaxcqp,
xsmincqp, xscmpeqqp, xscmpgeqp, and xscmpgtqp.
I have tested these
On Sat, Mar 27, 2021 at 04:07:18PM +0100, Florian Weimer wrote:
> This issue is still present.
>
> What about the patch below?
>
> Thanks,
> Florian
>
> rs6000: Do not build _Float128/Decimal routines with --disable-decimal-float
>
> Fixes commit 781183595acba67a37c66f59a0c1d9b5fee7e248 ("Add
On Sat, Mar 27, 2021 at 04:07:18PM +0100, Florian Weimer wrote:
> This issue is still present.
>
> What about the patch below?
>
> Thanks,
> Florian
>
> rs6000: Do not build _Float128/Decimal routines with --disable-decimal-float
>
> Fixes commit 781183595acba67a37c66f59a0c1d9b5fee7e248 ("Add
Ping patch.
| Subject: [PATCH V3] Do not build Decimal/Float128 conversions if
--disable-decimal-float.
| Message-ID: <20210304210803.ga...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone:
Ping patch.
| Subject: [PATCH, V3] Require GLIBC 2.32 for Decimal/_Float128 conversions.
| Message-ID: <20210304210135.ga32...@ibm-toto.the-meissners.org>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978)
[PATCH 2/2 V3] Do not build Decimal/Float128 conversions if
--disable-decimal-float.
This patch disables building the Decimal/_Float128 conversion functions if the
user configured the compiler with the --disable-decimal-float option.
This is a much simpler patch to disable building the
[PATCH V3] Require GLIBC 2.32 for Decimal/_Float128 conversions.
In the patch that I applied on March 2nd, I had code to provide support for
Decimal/_Float128 conversions if the user did not use at least GLIBC 2.32. It
did this by using __ibm128 as an intermediate type. The trouble is __ibm128
On Wed, Mar 03, 2021 at 11:33:52PM +, Joseph Myers wrote:
> On Wed, 3 Mar 2021, Michael Meissner via Gcc-patches wrote:
>
> > As we have discussed many times, on 32-bit BE, you cannot use hardware
> > _Float128 support on power9/power10 because there is no TImode in 3
On Tue, Mar 02, 2021 at 03:53:06PM -0600, Segher Boessenkool wrote:
> If you want to make decimal and/or QP float work only on 64-bit LE Linux
> you should say so. And in that case, that is certainly not acceptable
> if it doesn't "sorry" at configure time already.
Well in general the only
On Mon, Mar 01, 2021 at 05:15:44PM -0600, Segher Boessenkool wrote:
> On Mon, Mar 01, 2021 at 12:18:52PM -0500, Michael Meissner wrote:
> > The _sprintfkf.c file was including stdio.h to get the definition of
> > sprintf.
>
> (declaration of)
>
> > This patch modifies this so that stdio.h is
[PATCH 3/3 V2] Do not build Decimal/Float128 conversions if decimal is disabled.
This patch suppresses building the Decimal <-> Float128 conversions if the user
used --disable-decimal-float when configuring GCC.
I have done bootstraps on a little endian power9 system with each of the long
double
[PATCH 2/3 V2] Do not include stdio.h in libgcc's Decimal/Float128 conversions.
The _sprintfkf.c file was including stdio.h to get the definition of sprintf.
This patch modifies this so that stdio.h is not included in order to support
freestanding cross compilers that might not provide stdio.h.
[PATCH 1/3 V2] Fix __sprintfkf prototype in libgcc.
The prototype of __sprintfkf in _sprintfkf.h did not match the function in
_sprintfkf.c. This patch fixes the prototype. I also included the
_sprintfkf.h file in _sprintfkf.c to make sure the prototype is correct and to
eliminate a warning
I have broken the patches I submitted on Friday February 26th into 3 patches.
These patches allow us to build the libgcc library on PowerPC for VSX systems
and optionally enable/disable the Decimal support. If Decimal support is
disabled, then the Float128 <-> Decimal conversions are not built.
On Fri, Feb 26, 2021 at 04:36:20PM -0600, Segher Boessenkool wrote:
> On Fri, Feb 26, 2021 at 01:33:41AM -0500, Michael Meissner wrote:
> > Honor --disable-decimal-float in building _Float128 support.
> >
> > Joseph Myers reported that my previous patch to add conversions between
> > _Float128
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