On Tue, Jan 22, 2019 at 7:48 AM Joseph Myers wrote:
>
> On Mon, 21 Jan 2019, H.J. Lu wrote:
>
> > TI->SF and TI->DF conversions in libgcc2.c:
> >
> > FSTYPE
> > FUNC (DWtype u)
> > {
> > ...
> > }
> >
> > have no rounding mode support. We should replace __floattisf, __floattidf,
> > __floatunti
On Thu, Dec 6, 2018 at 9:31 AM wuyuan (E) wrote:
>
> Hi ARM maintainers:
> The taishanv110 core uses generic pipeline scheduling, which
> restricted the performance of taishanv110 core. By adding the pipeline
> scheduling of taishanv110 core in GCC,The performance of taishanv110 has been
On Fri, Nov 9, 2018 at 6:05 PM Uros Bizjak wrote:
>
> On Fri, Nov 9, 2018 at 10:54 AM Wei Xiao wrote:
> >
> > Hi Uros
> >
> > Thanks for the remarks!
> > I improve the patch as attached to address the issues you mentioned:
> > 1. No changes to substs any more.
> > 2. Adopt established approach (e
Hi there,
This patch intends to fix PR87853 by involving a new 'signed char'
vector type to avoid the impact of option -funsigned-char. Tested with
bootstrap and regression tests on x86_64. No regressions.
Is it OK to trunk and release branch?
BR,
Terry
diff --git a/gcc/ChangeLog b/gcc/ChangeLo
On Tue, Sep 4, 2018 at 11:53 AM, Paul Hua wrote:
> On Mon, Sep 3, 2018 at 8:29 PM Paul Hua wrote:
>>
>>
>
> Hi:
>
> The v2 patch add:
> * gcc/doc/invoke.texi (-mloongson-mmi): Document.
>
> Thanks
> Paul Hua
Hi Paul,
For the new files, I think the copyright year should be just 2018.
diff --git
Hi,
This is to update my email address per my recent job change.
BR,
Terry
2018-09-04 Xuepeng Guo
* MAINTAINERS: Update my email address.
Index: MAINTAINERS
===
--- MAINTAINERS (revision 264074)
+++ MAINTAINERS (working copy
On Thu, Apr 23, 2015 at 4:37 PM, Kyrill Tkachov wrote:
>
> On 23/04/15 09:25, Terry Guo wrote:
>>
>> On Thu, Apr 23, 2015 at 4:23 PM, Kyrill Tkachov
>> wrote:
>>>
>>> Hi Terry,
>>>
>>> On 23/04/15 02:56, Terry Guo wrote:
>>>&g
On Thu, Apr 23, 2015 at 4:23 PM, Kyrill Tkachov wrote:
> Hi Terry,
>
> On 23/04/15 02:56, Terry Guo wrote:
>>
>> /* { dg-do compile } */
>> -/* { dg-options "-march=armv6-m -mthumb -O3 -w -mfloat-abi=soft" } */
>> +/* { dg-options "-mthumb -O2 -m
Hi there,
This patch is to correct options in arm test case pr65710.c. I reused
some existing test case as template to produce this case, but forgot
to update the options. Is it OK to trunk?
BR,
Terry
2015-04-23 Terry Guo
* gcc.target/arm/pr65710.c: Update the options.
diff --git a/gcc
On Wed, Apr 22, 2015 at 10:30 AM, Segher Boessenkool
wrote:
> On Wed, Apr 22, 2015 at 10:21:43AM +0800, Terry Guo wrote:
>> gcc/ChangeLog:
>> 2015-04-22 Hale Wang
>> Terry Guo
>>
>>PR rtl-optimization/64818
>>* combin
On Wed, Apr 22, 2015 at 9:44 AM, Segher Boessenkool
wrote:
> On Tue, Apr 21, 2015 at 03:13:38PM +0800, Terry Guo wrote:
>> > Did you fix the comment? REG_USERVAR_P and HARD_REGISTER_P can be
>> > set for more than just register asm.
>>
>> Sorry for missing the
On Tue, Apr 21, 2015 at 11:03 AM, Segher Boessenkool
wrote:
> On Tue, Apr 21, 2015 at 09:39:16AM +0800, Terry Guo wrote:
>> Is this one ok to trunk?
>
> Probably, if you send the patch + changelog entry :-)
>
> Did you fix the comment? REG_USERVAR_P and HARD_REGISTER_P can b
Hi there,
Is this one ok to trunk?
BR,
Terry
On Wed, Apr 15, 2015 at 6:45 PM, Hale Wang wrote:
> Ping for trunk?
>
> Hale
>
>> -Original Message-
>> From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
>> Sent: Friday, February 27, 2015 4:04 AM
On Sat, Apr 11, 2015 at 5:48 AM, Gerald Pfeifer wrote:
> Hi Terry,
>
> I went ahead and committed some small changes to the description of
> -masm-syntax-unified. Let me know if you disagree or would like to
> see further changes.
>
> Gerald
>
Thanks for the improvement. I am totally ok with the
75 +325,6 @@ extern const char *arm_rewrite_selected_cpu (const char
>> *name);
>>
>> extern bool arm_is_constant_pool_ref (rtx);
>>
>> -/* Flags used to identify the presence of processor capabilities. */
>
> You've lost this comment in the new file. Was
On Wed, Mar 4, 2015 at 10:44 AM, Terry Guo wrote:
> On Mon, Mar 2, 2015 at 9:08 PM, Maxim Kuvyrkov
> wrote:
>>> On Mar 2, 2015, at 4:44 AM, Terry Guo wrote:
>>>
>>> Hi there,
>>>
>>> If target mode isn't specified via either gcc configur
On Mon, Mar 2, 2015 at 9:08 PM, Maxim Kuvyrkov
wrote:
>> On Mar 2, 2015, at 4:44 AM, Terry Guo wrote:
>>
>> Hi there,
>>
>> If target mode isn't specified via either gcc configuration option
>> --with-mode or command line, this patch intends to improve
On Mon, Mar 2, 2015 at 9:08 PM, Maxim Kuvyrkov
wrote:
>> On Mar 2, 2015, at 4:44 AM, Terry Guo wrote:
>>
>> Hi there,
>>
>> If target mode isn't specified via either gcc configuration option
>> --with-mode or command line, this patch intends to improve
?
BR,
Terry
gcc/ChangeLog:
2015-03-02 Terry Guo
* common/config/arm/arm-common.c (arm_is_target_thumb_only): New
function.
* config/arm/arm-protos.h (FL_ Macros): Move to ...
* config/arm/arm-opts.h (FL_ Macros): ... here.
(struct arm_arch_core_flag): New s
On Thu, Feb 26, 2015 at 1:55 PM, Segher Boessenkool
wrote:
> On Tue, Feb 17, 2015 at 11:39:34AM +0800, Terry Guo wrote:
>> On Sun, Feb 15, 2015 at 7:35 PM, Segher Boessenkool
>> wrote:
>> > Hi Terry,
>> >
>> > I still think this is stage1 material.
>&
On Tue, Feb 17, 2015 at 11:39 AM, Terry Guo wrote:
> On Sun, Feb 15, 2015 at 7:35 PM, Segher Boessenkool
> wrote:
>> Hi Terry,
>>
>> I still think this is stage1 material.
>>
>>> + /* Don't combine if dest contains a user specified register and i3
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Richard Earnshaw
> Sent: Wednesday, February 18, 2015 2:45 AM
> To: Terry Guo; gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw; Ramana Radhakrishnan
> Sub
On Sun, Feb 15, 2015 at 7:35 PM, Segher Boessenkool
wrote:
> Hi Terry,
>
> I still think this is stage1 material.
>
>> + /* Don't combine if dest contains a user specified register and i3
>> contains
>> + ASM_OPERANDS, because the user specified register (same with dest) in
>> i3
>> + w
On Fri, Feb 13, 2015 at 5:06 PM, Richard Sandiford
wrote:
> Segher Boessenkool writes:
>> On Thu, Feb 12, 2015 at 03:54:21PM +, Richard Sandiford wrote:
>>> "Hale Wang" writes:
>>> > Ping?
>>
>> It's not a regression (or is it?), so it is not appropriate for stage4.
>>
>>
>>> >> diff --git a
Hi there,
This patch intends to prevent gcc from putting volatile memory access into
IT block for target like cortex-m7.
gcc/ChangeLog:
2015-02-12 Terry Guo
* config/arm/arm.c (arm_tune_cortex_m7): New global variable.
* config/arm/arm.h (TARGET_NO_VOLATILE_CE): New macro
> -Original Message-
> From: Gerald Pfeifer [mailto:ger...@pfeifer.com]
> Sent: Thursday, January 29, 2015 2:53 AM
> To: Terry Guo
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw; Ramana Radhakrishnan
> Subject: RE: [Patch][wwwdocs]Deprecate the ARM TPCS related op
> -Original Message-
> From: Gerald Pfeifer [mailto:ger...@pfeifer.com]
> Sent: Monday, January 26, 2015 7:34 PM
> To: Terry Guo
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw; Ramana Radhakrishnan
> Subject: Re: [Patch][wwwdocs]Deprecate the ARM TPCS related op
Hi there,
This patch intends to update gcc 5.0 change.html to deprecate TPCS related
options because TPCS is obsoleted per the ABI document at
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042e/IHI0042E_aapcs.pdf.
Is it OK?
BR,
Terry
Index: htdocs/gcc-5/changes.html
===
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Ramana Radhakrishnan
> Sent: Friday, January 23, 2015 6:35 PM
> To: Tony Liu
> Cc: gcc-patches; Ramana Radhakrishnan; Richard Earnshaw
> Subject: Re: [PATCH, ARM, testsuite] I
. Tested
with GCC regression test, no regressions. Is it OK?
BR,
Terry
2015-01-14 Terry Guo
* config/arm/arm.c (arm_file_start): Update the assignment of
Tag_ABI_HardFP_use.diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 0ec526b..378bed9 100644
--- a/gcc/config/arm/arm.c
> -Original Message-
> From: Richard Earnshaw
> Sent: Monday, December 08, 2014 7:31 PM
> To: Terry Guo; gcc-patches@gcc.gnu.org
> Cc: Ramana Radhakrishnan
> Subject: Re: [Patch, ARM/Thumb1]Add a Thumb1 insn pattern to legalize the
> instruction that moves pc to lo
> -Original Message-
> From: Jakub Jelinek [mailto:ja...@redhat.com]
> Sent: Wednesday, December 17, 2014 4:20 PM
> To: Terry Guo
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [Backport]Is it ok to backport this bug fix to 4.8 branch?
>
> On Wed, Dec 17, 2014 at 04:
Hi Jakub,
Is it OK to back port revision 209293 to upstream 4.8 branch as it fixed bug
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60663? Thanks.
BR,
Terry
a legal instruction. Because gcc returns NO_REG for PC register, so no
valid pattern to match instruction that move pc to low register. This patch
intends to add a new insn pattern to legalize such thing.
Tested with GCC regression test. No regression. Is it OK to trunk?
BR,
Terry
2014-12-08 Terry Gu
Hi there,
This patch will document support and tuning for Cortex-M7 in GCC 5.0
changes. Is it ok to commit?
BR,
Terry
2014-11-26 Terry Guo
* htdocs/gcc-5/changes.html: Mention Cortex-M7.
Index: htdocs/gcc-5/changes.html
> -Original Message-
> From: Kyrill Tkachov [mailto:kyrylo.tkac...@arm.com]
> Sent: Tuesday, November 18, 2014 11:08 PM
> To: Terry Guo; gcc-patches@gcc.gnu.org
> Cc: ger...@pfeifer.com
> Subject: Re: [PATCH][wwwdocs] Update 5.0 changes.html with Thumb1 UAL
>
&
Hi there,
This patch documents recent Thumb-1 UAL feature in trunk. Is it OK?
BR,
TerryIndex: changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-5/changes.html,v
retrieving revision 1.27
diff -u -r1.27 changes.html
--- changes.ht
gcc/ChangeLog:
2014-11-14 Terry Guo
* config/arm/thumb1.md (*addsi3_cbranch_scratch): Updated to UAL
format.
gcc/testsuite/ChangeLog:
2014-11-14 Terry Guo
* gcc.target/arm/thumb1-ual-1.c: New test.diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index 3d6f80b
Hi there,
Attached patch intends to add pipeline description for ARM MCU Cortex-M7.
Is it ok to trunk?
BR,
Terry
2014-11-12 Terry Guo
* config/arm/arm.c (arm_issue_rate): Return 2 for cortex-m7.
* config/arm/arm.md (generic_sched): Exclude cortex-m7.
(generic_vfp
> -Original Message-
> From: Terry Guo [mailto:terry@arm.com]
> Sent: Friday, November 07, 2014 6:01 PM
> To: 'Christian Bruel'
> Cc: gcc-patches@gcc.gnu.org
> Subject: RE: [2/2][PATCH,ARM]Generate UAL assembly code for Thumb-1
> target
>
7; will be used rather than the 'mov'.
The multilib for ARM/Thumb1/hard-float all can be built. Tested with
regression test on armv4t thumb and v6m thumb. No regression. Is it ok to
trunk?
BR,
Terry
2014-11-11 Terry Guo
* doc/invoke.texi (-masm-syntax-unified): Reword and fi
> -Original Message-
> From: Christian Bruel [mailto:christian.br...@st.com]
> Sent: Friday, November 07, 2014 5:27 PM
> To: Terry Guo
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [2/2][PATCH,ARM]Generate UAL assembly code for Thumb-1
> target
>
> hi,
>
Hi there,
Attached patch intends to enable GCC generate UAL format code for Thumb1
target. Tested with regression test and no regressions. Is it OK to trunk?
BR,
Terry
2014-10-21 Terry Guo
* config/arm/arm.c (arm_output_mi_thunk): Use UAL for Thumb1
target.
* config
the inline
assembly code uses non-UAL, then gcc will insert some directives in final
assembly code. Is it ok to trunk?
BR,
Terry
2014-10-21 Terry Guo
* config/arm/arm.h (TARGET_UNIFIED_ASM): Also include thumb1.
(ASM_APP_ON): Redefined.
* config/arm/arm.c
The required Binutils support is
https://sourceware.org/ml/binutils/2014-09/msg00201.html.
Is it OK to trunk?
BR,
Terry
2014-09-24 Terry Guo
* config/arm/arm-cores.def (cortex-m7): New core name.
* config/arm/arm-fpus.def (fpv5-sp-d16): New fpu name.
(fpv5-d16): Ditto
Hi there,
The gcc now uses immediate_operand for const_double_operand, update this
split pattern accordingly. Tested with gcc regression test on thumb1 target,
no regression. Is it ok to trunk?
BR,
Terry
2014-08-20 Terry Guo
* config/arm/thumb1.md (64bit splitter): Replace
Hi there,
As the second and final patch in this series, it intends to update alu_reg
and alus_reg types for AArch64 port. With this change, the gcc can be
successfully built for AArch64. Is it OK to trunk?
BR,
Terry
2014-07-10 Terry Guo
* config/aarch64/aarch64.md (*addsi3_aarch64
alus_reg is
renamed to alus_sreg in terms of consistence. This is the first patch of
this series and intends to cover the files under gcc/config/arm. Tested with
gcc regression, no new regressions. Is it ok to trunk?
BR,
Terry
2014-07-10 Terry Guo
* config/arm/types.md (alu_reg): Replaced
> -Original Message-
> From: Richard Earnshaw
> Sent: Wednesday, June 18, 2014 4:31 PM
> To: Terry Guo
> Cc: gcc-patches@gcc.gnu.org; Ramana Radhakrishnan
> Subject: Re: [Patch, GCC/Thumb-1]Mishandle the label type insn in function
> thumb1_reorg
>
> On 10/0
thumb1 target are caused by
this reason. So with this patch, all of them passed and no new failures. Is
it ok to trunk?
BR,
Terry
2014-06-10 Terry Guo
* config/arm/arm.c (thumb1_reorg): Move to next basic block if the head
of current basic block isn’t a proper insn. diff --git a/gcc
> -Original Message-
> From: Ramana Radhakrishnan [mailto:ramana@googlemail.com]
> Sent: Wednesday, May 21, 2014 4:56 PM
> To: Terry Guo
> Cc: gcc-patches; Richard Earnshaw; Ramana Radhakrishnan
> Subject: Re: [Patch, GCC/Thumb1] Improve 64bit consta
Hi there,
I just committed attached patch to enable build multilib for ARM
embedded-4_9-branch.
BR,
Terry
2014-05-12 Terry Guo
* config.gcc (--with-multilib-list): Accept arm embedded cores.
* configure.ac (with_multilib_list): Export for being used in arm
embedded
On Mon, Apr 14, 2014 at 6:13 PM, Terry Guo wrote:
> On Thu, Apr 3, 2014 at 10:11 PM, Eric Botcazou wrote:
>>> I find the GCC function simplify_subreg fails to simplify rtx (subreg:SI
>>> (and:DI (reg/v:DI 115 [ a ]) (const_int 4294967295 [0x])) 4) to zero
>&g
Ping ...
BR,
Terry
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Terry Guo
> Sent: Friday, April 11, 2014 3:36 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw; Ramana Radhakrishnan
> Subjec
On Thu, Apr 3, 2014 at 10:11 PM, Eric Botcazou wrote:
>> I find the GCC function simplify_subreg fails to simplify rtx (subreg:SI
>> (and:DI (reg/v:DI 115 [ a ]) (const_int 4294967295 [0x])) 4) to zero
>> during the fwprop1 pass, considering the fact that the high 32-bit part of
>> (a & 0x
Hi there,
Could you please review patch at
http://gcc.gnu.org/ml/gcc-patches/2014-03/msg00790.html? Thanks.
BR,
Terry
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Terry Guo
> Sent: Monday, March 17, 2014 1
:
ldr r1, .L2+4
ldr r0, .L2
.L2:
.word 1
.word 1
The attached patch intends to split 64bit load to take advantage of such
chances. Tested with gcc regression test on cortex-m0. No new regressions.
Is it ok to stage 1?
BR,
Terry
gcc/
2014-04-11 Terry Guo
Hello Eric,
Would you please review my patch at
http://gcc.gnu.org/ml/gcc-patches/2014-03/msg01582.html? Thanks.
BR,
Terry
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Terry Guo
> Sent: Friday, March 28, 2014 3:48 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [Patch]Simplify SUBREG with operand whose target bits are cleared
Hi there,
When compile below case for ARM Thumb-2 target:
long long int
test (unsigned long long int a, unsigned int b)
{
return (a & 0x) * b;
}
I find the GCC function simplify_subreg fails to simplify rtx (subreg:SI
(and:DI (reg/v:DI 115 [ a ]) (const_int 4294967295 [0x])) 4)
K to trunk?
BR,
Terry
2014-03-17 Terry Guo
* config/arm/arm.md (cstoresi_leu_thumb1): New define_insn_and_split
pattern.
(cstoresi4): Use above new pattern.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 2ddda02..905a5b8 100644
--- a/gcc/config/arm/arm.md
t in arm.h.
In this way, the variable will be correctly reset and ready for being used
for Thumb1 target in future.
Tested with gcc regression test for Thumb1 target cortex-m0. No new
regressions.
Is it ok to trunk?
BR,
Terry
2014-03-17 Terry Guo
* config/arm/arm.h (machine_functio
y
2014-02-25 Terry Guo
* config/arm/arm.h (ASM_APP_OFF): Re-define it in a cleaner way.From fd607bf3a164e885a6e16a1028feff11b8a653bc Mon Sep 17 00:00:00 2001
From: Terry Guo
Date: Thu, 2 Jan 2014 15:08:55 +0800
Subject: [PATCH] patch
---
gcc/config/arm/arm.h | 3 +--
1 file change
Hi,
This small patch intends to add missing armv7e-m in the documentation of ARM
option -march. I will commit it to trunk and then back port to 4.7/4.8
branch as obvious.
BR,
Terry
2014-02-08 Terry Guo
* doc/invoke.texi: Document ARM -march=armv7e-m.
diff --git a/gcc/doc
> -Original Message-
> From: Richard Earnshaw
> Sent: Friday, January 17, 2014 12:22 AM
> To: Terry Guo
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [GCC, ARM] Backport trunk patch to 4.8 to reclassify ARM
> preload insn
>
> On 16/01/14 07:33, Terry Guo wro
(working copy)
@@ -1,3 +1,271 @@
+2014-01-16 Terry Guo
+
+ PR target/59826
+ Partial Backport from mainline r202323.
+ 2013-09-06 James Greenhalgh
+
+ * config/arm/types.md: Add "no_insn", "multiple" and "untyped"
+ types.
+ * con
> -Original Message-
> From: Richard Earnshaw
> Sent: Wednesday, January 15, 2014 10:30 PM
> To: Terry Guo
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [GCC, ARM] Backport trunk fix to 4.8 branch to properly
handle
> rtx of ARM PLD instruction
>
> On 15/0
> -Original Message-
> From: Terry Guo [mailto:terry@arm.com]
> Sent: Wednesday, January 15, 2014 8:21 PM
> To: Richard Earnshaw
> Cc: gcc-patches@gcc.gnu.org
> Subject: RE: [GCC, ARM] Backport trunk fix to 4.8 branch to properly
handle
> rtx o
>
> Preferably, particularly since you haven't supplied a testcase.
>
> R.
Bug is reported at http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59826. I
shall update the patch to include the test case.
BR,
Terry
> -Original Message-
> From: Richard Earnshaw
> Sent: Wednesday, January 15, 2014 5:54 PM
> To: Terry Guo
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [GCC, ARM] Backport trunk fix to 4.8 branch to properly
handle
> rtx of ARM PLD instruction
>
> On 15/0
regression test, no new
regressions. Is it ok to back port?
BR,
Terry
2014-01-15 Terry Guo
Backported from mainline r204575 and applied to file arm.c.
2013-11-08 James Greenhalgh
* config/arm/aarch-common.c
(search_term): New typedef.
(shift_rtx_costs
Hi There,
This patch intends to check value of --with-arch against the arm-arches.def,
rather than current solution that use hard coded things in config.gcc.
Tested with various values of --with-arch and it works. Is it ok to trunk?
BR,
Terry
2013-12-30 Terry Guo
* config.gcc (arm
> -Original Message-
> From: Richard Earnshaw
> Sent: Thursday, November 28, 2013 7:09 PM
> To: Terry Guo
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [Patch, ARM] Add v7m specific extra rtx cost table
>
> On 28/11/13 10:34, Terry Guo wrote:
> > Hello,
>
Hello,
This patch intends to add a specific extra rtx cost table for v7-m profile
targets. Tested with gcc regression test, no new regressions. Is it OK to
trunk?
BR,
Terry
2013-11-28 Terry Guo
* config/arm/aarch-cost-tables.h (v7m_extra_costs): New table.diff --git a/gcc/config
> -Original Message-
> From: Richard Earnshaw
> Sent: Tuesday, November 26, 2013 5:44 PM
> To: Terry Guo
> Cc: Ramana Radhakrishnan; gcc-patches@gcc.gnu.org
> Subject: Re: [Patch, ARM] Fix ICE when high register is used as pic base
> register for thumb1 target
&
Hi,
This patch back ported a trunk cortex-m4 FPU tuning to embedded-4_8-branch.
BR,
Terry
gcc/ChangeLog.arm
2013-11-28 Terry Guo
Backport mainline r198084
2013-04-19 Terry Guo
* config/arm/cortex-m4-fpu.md (cortex_m4_v): Delete cpu unit.
Replace with
Hi,
This patch back ported a trunk M4 CPU pipeline tuning to
embedded-4_8-branch.
BR,
Terry
gcc/ChangeLog.arm
2013-11-28 Terry Guo
Backport mainline r198021
2013-04-17 Terry Guo
* config/arm/cortex-m4.md: Add a new bypass.
The patch itself:
Index: gcc/config/arm
> -Original Message-
> From: Joey Ye [mailto:joey.ye...@gmail.com]
> Sent: Thursday, November 28, 2013 10:56 AM
> To: Terry Guo
> Cc: gcc-patches
> Subject: Re: [arm-embedded] Backport trunk thumb1 pic fix to embedded-
> 4_8-branch
>
> Terry, this is a bug fix
Hi,
This patch back ported trunk fix at r205391 to arm/embedded-4_8-branch.
BR,
Terry
gcc/ChangeLog.arm
2013-11-27 Terry Guo
Backport mainline r205391
2013-11-26 Terry Guo
* config/arm/arm.c (require_pic_register): Handle high pic base
register for thumb
Hi,
This backport intends to enable new arm rtx cost model in trunk for
embedded-4_8-branch. The backport incorporates all relevant trunk commits
and some minor tweaks for embedded-4_8-branch. Tested with gcc regression
test and found one regression related to case pr42575.c. The upstream gcc
has
Hi,
This patch intends to fix ICE when high register is used for pic base
register for thumb1 target. Tested with gcc regression test, no new
regressions. Is it OK to trunk?
BR,
Terry
gcc/ChangeLog:
2013-11-26 Terry Guo
* config/arm/arm.c (require_pic_register): Handle high pic
Hi,
The trunk patch to support new option -mslow-flash-data at revision 205342
is back ported to arm/embedded-4_8-branch. Tested with regression test and
no regressions.
BR,
Terry
gcc/ChangeLog:
2013-11-26 Terry Guo
Backport mainline r205342
2013-11-25 Terry Guo
> -Original Message-
> From: Richard Earnshaw
> Sent: Wednesday, November 20, 2013 10:41 PM
> To: Terry Guo
> Cc: gcc-patches@gcc.gnu.org; Ramana Radhakrishnan
> Subject: Re: [Patch, ARM] New feature to minimize the literal load for
armv7-
> m target
>
> O
Ping.
BR,
Terry
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Terry Guo
> Sent: Wednesday, November 06, 2013 2:11 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw; Ramana Radhakrishnan
> Subj
this purpose. So far this feature doesn't support PIC code and target that
isn't based on armv7-m.
Tested with GCC regression test on QEMU for cortex-m3. No new regressions.
Is it OK to trunk?
BR,
Terry
2013-11-06 Terry Guo
* doc/invoke.texi (-mslow-flash-data): Do
Hello,
The arm/embedded-4_7-branch is just synced with FSF 4.7 branch. Lots of bug
fixes are included now.
BR,
Terry
Hi there,
The FSF 4.7 branch still has bug
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54598. May I backport trunk fix
to 4.7 branch?
Thanks and best regards,
Terry
Hi,
I just did this trunk back port to enable 4.7 embedded branch to use single
multiply instruction when optimize for size. Without this back port, current
4.7 embedded branch will use a group instructions to replace single multiply
instruction.
BR,
Terry
gcc/
2013-08-28 Terry Guo
Hello Joey,
The thumb1 far jump patch is about an optimization to avoid unnecessary lr
save instruction. It is now in trunk. Is it OK to back port it to embedded
4.8 branch?
BR,
Terry
gcc/ChangeLog.arm
2013-08-05 Terry Guo
Backport from mainline r197956
2013-04-15 Joey
Hi Joey,
Attached patch is a backport to support cortex-r7 in gcc command line.
Tested and it works.
Is it OK to commit?
BR,
Terry
2013-08-05 Terry Guo
Backport from mainline r197153
2013-03-27 Terry Guo
* config/arm/arm-cores.def: Added core cortex-r7
Hi Joey,
This patch is to define multilibs for recently created embedded-4_8-branch.
Is it OK to commit?
BR,
Terry
2013-07-24 Terry Guo
* configure.ac (with_multilib_list): Export its value.
* Makefile.in (with_multilib_list): Import it from configure files
with GCC regression test on QEMU ARM926, no regression. Is it OK to
trunk and 4.8 branch?
BR,
Terry
gcc/ChangeLog:
2013-07-24 Terry Guo
* config/arm/arm.c (thumb1_size_rtx_costs): Assign proper cost for
shift_add/shift_sub0/shift_sub1 RTXs.
gcc/testsuite/ChangeLog:
2013-07-24
Ping.
BR,
Terry
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Terry Guo
> Sent: Monday, June 03, 2013 6:02 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw; Ramana Radhakrishnan
> Subject: [P
Hello,
This patch (trunk r197155)
http://gcc.gnu.org/ml/gcc-cvs/2013-03/msg00784.html
fixes an ICE in gcc 4.8:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57329
OK to backport to 4.8 branch? Tested with 4.8 regression test on QEMU, no
new regression.
BR,
Terry
K for trunk?
BR,
Terry
2013-04-16 Terry Guo
* config/arm/cortex-m4-fpu.md (cortex_m4_v): Delete cpu unit.
Replace with ...
(cortex_m4_v_a, cortex_m4_v_b): ... new cpu units.
(cortex_m4_v, cortex_m4_exa_va, cortex_m4_exb_vb): New reservations.
(cortex_m4_fmacs)
Hello Ramana,
Can you please review my patch at
http://gcc.gnu.org/ml/gcc-patches/2013-03/msg01252.html.
Thanks.
Terry
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Terry Guo
> Sent: Friday, March 29, 2013
long as the result of LDR isn't used
as memory address of STR.
Tested with various benchmarks on Cortex-M4 MPS. Except one regression
caused by register allocation, the others either show performance
improvement or no change.
Is it OK to trunk?
BR,
Terry
2013-03-29 Terr
Hi Richard,
Can you please help to review this patch?
BR,
Terry
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Terry Guo
> Sent: Monday, March 04, 2013 10:46 AM
> To: gcc-patches@gcc.gnu.org
> Subject:
Ping...
The patch is at http://gcc.gnu.org/ml/gcc-patches/2013-02/msg01105.html.
BR,
Terry
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Terry Guo
> Sent: Monday, February 25, 2013 10:23 AM
> To: gcc-patc
Hi,
This patch is to enable GCC to accept new command line option
-mcpu=cortex-r7. Is it OK to trunk?
BR,
Terry
2013-02-25 Terry Guo
* config/arm/arm-cores.def: Added core cortex-r7.
* config/arm/arm-tune.md: Regenerated.
* config/arm/arm-tables.opt: Regenerated
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