http://www.h-online.com/open/news/item/CERN-launches-Open-Hardware-Licence-1-1-1276096.html
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On Jul 8, 2011, at 12:26 PM, Mike Jarabek wrote:
> No autorouter is needed... Just place the generated symbols on a grid, so
> they don't touch, and add wire stubs to each pin. Each wire should have a
> netname attribute attached.
No need even for that. No graphics at all are required when yo
On Jul 8, 2011, at 2:47 PM,
wrote:
> I have been looking at the gschem file format, seems very
> straight forward and I created the symbols for the standard cells in the
> verilog netlists. A rats nest is fine, will never edit the schematic of
> any file created from the verilog file.
I set a
Dear Members,
I've just upgraded to newest available version of pcb opengl branch from git
(commit from 27 June, Only assign stencil planes where sub-compositing is
required) and I found out that silk screen is not drawn on far side of the
board.
Normally components that are on the far side are
Hi,
(Sorry for the top post)
No autorouter is needed... Just place the generated symbols on a grid, so they
don't touch, and add wire stubs to each pin. Each wire should have a netname
attribute attached.
The netlister will connect all similarly named nets together.
Any reason you can't jus
On Jul 7, 2011, at 4:31 PM,
wrote:
> I've looked at the mailing list archives and seen people ask but
> haven't seen if anyone has code to take a verilog netlist and create a
> gschem file from it. I don't care about what the schematic looks like,
> can be ugly. I just need to get it i
> Original Message
> Subject: Re: gEDA-user: verilog -> gschem
> From: Steven Michalske
> Date: Fri, July 08, 2011 1:46 pm
> To: gEDA user mailing list
> Will the gentlest backend for verilog accept symbols with the source
> attribute set, like hierarchy symbols, but > making
> Original Message
> Subject: Re: gEDA-user: verilog -> gschem
> From: Ouabache Designworks
> Date: Fri, July 08, 2011 9:43 am
> To: geda-user@moria.seul.org
>
>
> The only difference between that and and PCB layout program is that you
> don't care about trace width and you can
Will the gentlest backend for verilog accept symbols with the source attribute
set, like hierarchy symbols, but making them point to Verilog source not a
sch source?
Steve
On Jul 8, 2011, at 1:29 PM, wrote:
>> Original Message
>> Subject: Re: gEDA-user: verilog -> gschem
> Original Message
> Subject: Re: gEDA-user: verilog -> gschem
> From: John Griessen
> Date: Fri, July 08, 2011 9:27 am
> To: gEDA user mailing list
>
> On 07/07/11 17:31, fr...@frankthomson.net wrote:
>> I just need to get it into gschem format to run through
>> gnetlist to a
Message: 1
Date: Thu, 07 Jul 2011 15:31:44 -0700
From: <[1]fr...@frankthomson.net>
Subject: gEDA-user: verilog -> gschem
To: [2]geda-user@moria.seul.org
Message-ID:
<[3]20110707153144.97bc9b90117a8175dad249389209a753.5acdf95b97.wbe@e
mail04.secureserver.net>
On 07/07/11 17:31, fr...@frankthomson.net wrote:
I just need to get it into gschem format to run through
gnetlist to a different netlist format.
There is a gnetlist backend for verilog-ams.
You don't need to make schematics, just learn
enough scheme/guile to fix up the exiting
gnetlist ba
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