Using HP G72 notebook, intel I3, Intel graphics
On Thu, Sep 15, 2011 at 12:13 PM, DJ Delorie <[1]d...@delorie.com> wrote:
We're trying to track down the zoom bug. If you have access to a
windows machine, please try this PCB snapshot:
[2]ftp://ftp.delorie.com/pub/geda-window
...and pcb is the only CAD program I know of, that does like this
I've run across other PC layout tools which do this. Mechanical CAD
tools usually have (by default) Y+ pointing up, but for some reason PC
design tools occasionally have Y+ facing down. I don't remember any of
these
On Sun, Sep 5, 2010 at 2:19 PM, Peter Clifton <[1]pc...@cam.ac.uk>
wrote:
On Sun, 2010-09-05 at 00:18 +0200, Levente Kovacs wrote:
> On Sat, 4 Sep 2010 11:24:38 +
> Ineiev <[2]ine...@gmail.com> wrote:
>
> > Probably this patch may be used as a workaround.
>
On Tue, Aug 17, 2010 at 5:05 PM, kai-martin knaak
<[1]...@familieknaak.de> wrote:
Oliver King-Smith wrote:
> 1) It is useful for seeing the decoupling caps on various components
and
> checking they have been done to spec.
> 2) Often there are multiple power rails in the schema
May be unrelated, but I had a problem years ago running from a (samba)
SMB share and having the files corrupted. One thing I recall that made
a difference was to alter (reduce or turn off) the caching that is
normally engaged to improve performance. You may want to experiment
with
Flipping the anchor at 180 degrees rotation is IMHO unwanted and
unexpected magic. I think I remember being annoyed by this in the
past. What happens when you do this in a batch mode? Can it be
reversed?
It would be better if the on-screen font size matched the printed
size.
If the balls haven't been deformed, the surface tension of the solder
does help the part align. It's interesting to see the part get pulled
into position as the solder melts.
I've seen a switcher chip (can't remember the p/n at the moment) that
has on the order of 80 balls, most of
Be careful mounting a part like this upside down. If the back side
pad on the part is critical to grounding or heat removal (like some
switching power supply controllers) you could easily cause the part to
malfunction or worse yet, fail altogether.
Joe T
On Tue, Apr 28, 2009 at
I think a few small holes are better than one large one. What you are
trying to achieve is a path for heat and maybe flux, but not solder.
To get solder to the part, either pre-tin the pad or use paste. Then
you are just heating the pad to re-flow the solder. Trying to apply
sold
I've done this, but not always with success.
First, get some fine solder paste and a flux pen.
When you do the layout, put a pad on the other side of the board,
connect with a few vias to the part's bottom pad. Be sure to have a
solder resist opening on the back side pad.
Apply
I just sent out a board which I had quoted on FR4 and Rogers 4350.
The Rogers material was more expensive, but for sure not 4x more. I
won't get the boards back for a couple days yet, but I've seen other
proto's they did for us (on .031" Rogers 4350 w/ immersion silver
plating) and
I generally do this kind of analysis separate from my layout tool (PCB
or whatever) because many of the other parameters needed for the
calculation are not usually tracked or updated by the layout tool
(dielectric constant, dielectric thickness, stackup, copper thickness,
distance from external con
On Tue, Oct 21, 2008 at 9:02 AM, Stefan Salewski
<[EMAIL PROTECTED]> wrote:
Sometimes the crosshair snaps to center of grid, overlapping grid
points, which are in inverse video in this case. But sometimes
crosshair
snaps to a position close to grid points, but not overla
I took a different approach which is a little more work. I added a
field to my symbols called "loadstatus" which I mark for "no load",
"through hole", or blank. Blank is the default, and means a SMT part
that is loaded. It's not hard to use gnetlist -g bom2 (if I remember
correct
Haven't tried this out yet but have some questions:
- How close do you have to be to "grab" the object?
- Is it dependent in any way on zoom or the grid spacing?
- Once you have made the selection, is your "anchor" point highlighted in
any way (for relative move operations for example)?
I'm not s
I've always handled this by making the symbol and footprint match. In other
words - you need a 3-pin symbol to match your 3-pin footprint. There is a
"NC" gschem symbol in the library for this purpose. You do have to be
careful of how gnetlist handles the "NC" net. It should not appear in the
n
I think it has always worked this way. However, it would be nice if there
was a filter for the area selection rectangle. Having it default to
grabbing only instances of symbols would solve your problem, but there are
often times when you might want to grab a bunch of text or attributes and
that d
How many +5 and gound net connections are there in your design?
Joe T
On Sat, Jun 14, 2008 at 11:45 PM, Ben Jackson <[EMAIL PROTECTED]> wrote:
> On Sat, Jun 14, 2008 at 12:34:55PM -0400, Ian Chapman wrote:
> > I have a ground plane and I keep connecting 5V to it because the rats
> > show up as a
Some gerber generators and viewers have a means to specify the number of
significant digits past the decimal point in their co-ordinates (e.g. X.XXX
or something like it). Check to see if that is set correctly.
Regarding the hpgl reference - is this a means to convert to the HPGL vector
format th
On Fri, Mar 14, 2008 at 7:16 AM, John Griessen <[EMAIL PROTECTED]> wrote:
> I came across this in a trade magazine, Chip Design, and copy excerpts
> that suggest what the "best of breed" tools can do. The author sees the
> collection of abilities
> as most valuable, and it seems not to be a copyr
On Mon, Mar 10, 2008 at 5:16 PM, Dave N6NZ <[EMAIL PROTECTED]> wrote:
>
> DJ Delorie wrote:
> >> PCB needs first class support for oblong through-holes.
> >
> > Yup. I've talked about a "multi-pin" before; this is a pin with
> > arbitrary shaped copper/soldermask/etc on each layer.
> >
> Yes, whe
If your netlist gets large enough you will hit this problem with several of
the scheme back-ends. It has been discussed in the list before. I don't
remember the exact syntax to fix it, but search the archives for stack
overflow 20 and I'll bet you find it.
Joe T
On Fri, Mar 7, 2008 at 7:13
I've seen the same behavior going back several revisions. At some point
certain refdes text becomes unselectable. Sometimes restarting the program
helps, sometimes I can get it back by turning layers off and on as you
describe.
A related issue I've seen is that pcb sometimes has a preference for
The netlist output is fairly simple and is probably fields separated by
spaces, tabs, or commas.
What format is he using to read in the file? Is he writing it our as the
same format? (.CSV?)
I've run into something like this and found that Excel was filtering out
extra spaces or putting quote mark
My recollection is that pins (1) an (2) are on the same side of the
package. Number CCW when viewed from top. As DJ said, this seems to be
consistent for BJT and FET parts. Diodes are another matter - when the part
contains a pair all arrangements are possible :).
Joe T
On Feb 6, 2008 8:21 AM,
On Feb 2, 2008 11:23 AM, Jeffrey Baker <[EMAIL PROTECTED]> wrote:
> Nearly every major part I need for my latest project is packaged in a QFN
> (or LFCSP as they call it over at Analog Devices). I'm worried because the
> parts have round leads and Sunstone, the PCB prototype shop, says they can't
On Jan 17, 2008 11:01 AM, Levente <[EMAIL PROTECTED]> wrote:
> On Thu, 17 Jan 2008 12:38:08 -0500
> Dan McMahill <[EMAIL PROTECTED]> wrote:
>
> > DJ Delorie wrote:
> > >>> This was fixed at one point, such that pcb itself would remove
> > >>> the silk over pins and pads, but I haven't migrated t
On Jan 12, 2008 10:18 AM, Dave McGuire <[EMAIL PROTECTED]> wrote:
> On Jan 12, 2008, at 10:11 AM, Dan McMahill wrote:
> >> This is very off topic, but I think one who likes tubes should visit
> >> this
> >> site.
> >>
> >> http://paillard.claude.free.fr/
> >
> > I don't speak french, but that vide
On Jan 2, 2008 6:31 PM, Dan McMahill <[EMAIL PROTECTED]> wrote:
> Is anyone using or has anyone used the centroid files (.xy files) that
> pcb exports?
>
> I'm asking because I just fixed a bug which has been there since the
> code was first written that flipped everything about the x-axis and als
On Dec 11, 2007 1:43 PM, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
> It currently uses the clearance. I'm not sure which it *should* use,
> or if we should redesign it to be independently adjustable.
>
>
> ___
> geda-user mailing list
> geda-user@moria.se
...
> If the industry has its act together enough to make that fully
> automated, I'd be surprised and pleased. I think that small-quantity
> prototype assembly doesn't even bother with all that and uses
> manually-guided pick and place machines. Those would presumably zoom
> to the coordinates
On Dec 2, 2007 9:08 PM, Julian <[EMAIL PROTECTED]> wrote:
> Frank,
>It looks like the RS274x manual has sloppy code in it. The G04 code
> in line 1 is supposed to end with a "*" at the end of the line to signal
> it is finished (see section on G-codes in the manual). gerbv keeps
> reading unt
Unless something has changed recently, be aware that gnetlist will connect
all NC pins together on a net called No-Connect. You may need to manually
delete it from the netlist. If you make it "graphical" as Ben suggests, the
DRC may not see it(?) and thus can't flag it as an error. (Please chime
If you are routing the slot, it will probably look like a "plating to board
edge" violation if you intend to run metal right up to and into the slot.
Be sure to check with the fab house to see if they would support this. Many
will not. In the past we always had to work with them to make sure we
On 10/24/07, Ben Jackson <[EMAIL PROTECTED]> wrote:
>
> On Wed, Oct 24, 2007 at 12:01:58PM +, Kai-Martin Knaak wrote:
> > You are not alone. Some months ago I, filed a feature request:
> > /--
> > | Add more complex modes of track manipulation:
> > | a)
On 10/24/07, Kai-Martin Knaak <[EMAIL PROTECTED]> wrote:
>
> On Tue, 23 Oct 2007 19:00:27 -0700, joe tarantino wrote:
>
> > A subtle point is that the "snap to to pins/pads" mode used to snap to
> > the center point (midpoint of the line between the two defin
On 10/23/07, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
>
> > Only if "snap to pin/pad" is selected. Otherwise just snap to the
> > nearest grid point.
>
> Well, yeah.
>
> > Are you saying "if we're within one grid spacing of one of the defining
> > points for the pin/pad..."? I'm just trying to be
On 10/23/07, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
>
> Would it be sufficient to say "if we're within the radius of the
> pin/pad's copper, snap to the pin/pad, else use the grid" ?
Only if "snap to pin/pad" is selected. Otherwise just snap to the nearest
grid point.
Currently, it's "if we're
On 10/20/07, Ben Jackson <[EMAIL PROTECTED]> wrote:
>
> On Fri, Oct 19, 2007 at 02:26:49PM +, Kai-Martin Knaak wrote:
> > On Wed, 17 Oct 2007 16:16:23 -0700, Ben Jackson wrote:
> >
> > > File a SF bug and point me at it and I'll see about fixing it.
> >
> > done. (ID 1816572)
> >
> > Looking fo
On 10/19/07, John Doty <[EMAIL PROTECTED]> wrote:
>
>
> On Oct 18, 2007, at 9:19 PM, Ales Hvezda wrote:
>
> >
> >> Peter B wants (and I think this is a good thing) to start embedding
> >> symbols by default, so this code will change at some point.
> >
> > I'm still on the fence on this change. All
DJ,
Good stuff!
I can see a use for thindraw with ps output. For gerber output however, it
makes little sense.
Joe T
On 7/31/07, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
>
> Just checked these in, some of them correspond to sourceforge tracker
> bugs, but I haven't annotated those yet. Feedbac
On 7/31/07, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
>
> When an two-pin element is mirrored to the other side, it would be
> nice if the pins stay in the same spot on the board, regardless of the
> element's orientation (currently, the pins get swapped if the element
> is vertically-oriented).
Do
On 7/24/07, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
http://www-nw.uni-regensburg.de/~.grr06742.back.physik.uni-regensburg.de/PCB/GPS_BUG.PCB
I reproduced it.
> If I try to draw a copper rectangle on GND-comp it either doesn't
> draw one at all or scrambles it in the lower left corner. Smaller
e functions,
so large schematics cause this. The real solution is to rewrite them
as properly tail-recursive. The interim solution is to adjust the
stack size to be much bigger:
http://archives.seul.org/geda/dev/Jan-2002/msg00024.html
Matt
On 6/25/07, joe tarantino <[EMAIL PROTECTED]> wrote:
>
&
I've noticed the same thing. Any time planes are shown, the redraw is ~ 10x
slower than it used to be. Is this a consequence of the new "polygon
clipping" code? If so, is there a way to turn it off or configure/build so
that it isn't being used? What would I lose?
I've also seen warning messa
Per the instructions, I often run "gnetlist -g drc2 " to check my
schematics. I've noticed recently that I get a stack overflow message
shortly after it has read in all the files. It still produces the drc
output, but without any clue as to what caused the stack overflow. The
overflow seems
I've used this part and several others in the same package. My $.02
worth...
- I would also recommend using the .01 mil resolution co-ordinate syntax.
- My experience is that most shops like the part co-ordinate origin to be
the centroid, not on pin 1. I've also had problems setting the "mark"
On 3/7/07, Peter Baxendale <[EMAIL PROTECTED]> wrote:
On Tue, 2007-03-06 at 22:02 -0800, Dave N6NZ wrote:
> What is the easiest way to create "thermal vias"? Not a via with a
> thermal relief -- I can do that :) .. but a via with no thermal relief
> punched into polygons on both sides of the boa
I use a number of parts with backside thermal pads. Draw the rectangle as
you describe to comfortably surround the vias. Then with the mouse over the
rectangle hit 's'. This will flood the thermal reliefs on the vias. If you
want to ever de-solder the part from the back, make sure the pad on t
On 1/18/07, Kai-Martin Knaak <[EMAIL PROTECTED]> wrote:
On Thu, 18 Jan 2007 10:15:35 -0800, joeft wrote:
>>One end stays where it was and the other moves with the via - the
>>definition of rubber banding. Still, it's not what the user wants. This
>>is already an open bug on the SF tracker.
>>
>>
On 11/28/06, John Griessen <[EMAIL PROTECTED]> wrote:
No matter what package your lesstif or motif is in, it may be affected by
changes in Xwindows from xfree86 to xorg. Problem may be where programs expect
libraries to be... See below and adapt it to your case with Suse.
>> I have seen this a
On 11/28/06, John Griessen <[EMAIL PROTECTED]> wrote:
no link or use of the /usr/include/X11/SM dir by the latest packages for
lesstif and xorg - may be a bug... or a style change.
John G
debian package libsm6
contains files:
==
/usr/X11R6/lib/libSM.so.6.0
/usr/X11R
Ales,I didn't make a copy of the system-gschemrc file, but a previous installation did - and this was indeed the cause (good call!). This of course leads to the obvious question: How do I customize settings for the gschemrc file? If duplicating (some of) the initialization from system-gschemrc b
Across the top of my gschem main window I see two sets of labels for the pull-down menus:File Edit . Options Help File Edit .. Options HelpOnly the right hand set is sctive. The left hand set just brings up a little box which brings up a tiny X window when I click it.
Running on SuSe 9
Werner, Dan, ..Seems like the original issue I asked about got lost in this thread...What I see is that the problem with the grid not being drawn is repeatable. Any clue as to where this might be happening?
Werner asked if this should be submitted as a bug so it can be tracked. Should it?Thanks,J
: Gdk-CRITICAL **: gdk_draw_points: assertion `(points != NULL) && (npoints > 0)' failedin the window where I invoked PCB.Joe
On 9/26/06, Werner Hoch <[EMAIL PROTECTED]> wrote:
Hi Joe, DJ, Dan and all,On Monday 25 September 2006 20:35, joe tarantino wrote:> I don'
31d000)...(among other things)So is the missing grid related to what exporters are config'd? The problem is not printing - it's on-screen.
JoeOn 9/25/06, Werner Hoch <[EMAIL PROTECTED]> wrote:
Hi Joe and all,On Monday 25 September 2006 21:27, joe tarantino wrote:> I picked u
DJ,I picked up the rpm that Werner put together a few weeks ago. I presume that it is the gtk hid based on where it came from and it's similarity to what I was running (which was gtk). Any hints for a non-developer such as myself how to tell for sure?
Thanks,JoeOn 9/25/06, DJ Delorie <[EMAIL PROT
I don't recall seeing anyone mention this...The grid disappears when I view the back side of the board. Changing the grid size, color, or toggling it on and off don't seem to help.I'm using the 20060822 snapshot under SuSe
9.3Thanks,Joe
___
geda-user
Check your setting for the "Enable rubber band mode" under the settings menu.JoeOn 9/13/06, Harry Eaton <
[EMAIL PROTECTED]> wrote:Vaughn Treude wrote:>Hello all,>I'm new to gEDA; I've been playing with it for a few weeks now, mostly
>gschem and pcb. Whereas the gschem interface seems reasonably s
Another version you might try - uses the newer pcb file format:--Element["" "Fiducial mark, no drill, .050 diameter pad" "" "FID" 116000 354000 2000 2000 0 80 ""]
( Pad[-1 0 1 0 5000 5000 1 "" "1" ""] ElementArc [0 0 7500 7500 0 360 1000] )-- This one has a silkscreen circl
We've just completed a board which had us scratching our heads when we
ran the DRC. We also found problems in the gerber output.
I trimmed the file down to a very simple example (1 part, 1 via, 1
trace, 1 rectangle). The culprit is the rectangle. If you
place a rectangle under a pad for example
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