[gem5-dev] Keep a MemObject from Being Serialized?

Hey guys, This is more of a nice-to-have than a need-to-have: Is there a way to keep a MemObject (or any SimObject for that matter) from serializing to the checkpoint file when checkpointing? I've got an object that I'm changing either the quantity or type of when restoring from a checkpoint, an

[gem5-dev] changeset in gem5: se.py Ruby: Connect TLB walker ports

changeset dfc6a4ba338c in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=dfc6a4ba338c description: se.py Ruby: Connect TLB walker ports In order to ensure correct functionality of switch CPUs, the TLB walker ports must be connected to the Ruby system in

[gem5-dev] changeset in gem5: Standard Switch: Drain the system before swit...

changeset 4f54b0f229b5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=4f54b0f229b5 description: Standard Switch: Drain the system before switching CPUs When switching from an atomic CPU to any of the timing CPUs, a drain is unnecessary since no events

[gem5-dev] changeset in gem5: Base CPU: Initialize profileEvent to NULL

changeset 37e6eb40cf91 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=37e6eb40cf91 description: Base CPU: Initialize profileEvent to NULL The profileEvent pointer is tested against NULL in various places, but it is not initialized unless running in ful

[gem5-dev] changeset in gem5: Ruby: Modify Scons so that we can put .sm fil...

changeset 258753d3bc47 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=258753d3bc47 description: Ruby: Modify Scons so that we can put .sm files in extras Also allows for header files which are required in slicc generated code to be in a directory other

Re: [gem5-dev] Review Request: Ruby: Modify Scons so that we can put .sm files in extras

It's ready to go. I don't have commit access, so you or Nilay can push it when you get the chance. Jason On Wed, Sep 12, 2012 at 10:59 AM, Brad Beckmann wrote: >This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1306/ > > Ship it! > > What is the status

Re: [gem5-dev] Review Request: Ruby: Fix hard-coded block size assumption for multiple directories

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1366/ --- (Updated Sept. 12, 2012, 12:16 p.m.) Review request for Default. Description

Re: [gem5-dev] Review Request: Ruby: Fix hard-coded block size assumption for multiple directories

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1366/ --- (Updated Sept. 12, 2012, 12:15 p.m.) Review request for Default. Description

Re: [gem5-dev] Review Request: Ruby: Fix hard-coded block size assumption for multiple directories

> On Sept. 10, 2012, 7:58 p.m., Joel Hestness wrote: > > configs/ruby/Ruby.py, line 182 > > > > > > Is this distinction necessary? When the number of directory bits is 0, > > the DirectoryMemory doesn't use the numa_high_bi

Re: [gem5-dev] Review Request: AddrRange: Simplify AddrRange params Python hierarchy

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1377/#review3455 --- Ship it! It seems like you are maintaining the same basic functionality,

Re: [gem5-dev] Review Request: Mem: Add a maximum bandwidth to SimpleMemory

> On Sept. 12, 2012, 9:44 a.m., Ali Saidi wrote: > > src/mem/SimpleMemory.py, line 50 > > > > > > do we at least want to put this in the land of reasonable? 16GB/s? > > I merely kept it at this value to not affect any regres

Re: [gem5-dev] Review Request: Mem: Add a maximum bandwidth to SimpleMemory

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1416/ --- (Updated Sept. 12, 2012, 9:48 a.m.) Review request for Default. Description (upda

Re: [gem5-dev] Review Request: Mem: Add a maximum bandwidth to SimpleMemory

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1416/#review3453 --- src/mem/SimpleMemory.py

[gem5-dev] Review Request: Mem: Add a maximum bandwidth to SimpleMemory

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1416/ --- Review request for Default. Description --- Changeset 9220:1e6e9d3b75c2 --

Re: [gem5-dev] Review Request: AddrRange: Simplify AddrRange params Python hierarchy

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1377/#review3452 --- Any comments/feedback? - Andreas Hansson On Sept. 3, 2012, 9:13 p.m.,

Re: [gem5-dev] Review Request: Ruby: Modify Scons so that we can put .sm files in extras

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1306/#review3451 --- Ship it! What is the status of this patch? Can you check it in soon? -

Re: [gem5-dev] Review Request: Ruby: Fix hard-coded block size assumption for multiple directories

> On Sept. 10, 2012, 7:58 p.m., Joel Hestness wrote: > > configs/ruby/MOESI_hammer.py, line 152 > > > > > > All of this probe filter setup should be predicated on whether the > > probe filter is actually enabled (options.pf

Re: [gem5-dev] Review Request: Ruby: Fix hard-coded block size assumption for multiple directories

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1366/#review3450 --- Ship it! - Brad Beckmann On Aug. 22, 2012, 12:15 p.m., Jason Power wro

[gem5-dev] changeset in gem5: stats: remove duplicate instruction stats fro...

changeset 7e9e34d4203b in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=7e9e34d4203b description: stats: remove duplicate instruction stats from the commit stage these stats are duplicates of insts/opsCommitted, cause confusion, and are poorly named. d

Re: [gem5-dev] Review Request: AddrRange: Simplify Range by removing stream input/output

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1389/#review3448 --- Ship it! Ship It! - Ali Saidi On Sept. 3, 2012, 9:23 p.m., Andreas Ha

Re: [gem5-dev] Review Request: AddrRange: Simplify Range by removing stream input/output

> On Sept. 11, 2012, 9:39 a.m., Ali Saidi wrote: > > src/unittest/rangetest.cc, line 42 > > > > > > maybe keep the test and just don't use the parsing? > > > > Andreas Hansson wrote: > Will do > > Andreas Hansson wrote:

[gem5-dev] Deferred Python parameter resolution for CPU clock

Hi all, Following the introduction of Cycles as a parameter type, it would be good to get the cache latencies expressed in Cycles rather than absolute time (Ticks). To get there, a first step is to ensure that the caches have an appropriate clock period. My first stab at this was to change Bas

Re: [gem5-dev] Review Request: AddrRange: Simplify Range by removing stream input/output

> On Sept. 11, 2012, 9:39 a.m., Ali Saidi wrote: > > src/unittest/rangetest.cc, line 42 > > > > > > maybe keep the test and just don't use the parsing? > > > > Andreas Hansson wrote: > Will do After quite some time spen