[m5-dev] Loading/storing oddly sized memory blobs from instructions

2010-07-11 Thread Gabe Black
In ARM's SIMD instruction set extension Neon, there are some instructions which can load or store 3 of something, and that something can be 1, 2, 4, or 8 bytes. To implement this properly, I'm planning to add readBytes and writeBytes functions to the various ExecContexts which would load/store

Re: [m5-dev] Review Request: Stats: Allow backing up and restoring of stats which is needed for SMARTS

2010-07-11 Thread Nathan Binkert
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/56/#review70 --- Can you describe exactly how this is used? I'm assuming that when you're

Re: [m5-dev] Review Request: Sim: When one CPU is taking over from another, the new CPU's memory is only

2010-07-11 Thread Timothy Jones
On 2010-07-10 08:43:33, Steve Reinhardt wrote: Is the root problem here that when I have an A-B port connection, then I connect A to C, B still thinks it's connected to A even though it's not? (Where in this specific example, A is the cache, and B and C are different CPUs.) If so,

Re: [m5-dev] Review Request: CPU: Add functions to get the number of executed instructions and set the

2010-07-11 Thread Timothy Jones
On 2010-07-10 08:52:15, Steve Reinhardt wrote: src/cpu/base.cc, line 463 http://reviews.m5sim.org/r/51/diff/1/?file=751#file751line463 Is there a reason to allocate this dynamically instead of having a single static counter per CPU object? No, not at all. I'm not sure why I did

Re: [m5-dev] Review Request: CPU: Add functions to get the number of executed instructions and set the

2010-07-11 Thread Timothy Jones
On 2010-07-10 08:52:15, Steve Reinhardt wrote: src/sim/eventq.hh, line 489 http://reviews.m5sim.org/r/51/diff/1/?file=755#file755line489 I don't like getting rid of this assertion... it's actually pretty useful in knowing when something's not right. You should add some code

Re: [m5-dev] Review Request: BranchPred: Take the branch predictor out of O3CPU and make it a stand-alone

2010-07-11 Thread Timothy Jones
On 2010-07-10 09:59:37, Steve Reinhardt wrote: OK, looking a little closer I see that Impl is also used to get the DynInst type... but many of the methods called on DynInst (isUncondControl(), isCall(), isReturn()) are also StaticInst methods, and some of the others (like readPC())

Re: [m5-dev] Review Request: BranchPred: Take the branch predictor out of O3CPU and make it a stand-alone

2010-07-11 Thread Timothy Jones
On 2010-07-10 14:50:15, Korey Sewell wrote: src/cpu/pred/bpred_unit_impl.hh, line 191 http://reviews.m5sim.org/r/47/diff/1/?file=725#file725line191 Shouldnt this *not* be hardcoded to 16, but instead the true RAS size? Seems reasonable to me, I'll fix this. On

Re: [m5-dev] Review Request: Stats: Allow backing up and restoring of stats which is needed for SMARTS

2010-07-11 Thread Timothy Jones
On 2010-07-11 06:47:22, Nathan Binkert wrote: Can you describe exactly how this is used? I'm assuming that when you're in a sampling period, that you take stats normally, then before you fast forward, you save to backup(), you then continue to take stats in the primary and when

Re: [m5-dev] Review Request: BranchPred: Take the branch predictor out of O3CPU and make it a stand-alone

2010-07-11 Thread Korey Sewell
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/47/#review78 --- src/cpu/pred/bpred_unit_impl.hh http://reviews.m5sim.org/r/47/#comment222

Re: [m5-dev] Loading/storing oddly sized memory blobs from instructions

2010-07-11 Thread Steve Reinhardt
On Sat, Jul 10, 2010 at 11:37 PM, Gabe Black gbl...@eecs.umich.edu wrote: In ARM's SIMD instruction set extension Neon, there are some instructions which can load or store 3 of something, and that something can be 1, 2, 4, or 8 bytes. To implement this properly, I'm planning to add readBytes

Re: [m5-dev] Review Request: CPU: Add functions to get the number of executed instructions and set the

2010-07-11 Thread Steve Reinhardt
On 2010-07-10 08:52:15, Steve Reinhardt wrote: src/sim/sim_object.cc, line 275 http://reviews.m5sim.org/r/51/diff/1/?file=757#file757line275 I'd prefer a more informative message like Error: setMaxInsts called on non-CPU (and same with the following function).

Re: [m5-dev] Review Request: SimpleCPU: Allow Simple CPUs to warm a branch predictor by creating a pointer

2010-07-11 Thread Steve Reinhardt
I think it's fine like it is. Gabe is rightly concerned that some parts of SimpleCPU are not so simple anymore, particularly timing.cc, but your change doesn't impact those parts so I don't see a problem with it. Steve On Sun, Jul 11, 2010 at 11:01 AM, Timothy M Jones tjon...@inf.ed.ac.uk

Re: [m5-dev] Review Request: CPU: Add functions to get the number of executed instructions and set the

2010-07-11 Thread Ali Saidi
On 2010-07-10 08:52:15, Steve Reinhardt wrote: src/sim/eventq.hh, line 489 http://reviews.m5sim.org/r/51/diff/1/?file=755#file755line489 I don't like getting rid of this assertion... it's actually pretty useful in knowing when something's not right. You should add some code

Re: [m5-dev] Review Request: CPU: Add functions to get the number of executed instructions and set the

2010-07-11 Thread Steve Reinhardt
On 2010-07-10 08:52:15, Steve Reinhardt wrote: src/sim/eventq.hh, line 489 http://reviews.m5sim.org/r/51/diff/1/?file=755#file755line489 I don't like getting rid of this assertion... it's actually pretty useful in knowing when something's not right. You should add some code

Re: [m5-dev] Review Request: O3CPU: O3's tick event gets squashed when it is switched out. When repeatedly

2010-07-11 Thread Nathan Binkert
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/50/#review84 --- src/cpu/o3/cpu.cc http://reviews.m5sim.org/r/50/#comment230 As an

Re: [m5-dev] Review Request: Syscall: Don't close the simulator's standard file descriptors.

2010-07-11 Thread Nathan Binkert
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/52/#review85 --- src/sim/syscall_emul.cc http://reviews.m5sim.org/r/52/#comment231 I

Re: [m5-dev] Review Request: Sim: Add functionality to the simulation scripts to allow running with

2010-07-11 Thread Nathan Binkert
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/57/#review86 --- configs/common/Options.py http://reviews.m5sim.org/r/57/#comment232

[m5-dev] sparc64-linux writev syscall patch / unhandled trap

2010-07-11 Thread Ioannis Ilkos
Hello, I have been using the m5-stable from the repository the last few days. In order to compile sparc64-linux binaries for SE mode I built a cross compiler toolchain which linked against newer glibc versions. It turned out the newer glibc (my test programs were linked with glibc-2.8 with

Re: [m5-dev] Review Request: Cache: Provide a function to mark caches as ready from python.

2010-07-11 Thread Steve Reinhardt
On 2010-07-10 08:57:34, Steve Reinhardt wrote: I'm curious about the overall need for this... is there really a situation where it matters? If there's some path that's not appropriately setting/checking/ignoring the whenReady field I'd rather fix that than add this feature.

Re: [m5-dev] Review Request: CPU: Add functions to get the number of executed instructions and set the

2010-07-11 Thread Steve Reinhardt
On 2010-07-10 08:52:15, Steve Reinhardt wrote: src/sim/eventq.hh, line 489 http://reviews.m5sim.org/r/51/diff/1/?file=755#file755line489 I don't like getting rid of this assertion... it's actually pretty useful in knowing when something's not right. You should add some code