In ARM's SIMD instruction set extension Neon, there are some
instructions which can load or store 3 of something, and that something
can be 1, 2, 4, or 8 bytes. To implement this properly, I'm planning to
add readBytes and writeBytes functions to the various ExecContexts which
would load/store
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Can you describe exactly how this is used? I'm assuming that when you're
On 2010-07-10 08:43:33, Steve Reinhardt wrote:
Is the root problem here that when I have an A-B port connection, then I
connect A to C, B still thinks it's connected to A even though it's not?
(Where in this specific example, A is the cache, and B and C are different
CPUs.) If so,
On 2010-07-10 08:52:15, Steve Reinhardt wrote:
src/cpu/base.cc, line 463
http://reviews.m5sim.org/r/51/diff/1/?file=751#file751line463
Is there a reason to allocate this dynamically instead of having a
single static counter per CPU object?
No, not at all. I'm not sure why I did
On 2010-07-10 08:52:15, Steve Reinhardt wrote:
src/sim/eventq.hh, line 489
http://reviews.m5sim.org/r/51/diff/1/?file=755#file755line489
I don't like getting rid of this assertion... it's actually pretty
useful in knowing when something's not right. You should add some code
On 2010-07-10 09:59:37, Steve Reinhardt wrote:
OK, looking a little closer I see that Impl is also used to get the DynInst
type... but many of the methods called on DynInst (isUncondControl(),
isCall(), isReturn()) are also StaticInst methods, and some of the others
(like readPC())
On 2010-07-10 14:50:15, Korey Sewell wrote:
src/cpu/pred/bpred_unit_impl.hh, line 191
http://reviews.m5sim.org/r/47/diff/1/?file=725#file725line191
Shouldnt this *not* be hardcoded to 16, but instead the true RAS size?
Seems reasonable to me, I'll fix this.
On
On 2010-07-11 06:47:22, Nathan Binkert wrote:
Can you describe exactly how this is used? I'm assuming that when you're
in a sampling period, that you take stats normally, then before you fast
forward, you save to backup(), you then continue to take stats in the
primary and when
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src/cpu/pred/bpred_unit_impl.hh
http://reviews.m5sim.org/r/47/#comment222
On Sat, Jul 10, 2010 at 11:37 PM, Gabe Black gbl...@eecs.umich.edu wrote:
In ARM's SIMD instruction set extension Neon, there are some
instructions which can load or store 3 of something, and that something
can be 1, 2, 4, or 8 bytes. To implement this properly, I'm planning to
add readBytes
On 2010-07-10 08:52:15, Steve Reinhardt wrote:
src/sim/sim_object.cc, line 275
http://reviews.m5sim.org/r/51/diff/1/?file=757#file757line275
I'd prefer a more informative message like Error: setMaxInsts called
on non-CPU (and same with the following function).
I think it's fine like it is. Gabe is rightly concerned that some
parts of SimpleCPU are not so simple anymore, particularly timing.cc,
but your change doesn't impact those parts so I don't see a problem
with it.
Steve
On Sun, Jul 11, 2010 at 11:01 AM, Timothy M Jones tjon...@inf.ed.ac.uk
On 2010-07-10 08:52:15, Steve Reinhardt wrote:
src/sim/eventq.hh, line 489
http://reviews.m5sim.org/r/51/diff/1/?file=755#file755line489
I don't like getting rid of this assertion... it's actually pretty
useful in knowing when something's not right. You should add some code
On 2010-07-10 08:52:15, Steve Reinhardt wrote:
src/sim/eventq.hh, line 489
http://reviews.m5sim.org/r/51/diff/1/?file=755#file755line489
I don't like getting rid of this assertion... it's actually pretty
useful in knowing when something's not right. You should add some code
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src/cpu/o3/cpu.cc
http://reviews.m5sim.org/r/50/#comment230
As an
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src/sim/syscall_emul.cc
http://reviews.m5sim.org/r/52/#comment231
I
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configs/common/Options.py
http://reviews.m5sim.org/r/57/#comment232
Hello,
I have been using the m5-stable from the repository the last few days. In order
to compile sparc64-linux binaries for SE mode I built a cross compiler
toolchain which linked against newer glibc versions. It turned out the newer
glibc (my test programs were linked with glibc-2.8 with
On 2010-07-10 08:57:34, Steve Reinhardt wrote:
I'm curious about the overall need for this... is there really a situation
where it matters? If there's some path that's not appropriately
setting/checking/ignoring the whenReady field I'd rather fix that than add
this feature.
On 2010-07-10 08:52:15, Steve Reinhardt wrote:
src/sim/eventq.hh, line 489
http://reviews.m5sim.org/r/51/diff/1/?file=755#file755line489
I don't like getting rid of this assertion... it's actually pretty
useful in knowing when something's not right. You should add some code
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