Re: [m5-dev] possible contributions to M5

On Mon, Jul 12, 2010 at 8:20 AM, Jiayuan Meng wrote: > Dear M5 Team, > I'll soon start to work on integrating our M5-based simulator, MV5, into > M5. I've read some documentation on the current status of M5, and I'd like > to share my plan/ideas with you and hear your suggestions. > Since M5 will

[m5-dev] Different cache line sizes in different cache levels and L1s

Hi m5-dev list, My understanding of the cache subsystem in M5 is that all caches (L1s in all cores and L2 in a CMP system) must have the same line size. I understand that it is more efficient, especially for the coherence protocol. However, I think it is reasonable for different caches to have

Re: [m5-dev] possible contributions to M5

> Is this inorder model detailed (in terms of pipeline stages, branch > prediciton, Functional Units, etc.)? > > Is it functional within Full system mode? > > I'm guessing that this would be a good contribution but I'm wondering if > this would somewhat antiquate the actual inorderCPU model that is

Re: [m5-dev] possible contributions to M5

> > 1. An in-order CPU module with multi-threading (switching threads upon > cache > > accesses) based on TimingSimpleCPU > This is probably #1 on the priority list > Is this inorder model detailed (in terms of pipeline stages, branch prediciton, Functional Units, etc.)? Is it functional within Fu

Re: [m5-dev] possible contributions to M5

> I'll soon start to work on integrating our M5-based simulator, MV5, into > M5. I've read some documentation on the current status of M5, and I'd like > to share my plan/ideas with you and hear your suggestions. > Since M5 will soon replace its entire memory system modeling with Ruby&Gems, > it se

Re: [m5-dev] a question on CPU assertions

I will try it tomorrow and let you know. On Mon, Jul 12, 2010 at 6:51 PM, Gabriel Michael Black < gbl...@eecs.umich.edu> wrote: > Did that patch fix it? > > Gabe > > > Quoting Gabe Black : > > Here's more or less what's going on as far as the register index. The >> load microop needs to store i

Re: [m5-dev] a question on CPU assertions

Did that patch fix it? Gabe Quoting Gabe Black : Here's more or less what's going on as far as the register index. The load microop needs to store into register 1, and it needs to be sure it stores into the version visible from the "user" mode. It does that by applying the intRegInMode functio

Re: [m5-dev] Review Request: Syscall: Don't close the simulator's standard file descriptors.

> On 2010-07-11 15:25:09, Nathan Binkert wrote: > > src/sim/syscall_emul.cc, line 190 > > > > > > I personally feel that the use of ?: here isn't warranted. It hides > > what this line of code is actually doing. Much better IM

Re: [m5-dev] Review Request: Sim: Add functionality to the simulation scripts to allow running with

> On 2010-07-11 16:04:10, Nathan Binkert wrote: > > configs/common/Options.py, line 106 > > > > > > Why exactly do these parameter names have a colon in them? Is there a > > particular reason that --smarts-k doesn't work? Also

Re: [m5-dev] O3CPU + translateTiming

Hi Min, The way that the TLB deals with a timing translation is specific to each ISA. I don't have much experience with anything other than Power but for that ISA, yes, you're correct. The timing translation is just a wrapper around the atomic translation. It seems from a quick check that

[m5-dev] O3CPU + translateTiming

Hi, This question is regarding the changeset ( http://repo.m5sim.org/m5?cmd=changeset;node=a123bd350935). This initiates a timing translation and passes the read or write on to the processor before waiting for it to finish It looks like even in the event of TLB miss, TLB-walk does not delay th

Re: [m5-dev] sparc64-linux writev syscall patch / unhandled trap

getcontext() and setcontext() seem far more evil than updating a simple TLS register. getcontext() seems to copy all of the processor/process state into a struct and return that to the user. setcontext() takes something from getcontext() and restores it (including things like the PC). http://www.

Re: [m5-dev] how to use m5threads?

Hi Eberle, The Makefile builds TWO sets of binaries… one called test_XXX_p using the pthreads library, and one called test_XXX using the m5threads library (i.e. pthreads.o), so that seems to be ok… Was the same target name specified for both before? Hmm, is the command I use to run the binary ok

Re: [m5-dev] MESI_CMP directory protocol with more than 2 processors

Hi Brad, I tried to run a parsec benchmark in the way you suggested, using checkpoint. I created the checkpoint using non ruby ALPHA, and while using the same again to run the checkpoint, the execution completed successfully in a relatively short amount of time. But when I tried to run the checkpo

Re: [m5-dev] sparc64-linux writev syscall patch / unhandled trap

Thanks a lot for the information, the +0x100 part on the trap table is what had me confused. Turns out that the glibc implementation of sigsetjmp / siglongjmp is based on the get_context / set_context traps respectively (see /sysdeps/unix/sysv/linux/sparc/sparc64/setjmp.S for example). I believ

Re: [m5-dev] possible contributions to M5

Hi, Jiayuan, Your list of contributions looks awesome!!! I would prefer the order of 3, 4, 1, 2. Leonard On Mon, Jul 12, 2010 at 10:20 AM, Jiayuan Meng wrote: > Dear M5 Team, > > I'll soon start to work on integrating our M5-based simulator, MV5, into > M5. I've read some documentation on t

[m5-dev] possible contributions to M5

Dear M5 Team, I'll soon start to work on integrating our M5-based simulator, MV5, into M5. I've read some documentation on the current status of M5, and I'd like to share my plan/ideas with you and hear your suggestions. Since M5 will soon replace its entire memory system modeling with Ruby&Gems,

Re: [m5-dev] Loading/storing oddly sized memory blobs from instructions

On Mon, Jul 12, 2010 at 2:25 AM, Gabe Black wrote: > Steve Reinhardt wrote: > > On Sat, Jul 10, 2010 at 11:37 PM, Gabe Black > wrote: > > > >> In ARM's SIMD instruction set extension Neon, there are some > >> instructions which can load or store 3 of something, and that something > >> can be 1,

Re: [m5-dev] a question on CPU assertions

Here's more or less what's going on as far as the register index. The load microop needs to store into register 1, and it needs to be sure it stores into the version visible from the "user" mode. It does that by applying the intRegInMode function which shifts the register index 1 by MODE_USER * the

Re: [m5-dev] sparc64-linux writev syscall patch / unhandled trap

Your patch looks reasonable. You likely already did this, but since you're working with m5-stable which is fairly old, please be sure to check the development repository just in case your problem was already fixed. I just checked and this isn't there either, but that's one of the hazards of using m