s working fine for 1 loads with 4 processors. Since your
testing with ruby random tester, would the processor architecture even
come in to play?
--
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
commit a patch to eliminate the Sequencer related warnings.
--
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
.cc: In member function 'void
Sequencer::issueRequest(const RubyRequest&)':
build/ARM_FS/mem/ruby/system/Sequencer.cc:616: warning: 'ctype' may be used
uninitialized in this function
build/ARM_FS/mem/ruby/system/Sequencer.cc:653: warning: 'amtype' may be used
uninit
changeset e21f6e70169e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e21f6e70169e
description:
Ruby: Remove CacheMsg class from SLICC
The goal of the patch is to do away with the CacheMsg class currently
in use
in coherence protocols. In place of CacheM
On Sat, 19 Mar 2011, Nilay Vaish wrote:
On Fri, 18 Mar 2011, Lisa Hsu wrote:
What's going on with this patch? I don't believe it's been committed but
it
seems like it should. I've also got some patches waiting behind this
because they used to touch CacheMsg and I don&
/DMASequencer.cc c1c6f36e118e
src/mem/ruby/system/RubyPort.cc c1c6f36e118e
src/mem/ruby/system/Sequencer.cc c1c6f36e118e
Diff: http://reviews.m5sim.org/r/327/diff
Testing
---
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http
I had committed an error in one of the my recent patches. I have committed
a patch that should fix this error.
--
Nilay
On Sun, 20 Mar 2011, Cron Daemon wrote:
See /z/m5/regression/regress-2011-03-20-03:00:01 for details.
___
m5-dev mailing list
changeset c1c6f36e118e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c1c6f36e118e
description:
SLICC: Remove WakeUp* import calls from ast/__init__.py
I had recently committed a patch that removed the WakeUp*.py files from
the
slicc/ast directory. I had
changeset 5955406f7ed0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5955406f7ed0
description:
Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent c
changeset b043c0efa024 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b043c0efa024
description:
Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code us
/zizzer/encumbered RUBY=True -j 7 -Q' 'quick'
--
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
On Fri, 18 Mar 2011, Lisa Hsu wrote:
What's going on with this patch? I don't believe it's been committed but it
seems like it should. I've also got some patches waiting behind this
because they used to touch CacheMsg and I don't want to mess Nilay up, so
I've be
9a6a02a235f1
Diff: http://reviews.m5sim.org/r/602/diff
Testing
---
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
/CacheMemory.cc 9a6a02a235f1
src/mem/ruby/system/Sequencer.hh 9a6a02a235f1
src/mem/ruby/system/Sequencer.cc 9a6a02a235f1
Diff: http://reviews.m5sim.org/r/601/diff
Testing
---
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org
changeset 9a6a02a235f1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9a6a02a235f1
description:
SLICC: Remove external_type for structures
In SLICC, in order to define a type a data type for which it should not
generate any code, the keyword external_type
changeset 099771c7725d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=099771c7725d
description:
SLICC: Remove the keyword wake_up_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_dependents was introduced. This patch rem
changeset f3d1493787d4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f3d1493787d4
description:
SLICC: Remove the keyword wake_up_all_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_all_dependents was introduced. This p
On Sat, 12 Mar 2011, Steve Reinhardt wrote:
On Sat, Mar 12, 2011 at 1:34 PM, Nilay Vaish wrote:
On Fri, 11 Mar 2011, Steve Reinhardt wrote:
Thanks for the explanation... I was expecting to see a loop on
L1DcacheMemory like before and I missed the one on system.ruby.network.
In the short
---
Both MOESI CMP token and Hammer have been compiled and tested with random
tester.
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
been compiled and tested with random tester.
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
under system and rest of Ruby components under RubySystem, we
are creating two paths in the graph that are running parallel to each
other, even though we have dependence between them. I would rather have a
tree / directed acyclic structure.
Thanks
On Thu, 10 Mar 2011, Nilay Vaish wrote:
Creating root params
Creating root
Getting root
Done creating root
Creating system params
Getting system.physmem
Creating system
Getting system
Done creating system
Creating system.physmem params
Creating system.physmem
Getting system.physmem
add pointers for RubyPort objects to RubySystem.
These would be used to inform RubyPort objects about the RubySystem to
which they belong. Through RubySystem, a RubyPort would be able to access
the cache memories and thus perform functional accesses.
Thanks
Nilay
Nate, Gabe,
Thanks, I am able to make use of VectorParam.
Nilay
On Thu, 10 Mar 2011, Gabe Black wrote:
Here's one:
http://repo.m5sim.org/m5/file/77aa0f94e7f2/src/cpu/BaseCPU.py#l91
Gabe
On 03/10/11 16:40, nathan binkert wrote:
I'm traveling so I don't have Access to code
Can you point out an example of vector parameter? That should serve my
purpose.
Thanks
Nilay
On Thu, 10 Mar 2011, nathan binkert wrote:
As I understand, we use Python objects to initialize C++ objects. Is it
possible to pass a pointer to an array (dynamic sized) from Python to C++?
What do
As I understand, we use Python objects to initialize C++ objects. Is it
possible to pass a pointer to an array (dynamic sized) from Python to C++?
Thanks
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
I made some changes to MESI_CMP_directory.py and those changes are
reflected in the output. The l1 and l2 controllers are now being attached
to ruby instead of system.
Nilay
On Thu, 10 Mar 2011, Nilay Vaish wrote:
I had originally put a print statement in getCCObject(), so using the word
ing system.ruby params
Getting system.ruby.network
Getting system.ruby.network.topology
Getting system.ruby.network.topology.ext_links0
Getting system.ruby.l1_cntrl0
Getting system.ruby.l1_cntrl0.L1DcacheMemory
Getting system.ruby
Getting system.ruby.network
--
Nilay
On Thu, 10 Mar 2011, Steve Reinhardt wrote:
Steve, here is the output after putting in the print statements.
Creating root params
Creating root
Done creating root
Creating system params
Creating system
Done creating system
Creating system.l1_cntrl0 params
Nilay
On Wed, 9 Mar 2011, Steve Reinhardt wrote:
It seems odd that it
.L1DcacheMemory
This is the output I obtained from SimObject.py, clearly there is a cycle.
Should not the cache controllers be part of ruby, instead of being part of
system? Once they become part of ruby, it should be possible to traverse
the controller array and figure out all the caches.
Nilay
On Wed, 9
What exactly happens on the function call Param.RubySystem(Parent.any,
"Ruby System") ?
Nilay
On Wed, 9 Mar 2011, Steve Reinhardt wrote:
Does the RubySystem object have a pointer to a RubyCache object?
You could also go into the python code and add some print statements to get
a
IIRC, I was expecting some response from Ali as to why M5_DUMMY_RETURN
should or should not work. I did not poke in any further. To me it is a
compiler bug that we have to work with. I think return panic(""); works
with both 4.2 and 4.4 series, but we probably do not want that.
--
Nil
soc = Param.Int("");
replacement_policy = Param.String("PSEUDO_LRU", "");
start_index_bit = Param.Int(6, "index start, default 6 for 64-byte
line");
--
Nilay
On Tue, March 8, 2011 6:35 pm, Steve Reinhardt wrote:
> It probably means that two objects have pointe
Somayeh, there is an update option available in postreview. I think it is
-u . You can use that to post update already created
review requests.
--
Nilay
On Wed, 9 Mar 2011, Somayeh Sardashti wrote:
---
This is an automatically
When does the following error occurs? Is it that an object is being
accessed while it is being created?
File
"/afs/cs.wisc.edu/u/n/i/nilay/private/Architecture/GEM5/m5/src/python/m5/SimObject.py",
line 834, in getCCObject
raise RuntimeError, "%s: Cycle found in configur
ther it is
possible to add those controllers to the sequencer from within those
python files. But it seems that it is not required at all.
Thanks
Nilay
On Mon, 7 Mar 2011, Steve Reinhardt wrote:
Right now it may only be documented in the ASPLOS tutorial slides.
Basically you don't generally
no particular reason for that. Since Sequencer handles that timing
acesses, I thought that should be the file that would contain the code for
functional accesses. I am fine with functional access code going in to
RubyPort.
--
Nilay
On Mon, 7 Mar 2011, Beckmann, Brad wrote:
Hi Nilay,
Please
Suppose I add a data member to the Sequencer class. How can I access this
data member in configs/ruby/*.py? I am not able to figure out how the
Python classes are related to the C++ classes.
--
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http
in configs/ruby. And then RubyPort can pass on functional accesses to the
Sequencer, which will look up all the caches and take the correct action.
I think this can be made to work.
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org
src/mem/slicc/parser.py 159c07f22c8e
Diff: http://reviews.m5sim.org/r/534/diff
Testing
---
I have compiled all the protocols in debug mode. That should be enough.
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman
dress same as stalling on a cache block?
If it
is, then certainly I do not see the need for wakeUpAllDependents(), at least
not in
the MESI L1 cache controller. But in case the two are not same, then I think we
would
need to wake up all requests whenever there is a transition from a t
.
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
changeset 2e1ee8ec6266 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2e1ee8ec6266
description:
Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
At a couple of places in PerfectSwitch.cc and MessageBuffer.cc,
DPRINTF()
has not been provided with
---
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
How can I test whether or not functional accesses to the memory are
working correctly? Do we have some regression test for this?
Thanks
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
read.
Nilay
On Fri, 25 Feb 2011, Beckmann, Brad wrote:
Yes, that is correct. The RubyPort::M5Port::recvFunctional() function is where
we need to add the new support.
Brad
-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
On Behalf Of Nilay Vaish
Sent: F
I am talking about real silicon. Then, how does gdb makes changes to
values of variables?
Nilay
On Sat, 26 Feb 2011, Beckmann, Brad wrote:
Hi Nilay,
What exactly are you referring to as the "underlying processor"? Are you
referring to real silicon?
Actual hardware doesn
.
Nilay
On Fri, 25 Feb 2011, Beckmann, Brad wrote:
Yes, that is correct. The RubyPort::M5Port::recvFunctional() function is where
we need to add the new support.
Brad
-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
On Behalf Of Nilay Vaish
Sent
changeset 05a2f6ac1f8e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=05a2f6ac1f8e
description:
Ruby: Remove store buffer
This patch removes the store buffer from Ruby. It is not in use
currently.
Since libruby is being and store buffer makes calls to li
changeset 6782b51ae8a8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6782b51ae8a8
description:
Ruby: Remove libruby
This patch removes libruby_internal.hh, libruby.hh and libruby.cc. It
moves
the contents to libruby.hh to RubyRequest.hh and RubyRequest.
changeset 04078b1214dd in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=04078b1214dd
description:
Ruby: Make Address.hh independent of RubySystem
This patch changes Address.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All
changeset 722a0d28ee83 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=722a0d28ee83
description:
Ruby: Make DataBlock.hh independent of RubySystem
This patch changes DataBlock.hh so that it is not dependent on
RubySystem.
This dependence seems unecessary.
ad of the PhysicalMemory.
--
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
> On 2011-02-25 09:43:34, Nathan Binkert wrote:
> > It seems that this diff should just be folded into the remove libruby diff.
I will do that before committing these to repository.
- Nilay
---
This is an automatically generat
src/mem/ruby/common/DataBlock.hh 4a59661d3fd1
src/mem/ruby/common/DataBlock.cc 4a59661d3fd1
Diff: http://reviews.m5sim.org/r/503/diff
Testing
---
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5
UNKNOWN
src/mem/ruby/filters/NonCountingBloomFilter.cc UNKNOWN
Diff: http://reviews.m5sim.org/r/504/diff
Testing
---
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
/mem/ruby/common/DataBlock.hh 4a59661d3fd1
src/mem/ruby/common/DataBlock.cc 4a59661d3fd1
Diff: http://reviews.m5sim.org/r/503/diff
Testing
---
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
/stb_interface.hh 4a59661d3fd1
src/mem/ruby/storebuffer/stb_interface.cc 4a59661d3fd1
src/mem/ruby/storebuffer/storebuffer.hh 4a59661d3fd1
src/mem/ruby/storebuffer/storebuffer.cc 4a59661d3fd1
Diff: http://reviews.m5sim.org/r/507/diff
Testing
---
Thanks,
Nilay
4a59661d3fd1
src/mem/ruby/storebuffer/storebuffer.hh 4a59661d3fd1
src/mem/ruby/storebuffer/storebuffer.cc 4a59661d3fd1
src/mem/ruby/system/RubyPort.hh 4a59661d3fd1
src/mem/ruby/system/Sequencer.cc 4a59661d3fd1
Diff: http://reviews.m5sim.org/r/439/diff
Testing
---
Thanks,
Nilay
/TraceRecord.hh 4a59661d3fd1
src/mem/ruby/recorder/Tracer.hh 4a59661d3fd1
Diff: http://reviews.m5sim.org/r/506/diff
Testing
---
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
/NonCountingBloomFilter.cc UNKNOWN
Diff: http://reviews.m5sim.org/r/504/diff
Testing
---
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
4a59661d3fd1
src/mem/ruby/common/DataBlock.hh 4a59661d3fd1
src/mem/ruby/common/DataBlock.cc 4a59661d3fd1
Diff: http://reviews.m5sim.org/r/503/diff
Testing
---
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman
Can we impose restriction on the membership of the wiki? It seems that
bogus pages are being created. For example --
http://m5sim.org/wiki/index.php/User:MiriamGSpeights
--
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman
rees that it is not
required in its present form.
--
Nilay
Brad
From: Steve Reinhardt [mailto:ste...@gmail.com]
Sent: Thursday, February 24, 2011 11:20 AM
To: M5 Developer List
Cc: Beckmann, Brad
Subject: Re: [m5-dev] Store Buffer
On Thu, Feb 24, 2011 at 11:08 AM, Beckmann, Brad
ma
to bypass SLICC) .
Thanks
Arka
--
Nilay
On 02/23/2011 11:29 PM, Beckmann, Brad wrote:
Sorry, I should have been more clear. It fundamentally comes down to how
does the Ruby interface help support memory consistency, especially
considering more realistic buffering between the CPU and memor
Brad,
In case we remove libruby, what becomes of the store buffer? In fact, is
store buffer in use?
Thanks
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/493/#review885
---
Ship it!
- Nilay
On 2011-02-22 14:36:40, Brad Beckmann wrote
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/494/#review884
---
Ship it!
- Nilay
On 2011-02-22 14:36:31, Brad Beckmann wrote
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/495/#review883
---
Ship it!
- Nilay
On 2011-02-22 14:36:23, Brad Beckmann wrote
/StateDeclAST.py
<http://reviews.m5sim.org/r/496/#comment1249>
The copyright needs to be changed.
src/mem/slicc/ast/TypeFieldStateAST.py
<http://reviews.m5sim.org/r/496/#comment1250>
The copyright needs to be changed.
- Nilay
On 2011-02-22 14:36:11, Brad Be
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/492/#review877
---
Ship it!
- Nilay
On 2011-02-18 14:55:40, Korey Sewell wrote
changeset 44f1ac4f587f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=44f1ac4f587f
description:
Ruby: clean MOESI CMP directory protocol
The L1 cache controller file contains references to foo and goo queues,
which
are not in use at all. These have been
changeset 5e58eaf00b58 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5e58eaf00b58
description:
Ruby: Machine Type missing in MOESI CMP directory protocol
In certain actions of the L1 cache controller, while creating an
outgoing
message, the machine type
I am trying to push a couple of change sets, but I keep getting the
following response
remote: abort: No space left on device
abort: unexpected response: empty string
Can some one look into this?
--
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
> On 2011-02-18 08:10:43, Korey Sewell wrote:
> > Should the "remove of foo/goo queues" and the "adding of MachineType" be
> > separate (albeit small) patches?
I'll commit them as separate patches.
- Nilay
.
Thanks,
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
On Thu, 17 Feb 2011, Nilay Vaish wrote:
On Wed, 16 Feb 2011, Beckmann, Brad wrote:
Hi Nilay,
I'm not quite sure what you mean by "appended to while you drain", but I
think you are asking whether the input ports will receive messages that are
scheduled for the same cycle
On Wed, 16 Feb 2011, Beckmann, Brad wrote:
Hi Nilay,
I'm not quite sure what you mean by "appended to while you drain", but I
think you are asking whether the input ports will receive messages that
are scheduled for the same cycle as the current cycle. Is that right?
If s
ons command for compilation, that
would prevent html files from being generated.
--
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Sure!
On Wed, 16 Feb 2011, Gabriel Michael Black wrote:
Could you please use review board? I wouldn't know what I'm looking at, but
other people might want a chance to look it over.
Gabe
Quoting Nilay Vaish :
Can you email your patch, I'll take a look and commit the
Can you email your patch, I'll take a look and commit the changes to the
repository.
Thanks!
Nilay
On Wed, 16 Feb 2011, Joseph Pusdesris wrote:
Bump.
-Joseph
On Fri, Feb 11, 2011 at 3:28 PM, Joseph Pusdesris wrote:
I have noticed that many of the action definitions are mi
?
I know LD_PROFILE can be used for profiling shared objects, but I do not
have a C library compiled with profiling symbols included.
--
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
to confirm this.
--
Nilay
I thought of this a moment ago, so I have not confirmed this empirically.
The CacheController's wakeup function includes a while loop, in which all
the queues are checked. Consider the Hammer protocol's L1 Cache Controller.
It has four incoming queues - t
ighest (about 5%). For ruby
random tester profile, the wakeup function takes about 11% of the time.
--
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Hi Brad,
I have checked in the patch dealing with Perfect Switch. I am will clean
the patch that removes CacheMsg class soon. What to take up next? I am
kind of bored with this optimization stuff right now.
--
Nilay
___
m5-dev mailing list
m5-dev
changeset e5550966464a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e5550966464a
description:
Ruby: Improve Change PerfectSwitch's wakeup function
Currently the wakeup function for the PerfectSwitch contains three
loops -
loop on number of virtual net
before.
--
Nilay
On Mon, 14 Feb 2011, Nilay Vaish wrote:
Brad, this patch to affects the number of ticks required for performing a
particular number of loads. I don't expect such a thing to happen. Do you?
--
Nilay
On Wed, 9 Feb 2011, Brad Beckmann
Brad, this patch to affects the number of ticks required
for performing a particular number of loads. I don't expect such a thing
to happen. Do you?
--
Nilay
On Wed, 9 Feb 2011, Brad Beckmann wrote:
---
This is an automati
changeset e8f4bb35dca9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e8f4bb35dca9
description:
Ruby: Reorder Cache Lookup in Protocol Files
The patch changes the order in which L1 dcache and icache are looked up
when
a request comes in. Earlier, if a re
-n
4 -l 200
--
Nilay
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
On Wed, 9 Feb 2011, nathan binkert wrote:
One simple nitpick before you commit is to fix the commit message so you put
a proper summary line.
Nate
What would you like it to be?
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/list
> just the vnet id?
I would change that. It is a left over from the earlier approach that I
was thinking of taking, the one in which all messages were queued in the
Perfect Switch as well.
- Nilay
---
This is an automatically
Hi Brad, did you miss out on the '_' in _dma_devices?
--
Nilay
diff -r 6f5299ff8260 -r 00ad807ed2ca configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.pySun Feb 06 22:14:18 2011 -0800
+++ b/configs/example/ruby_fs.pySun Feb 06 22:14:18 2011 -0800
@@ -109,
changeset 9c245e375e05 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9c245e375e05
description:
MESI CMP: Unset TBE pointer in L2 cache controller
The TBE pointer in the MESI CMP implementation was not being set to NULL
when the TBE is deallocated. This r
I found the error in MESI CMP. In the L2 cache controller, when the TBE is
deallocated, the pointer was not being set to NULL.
--
Nilay
On Mon, 7 Feb 2011, Arkaprava Basu wrote:
Nilay,
If the same test completes with larger threshold then it certainly a
case of false positive and
changeset 68f37178b408 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=68f37178b408
description:
Orion: Replace printf() with fatal()
The code for Orion 2.0 makes use of printf() at several places where
there as
an error in configuration of the model. The
requests remain un-fulfilled because of later requests for the same
address.
--
Nilay
On Mon, 7 Feb 2011, Beckmann, Brad wrote:
Yep, if I increase the deadlock threshold to 5 million cycles, the
deadlock warning is not encountered. However, I don't think that we
should increase the de
I can do it. I have replaced all of the printf()s with fatal()s.
Is this correct, or should I use panic() instead?
--
Nilay
On Mon, 7 Feb 2011, Beckmann, Brad wrote:
I agree Nilay. Do you want to push that patch, or would you like me to
take care of it? Ideally Tushar should do it, but
Korey, I think the printf statements should be replaced with fatal() or
panic() instead.
--
Nilay
On Mon, 7 Feb 2011, Korey Sewell wrote:
changeset 5f2a2deb377d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5f2a2deb377d
description:
ruby: add stdio header in
not compile cleanly for me. I had change it fatal()
and include the header file base/misc.hh.
--
Nilay
On Mon, 7 Feb 2011, Beckmann, Brad wrote:
FYI...If my local regression tests are correct. This patch does not fix
all the problems with the MESI_CMP_directory protocol. One of the
patches
101 - 200 of 424 matches
Mail list logo
