On Wed, Jul 14, 2010 at 6:46 AM, Jiayuan Meng jerryh...@gmail.com wrote:
Thank you all for the suggestions!
=== I have the following questions: ===
1. how would M5 support plugins with pseudo instructions in the ISA?
Following Gabe's thoughts:
* M5 can provide general, customizable pseudo
Got it! I'll take a look at m5threads and prepare the patches to upload!
Thanks!
Jiayuan
On Thu, Jul 15, 2010 at 9:51 AM, Steve Reinhardt ste...@gmail.com wrote:
On Wed, Jul 14, 2010 at 6:46 AM, Jiayuan Meng jerryh...@gmail.com wrote:
Thank you all for the suggestions!
=== I have the
Thank you all for the suggestions!
=== I have the following questions: ===
1. how would M5 support plugins with pseudo instructions in the ISA?
Following Gabe's thoughts:
* M5 can provide general, customizable pseudo instructions
One possibility is to have this pseudo instruction
On Mon, Jul 12, 2010 at 8:20 AM, Jiayuan Meng jerryh...@gmail.com wrote:
Dear M5 Team,
I'll soon start to work on integrating our M5-based simulator, MV5, into
M5. I've read some documentation on the current status of M5, and I'd like
to share my plan/ideas with you and hear your suggestions.
2. SIMD cores: Based on TimingSimpleCPU.
This sounds pretty interesting too. Does the ISA matter much, or do
you think it could be pretty generic? Did you add new instructions to
do things?
Yes, I amended the Alpha ISA and added two instructions to mark the begin
and end of branch
1. An in-order CPU module with multi-threading (switching threads upon
cache
accesses) based on TimingSimpleCPU
This is probably #1 on the priority list
Is this inorder model detailed (in terms of pipeline stages, branch
prediciton, Functional Units, etc.)?
No it's not detailed (so
Hi Steve,
Personally I would say 2,3,4,1... but I can understand how others
might have different priorities. (Actually I haven't seen two people
with the same order yet!)
Maybe I should first re-take Stats101 to measure the best average of the
ordering :)
I think a key question that
Jiayuan Meng wrote:
2. SIMD cores: Based on TimingSimpleCPU.
This sounds pretty interesting too. Does the ISA matter much, or do
you think it could be pretty generic? Did you add new instructions to
do things?
Yes, I amended the Alpha ISA and added two instructions to
Dear M5 Team,
I'll soon start to work on integrating our M5-based simulator, MV5, into
M5. I've read some documentation on the current status of M5, and I'd like
to share my plan/ideas with you and hear your suggestions.
Since M5 will soon replace its entire memory system modeling with RubyGems,
Hi, Jiayuan,
Your list of contributions looks awesome!!! I would prefer the order of 3,
4, 1, 2.
Leonard
On Mon, Jul 12, 2010 at 10:20 AM, Jiayuan Meng jerryh...@gmail.com wrote:
Dear M5 Team,
I'll soon start to work on integrating our M5-based simulator, MV5, into
M5. I've read some
I'll soon start to work on integrating our M5-based simulator, MV5, into
M5. I've read some documentation on the current status of M5, and I'd like
to share my plan/ideas with you and hear your suggestions.
Since M5 will soon replace its entire memory system modeling with RubyGems,
it seems
1. An in-order CPU module with multi-threading (switching threads upon
cache
accesses) based on TimingSimpleCPU
This is probably #1 on the priority list
Is this inorder model detailed (in terms of pipeline stages, branch
prediciton, Functional Units, etc.)?
Is it functional within Full
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