[gem5-users] Re: Microcode_ROM Instruction and fetchRomMicroop() Function

instructions from the ROM to handle interrupts. For example, for the timer interrupt the linux updates process cgroup times for, do soft irqs, and reschedule, etc. Hope this helps. Br, Yuan. On 1/18/24 00:22, Abdelrahman S. Hussein via gem5-users wrote: Hello, I am looking

[gem5-users] Re: Squashing Instructions after Page Table Fault

ore than initially thought. With reference to the answer of Yuan, I guess that I also need to change stuff in the function chain for handling a fault. Can anyone confirm this? Best regards, Robin Gesendet: Mittwoch, 04. Oktober 2023 um 17:00 Uhr Von: "Eliot Moss via gem5-users" <ma

[gem5-users] Re: Squashing Instructions after Page Table Fault

or the above discussions. Hope this helps. PS. Page access write is checked at the translate function in tlb.cc. Br, Yuan On 9/29/23 12:28, reverent.green--- via gem5-users wrote: A short addition. I also couldn't find a specific check for the user/supervisor Page Table Attribute anywhere

[gem5-users] PyGILState_Check() failure

Hi, We encountered the following error when I am using X86KvmCPU and TimingSimpleCPU to make checkpoints in FS. "pybind11::object_api<>::operator() PyGILState_Check() failure." The same problem is reproduced in Ubuntu 20.04 and 22.04. My guess is some simobjects grabbed the

[gem5-users] Re: Problems with Deprecated names are not supported by the compiler

Hi Jason, Now the gem5 can work successfully with your help. And I am learning the detailed operations by following the learning_gem5. Thanks for your help! Regards, Xihui ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send

[gem5-users] Re: Problems with Deprecated names are not supported by the compiler

Hi Jason, Thanks for your help. But there are lots of errors in the first time to build gem5. scons: *** [build/X86/mem/ruby/protocol/DMA_Controller.py.cc] CalledProcessError : Command '['/home/xihui/下载/gem5/build/X86/marshal', 'build/X86/mem/ruby/protocol/DMA_Controller.py']' died with

[gem5-users] Problems with Deprecated names are not supported by the compiler

Hello everyone： I am a beginner with GEM5. There was a problem when I ran the project for the first time. Warning: Deprecated names are not supported by the compiler. I found no solution in the mailing list and website. Could you please give me any help to fix it?

[gem5-users] NVM interface in full system

Hi, All, The new gem5 can support NVM interface now. However, it seems that this nvm interface cannot work well with full system. Anyone in our community knows the status of this NVM with full system? Thanks and regards Yuan ___ gem5-users mailing list

[gem5-users] Re: GDB debug help

Hi, Abhishek, Thanks for your help. Do you have any hints about gdb backtrace in gem5? I am new to gdb debugging. Best regards. On Fri, Oct 2, 2020 at 12:03 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hi Yuan, > > Can you just backtrace using gdb, this will

[gem5-users] Re: GDB debug help

from: > > > > (gdb) p curTick > $1 = {Tick (void)} 0x562aea48 > > > > Could you try doing: > > > > (gdb) p curTick() > > > > It should display the current Tick time > > > > Giacomo > > > > *From:* Shougang Yuan via ge

[gem5-users] GDB debug help

h it? Can some please help me out? Thanks for your help. Best regards. Yuan ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] How to initialize the the Stats:Scalar value and convert it to unsigned value

Hi, All, I am trying to use gem5 internal scalar data type(Stats:Scalar), I tried to initialize it to a fixed value and register it in the regStats() function, but after the simulation, I found the value dumped out is 0. And also, if I want to do some calculation based on this value and convert

[gem5-users] tutorials about gem5-gpu

Hi, All, I am trying to get started with gem5-gpu, are there any tutorials about it for beginners? Best regards. Shougang ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] dump out the register value of each instruction

Hi, All, I want to dump out the source register and destination register value of each instruction. Suppose I have one instruction MOV_R_M : ld rax, DS:[rdx + 0x20]. How can I dump out the value of register *rax* and *rdx*. >From the debug trace like Exec or ExecAll. I can see that the result

[gem5-users] Re: Running a program on GEM5 for specific number of instructions

If you are talking about the SE mode, you can use the se.py. The fast forward option and max instruction option will be helpful. On Wed, Jul 8, 2020 at 2:28 PM ABD ALRHMAN ABO ALKHEEL via gem5-users < gem5-users@gem5.org> wrote: > Hi All, > > I want to run a program for 100k instructions but I

[gem5-users] Re: How to track the register values of instructions.

the instruction queue and the ROB. Best regards. Yuan On Tue, Jul 7, 2020 at 5:35 PM Jason Lowe-Power wrote: > Hi Yuan, > > A couple of suggestions: > 1. You can use "--debug-file" to output to a file. Or, you can even use a > named pipe with grep to filter out only

[gem5-users] Re: How to track the register values of instructions.

or dynamic instruction classes, but seems that these values are not carried/stored with each instruction? Am I correct? Could you please give more hints? Best regards. Yuan On Thu, Jul 2, 2020 at 11:07 AM Jason Lowe-Power wrote: > Hi Yuan, > > You might find the Exec and ExecAll de

[gem5-users] gem5 functional mode simulation

Hi, All, I want to use the functional simulator of gem5 to verify the results of some program. But I did not find a lot of information online about the functional mode. So how can we use functional mode in gem5? Best regards. Yuan ___ gem5-users

[gem5-users] How to track the register values of instructions.

Hi, All, I am trying to modify the gem5 code and suffer some memory corruption bugs. I want to look at more details of each instruction. So is there a way to dump out the register value of each instruction. Best regards. Yuan ___ gem5-users mailing

[gem5-users] Re: How to modify the simulator to load shared libs

61cf08e47cd/configs/common/Options.py#L402 > > On Tue, Jun 9, 2020 at 4:31 PM Shougang Yuan wrote: > > > > I tried as you said, but the error message is "error: no such option: > --redirects", and I check the options.py file in the configs/common > dir

[gem5-users] Re: How to modify the simulator to load shared libs

40 AM Ciro Santilli wrote: > --redirects /lib64=/path/to/where/you/symlinked/everything > > The linker will search in /lib64 normally, then gem5 will redirect > that file read to the path with all symlinks. > > On Tue, Jun 9, 2020 at 3:26 PM Shougang Yuan wrote: > > > >

[gem5-users] Re: How to modify the simulator to load shared libs

try to understand that, theoretically it feels like it should > work. > > > On Mon, Jun 8, 2020 at 6:05 PM Shougang Yuan via gem5-users > wrote: > > > > Hi, All, > > > > I am currently trying to run some benchmarks that need some shared libs. > If I run these benchm

[gem5-users] Re: benchmark exits with last active thread context

The benchmarks used (and where they may be obtained, if possible). > - The exact output, including error, you received. > > Kind regards, > Bobby > -- > Dr. Bobby R. Bruce > Room 2235, > Kemper Hall, UC Davis > Davis, > CA, 95616 > > web: https://www.bobbybruce.net

[gem5-users] How to modify the simulator to load shared libs

Hi, All, I am currently trying to run some benchmarks that need some shared libs. If I run these benchmarks on physical machines, I need to reset LD_LIBRARY_PATH to load these libs. But when I run the benchmarks with gem5, I tried to use --env options and --redirects options to set

[gem5-users] Re: How to add shared libs that used by benchmarks to the simulator

On Mon, Jun 8, 2020 at 10:42 AM Ciro Santilli wrote: > Have you tried --redirects as mentioned at > > https://stackoverflow.com/questions/5054/how-to-run-a-dynamically-linked-executable-syscall-emulation-mode-se-py-in-gem5/50696098#50696098 > ? > > On Mon, Jun 8

[gem5-users] Re: How to add shared libs that used by benchmarks to the simulator

In syscall emulation mode. I tried to use --env option with myse.py, but it still shows the same error. On Mon, Jun 8, 2020 at 3:39 AM Ciro Santilli wrote: > Syscall emulation or full system? > > On Sun, Jun 7, 2020 at 10:01 PM Shougang Yuan via gem5-users > wrote: > > >

[gem5-users] How to add shared libs that used by benchmarks to the simulator

HI, All, I am trying to run some benchmarks that need some shared libs, and these shared libs are imported by setting the environment variables "LD_LIBRARY_PATH" if I run it on physical machines. But if I run the benchmarks with gem5, the error message is "error while loading shared libraries:

[gem5-users] benchmark exits with last active thread context

Hi, All, I am trying to run some benchmarks with gem5, and it always exits with the last active thread context. But actually, the program has never been executed. Any hints about this? THanks a lot. Best regards. Shougang ___ gem5-users mailing list --

[gem5-users] Question about environment variables

Hi, All, I have c++ code that originally runs on physical machines with the ubuntu system, and to run these code on physical machines, I need to set some environment variables through export command or by modifying the bashrc files. Now I want to run the same code with gem5. So how can I add

[gem5-users] Re: Protobuf error on different ubuntu version

sion which is not breaking with Wundef. > > I’ve found that protobuf 3.6.1 is gem5 compatible > > > > Giacomo > > > > > > *From:* Shougang Yuan via gem5-users > *Sent:* 22 May 2020 20:57 > *To:* gem5 users mailing list > *Cc:* Shougang Yuan &g

[gem5-users] Protobuf error on different ubuntu version

Hi, All, I developed some code based on gem5 and ran it on ubuntu16 before. Recently I have installed a newer version of ubuntu18 and tried to re-run my code. I pulled the cold to my private github repo on ubuntu16 and clone it again to the ubuntu18, but I suffered the error as shown in the

Re: [gem5-users] Linux boot

Hi, Abhishek, I also have similar questions. I can boot the ubuntu18.04 and kernel 5.2.3 with timingSimpleCPu and KVM, but I want to run simulation with DeriveO3CPU. Do you know how to change the CPU to DeriveO3 after we boot the system with kvm or timingsimple cou? Best regards. Yuan On Thu

[gem5-users] CPU scheduler

Dear All, I am trying to find the code about cpu scheduler in SE mode about multi-core simulation setup. I mean, when we configured several O3 cpus and assigned a program to each core, how are these cpus been scheduled? Can anyone provide some details about this? Thanks. Best regards. Yuan

[gem5-users] Exact meaning of ExtMachInst

used about this part. Thanks. Best regards. Yuan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] 回复： 回复： ask for help about simulate with noncherentcahe

ned the L3 cache as an instance of NoncoherentCache, and define the L3Bus similar to L2Xbar. But I suffered the previous error and can not resolve it. Instead, I use Cache for L3 and make my code work. But I am still wondering how you get rid of this error. Best regards. Yuan On Wed, Dec 25, 2019

[gem5-users] Question about No-coherent cache as last level cache

Hi, All, I added a last level cache(L3 cache) to the system I simulated, I configured the L3/LLC in Caches.py as an instance of Cache class, I defined the L3Bus as a SystemXbar instance. And is this case, it works fine for all spec2006 benchmarks. But when I change the L3 cache as an instance of

Re: [gem5-users] Question about compile after adding global funcs

. Yuan On Thu, Nov 7, 2019 at 9:52 AM Francisco Carlos wrote: > Hi, Yuan > > Did you use #ifdef in your file my_func.hh? > > You should use #ifdef to avoid multiple definitions and circular includes. > > So, in the first line of your file my_func.hh, you must insert

[gem5-users] Question about compile after adding global funcs

the error of multiple definition of “the name of my func”. Does anyone have some hints on this? Best, Yuan Sent from Mail for Windows 10 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] TimeBuffer in O3 cpu

anyone knows more about this part. Best regards. Yuan Sent from Mail for Windows 10 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Where is the different namespace defined in CPUdirectory.

Thanks, Ciro. And do you know where is the cpu policy class are defined? Best regards. Yuan Sent from Mail for Windows 10 From: Ciro Santilli Sent: Sunday, October 27, 2019 3:21 AM To: gem5 users mailing list; yuan Subject: Re: [gem5-users] Where is the different namespace defined

[gem5-users] Where is the different namespace defined in CPU directory.

are defined and how the build/X86 code is generated when we build them. Or is there any documents about this part. Best regards. Yuan Sent from Mail for Windows 10 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman

[gem5-users] Memory Command

Hi, All I am trying to read through the code in src/mem/, but I find that there are a lot memory command defined in packet.hh. Are there any docs for these memory commands? I am confused with some of these memory commands. Best, Yuan Sent from Mail for Windows 10

Re: [gem5-users] Question about multi-program simulation usingspec2006

environment? Best regards. Yuan Sent from Mail for Windows 10 From: Jason Lowe-Power Sent: Tuesday, September 24, 2019 10:48 AM To: gem5 users mailing list Subject: Re: [gem5-users] Question about multi-program simulation usingspec2006 Hi Yuan, Generally, it is difficult to get multiprogrammed

[gem5-users] Question about multi-program simulation using spec2006

, but the others have no statistics. I tried to dump out the instruction counter of each core but find that not all cores can dump out this info. Does anyone has any hints about this? Thanks all. Best regards. Yuan Sent from Mail for Windows 10 ___ gem5

Re: [gem5-users] Question about muti-processor simulation on se mode

Hi, Ciro Santilli, Thanks for your kind help, I have checked the spec2006 benchmarks, it does not spawn threads. Spec2006 is single thread program. That’s why I can not get statistics of all processors. Best, Yuan Sent from Mail for Windows 10 From: Ciro Santilli Sent: Monday, September 9

Re: [gem5-users] Question about muti-processor simulation on se mode

running spec benchmark with multi core on se mode. Best regards. Shougang On Sat, Sep 7, 2019 at 10:12 PM Ciro Santilli wrote: > > > On Sun, Sep 8, 2019 at 12:57 AM yuan wrote: > >> Hi, Ciro Santilli, >> >> >> >> I have tried the whole afternoon about th

[gem5-users] Question about muti-processor simulation on se mode

Hi, all, I am trying to simulate a system with 4 cores, a test command line is as follow: build/X86/gem5.opt configs/example/se.py -n 4 --cpu-type=DerivO3CPU --mem-type=DDR4_2400_8x8 --mem-size=8GB --caches --l1d_size=64kB --l1i_size=32kB --l2cache --l2_size=512kB -c

Re: [gem5-users] how to define combined debug flags.

Hi, Francisco Carlos, Thanks. This is exactly the piece of code I want look into. Thank you so much. Best regards. Yuan Sent from Mail for Windows 10 From: Francisco Carlos Sent: Monday, September 2, 2019 10:54 AM To: gem5 users mailing list Subject: Re: [gem5-users] how to define combined

Re: [gem5-users] how to define combined debug flags.

flags like this by ourselves. Best regards. Yuan Sent from Mail for Windows 10 From: Francisco Carlos Sent: Monday, September 2, 2019 10:44 AM To: gem5 users mailing list Subject: Re: [gem5-users] how to define combined debug flags. Hi Yuan, You can use, for example: ./build/x86/gem5.opt --debug

[gem5-users] how to define combined debug flags.

flags defined by myself in different files and I want to dump them out in simulation, how can I do it? Can anyone give some hints? Thanks so much. Best regards. Yuan Sent from Mail for Windows 10 ___ gem5-users mailing list gem5-users@gem5.org http

[gem5-users] How to run SE on multicores to speedup simulation ?

, Kevin Yuan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] How to reply in gem5 mailinglist

Hi, all, I tried to post some questions on gem5 user mailing list, but when I got some response I can find the right way to reply. Can anyone give some hints about this. Thanks so much. Best regards. Yuan Sent from Mail for Windows 10 ___ gem5

[gem5-users] question about build errors

Hi, all, Today I suffered from a weird problem when building gem5. I make some changes and then re-build it, but the error shows like this. And when I get a new repo from gem5 without any modification, the same error shows up again. Anyone knows what happened to this? In file included from

[gem5-users] what is the meaning of packet id in Packet.hh

Hi, all, I find that there is a member in packet.hh called id. And this id is initialized in Packet constructor by the get() of shared_ptr, I am wondering what is the exact meaning of the member id in packet class. Could anyone please help to give some hints about this? Best regards.

[gem5-users] Question about read/write/executed unmapped address

that this error is dumped out at the fault.cc file, but I am wondering what is the main reason for this kind of bugs? And how to debug this kind of errors? Can anyone give some hints? Thanks so much. Best regards. Yuan Sent from Mail for Windows 10

[gem5-users] Questions about simulation configure!

nothing there? Does anyone knows about this? Thank you so much. Best regards. Yuan Sent from Mail for Windows 10 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] questions about template policies in O3CPU

this template usage? Does anyone know about this part. Thanks so much. Best regards. Yuan Sent from Mail for Windows 10 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Question about writeClean command

just write this dirty block to the next level but do not evict the current block from cache? Best regards. Yuan Sent from Mail for Windows 10 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Question about m5.switchCpus()

Assertion `old_itb_port->isConnected()' failed. Does anyone has insight about this part or know how to implement fast-forwarding in our own script? Best regards. Yuan Sent from Mail for Windows 10 ___ gem5-users mailing list gem5-users@gem5.org htt

[gem5-users] Questions about modeling variable dram packet delay?

Hi, all, I am trying to model a variable latency dram system, in which every dram packet has different latency instead of a fixed latency. I tried to add the latency in the readyTime for each dram pkt. But it disturbed the power event because some refresh events were not satisfied in time and

[gem5-users] Increasing stack size by one page

Hi, All, I am using gem5 with X86 ISA, and now trying to run the spec2006 benchmark(bzip2 exactly). I use the test input to get the naïve test result. The command line is build/X86/gem5.opt config/examples/se.py --mem-type=DDR4_2400_8x8 --mem-size=4GB –cpu-type=TimingSimpleCPU

[gem5-users] Panic: Resetting mouse warp mode unimplemented

x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[0x7fb9813d711c] /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6ffd)[0x7fb98129ff5d] --- END LIBC BACKTRACE --- Aborted (core dumped) Shougang Yuan ___ gem5-users mailin

[gem5-users] Write through cache

Hi, there, I am wondering how to enable write through policy in gem5? I tried to use pkt->SetWritethrough() for each write request in cache class. But it seems that these write requests never go down stream to the lower level cache and eventually to memory controller. Does anyone know how to

Re: [gem5-users] Error when compiling gem5

Hello Ciro, Thank you for your reply. Your way solves the problem. I am now using GCC 6.1.0 which compiles gem5 fine. Mr. Yuan Yao PhD Student ESY, ICT KTH Royal Institute of Technology <mailto:yuan...@kth.se> yuan...@kth.se <https://www.linkedin.com/in/yuan-yao-085

[gem5-users] Error when compiling gem5

;() && { return std::move(v); } Can anyone kindly give me a hint? I am using python-2.7.2, gcc-4.8.0, and scons-2.1.0, without system root privilege. I guess this error has something to do with the c++11 support, since the error is related to pybind11. Best, Yuan

Re: [gem5-users] Wakeup after restoring checkpoint (Yuan Yao)

From: gem5-users [gem5-users-boun...@gem5.org] on behalf of Erfan Azarkhish [e.azarkh...@gmail.com] Sent: Tuesday, June 30, 2015 7:42 AM To: gem5 users mailing list Subject: Re: [gem5-users] Wakeup after restoring checkpoint Dear Yuan, I faced the same

[gem5-users] How to change the router frequency in Garnet

with the PARSEC benchmark (currently I use CANNEAL, which is communication extensive), I get very little difference in terms of IPC. So, I think Router::checkReschedule() is not the right place for the router frequency tuning, is it? Best Regards == Yuan Yao

[gem5-users] Wakeup after restoring checkpoint

. It seems the wake up event of MyComponent is not registered successfully. But I am not sure about this... Based on this observation, my question is: - How to wake up your own component after restoring from a checkpoint? Best Regards == Yuan Yao (Mr.) PhD

Re: [gem5-users] O3CPU LSQ store-to-load forwarding

Thanks Henry, I see that. Regards, Yuan On 25 Oct, 2013, at 7:20 PM, Huang, Henry henry.hu...@amd.com wrote: Yuan, O3CPU does support STLF. You may see function LSQUnitImpl::read(Request *req, Request *sreqLow, Request *sreqHigh, uint8_t *data, int load_idx) in source file

[gem5-users] O3CPU LSQ store-to-load forwarding

Hi, all, Does the O3CPU LSQ support store-to-load forwarding? From the L1 memory trace, I can see a load issued to memory for exactly the same address (no only the cacheline address) to an outstanding store. Regards, Yuan ___ gem5-users mailing list

Re: [gem5-users] About executing multi loads

I am experiencing the same issue. Wherever one CPU executes exit(), the muti-programmed simulation terminates. Anybody can help? On 11 Oct, 2013, at 1:14 AM, Rodrigo Reynolds Ramírez rodrigo.r...@hotmail.com wrote: Hello everyone; I am using gem5 for multi loads, I am using the below line

Re: [gem5-users] About executing multi loads

[mailto:gem5-users-boun...@gem5.org] On Behalf Of Yuan Yao Sent: Monday, October 21, 2013 2:00 PM To: gem5 users mailing list Subject: Re: [gem5-users] About executing multi loads I am experiencing the same issue. Wherever one CPU executes exit(), the muti-programmed simulation terminates. Anybody

[gem5-users] Uncacheable load panic

Dear all, I am experiencing the same problem to the thread posted before http://www.mail-archive.com/gem5-users@gem5.org/msg08426.html The panic shows during the freeing init memory stage of linux boot. Uncachable load [sn:e7b52] PC (0xc014e7a0=0xc014e7a4).(0=1) Has anyone fixed this? Best

[gem5-users] mandatory queue recycle function

of the queue? Any help will be highly appreciated. Yuan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] panic: Page table fault when accessing virtual address 0x9

Yuan Yao liked your message with Boxer. On Sun, Aug 11, 2013 at 08:41 AM, Xiangyang Guo wrote:HI, I'm sorry that the virtual address is 0x7dffe90. I made a mistake in my previous email. So could any one give me some hints? Thanks Xiangyang On Sat, Aug 10, 2013 at 5:12 PM, Xiangyang Guo ece

[gem5-users] Cache Transition Problem

Hello All: I use Gems + Simics 3.0 I compile Ruby with Garnet and it runs well when I use 16 cores. But when I configure Ruby to 64 cores, I got the following error when I run tester.exec: Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event,

[gem5-users] How many event queues in Garnet?

Hello Dear All: Wish you all good. I'm new to gems. And here i want to ask two simple questions. 1, How many event queues are there in Garnet? Since garnet is a event driven network model, are all the events stored in a single global event queue? 2, How the events are fetched

[gem5-users] Anyone use Garnet standalone?

by the creator of Garnet, Niket. So if you guys happen to have this tester file, i think the name is tester-network-only.tgz , could you please send it to me through my private email? Thanks! Best Regards == Yuan Yao, Master Student of System-on-Chip (SoC), KTH

[gem5-users] IS FS simulation Necessary?

Hi Nilay I took so long time to figure out how to make FS simulation work with Ruby system. Does that mean I should have considered SE at the very beginning and I just wasted time to work with FS since SE can do every thing and faster? ___ gem5-users

Re: [gem5-users] Checkpointing error on ALPHA_MOESI_hammer full system mode

MemoryVector::populatePages(uint8*): Assertion `m_pages[i] == 0' failed the ASSERTION fails, so we can just use m_pages[i] = 0 in the for loop and delete the ASSERTION in this populate function remember the restore default type is atomic, use --restore-with-cpu=THE TYPE YOU CHECKPOINT WITH

Re: [gem5-users] IS FS simulation NECESSARY?

THX Nilay Thank you very much for the reply! Your explaination is so clear and I will keep going in FS! ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] SE simulation does support Ruby?

Hi all I am working on RUBY FS stuffs, and I found it is so slow to use FS simulation and let os kernel to schedual threads among cores. I heared SE simulation can allocate threads manually and save a lot of time. I wonder whether we can use SE with Ruby cache system and garnet network and

[gem5-users] Alpha Ruby Full System: 'm5 checkpoint' Fails

Hi there I wonder that the command 'm5 checkpoint' does not work for a Alpha Ruby full system simulation! After I boot up a RUBY model ALPHA full system successfully, I use the command 'm5 checkpoint' in the sell of the simulated system, I encounter a RUNTIME ERROR below and

Re: [gem5-users] A segmentation fault of running ruby memory model

info: Entering event queue @ 2747178166000. Starting simulation... panic: RubyPort::M5Port::recvAtomic() not implemented! @ cycle 2747178166500 [recvAtomic:build/ALPHA/mem/ruby/system/RubyPort.cc, line 125] this panic occurs probably because that we take checkpoint using Atomic model first and

[gem5-users] ERROR Checkpointing in ALPHA full system

Hi all Now, I can boot up a 16-core ALPHA ruby_fs system successfully, with MESI_CMP_directory protocol. When I used the m5 checkpoint command in the sell, the simulation aborted with the following information: Runtime Error at MESI_CMP_directory-L1cache.sm:221, Ruby Time: 23014921238: