Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-18 Thread Shmuel Metz (Seymour J.)
In <012501cc8d4e$0f098770$2d1c9650$@net>, on 10/18/2011 at 12:26 AM, Micheal Butz said: >SRB was the only way to go, Why wouldn't an IRB work? -- Shmuel (Seymour J.) Metz, SysProg and JOAT ISO position; see We don't care. We don't h

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-18 Thread Shmuel Metz (Seymour J.)
In <011b01cc8d43$10639a30$312ace90$@net>, on 10/17/2011 at 11:07 PM, Micheal Butz said: >I normally get 0F8 when I am in XMEM mode and issue a SVC I didn't >abended on a SVC I abended whitin STM of the SETFRR inst No. You got the ABEND on the breakpoint that TESTAUTH inserted in place of th

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-18 Thread Chris Craddock
On Tue, Oct 18, 2011 at 10:20 AM, Micheal Butz wrote: > Is all that's required for setting a recovery routine for the SRB is > setting > a address in SRBFRRA ? > > At the risk of sending you off on another tangent, "yes". But, what would you *DO* with

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-18 Thread Micheal Butz
tober 18, 2011 3:10 AM To: IBM-MAIN@bama.ua.edu Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 0014 under TESTAUTH On Tue, 18 Oct 2011 00:26:08 -0400 Micheal Butz wrote: :>I am trying to issue a branch entry form of a macro in a other address :>space since the specifications say PASN=HASN=SASN

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-18 Thread Tom Harper
give details on WHAT you are trying to accomplish - not how you are trying to do it. :>-Original Message- :>From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf :>Of Chris Craddock :>Sent: Tuesday, October 18, 2011 12:05 AM :>To: IBM-MAIN@bama.u

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-18 Thread McKown, John
> -Original Message- > From: IBM Mainframe Discussion List > [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Lizette Koehler > Sent: Monday, October 17, 2011 9:54 PM > To: IBM-MAIN@bama.ua.edu > Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 0014 under TESTAUTH > >

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-18 Thread Binyamin Dissen
trying to do it. :>-Original Message- :>From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf :>Of Chris Craddock :>Sent: Tuesday, October 18, 2011 12:05 AM :>To: IBM-MAIN@bama.ua.edu :>Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 0014 under

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-17 Thread Micheal Butz
ssue a SVC I didn't abended > on a SVC I abended whitin STM of the SETFRR inst > > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf > Of Lizette Koehler > Sent: Monday, October 17, 2011 10:54 PM > To: IBM

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-17 Thread Chris Craddock
a SVC I didn't abended > on a SVC I abended whitin STM of the SETFRR inst > > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf > Of Lizette Koehler > Sent: Monday, October 17, 2011 10:54 PM > To: IBM-MAIN@bama.ua.edu >

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-17 Thread Wayne Driscoll
When you set a breakpoint in TSO TEST (or TESTAUTH), the TEST processor copies the current instruction off, and then inserts an SVC 97 instruction (0A61). Because you have an EUT FRR established, you are prohibited from issuing SVC instructions (other than 13). Because of this, when the TEST

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-17 Thread Micheal Butz
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Lizette Koehler Sent: Monday, October 17, 2011 10:54 PM To: IBM-MAIN@bama.ua.edu Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 0014 under TESTAUTH > Hi, > > > > I am trying to establish a FRR in a TSO

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-17 Thread Lizette Koehler
> Hi, > > > > I am trying to establish a FRR in a TSO command processor program that is not re- > entrant this is because > > Later I schedule a SRB and I want to use the routine I established as a FRR, as input > to the SRBFRRA parameter > Did you review the abend and code? S0F8 - 14 - TH