I had guessed that an APF-authorized but otherwise "ordinary" program
running with Key 8 would be able to issue an SPKA with an "address" of
xx8x in problem state without getting a S0C2. I appear to have guessed
wrong. I just wanted to do a reality check to make sure I had not
fat-fingered some
: IBM-MAIN@LISTSERV.UA.EDU
Subject: Question on SPKA and Control Register 3
I had guessed that an APF-authorized but otherwise "ordinary" program running
with Key 8 would be able to issue an SPKA with an "address" of xx8x in
problem state without getting a S0C2. I appear to have
: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Blaicher, Christopher Y.
Sent: Monday, December 12, 2016 1:54 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
I don't know for sure, but could it be that there is no assurance that it
says "Bits 0-55 and 60-63 of the second-operand address
are ignored.")
Anyone have any ideas?
Charles
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Charles Mills
Sent: Monday, December 12, 2016 1:59 PM
To: IBM-MAIN@LISTSER
Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Charles Mills
Sent: Monday, December 12, 2016 3:54 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
Hmmm. I am seeing the following in Extended Addressability:
"All programs are initially dispatched wi
> There is a preceding MODESET KEY=ZERO. It wouldn't make sense for that
to
> reset Control Register 3, turning on bit 0 and off bit 8, would it? "You
can
> set any SPK you want, so long as it is the one you already have."
The MODESET documentation says:
,MODE=PROB,
MODE=SUP
Specifies t
It would not fail under MVS.
My guess is that you are not checking the correct thing.
Post the minidump.
On Mon, 12 Dec 2016 13:49:09 -0800 Charles Mills wrote:
:>I had guessed that an APF-authorized but otherwise "ordinary" program
:>running with Key 8 would be able to issue an SPKA with an "
>I had guessed that an APF-authorized but otherwise "ordinary" program
>running with Key 8 would be able to issue an SPKA with an "address" of
>xx8x in problem state without getting a S0C2.
Whether APF-authorized or not, it can. If your program is getting S0C2,
then you are most likely not do
ubject: Re: Question on SPKA and Control Register 3
>I had guessed that an APF-authorized but otherwise "ordinary" program
>running with Key 8 would be able to issue an SPKA with an "address" of
>xx8x in problem state without getting a S0C2.
Whether APF-author
Charles Mills wrote:
>* Enter APF-authorized and with Key=8
> MODESET KEY=ZERO,MODE=SUP
>* do stuff (one)
> MODESET MODE=PROB
>* do stuff (two)
> MODESET KEY=NZERO
>leaves you in a state in which SPKA 8's will fail.
When? Does it fail during stuff 1 or stuff 2? From what you wr
M Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Charles Mills
Sent: Tuesday, December 13, 2016 6:06 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
@Peter, @Bin, it's really failing and there is no flaw (I believe!) in the
SPKA co
016 6:35 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
Charles Mills wrote:
>* Enter APF-authorized and with Key=8
> MODESET KEY=ZERO,MODE=SUP
>* do stuff (one)
> MODESET MODE=PROB
>* do stuff (two)
> MODESET KEY=NZERO
>
You have received a secure message from "Vitullo, Carmen P"
entitled, "RE: Question on SPKA and Control
Register 3".
You can view the message (before 12/27/2016) at the following web address:
https://mg.usablecs.com/
t;Carmen P Vitullo"
To: IBM-MAIN@LISTSERV.UA.EDU
Sent: Tuesday, December 13, 2016 8:53:36 AM
Subject: Re: Question on SPKA and Control Register 3
You have received a secure message from "Vitullo, Carmen P"
entitled, "RE: Question on SPKA and Control
Register 3".
You
Sent: Tuesday, December 13, 2016 7:08 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
Sorry again folks - I forgot NOT to send replies via my work email
Not sure my assembler is very weak, but don't you have to specify supervisor
state when se
ok, thanks, all the example I have specify both for some reason, thanks
Carmen
- Original Message -
From: "Charles Mills"
To: IBM-MAIN@LISTSERV.UA.EDU
Sent: Tuesday, December 13, 2016 9:20:36 AM
Subject: Re: Question on SPKA and Control Register 3
Neither. They are i
IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Charles Mills
Sent: Tuesday, December 13, 2016 6:48 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
Okay, there is just no doubt in my mind that the use of MODESET precludes
the use of SP
:>
:>@Peter, @Jim -- if you're following this, I'm testing on V2R2 but could
:>readily try on V2R1 or V1R13.
:>
:>Charles
:>
:>-Original Message-
:>From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
:>Behalf Of Charles Mills
:>Sent:
Y=ZERO slows it down
significantly. Does it double the path length in MVS?
Charles
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Binyamin Dissen
Sent: Tuesday, December 13, 2016 9:28 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA an
On Mon, 12 Dec 2016 22:04:45 -0500, Jim Mulder wrote:
> The MODESET documentation says:
>
>,MODE=PROB,
> MODE=SUP
>Specifies that the PSW problem state indicator
>(bit 15) is to be either turned on (PROB) or turned off (SUP). If the
>MODESET operation completes with a problem state PSW, th
al Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf
Of Tom Marchant
Sent: Tuesday, December 13, 2016 10:28 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
On Mon, 12 Dec 2016 22:04:45 -0500, Jim Mulder wrote:
>
: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf
Of Charles Mills
Sent: Tuesday, December 13, 2016 10:39 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
I think it is in a less than ideal spot in the text. It appears to apply to t
t;Charles
:>
:>-Original Message-
:>From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Charles Mills
:>Sent: Tuesday, December 13, 2016 10:39 AM
:>To: IBM-MAIN@LISTSERV.UA.EDU
:>Subject: Re: Question on SPKA and Control Register 3
:>
:>
>Yep, it is a bug.
>The PSW key mask has key 0 and key9 after the combination. Not key 8. I
would
>not expect MODESET to alter the key mask.
No it is not a bug. The "expectation" is incorrect. The updating of the
PKM is fully documented and is what we wanted it to be.
If you want to be switch
5:39 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
>Yep, it is a bug.
>The PSW key mask has key 0 and key9 after the combination. Not key 8.
>I
would
>not expect MODESET to alter the key mask.
No it is not a bug. The "expectation" is
I would argue that the principal of "least astonishment" would suggest that
granting key0 would not imply the loss of current key. But I guess doc is doc.
On Wed, 14 Dec 2016 08:38:50 -0500 Peter Relson wrote:
:>>Yep, it is a bug.
:>
:>>The PSW key mask has key 0 and key9 after the combination.
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Binyamin Dissen
Sent: Wednesday, December 14, 2016 6:15 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
I would argue that the principal of "least astonishment" would s
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf
Of Charles Mills
Sent: Tuesday, December 13, 2016 11:04 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
To close the loop on this, it seems pretty clear that any SVC form of MO
A.EDU] On Behalf
Of Rob Scott
Sent: Wednesday, December 14, 2016 7:14 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
Charles
I am struggling to understand why you would want to run key0 and problem state
anyway - it seems like a very strange brew and a bit
On 12/14/2016 6:04 AM, Charles Mills wrote:
My only interest in using SPKA was to avoid having to use an SVC just to
effectively reduce my privileges (key 0 to key 8). The program does this
switch from key 8 to key 0 and back over a million times per hour per LPAR
at several locations. Using an
On Wed, Dec 14, 2016 at 10:12 AM, Charles Mills wrote:
> Well, yes, the why is to access shared 64-bit common.
>
> It's worked well for years. A PC service to move some data and increment a
> pointer (millions of times per hour) seemed like overkill.
>
> Charles
>
>
​Just talking out of my hat, w
@LISTSERV.UA.EDU] On Behalf
Of Charles Mills
Sent: Wednesday, December 14, 2016 4:12 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
Well, yes, the why is to access shared 64-bit common.
It's worked well for years. A PC service to move some data and increment a
po
AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
On Wed, Dec 14, 2016 at 10:12 AM, Charles Mills wrote:
> Well, yes, the why is to access shared 64-bit common.
>
> It's worked well for years. A PC service to move some data and
> increment a pointer (mi
Interesting. I have avoided going there, but perhaps I should.
Charles
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf
Of Ed Jaffe
Sent: Wednesday, December 14, 2016 8:36 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and
: Re: Question on SPKA and Control Register 3
I am not sure how much more efficient using a two MODESET SVCs to flip in and
out of Key0/Sup would be compared to a single PC-ss.
I would also advise to not use key0 for any of your application memory unless
absolutely necessary.
Have you
On 12/14/2016 8:47 AM, Charles Mills wrote:
Interesting. I have avoided going there, but perhaps I should.
The code (originally developed many, many years ago) builds and saves a
model left-half PSW at initialization time, thus allowing the actual
switch back to problem state and TCB key to b
Thanks!
Charles
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf
Of Ed Jaffe
Sent: Wednesday, December 14, 2016 10:00 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
On 12/14/2016 8:47 AM, Charles
On Wed, 14 Dec 2016 10:00:19 -0800, Ed Jaffe wrote:
>Obviously, this will need to be looked at if we ever move it above the
>bar...
... or run AMODE 64.
If I was to implement something like this now, I would build a 128-bit
PSW and use LPSWE.
--
Tom Marchant
-
On 12/14/2016 10:29 AM, Tom Marchant wrote:
On Wed, 14 Dec 2016 10:00:19 -0800, Ed Jaffe wrote:
Obviously, this will need to be looked at if we ever move it above the
bar...
... or run AMODE 64.
If this module ever runs AMODE(64), all we need to do is change this:
OILH R15,X'8000'
On 14 December 2016 at 08:38, Peter Relson wrote:
> No it is not a bug. The "expectation" is incorrect. The updating of the
> PKM is fully documented and is what we wanted it to be.
I'm not saying it's a bug, but it feels immediately wrong for reasons
I'm having trouble articulating. I guess may
was sufficiently persuasive.
Charles
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf
Of Tony Harminc
Sent: Wednesday, December 14, 2016 11:35 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
On 14 Decem
>I think I mentioned that I believe in "least privilege." I don't want to
run
>an entire LE/C++ started task in supervisor state.
When "belief" gets into the way of "function", it could be time to
re-examine. Perhaps you should look for a way that does not require you to
be doing key 0 stuff (
t: Thursday, December 15, 2016 4:21 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
>I think I mentioned that I believe in "least privilege." I don't want
>to
run
>an entire LE/C++ started task in supervisor state.
When "beli
its on exit: the
> current key, key 9, and the TCB key (typically 8).
>
> Charles
>
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> Behalf Of Peter Relson
> Sent: Thursday, December 15, 2016 4:21 PM
> To: IBM-MAIN@L
On 12/15/2016 4:21 PM, Peter Relson wrote:
After it showed up on a customer's STROBE report, we switched over to
using LPSW instead...
If you're unlucky enough to hit the edge case, you will lose the PER bit
by doing so.
Actually, that's a good point. If we get interrupted after the STOSM an
> >> After it showed up on a customer's STROBE report, we switched over to
> >> using LPSW instead...
> > If you're unlucky enough to hit the edge case, you will lose the PER
bit
> > by doing so.
>
> Actually, that's a good point. If we get interrupted after the STOSM and
> before the LPSW, and
IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Jim Mulder
Sent: Friday, December 16, 2016 4:42 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Question on SPKA and Control Register 3
> >> After it showed up on a customer's STROBE report, we switched over
> >> to using LPSW instead...
> >
> > And that means that PSW and your code need to be in fixed or DREF
storage.
>
> Not arguing at all, just trying to educate myself ... why? I don't see
> anything in PoOp about STNSM needing fixed storage.
PoOp doesn't know anything fixed storage. And it isn't the
STNSM that needs the storag
I presume the target of Ed's STOSM is in the PSW he's fixing to load. So,
after changing the code to use the STNSM, he'd need to add an OI
PSWMASK,X'03' before the LPSW, as it really sounds like he doesn't want to
run disabled after that.
Right?
On Fri, Dec 16, 2016 at 9:27 PM, Jim Mulder wrote
> I presume the target of Ed's STOSM is in the PSW he's fixing to load.
So,
> after changing the code to use the STNSM, he'd need to add an OI
> PSWMASK,X'03' before the LPSW, as it really sounds like he doesn't want
to
> run disabled after that.
>
> Right?
Not right. STNSM is Store *Then* An
>I presume the target of Ed's STOSM is in the PSW he's fixing to load. So,
>after changing the code to use the STNSM, he'd need to add an OI
>PSWMASK,X'03' before the LPSW, as it really sounds like he doesn't want
to
>run disabled after that.
>Right?
Nope. The value placed into "PSW" is the time
On 12/17/2016 7:36 AM, Peter Relson wrote:
I will mention that, unless you are returning to your caller by PR or
perhaps your RB ends, you might want to avoid using a "model PSW" and
instead use "EPSW" in order to make sure that you have all of the current
bits that might conceivably apply (now
On 12/16/2016 4:42 PM, Jim Mulder wrote:
Your code must be changed from STOSM PSWMASK,0 to
STNSM PSWMASK,X'FC' . And that means that PSW and your
code need to be in fixed or DREF storage.
Thank you, my friend. Thy will be done...
--
Edward E Jaffe
Phoenix Software International, Inc
831 P
On 17 December 2016 at 11:10, Ed Jaffe wrote:
> Yeah. This code was written back in the 1980s before EPSW (which is a GREAT
> instruction BTW that came out only about 30 years too late) was even a
> glimmer in some hardware developers eye. ;)
It couldn't exist before SIE, because it breaks the pr
On Sat, 17 Dec 2016 23:25:00 -0500, Tony Harminc wrote:
>A problem program must not be (architecturally, not by heuristics) able
>to discover that it's running in a virtual machine.
This is no longer true. When STLFE (problem state) reports the presence of the
store-hypervisor-information facil
ject:Re: Question on SPKA and Control Register 3
Sent by:IBM Mainframe Discussion List
On Sat, 17 Dec 2016 23:25:00 -0500, Tony Harminc wrote:
>A problem program must not be (architecturally, not by heuristics) able
>to discover that it's running in a virtual machine.
This is
On 12/17/2016 8:25 PM, Tony Harminc wrote:
It couldn't exist before SIE, because it breaks the pre-SIE VM. A
problem program must not be (architecturally, not by heuristics) able
to discover that it's running in a virtual machine. To boot, the PSW
would be wrong most of the time.
This code was
57 matches
Mail list logo
