Hi Tudor,
> -Original Message-
> From: tudor.amba...@microchip.com
> Sent: Wednesday, July 31, 2019 6:37 PM
> To: Naga Sureshkumar Relli ;
> boris.brezil...@collabora.com;
> marek.va...@gmail.com; vigne...@ti.com
> Cc: rich...@nod.at; linux-kernel@vger
> -Original Message-
> From: Boris Brezillon
> Sent: Wednesday, July 31, 2019 6:08 PM
> To: Naga Sureshkumar Relli
> Cc: tudor.amba...@microchip.com; marek.va...@gmail.com; vigne...@ti.com;
> rich...@nod.at; linux-kernel@vger.kernel.org; linux-...@lists.infradead
,
> default:
> break;
> }
> +
> + if (nor->info->flags & SPI_S3AN)
> + s3an_post_sfdp_fixups(nor);
> }
>
Instead of checking the flags, why can't we call directly the nor_fixups?
like Boris implementation nor->info->
Add driver for arm pl353 static memory controller nand interface.
This controller is used in Xilinx Zynq SoC for interfacing the
NAND flash memory.
Signed-off-by: Naga Sureshkumar Relli
---
xilinx zynq TRM link:
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
Hi Boris,
> -Original Message-
> From: Boris Brezillon
> Sent: Wednesday, July 17, 2019 2:34 PM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; bbrezil...@kernel.org; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@
> -Original Message-
> From: Boris Brezillon
> Sent: Wednesday, July 17, 2019 1:25 PM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; bbrezil...@kernel.org; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gmail.com;
Hi Boris,
> -Original Message-
> From: Boris Brezillon
> Sent: Tuesday, July 16, 2019 1:15 PM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; bbrezil...@kernel.org; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gmail.com;
Add check before assigning chip->ecc.read_page() and chip->ecc.write_page()
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v18
- None
---
drivers/mtd/nand/raw/nand_micron.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_micro
Add driver for arm pl353 static memory controller nand interface.
This controller is used in Xilinx Zynq SoC for interfacing the
NAND flash memory.
Reviewed-by: Helmut Grohne
Signed-off-by: Naga Sureshkumar Relli
---
xilinx zynq TRM link:
https://www.xilinx.com/support/documentation/user_guides
Hi Boris,
> -Original Message-
> From: linux-mtd On Behalf Of Naga
> Sureshkumar
> Relli
> Sent: Wednesday, June 26, 2019 6:04 PM
> To: Boris Brezillon
> Cc: vigne...@ti.com; bbrezil...@kernel.org; helmut.gro...@intenta.de;
> rich...@nod.at;
> linux-kerne
Hi Boris,
> -Original Message-
> From: Boris Brezillon
> Sent: Wednesday, July 3, 2019 4:37 PM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; helmut.gro...@intenta.de; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gm
Hi Boris,
Thanks for the review.
> -Original Message-
> From: Boris Brezillon
> Sent: Wednesday, July 3, 2019 11:56 AM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; helmut.gro...@intenta.de; rich...@nod.at;
> dw...@infradead.org; computersforpe...@g
Hi Miquel,
> -Original Message-
> From: linux-mtd On Behalf Of Helmut
> Grohne
> Sent: Tuesday, June 25, 2019 7:41 PM
> To: Naga Sureshkumar Relli
> Cc: vigne...@ti.com; bbrezil...@kernel.org; yamada.masah...@socionext.com;
> rich...@nod.at; linux-kernel@vger
Hi Miquel,
> -Original Message-
> From: Miquel Raynal
> Sent: Thursday, June 27, 2019 9:58 PM
> To: Naga Sureshkumar Relli
> Cc: Naga Sureshkumar Relli ; r...@kernel.org;
> martin.lund@keep-it-
> simple.com; rich...@nod.at; linux-kernel@vger.kernel.org; Bori
Hi Boris,
> -Original Message-
> From: Boris Brezillon
> Sent: Wednesday, June 26, 2019 5:50 PM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; helmut.gro...@intenta.de; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@
Hi Boris,
> -Original Message-
> From: Boris Brezillon
> Sent: Wednesday, June 26, 2019 5:34 PM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; helmut.gro...@intenta.de; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@
Hi Boris,
> -Original Message-
> From: Boris Brezillon
> Sent: Wednesday, June 26, 2019 4:57 PM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; helmut.gro...@intenta.de; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@
Hi Boris,
> -Original Message-
> From: Boris Brezillon
> Sent: Wednesday, June 26, 2019 12:18 PM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; helmut.gro...@intenta.de; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@
Add driver for arm pl353 static memory controller nand interface.
This controller is used in Xilinx Zynq SoC for interfacing the
NAND flash memory.
Reviewed-by: Helmut Grohne
Signed-off-by: Naga Sureshkumar Relli
---
xilinx zynq TRM link:
https://www.xilinx.com/support/documentation/user_guides
Add check before assigning chip->ecc.read_page() and chip->ecc.write_page()
Signed-off-by: Naga Sureshkumar Relli
---
drivers/mtd/nand/raw/nand_micron.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_micron.c
b/drivers/mtd/na
Hi Helmut,
> -Original Message-
> From: Helmut Grohne
> Sent: Friday, June 21, 2019 2:12 PM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; marek.va...@gmail.com; vigne...@
On Mon, Jan 28, 2019 at 10:27:39AM +0100, Miquel Raynal wrote:
Hi Miquel,
> Hi Naga,
>
> Naga Sureshkumar Relli wrote on Mon, 28 Jan 2019
> 06:04:53 +:
>
> > Hi Boris & Miquel,
> >
> > Could you please provide your thoughts on this driver to support HW
Add driver for arm pl353 static memory controller nand interface with
HW ECC support. This controller is used in Xilinx Zynq SoC for
interfacing the NAND flash memory.
Signed-off-by: Naga Sureshkumar Relli
---
xilinx zynq TRM link:
https://www.xilinx.com/support/documentation/user_guides/ug585
Hi,
Please ignore this patch.
Thanks,
Naga Sureshkumar Relli
> -Original Message-
> From: Naga Sureshkumar Relli
> Sent: Monday, June 17, 2019 1:21 PM
> To: miquel.ray...@bootlin.com; helmut.gro...@intenta.de
> Cc: rich...@nod.at; dw...@infradead.org; computersfor
Add driver for arm pl353 static memory controller nand interface with
HW ECC support. This controller is used in Xilinx Zynq SoC for
interfacing the NAND flash memory.
Signed-off-by: Naga Sureshkumar Relli
---
xilinx zynq TRM link:
https://www.xilinx.com/support/documentation/user_guides/ug585
Hi Helmut,
> -Original Message-
> From: Helmut Grohne
> Sent: Monday, April 29, 2019 5:48 PM
> To: Naga Sureshkumar Relli
> Cc: bbrezil...@kernel.org; miquel.ray...@bootlin.com; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gmail.
Hi Miquel,
> -Original Message-
> From: Miquel Raynal
> Sent: Monday, April 29, 2019 5:54 PM
> To: Naga Sureshkumar Relli
> Cc: Helmut Grohne ; bbrezil...@kernel.org;
> rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gma
Hi Helmut,
> -Original Message-
> From: Helmut Grohne
> Sent: Monday, April 29, 2019 5:48 PM
> To: Naga Sureshkumar Relli
> Cc: bbrezil...@kernel.org; miquel.ray...@bootlin.com; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gmail.
Hi Helmut,
> -Original Message-
> From: Helmut Grohne
> Sent: Thursday, April 25, 2019 4:54 PM
> To: Naga Sureshkumar Relli
> Cc: bbrezil...@kernel.org; miquel.ray...@bootlin.com; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gmail.
Hi Helmut,
> -Original Message-
> From: Helmut Grohne
> Sent: Tuesday, April 23, 2019 6:15 PM
> To: Naga Sureshkumar Relli
> Cc: bbrezil...@kernel.org; miquel.ray...@bootlin.com; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gmail.
Alpha and some of the architectures are missing readsl/writesl functions.
so the zynq-qspi driver won't be able to build on these arches. hence use
ioread32_rep()/iowrite32_rep() instead of readsl()/writesl().
Signed-off-by: Naga Sureshkumar Relli
Reported-by: kbuild test robot
---
Verifie
Add driver for arm pl353 static memory controller nand interface with
HW ECC support. This controller is used in Xilinx Zynq SoC for
interfacing the NAND flash memory.
Signed-off-by: Naga Sureshkumar Relli
---
xilinx zynq TRM link:
https://www.xilinx.com/support/documentation/user_guides/ug585
Hi,
> -Original Message-
> From: linux-spi-ow...@vger.kernel.org On
> Behalf Of
> Mark Brown
> Sent: Wednesday, April 10, 2019 5:55 PM
> To: YueHaibing
> Cc: Naga Sureshkumar Relli ; vigne...@ti.com; linux-
> ker...@vger.kernel.org; linux-...@vger.
t for Zynq QSPI controller")
Signed-off-by: YueHaibing
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v3
- Updated the Author name
- Removed extra line between Fixes and rest of the tags
Changes in v2
- Added static inline to the function spi_mem_default_supports_op();
---
include/lin
Hi Mark,
> -Original Message-
> From: Mark Brown
> Sent: Wednesday, April 10, 2019 4:01 PM
> To: Naga Sureshkumar Relli
> Cc: yuehaib...@huawei.com; vigne...@ti.com; linux-kernel@vger.kernel.org;
> linux-
> s...@vger.kernel.org; Michal Simek ;
> nagasures...
Hi Randy,
I have sent the patch on top of the patch sent by yuehaib...@huawei.com.
Thanks,
Naga Sureshkumar Relli
> -Original Message-
> From: Randy Dunlap
> Sent: Tuesday, April 9, 2019 8:52 PM
> To: Stephen Rothwell ; Linux Next Mailing List n...@vger.kernel.org>
>
oller")
Signed-off-by: YueHaibing
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v2
- Added static inline to the function spi_mem_default_supports_op();
---
include/linux/spi/spi-mem.h | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/include/linux/spi/spi-m
Hi Vignesh,
> -Original Message-
> From: linux-spi-ow...@vger.kernel.org On
> Behalf Of
> Naga Sureshkumar Relli
> Sent: Wednesday, April 10, 2019 10:53 AM
> To: YueHaibing ; Vignesh Raghavendra ;
> broo...@kernel.org
> Cc: linux-kernel@vger.kernel.org; l
Hi Vignesh,
> -Original Message-
> From: linux-spi-ow...@vger.kernel.org On
> Behalf Of
> YueHaibing
> Sent: Wednesday, April 10, 2019 9:03 AM
> To: Vignesh Raghavendra ; broo...@kernel.org; Naga
> Sureshkumar Relli
>
> Cc: linux-kernel@vger.kernel.org
Hi Vignesh,
Thanks for the review.
> -Original Message-
> From: Vignesh Raghavendra
> Sent: Friday, April 5, 2019 10:14 AM
> To: Naga Sureshkumar Relli ; broo...@kernel.org;
> bbrezil...@kernel.org
> Cc: linux-...@vger.kernel.org; dw...@infradead.org; marek.va...
-off-by: Naga Sureshkumar Relli
---
Changes in v2
- Export spi_mem_default_supports_op(), so that controller drivers
can use it
- Removed the code, which modifies calling spi_mem_default_supports_op()
before calling ctrl->supports_op()
Changes in v1
- None
---
drivers/spi/spi-me
Add support for QSPI controller driver used by Xilinx Zynq SOC.
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v2
- Updated the driver to call spi_mem_default_supports_op() from
ctrl->supports_op()
Changes in v1
- Added COMPILE_TEST macro
- converted MASKs to GENMASK() and
This patch adds the dts binding document for Zynq SOC QSPI controller.
Reviewed-by: Rob Herring
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v2
- None
---
.../devicetree/bindings/spi/spi-zynq-qspi.txt | 25 ++
1 file changed, 25 insertions(+)
create mode
n We are currently not targetting for
dual stacked/dual parallel handling. There are changes needed in the
framework to handle this. so this update is only for the Single mode.
Naga Sureshkumar Relli (3):
dt-bindings: spi: Add device tree binding documentation for Zynq QSPI
controller
spi: spi
Hi Vignesh,
> -Original Message-
> From: linux-spi-ow...@vger.kernel.org On
> Behalf Of
> Vignesh Raghavendra
> Sent: Friday, March 29, 2019 4:32 PM
> To: Boris Brezillon ; Naga Sureshkumar Relli
>
> Cc: broo...@kernel.org; bbrezil...@kernel.org; linux-.
Hi Helmut,
> -Original Message-
> From: Helmut Grohne
> Sent: Thursday, March 28, 2019 5:21 PM
> To: Naga Sureshkumar Relli
> Cc: bbrezil...@kernel.org; miquel.ray...@bootlin.com; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gmail.
Call spi_mem_default_supports_op() first, before calling controller
specific ctlr->supports_op().
With this, controller drivers can drop checking the buswidths again.
Suggested-by: Vignesh Raghavendra
Signed-off-by: Naga Sureshkumar Relli
---
Details can be found at https://lkml.org/lkml/201
Add support for QSPI controller driver used by Xilinx Zynq SOC.
Signed-off-by: Naga Sureshkumar Relli
---
Changes
- Added COMPILE_TEST macro
- converted MASKs to GENMASK() and BIT() macros
- Renamed MODEBITS to ZYNQ_QSPI_MODEBITS
- Removed checking buswidth() code, as it is already handled
This patch adds the dts binding document for Zynq SOC QSPI controller.
Reviewed-by: Rob Herring
Signed-off-by: Naga Sureshkumar Relli
---
.../devicetree/bindings/spi/spi-zynq-qspi.txt | 25 ++
1 file changed, 25 insertions(+)
create mode 100644 Documentation
n We are currently not targetting for
dual stacked/dual parallel handling. There are changes needed in the
framework to handle this. so this update is only for the Single mode.
This is tested with spi-v5.0 tag
Naga Sureshkumar Relli (3):
dt-bindings: spi: Add device tree binding documentation for
Hi Helmut,
> -Original Message-
> From: Helmut Grohne
> Sent: Tuesday, March 26, 2019 6:57 PM
> To: Naga Sureshkumar Relli
> Cc: bbrezil...@kernel.org; miquel.ray...@bootlin.com; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gmail.
Hi Vignesh,
Thanks for the review.
> -Original Message-
> From: linux-spi-ow...@vger.kernel.org On
> Behalf Of
> Vignesh Raghavendra
> Sent: Wednesday, March 20, 2019 10:42 PM
> To: Naga Sureshkumar Relli ; broo...@kernel.org;
> bbrezil...@kernel.org
> Cc: linux
Hi Paul,
Thank you very much for your testing.
> -Original Message-
> From: Paul Kocialkowski
> Sent: Wednesday, March 13, 2019 2:22 PM
> To: Naga Sureshkumar Relli ; broo...@kernel.org;
> bbrezil...@kernel.org
> Cc: rich...@nod.at; linux-kernel@vger
Hi Miquel,
Thanks for the review.
I will update the driver to remove legacy hooks.
Apart from that, Do you have any other comments on this driver?
If any, I will fix those.
Thanks,
Naga Sureshkumar Relli
> -Original Message-
> From: Naga Sureshkumar Relli
> Sent: Monday, Marc
Hi Vignesh,
> -Original Message-
> From: linux-spi-ow...@vger.kernel.org On
> Behalf Of
> Vignesh Raghavendra
> Sent: Friday, March 8, 2019 10:20 AM
> To: Naga Sureshkumar Relli ; broo...@kernel.org;
> bbrezil...@kernel.org
> Cc: linux-...@vger.kernel.org; dw...
Hi Miquel,
> -Original Message-
> From: Miquel Raynal
> Sent: Monday, March 4, 2019 3:13 PM
> To: Naga Sureshkumar Relli
> Cc: bbrezil...@kernel.org; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; marek.va...@gmail.com;
> linux-...@lists.infrad
Hi Vignesh,
Thanks for the review.
> -Original Message-
> From: Vignesh Raghavendra
> Sent: Friday, March 1, 2019 3:42 PM
> To: Naga Sureshkumar Relli ; broo...@kernel.org;
> bbrezil...@kernel.org
> Cc: linux-...@vger.kernel.org; dw...@infradead.org; marek.va...
Add support for QSPI controller driver used by Xilinx Zynq SOC.
Signed-off-by: Naga Sureshkumar Relli
---
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile| 1 +
drivers/spi/spi-zynq-qspi.c | 780
3 files changed, 789 insertions
n We are currently not targetting for
dual stacked/dual parallel handling. looks like there are changes
needed in the framework to handle this. so this RFC is only for the
Single mode.
This is tested with current master branch of Linux.
Naga Sureshkumar Relli (2):
dt-bindings: spi: Add device
This patch adds the dts binding document for Zynq SOC QSPI
controller.
Signed-off-by: Naga Sureshkumar Relli
---
.../devicetree/bindings/spi/spi-zynq-qspi.txt | 25 ++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq
Add driver for arm pl353 static memory controller nand interface with
HW ECC support. This controller is used in Xilinx Zynq SoC for
interfacing the NAND flash memory.
Signed-off-by: Naga Sureshkumar Relli
---
xilinx zynq TRM link:
https://www.xilinx.com/support/documentation/user_guides/ug585
Hi Miquel,
> -Original Message-
> From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> Sent: Monday, January 28, 2019 2:58 PM
> To: Naga Sureshkumar Relli
> Cc: r...@kernel.org; marek.va...@gmail.com; rich...@nod.at;
> martin.lund@keep-it-
> simple.com; linux-k
Hi Boris & Miquel,
Could you please provide your thoughts on this driver to support HW-ECC?
As I said previously, there is no way to detect errors beyond N bit.
I am ok to update the driver based on your inputs.
Thanks,
Naga Sureshkumar Relli
> -Original Message-
> From:
Hi Romain,
> -Original Message-
> From: Romain Perier [mailto:romain.per...@gmail.com]
> Sent: Monday, January 7, 2019 3:56 PM
> To: Naga Sureshkumar Relli
> Cc: Miquel Raynal ; Boris Brezillon
> ; linux-...@lists.infradead.org;
> peterpand...@micron.com;
> linu
Hi,
> -Original Message-
> From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> Sent: Wednesday, January 2, 2019 2:04 PM
> To: Romain Perier
> Cc: Naga Sureshkumar Relli ; Boris Brezillon
> ; linux-...@lists.infradead.org;
> peterpand...@micron.com;
> linu
Hi Miquel,
> -Original Message-
> From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> Sent: Wednesday, December 19, 2018 7:57 PM
> To: Naga Sureshkumar Relli
> Cc: Boris Brezillon ; r...@kernel.org;
> rich...@nod.at;
> linux-kernel@vger.kernel.org; marek.va..
Hi Miquel,
> -Original Message-
> From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> Sent: Monday, December 17, 2018 10:11 PM
> To: Naga Sureshkumar Relli
> Cc: Boris Brezillon ; r...@kernel.org;
> rich...@nod.at; linux-
> ker...@vger.kernel.org; marek.v
Hi Miquel,
> -Original Message-
> From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> Sent: Wednesday, December 12, 2018 6:48 PM
> To: Naga Sureshkumar Relli
> Cc: Boris Brezillon ; r...@kernel.org;
> rich...@nod.at; linux-
> ker...@vger.kernel.org; marek.v
Hi Miquel,
> -Original Message-
> From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> Sent: Wednesday, December 12, 2018 2:40 PM
> To: Naga Sureshkumar Relli
> Cc: Boris Brezillon ; r...@kernel.org;
> rich...@nod.at; linux-
> ker...@vger.kernel.org; marek.v
Hi Miquel,
> -Original Message-
> From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> Sent: Wednesday, December 12, 2018 1:42 PM
> To: Naga Sureshkumar Relli
> Cc: Boris Brezillon ; r...@kernel.org;
> rich...@nod.at; linux-
> ker...@vger.kernel.org; marek.v
will
Use nand_chech_erased_ecc_chunk() to see the bitflips.
If it is ok, I will update the driver and will send new patch, but do you have
any other comments on v12?
Thanks,
Naga Sureshkumar Relli
> -Original Message-
> From: linux-mtd [mailto:linux-mtd-boun...@lists.infradead.org] On Be
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Naga Sureshkumar Relli
Reviewed-by: Linus Walleij
---
Changes in v13:
- Added change log
Changes in v12:
- None
Changes in v11:
- Changed the subject to dt-bindings
- Restuctured dt binings to represent
Add driver for arm pl353 static memory controller. This controller is used in
Xilinx Zynq SoC for interfacing the NAND and NOR/SRAM memory devices.
Signed-off-by: Naga Sureshkumar Relli
Reviewed-by: Linus Walleij
---
Changes in v13:
- Fixed sparse warnings
- Fixed check-patch --strict
series make use of ->exec_op().
Naga Sureshkumar Relli (2):
dt-bindings: memory: Add pl353 smc controller devicetree binding
information
memory: pl353: Add driver for arm pl353 static memory controller
.../bindings/memory-controllers/pl353-smc.txt | 47 +++
drivers/memory/Kcon
Hi Michal,
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Wednesday, December 5, 2018 8:13 PM
> To: Naga Sureshkumar Relli ; mma...@broadcom.com;
> f.faine...@gmail.com; la...@linux-mips.org; tred...@nvidia.com;
> dig...@gmail.com; d
Hi Michal,
Ok, will update and will send new patch.
Thanks,
Naga Sureshkumar Relli
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Wednesday, December 5, 2018 8:17 PM
> To: Naga Sureshkumar Relli ; mma...@broadcom.com;
> f.faine..
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Tuesday, November 20, 2018 9:55 PM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; mar
Add driver for arm pl353 static memory controller. This controller is used in
Xilinx Zynq SoC for interfacing the NAND and NOR/SRAM memory devices.
Signed-off-by: Naga Sureshkumar Relli
Reviewed-by: Linus Walleij
---
drivers/memory/Kconfig | 9 +
drivers/memory/Makefile| 1
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Naga Sureshkumar Relli
Reviewed-by: Linus Walleij
---
.../bindings/memory-controllers/pl353-smc.txt | 47 ++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree
Hi Boris & Miquel,
> -Original Message-
> From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> Sent: Tuesday, November 20, 2018 6:06 PM
> To: Boris Brezillon
> Cc: Naga Sureshkumar Relli ; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com;
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, November 19, 2018 1:33 PM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; mar
H Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, November 19, 2018 1:13 AM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; mar
Hi,
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Friday, November 16, 2018 6:04 PM
> To: Martin Lund ; Naga Sureshkumar Relli
>
> Cc: boris.brezil...@bootlin.com; miquel.ray...@bootlin.com; rich...@nod.at;
> David
>
else {
> + mtd->ecc_stats.corrected += stat;
> + max_bitflips = max_t(unsigned int, max_bitflips,
> + stat);
> + }
> + }
> + }
> +
> + return max_bitflips;
> +}
> +
> +
Thanks,
Naga Sureshkumar Relli.
Hi Boris & Martin,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, November 12, 2018 4:28 PM
> To: Martin Lund
> Cc: Naga Sureshkumar Relli ; miquel.ray...@bootlin.com;
> rich...@nod.at; dw...@infradead.org; compu
Hi Miquel,
> -Original Message-
> From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> Sent: Friday, November 9, 2018 6:24 PM
> To: Naga Sureshkumar Relli
> Cc: Boris Brezillon ; rich...@nod.at;
> dw...@infradead.org;
> computersforpe...@gmail.com; marek.va
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Friday, November 9, 2018 1:38 PM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; mar
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Friday, November 9, 2018 11:59 AM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; mar
Add the basic driver for Arasan NAND Flash Controller used in
Zynq UltraScale+ MPSoC. It supports HW ECC and upto 24bit correction
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v12:
- Rebased on top of 4.20
- As suggested by Boris, instead of checking the command using nfc_op.cmds
This patch adds the dts binding document for arasan nand flash controller
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v12:
- Removed interrupt-parent description as it is implied as suggested by
Rob Herring
- Added missing ';' as required
Changes in v11:
- Updated
, it also adds a new varaible called mode in struct
nand_sdr_timings,
which will give directly the sdr operating mode. and it is useful for some
controllers,
where we can set direclty the operating mode instead of timings.
Naga Sureshkumar Relli (3):
dt-bindings: mtd: arasan: Add device tree
Some NAND controllers need SDR timing mode value, instead of timings.
i.e the NAND controller will change its operating mode by
just configuring the sdr timing mode number. So add a mode field to
struct nand_sdr_timings
Signed-off-by: Naga Sureshkumar Relli
Reviewed-by: Boris Brezillon
Hi Miquel,
> -Original Message-
> From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> Sent: Monday, October 29, 2018 3:21 PM
> To: Naga Sureshkumar Relli
> Cc: boris.brezil...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; mar
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Thursday, October 4, 2018 1:17 AM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; mar
Hi Boris,
Sorry for the late reply.
I am busy with some other work.
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Thursday, October 4, 2018 1:09 AM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; ric
Hi Rob,
Thanks for the review.
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Wednesday, September 26, 2018 6:48 PM
> To: Naga Sureshkumar Relli
> Cc: boris.brezil...@bootlin.com; miquel.ray...@bootlin.com; rich...@nod.at;
> dw...@infradead.o
Add the basic driver for Arasan NAND Flash Controller used in
Zynq UltraScale+ MPSoC. It supports HW ECC and upto 24bit correction
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v11:
Fixed the below commits given by Boris
- implemented separate hooks for each pattern
- Changed
Some NAND controllers needs sdr timing mode value, instead of
timings parameters. i.e the NAND controller will change its operating
mode by just configuring the sdr timing mode number. so add mode parameter
in struct nand_sdr_timings.
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v11
This patch adds the dts binding document for arasan nand flash controller
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v11:
- Updated compatible description as suggested by Boris
- Removed arasan-has-dma property
Changes in v10:
- None
Changes in v9:
- None
Changes in v8:
- Updated
, it also adds a new varaible called mode in
struct nand_sdr_timings, which will give directly the sdr operating
mode. and it is useful for some controllers, where we can configure
direclty the operating mode instead of timings.
Naga Sureshkumar Relli (3):
dt-bindings: mtd: arasan: Add device
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