Smatch reports this issue
security.c:416:6: warning: symbol '__nvdimm_security_overwrite_query' was not
declared. Should it be static?
__nvdimm_security_overwrite_query is only used in security.c so change
its storage-class specifier to static
Signed-off-by: Tom Rix
---
driv
On 4/20/21 10:27 AM, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
Gracefully ignore misconfigured port entries encountered in
incorrect FPGA images.
Signed-off-by: Matthew Gerlach
---
drivers/fpga/dfl-pci.c | 16 +++-
1 file changed, 15 insertions(+), 1 deleti
On 4/14/21 4:58 AM, w...@ise.pw.edu.pl wrote:
Hi,
I'm working both on DMA engines implementations in FPGA and their
Linux drivers.
Now I need to create an engine that takes the hugepages-backed buffer
allocated
by the user-space application and passes it to the device.
My current solution:
h
On 4/12/21 12:53 PM, Russ Weight wrote:
Add macros and definitions required by the MAX10 BMC
Secure Update driver.
Signed-off-by: Russ Weight
Acked-by: Lee Jones
---
v9:
- Rebased on next-20210412
v8:
- Previously patch 1/6 in "Intel MAX10 BMC Secure Update Driver"
- Rebased on next
On 4/9/21 11:50 AM, Max Zhen wrote:
Hi Tom,
On 3/31/21 6:03 AM, Tom Rix wrote:
On 3/23/21 10:29 PM, Lizhi Hou wrote:
The PCIE device driver which attaches to management function on Alveo
devices. It instantiates one or more group drivers which, in turn,
instantiate platform drivers. The
Acked-by: Lee Jones
lgtm
Reviewed-by: Tom Rix
---
v2: change variable name from m10bmc_bmc_subdevs to m10bmc_d5005_subdevs
added Acked-by: Lee Jones
---
drivers/hwmon/intel-m10-bmc-hwmon.c | 122
drivers/mfd/intel-m10-bmc.c | 10 +++
2
On 4/13/21 3:58 PM, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
This patch adds a Device Feature List (DFL) bus driver for the
Altera SPI Master controller. The SPI master is connected to an
Intel SPI Slave to Avalon Master Bridge inside an Intel MAX10
BMC Chip.
Signed-off-
On 4/12/21 8:51 PM, Jiapeng Chong wrote:
Fix the following gcc warning:
drivers/fpga/xilinx-pr-decoupler.c:32:19: warning: unused function
'xlnx_pr_decouple_read' [-Wunused-function].
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/fpga/xilinx-pr-decoupler.c | 6 --
On 3/23/21 10:29 PM, Lizhi Hou wrote:
Update fpga Kconfig/Makefile and add Kconfig/Makefile for new drivers.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
MAINTAINERS| 11 +++
drivers/Makefile | 1 +
d
res || !strncmp(res->name, gate->ep_name, strlen(res->name) + 1)) {
+ xleaf_put_leaf(pdev, leaf);
+ return;
+ }
+
+ /* higher level axigate instance created, make sure the gate is opened.
*/
ok
only minor ws issue, otherwise good to go
Reviewed-by:
}
+
+ if (status & BIT(0))
+ break;
+ msleep(XRT_CALIB_READ_INTERVAL);
ok
Reviewed-by: Tom Rix
+ times--;
+ }
+
+ if (!times) {
+ xrt_err(calib->pdev,
+ "MIG calibration ti
goto failed;
+ }
+
+ CLKFREQ_INFO(clkfreq, "successfully initialized clkfreq subdev");
+
+ return 0;
+
+failed:
+ return ret;
+}
+
+static struct xrt_subdev_endpoints xrt_clkfreq_endpoints[] = {
+ {
+ .xse_names = (struct xrt_subdev_ep_names[]) {
me, NULL, XRT_MD_PROP_CLK_FREQ,
+ (const void **)&freq, NULL);
+ if (err) {
+ xrt_info(clock->pdev, "no default freq");
+ return 0;
+ }
+
+ err = set_freq(clock, be16_to_cpu(*freq));
+
+ return err;
+}
+
+s
p_bulk_read(devctl->regmap[rw_arg->xdr_id],
rw_arg->xdr_offset,
+ rw_arg->xdr_buf,
+ rw_arg->xdr_len /
devctl_regmap_config.reg_stride);
+ break;
+ }
ok, *_WRITE removed.
Thanks for
failed:
+ mutex_unlock(&icap->icap_lock);
+
+ return err;
+}
+
+/*
+ * Discover the FPGA IDCODE using special sequence of canned commands
+ */
+static int icap_probe_chip(struct icap *icap)
+{
+ int err;
+ u32 val = 0;
ok, thanks for demagic-ing this function.
Lo
Please add to this patch cover letter what you want to discuss.
Got this new feature, not sure about ...
Tom
On 4/2/21 2:09 AM, Nava kishore Manne wrote:
> Nava kishore Manne (3):
> fpga: region: Add fpga-region property 'fpga-config-from-dmabuf'
> fpga: support loading from a pre-allocated
XRT_SUBDEV_CLOCK, instance);
> + if (!leaf) {
> + xrt_err(pdev, "does not get clock subdev");
> + return;
> + }
> +
> + xleaf_call(leaf, XRT_CLOCK_VERIFY, NULL);
> + xleaf_put_leaf(pdev, leaf);
> +}
ok on removing ucs_
local use of 'regmap' conflicts with global meaning.
reword local regmap to something else.
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> Add VSEC driver. VSEC is a hardware function discovered by walking
> PCI Express configure space. A platform device node will be created
> for it. VSEC provides boar
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> platform driver that handles IOCTLs, such as hot reset and xclbin download.
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max Zhen
> Signed-off-by: Lizhi Hou
> ---
> drivers/fpga/xrt/include/xmgmt-main.h | 34 ++
> drivers/fpga/xrt/mgmt/main.c
small alloc's should use kzalloc.
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> fpga-mgr and region implementation for xclbin download which will be
> called from main platform driver
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max Zhen
> Signed-off-by: Lizhi Hou
> ---
> drivers/fpga/xrt/mgmt/f
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> The PCIE device driver which attaches to management function on Alveo
> devices. It instantiates one or more group drivers which, in turn,
> instantiate platform drivers. The instantiation of group and platform
> drivers is completely dtb driven.
>
> Signed
Several just for debugging items, consider adding a CONFIG_XRT_DEBUGGING
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> Infrastructure code providing APIs for managing leaf driver instance
> groups, facilitating inter-leaf driver calls and root calls.
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max
This was split from 'fpga: xrt: platform driver infrastructure'
and fpga: xrt: managment physical function driver (root)
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> Contains common code for all root drivers and handles root calls from
> platform drivers. This is part of root driver infrastructure.
>
It is unclear from the changelog if this new patch was split from an existing
patch or new content.
the file ops seem to come from mgmnt/main.c, which call what could be file ops
here. why is this complicated redirection needed ?
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> Helper functions for cha
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> group driver that manages life cycle of a bunch of leaf driver instances
> and bridges them with root.
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max Zhen
> Signed-off-by: Lizhi Hou
> ---
> drivers/fpga/xrt/include/group.h | 25 +++
> drivers/fpg
bisectablity may be/is an issue.
Moritz,
building happens on the last patch, so in theory there will never be a build
break needing bisection. Do we care about the misordering of serveral of these
patches?
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> xrt-lib kernel module infrastructure code to r
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> Alveo FPGA firmware and partial reconfigure file are in xclbin format. This
> code enumerates and extracts sections from xclbin files. xclbin.h is cross
> platform and used across all platforms and OS.
ok
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Ma
On 3/27/21 11:09 AM, Moritz Fischer wrote:
> Hi Richard, Russ,
>
> On Thu, Feb 25, 2021 at 01:07:14PM +, Gong, Richard wrote:
>> Hi Moritz,
>>
>> Sorry for asking.
>>
>> When you have chance, can you help review the version 5 patchset submitted
>> on 02/09/21?
>>
>> Regards,
>> Richard
>>
>>
Do not reorder function definitions, this makes comparing changes from the
previous patchset difficult.
A general issue with returning consistent error codes. There are several cases
where fdt_* code are not translated.
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> XRT drivers use device tree as met
general problem with xmgmt needing to be changed to xrt-mgmt
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> Describe XRT driver architecture and provide basic overview of
> Xilinx Alveo platform.
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max Zhen
> Signed-off-by: Lizhi Hou
> ---
> Documentati
On 3/23/21 6:16 AM, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> gcc-11 with KASAN on 32-bit arm produces a warning about a function
> that needs a lot of stack space:
>
> drivers/net/wireless/cisco/airo.c: In function 'setup_card.constprop':
> drivers/net/wireless/cisco/airo.c:3960:1: error:
tk format specifier")
This was for a different reason.
imo, you do not need to include what another patch did.
so you could also just remove this bit from the commit log.
The change itself looks good.
Reviewed-by: Tom Rix
>
> Fixes: 0b437e64e0af ("drm/amdgpu: remove h fr
-git a/MAINTAINERS b/MAINTAINERS
>> index aa84121c5611..1f68e9ff76de 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -9193,7 +9193,8 @@ F: tools/power/x86/intel-speed-select/
>> INTEL STRATIX10 FIRMWARE DRIVERS
>> M: Richard Gong
>> -
0 FIRMWARE DRIVERS
M: Richard Gong
-L: linux-kernel@vger.kernel.org
+R: Tom Rix
+L: linux-f...@vger.kernel.org
S: Maintained
F: Documentation/ABI/testing/sysfs-devices-platform-stratix10-rsu
F: Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
I also added mysel
On 3/16/21 4:54 PM, Lizhi Hou wrote:
>
>
> On 03/04/2021 05:39 AM, Tom Rix wrote:
>> CAUTION: This message has originated from an External Source. Please use
>> proper judgment and caution when opening attachments, clicking links, or
>> responding to this email.
&
On 3/16/21 2:23 PM, Lizhi Hou wrote:
> Hi Tom,
>
>
> On 02/26/2021 09:22 AM, Tom Rix wrote:
>> On 2/17/21 10:40 PM, Lizhi Hou wrote:
>>> platform driver that handles IOCTLs, such as hot reset and xclbin download.
>>>
>>> Signed-off-by: Sonal Santan
&
On 3/16/21 1:29 PM, Max Zhen wrote:
> Hi Tom,
>
>
> On 2/26/21 7:01 AM, Tom Rix wrote:
>> CAUTION: This message has originated from an External Source. Please use
>> proper judgment and caution when opening attachments, clicking links, or
>> responding to this e
On 3/12/21 11:36 AM, Russ Weight wrote:
> Extend the MAX10 BMC Secure Update driver to provide sysfs
> files to expose the canceled code signing key (CSK) bit
> vectors. These use the standard bitmap list format
> (e.g. 1,2-6,9).
>
> Signed-off-by: Russ Weight
>
> create mode 100644
> Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-secure
> create mode 100644 drivers/fpga/intel-m10-bmc-secure.c
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-secure
> b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-secure
>
On 3/11/21 7:25 AM, Krzysztof Kozlowski wrote:
> Hi,
>
> All three Intel arm64 SoCFPGA architectures (Agilex, N5X and Stratix 10)
> are basically flavors/platforms of the same architecture. At least from
> the Linux point of view. Up to a point that N5X and Agilex share DTSI.
> Having three top
On 3/9/21 6:51 PM, Moritz Fischer wrote:
> Hi Tom,
> On Tue, Mar 09, 2021 at 08:03:09AM -0800, Tom Rix wrote:
>> Moritz,
>>
>> This and the next patchset apply to today's char-misc-next.
>>
>> However they conflicts with other in flight linux-fpga patchse
On 3/10/21 1:45 AM, Lee Jones wrote:
> On Wed, 10 Mar 2021, Krzysztof Kozlowski wrote:
>
>> Prepare for merging Stratix 10, Agilex and N5X into one arm64
>> architecture by first renaming the ARCH_STRATIX10 into ARCH_SOCFPGA64.
>>
>> The existing ARCH_SOCFPGA (in ARMv7) Kconfig symbol cannot be u
Moritz,
This and the next patchset apply to today's char-misc-next.
However they conflicts with other in flight linux-fpga patchsets.
Since I believe these patchsets came first, I think they should have preference.
This feature of updating is needed for the basic operation of the fpga.
Tom
On
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> Add partition isolation platform driver. partition isolation is
> a hardware function discovered by walking firmware metadata.
> A platform device node will be created for it. Partition isolation
> function isolate the different fpga regions
>
> Signed-off-
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> Add DDR calibration driver. DDR calibration is a hardware function
> discovered by walking firmware metadata. A platform device node will
> be created for it. Hardware provides DDR calibration status through
> this function.
>
> Signed-off-by: Sonal Santan
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> Add clock frequence counter driver. Clock frequence counter is
> a hardware function discovered by walking xclbin metadata. A platform
> device node will be created for it. Other part of driver can read the
> actual clock frequence through clock frequence c
why are clock and clkfeq separated ?
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> Add clock driver. Clock is a hardware function discovered by walking
> xclbin metadata. A platform device node will be created for it. Other
> part of driver configures clock through clock driver.
>
> Signed-off-by: Sonal
shutdown manager node
> example node as suggested by Tom Rix.
>
> .../bindings/fpga/xilinx-pr-decoupler.txt | 24 ++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
>
using same driver for both IP's.
>
> Signed-off-by: Nava kishore Manne
> ---
> Changes for v2:
> -Fixed some minor coding issues as suggested by
> Tom Rix.
>
> drivers/fpga/Kconfig | 9 +++-
> drivers/fpga/xilinx-pr
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> Add devctl driver. devctl is a type of hardware function which only has
> few registers to read or write. They are discovered by walking firmware
> metadata. A platform device node will be created for them.
>
> Signed-off-by: Sonal Santan
> Signed-off-by:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> Add ICAP driver. ICAP is a hardware function discovered by walking
What does ICAP stand for ?
> firmware metadata. A platform device node will be created for it.
> FPGA bitstream is written to hardware through ICAP.
>
> Signed-off-by: Sonal Santan
> Signed
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> Add UCS driver. UCS is a hardware function discovered by walking xclbin
What does UCS stand for ? add to commit log
> metadata. A platform device node will be created for it.
> UCS enables/disables the dynamic region clocks.
>
> Signed-off-by: Sonal Santan
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> Add VSEC driver. VSEC is a hardware function discovered by walking
> PCI Express configure space. A platform device node will be created
> for it. VSEC provides board logic UUID and few offset of other hardware
> functions.
Is this vsec walking infra or is
On 2/26/21 1:23 PM, Lizhi Hou wrote:
> Hi Tom,
>
>
snip
>>
>> I also do not see a pragma pack, usually this is set of 1 so the compiler
>> does not shuffle elements, increase size etc.
> This data structure is shared with other tools. And the structure is well
> defined with reasonable alignme
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> fpga-mgr and region implementation for xclbin download which will be
> called from main platform driver
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max Zhen
> Signed-off-by: Lizhi Hou
> ---
> drivers/fpga/xrt/mgmt/fmgr-drv.c| 187 +++
>
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> platform driver that handles IOCTLs, such as hot reset and xclbin download.
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max Zhen
> Signed-off-by: Lizhi Hou
> ---
> drivers/fpga/xrt/include/xmgmt-main.h | 37 ++
> drivers/fpga/xrt/mgmt/main-impl.h
A question i do not know the answer to.
Seems like 'golden' is linked to a manufacturing (diagnostics?) image.
If the public will never see it, should handling it here be done ?
Moritz, do you know ?
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> The PCIE device driver which attaches to management fu
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> infrastructure code providing APIs for managing leaf driver instance
> groups, facilitating inter-leaf driver calls and root calls, managing leaf
> driver device nodes.
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max Zhen
> Signed-off-by: Lizhi Hou
The first patch is a fix that is targeted for stable.
Tom
On 2/25/21 5:07 AM, Gong, Richard wrote:
> Hi Moritz,
>
> Sorry for asking.
>
> When you have chance, can you help review the version 5 patchset submitted on
> 02/09/21?
>
> Regards,
> Richard
>
> -Original Message-
> From: richar
Richard,
I see this is for stable.
Your mainline patchset looks ok with me, has it been accepted yet for mainline ?
Reviewed-by: Tom Rix
On 2/23/21 6:15 AM, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Clean up COMMAND_RECONFIG_FLAG_PARTIAL flag by resetting it to
Yilun,
Is there anything outstanding or remaining to be done ?
Tom
On 2/3/21 5:59 PM, Xu Yilun wrote:
> This patchset supports some dfl device drivers written in userspace.
>
> In the patchset v1, the "driver_override" interface should be used to bind
> the DFL UIO driver to DFL devices. But the
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> group driver that manages life cycle of a bunch of leaf driver instances
> and bridges them with root.
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max Zhen
> Signed-off-by: Lizhi Hou
> ---
> drivers/fpga/xrt/include/group.h | 27
> drivers/fp
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> xrt-lib kernel module infrastructure code to register and manage all
> leaf driver modules.
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max Zhen
> Signed-off-by: Lizhi Hou
> ---
> drivers/fpga/xrt/lib/main.c | 274 ++
The following commit has been merged into the timers/urgent branch of tip:
Commit-ID: 7da390694afbaed8e0f05717a541dfaf1077ba51
Gitweb:
https://git.kernel.org/tip/7da390694afbaed8e0f05717a541dfaf1077ba51
Author:Tom Rix
AuthorDate:Mon, 18 Jan 2021 13:19:55 -08:00
Committer
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> Alveo FPGA firmware and partial reconfigure file are in xclbin format.
This code enumerates and extracts
> Add
> code to enumerate and extract sections from xclbin files. xclbin.h is cross
> platform and used across all platforms and OS
>
> Signed-off-by:
As I am looking through the files, I have this comment.
fpga/ is currently a single directory, while files could be organized in
subdirectories like
dfl/pci.c
instead have the possible subdir name as a prefix to the filename.
dfl-pci.c
For consistency,
xrt/metadata/metadata.c
should be
xrt
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> XRT drivers use device tree as metadata format to discover HW subsystems
> behind PCIe BAR. Thus libfdt functions are called for driver to parse
for the driver to parse the
> device tree blob.
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max Zhen
> Si
>From the documentation, there are a couple of big questions and a bunch of
>word smithing.
pseudo-bus : do we need a bus ?
xrt-lib real platform devices that aren't fpga, do they need to move to another
subsystem ?
Overall looks good, love the ascii art!
On 2/17/21 10:40 PM, Lizhi Hou wrote:
On 2/17/21 10:40 PM, Lizhi Hou wrote:
> Hello,
>
> This is V3 of patch series which adds management physical function driver for
> Xilinx
> Alveo PCIe accelerator cards,
> https://www.xilinx.com/products/boards-and-kits/alveo.html
> This driver is part of Xilinx Runtime (XRT) open source stack.
On 2/15/21 7:13 AM, Dinghao Liu wrote:
> When cmd == SNDRV_PCM_TRIGGER_STOP, we should also check
> the return value of skl_decoupled_trigger() just like what
> we have done in case SNDRV_PCM_TRIGGER_PAUSE_RELEASE.
>
> Signed-off-by: Dinghao Liu
> ---
> sound/soc/intel/skylake/skl-pcm.c | 3 +++
Russ, Moritz
This patchset still applies.
Updating the fpga is a fairly important feature.
Are there any dependencies we are waiting on ?
Tom
On 1/5/21 2:59 PM, Russ Weight wrote:
> The FPGA Security Manager class driver provides a common
> API for user-space tools to manage updates for secure
On 2/15/21 6:41 AM, Richard Gong wrote:
> Hi Tom,
>
> On 2/13/21 9:44 AM, Tom Rix wrote:
>>
>> On 2/9/21 2:20 PM, richard.g...@linux.intel.com wrote:
>>> From: Richard Gong
>>>
>>> Clean up COMMAND_RECONFIG_FLAG_PARTIAL flag by resetting it t
On 2/9/21 2:20 PM, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Clean up COMMAND_RECONFIG_FLAG_PARTIAL flag by resetting it to 0, which
> aligns with the firmware settings.
>
> Fixes: 36847f9e3e56 ("firmware: stratix10-svc: correct reconfig flag and
> timeout values")
> Signed-o
On 2/10/21 2:15 AM, Alexandru Ardelean wrote:
> From: Mircea Caprioru
>
> This patch adds support for vco maximum and minimum ranges in accordance
> with fpga speed grade, voltage, device package, technology and family. This
> new information is extracted from two new registers implemented in th
On 1/25/21 6:22 PM, Moritz Fischer wrote:
> On Mon, Jan 25, 2021 at 11:00:38AM -0800, Tom Rix wrote:
Snip
>>
>>> + depends on FPGA_DFL
>>> + help
>>> + Generic DFL (Device Feature List) driver for Userspace I/O devices.
>>> + It is useful
On 2/8/21 7:01 AM, Martin Hundebøll wrote:
> Update pci_ids.h with the vendor ID for Silicom Denmark. The define is
> going to be referenced in driver(s) for FPGA accelerated smart NICs.
>
> Signed-off-by: Martin Hundebøll
Reviewed-by: Tom Rix
> ---
>
> Changes since
On 2/3/21 3:06 PM, Russ Weight wrote:
>
> On 2/3/21 7:25 AM, Tom Rix wrote:
>> ..snip..
>>
>> On 2/2/21 3:06 PM, Russ Weight wrote:
>>> diff --git a/drivers/fpga/dfl-afu.h b/drivers/fpga/dfl-afu.h
>>> index 576e94960086..e5020e2b1f3d 100644
>>>
..snip..
On 2/2/21 3:06 PM, Russ Weight wrote:
> diff --git a/drivers/fpga/dfl-afu.h b/drivers/fpga/dfl-afu.h
> index 576e94960086..e5020e2b1f3d 100644
> --- a/drivers/fpga/dfl-afu.h
> +++ b/drivers/fpga/dfl-afu.h
> @@ -80,7 +80,7 @@ struct dfl_afu {
> };
>
> /* hold pdata->lock when call __af
ure List) driver for Userspace I/O devices.
> + It is useful to provide direct access to DFL devices from userspace.
> + A sample userspace application using this driver is available for
> + download in a git repository:
> +
> + git clone https://github.com/OPA
On 1/27/21 1:43 PM, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Clean up COMMAND_RECONFIG_FLAG_PARTIAL flag by resetting it to 0, which
> aligns with the firmware settings.
For fixes, you need to have a 'Fixes: ... ' line in the comment.
This lets folks doing the stable branch
.../devicetree/bindings/clock/adi,axi-clkgen.yaml | 1 +
> drivers/clk/Kconfig | 1 -
> drivers/clk/clk-axi-clkgen.c | 11 +++
> 3 files changed, 12 insertions(+), 1 deletion(-)
This whole set looks fine.
Reviewed-by: Tom Rix
> Signed-off-by: Xu Yilun
> ---
> drivers/mfd/intel-m10-bmc.c | 12 +---
> include/linux/mfd/intel-m10-bmc.h | 2 +-
> 2 files changed, 6 insertions(+), 8 deletions(-)
Thanks for adding M10BMC_LEGACY_BUILD_VER
Reviewed-by: Tom Rix
> diff --git a/drivers/mfd/in
100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -9132,6 +9132,15 @@ F: include/linux/mei_cl_bus.h
> F: include/uapi/linux/mei.h
> F: samples/mei/*
>
I am interested in reviewing these files like I do with
FPGA DFL DRIVERS
So can you add
R: Tom Rix
if you have
t;
> Signed-off-by: Matthew Gerlach
> Signed-off-by: Xu Yilun
> ---
> v2: no change.
v2: Use M10BMC_LEGACY_BUILD_VER
Looks good.
Reviewed-by: Tom Rix
> ---
> drivers/mfd/intel-m10-bmc.c | 13 +
> include/linux/mfd/intel-m10-bmc.h | 5 -
> 2 f
On 1/25/21 6:40 PM, Xu Yilun wrote:
> On Mon, Jan 25, 2021 at 06:22:55PM -0800, Moritz Fischer wrote:
>> On Mon, Jan 25, 2021 at 11:00:38AM -0800, Tom Rix wrote:
>>> On 1/25/21 12:49 AM, Xu Yilun wrote:
>>>> This patch supports the DFL drivers be written in users
On 1/25/21 12:49 AM, Xu Yilun wrote:
> This patch supports the DFL drivers be written in userspace. This is
> realized by exposing the userspace I/O device interfaces.
>
> The driver now only binds the ether group feature, which has no irq. So
> the irq support is not implemented yet.
>
> Signed-
On 1/25/21 12:56 PM, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Add COMMAND_AUTHENTICATE_BITSTREAM command flag for new added bitstream
> authentication feature. Authenticating a bitstream is to make sure a signed
> bitstream has the valid signatures.
>
> Except for the actual
t | 23 +++
> 1 file changed, 23 insertions(+)
This looks fine.
Reviewed-by: Tom Rix
On 1/23/21 8:24 PM, Moritz Fischer wrote:
> Tom,
>
> On Sun, Jan 17, 2021 at 08:18:15AM -0800, t...@redhat.com wrote:
>> From: Tom Rix
>>
>> Check that the ioctl DFL_FPGA_PORT_ERR_GET_IRQ_NUM returns
>> an expected result.
>>
>> Tested on vf devi
On 1/22/21 3:52 PM, Moritz Fischer wrote:
> On Fri, Jan 22, 2021 at 11:29:28AM -0800, t...@redhat.com wrote:
>> From: Tom Rix
>>
>> Every FPGA has several subdevices in other subsystems.
>> The new FPGA subdevices section is necessary to ensure changes to
>>
On 1/21/21 12:05 AM, Xu Yilun wrote:
> On Wed, Jan 20, 2021 at 07:32:53AM -0800, Tom Rix wrote:
>> On 1/19/21 6:34 PM, Xu Yilun wrote:
>>> From: Matthew Gerlach
>>>
>>> This patch adds access tables to the MAX 10 BMC regmap. This prevents
>>> the h
On 1/17/21 8:22 AM, Moritz Fischer wrote:
> Greg,
>
> On Sun, Jan 17, 2021 at 04:45:04PM +0100, Greg KH wrote:
>> On Wed, Jan 13, 2021 at 09:54:07AM +0800, Xu Yilun wrote:
>>> This patch supports the DFL drivers be written in userspace. This is
>>> realized by exposing the userspace I/O device in
#define M10BMC_SYS_BASE 0x300800
> -#define M10BMC_MEM_END 0x20fc
> +#define M10BMC_MEM_END 0x1fff
Reviewed-by: Tom Rix
>
> /* Register offset of system registers */
> #define NIOS2_FW_VERSION 0x0
On 1/19/21 6:34 PM, Xu Yilun wrote:
> From: Matthew Gerlach
>
> This patch adds access tables to the MAX 10 BMC regmap. This prevents
> the host from accessing the unwanted I/O space. It also filters out the
> invalid outputs when reading the regmap debugfs interface.
>
> Signed-off-by: Matthew
On 1/19/21 5:48 PM, Guoqing Chi wrote:
> On Tue, 19 Jan 2021 06:54:45 -0800
> Tom Rix wrote:
>
>> On 1/19/21 3:22 AM, Guoqing Chi wrote:
>>> From: chiguoqing
>>>
>>> Adding mutex_lock, when read and write reg need to use this lock to
>>
eturn -EINVAL;
> + err = -EINVAL;
> + goto exit;
> }
>
> master->num_chipselect = pdata->num_chipselect;
Reviewed-by: Tom Rix
On 1/5/21 3:08 PM, Russ Weight wrote:
...
> .../testing/sysfs-driver-intel-m10-bmc-secure | 61 ++
> MAINTAINERS | 2 +
> drivers/fpga/Kconfig | 11 +
> drivers/fpga/Makefile | 3 +
> drivers/fpga/intel-m1
On 1/19/21 3:22 AM, Guoqing Chi wrote:
> From: chiguoqing
>
> Adding mutex_lock, when read and write reg need to use this lock to
> avoid race.
>
> Signed-off-by: Guoqing Chi
> ---
> v2:Follow write function to fix read function.
> Adding mutex init in core probe function.
> Adding break in swi
On 1/18/21 7:15 AM, Daniel Lezcano wrote:
> On 18/01/2021 14:49, t...@redhat.com wrote:
>> From: Tom Rix
>>
>> When DEBUG is defined this error occurs
>>
>> drivers/clocksource/mxs_timer.c:138:1: error:
>> expected ‘;’ before ‘}’ token
>>
On 1/18/21 2:05 AM, chiguoqing wrote:
> Adding mutex_lock, when read and write reg need to use this lock to
> avoid race.
>
> Signed-off-by: Guoqing Chi
> ---
> drivers/iio/imu/bmi160/bmi160.h | 2 ++
> drivers/iio/imu/bmi160/bmi160_core.c | 17 +
> 2 files changed, 15 ins
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