Felix,
On Tue, Apr 12, 2011 at 6:54 AM, Felix Radensky wrote:
> On 04/12/2011 07:05 AM, Aggrwal Poonam-B10812 wrote:
>> As such there is no hardware fix related to this issue between RevC to
>> RevD. The solution was a software patch to resolve the issue related to
>> IRQ0.
>
> Are you sure ? Ple
Hello Prabhakar,
On Fri, Apr 8, 2011 at 10:31 AM, Kushwaha Prabhakar-B32579
wrote:
> Hi Leon,
>
>
>> -Original Message-
>> From: Leon Woestenberg [mailto:leon.woestenb...@gmail.com]
>> Sent: Friday, April 08, 2011 1:55 PM
>> To: Kushwaha Prabhakar-B32
Hello Prabhakar,
On Fri, Apr 8, 2011 at 5:44 AM, Kushwaha Prabhakar-B32579
wrote:
>> -Original Message-
>> From: linux-ide-ow...@vger.kernel.org [mailto:linux-ide-
>> ow...@vger.kernel.org] On Behalf Of Leon Woestenberg
>> Sent: Thursday, April 07, 2011 10:23 PM
&
Hello,
On Thu, Dec 17, 2009 at 9:28 PM, Felix Radensky wrote:
> Kumar Gala wrote:
>> On Dec 17, 2009, at 2:59 AM, Mahajan Vivek-B08308 wrote:
Thanks a lot. If I understand you correctly, the only way I can get
ath9k driver to work on this board using legacy interrupts is to wait for a
>
Hello Martyn,
thanks for a confirmation.
On Thu, Apr 7, 2011 at 10:27 AM, Martyn Welch wrote:
> On 06/04/11 18:00, Leon Woestenberg wrote:
>>
>> Does anyone know of a working setup of sata_sil24 on a big endian
>> powerpc system?
>
> Yes, I think we even use it on a
reference to Felix' thread?
"Problem with mini-PCI-E slot on P2020RDB"
Best regards,
Leon.
> --Prabhakar
>
>> -Original Message-
>> From: linux-ide-ow...@vger.kernel.org [mailto:linux-ide-
>> ow...@vger.kernel.org] On Behalf Of Leon Woestenberg
>> S
Hello Felix,
On Wed, Apr 6, 2011 at 10:49 PM, Felix Radensky wrote:
> I think there's a hardware problem with mini PCI-E slot
> on P2020RDB related to legacy IRQ routing. See this
> thread for details
> http://www.mail-archive.com/linuxppc-dev@lists.ozlabs.org/msg40037.html
>
Thanks for the heads
Hello Jeff, all,
On Wed, Apr 6, 2011 at 8:12 PM, Jeff Garzik wrote:
> On 04/06/2011 01:48 PM, Moffett, Kyle D wrote:
>> On Apr 06, 2011, at 13:00, Leon Woestenberg wrote:
>>> after investigating problems with sata_sil24.c on a freescale p2020
>>> soc, I wonder if this
Hello,
after investigating problems with sata_sil24.c on a freescale p2020
soc, I wonder if this driver works on powerpc at all?
Does anyone know of a working setup of sata_sil24 on a big endian
powerpc system?
Regards,
--
Leon
___
Linuxppc-dev mailin
Hello Prabhakar, Kumar,
(I missed the original post, due to temporarely being unsubscribed, I
am responding to Kumar's reply).
On Thu, Mar 31, 2011 at 10:22 AM, Kumar Gala wrote:
> On Mar 24, 2011, at 11:47 PM, Prabhakar Kushwaha wrote:
>
>> PCIe memory address space is 1:1 mapped with u-boot.
>
Hello,
first off, I like your idea. This is my public reply, I'll give a
personal reply later.
On Sat, Sep 26, 2009 at 1:38 PM, Konstantinos Margaritis
wrote:
> I'm considering funding the design & production of a new PowerPC system
> (well, the motherboard, the rest are typical pc stuff and a c
Hello Felix,
On Thu, Sep 17, 2009 at 6:17 AM, Felix Radensky wrote:
> On my custom MPC8536 based board running 2.6.31 kernel
> FPGA is connected via x2 PCI-E lane. FPGA is identified
> during PCI scan and is visible via lspci.
>
I committed a PCI Express device driver for an Altera FPGA (chainin
Hello,
On Mon, Sep 7, 2009 at 1:01 PM, Leon
Woestenberg wrote:
> on my MPC8536DS development board, a PCIe card does not get detected
> by Linux, u-boot does list it.
>
> I'm suspecting the PCIe bridge (?) to not initialize correctly, but
> that is a wild guess. See the u-boot
Hello,
On Wed, Aug 19, 2009 at 12:53 PM, Alan Cox wrote:
> On Wed, 19 Aug 2009 10:38:06 +0100
>
> in drivers because there is driver code that uses spin_is_locked() in
> fairly sensible fashion when dealing with locking.
>
One use is to measure lock contention hits on a particular spin lock.
How
Hello,
On Thu, Jun 18, 2009 at 4:04 PM, Kumar Gala wrote:
> On Jun 18, 2009, at 8:09 AM, Anton Vorontsov wrote:
>> On Thu, Jun 18, 2009 at 08:19:44AM +0200, Rini van Zetten wrote:
>>>
>>> This patch adds the possibility to have a spi device without a cs.
>>>
> That is a good question. What HW is
Hello,
On Wed, Jun 17, 2009 at 2:16 PM, Norbert van
Bolhuis wrote:
>>
>> I'll be testing the design tomorrow on the reference board, I'll
>> report results in this thread.
>
> Interesting.
> Looking forward to the results.
>
Design works as expected on the now slightly modified MPC8313E-RDB
board.
Hello Kumar, all,
On Mon, Jun 8, 2009 at 4:59 PM, Leon
Woestenberg wrote:
> using 2.6.30-rc6, I get the following problems when I read from a SSD
> disk, connected to the
> 3.0 Gb SATA controller of the MPC8315E SoC rev 1.0 running Linux 2.6.30-rc6.
>
Result on a first batch of bisect
Hello,
On Wed, Jun 17, 2009 at 12:09 PM, Leon
Woestenberg wrote:
> Quoting David Hawkins, who gave a very clear explanation:
> <...>
> If you have the Flash BUSY# signal, then this scheme works
> great, since using HRESET# low and BUSY# low to create a
> PORESET# source is
Hello all,
On Wed, Jun 17, 2009 at 10:35 AM, Norbert van
Bolhuis wrote:
> Hi Leon,
>
> I doubt if there are working designs for this.
> ...
> In u-boot the watchdog (if enabled with CONFIG_WATCHDOG) is normally
> strobed in the decrementer interrupt routine (timer_interrupt). So
> I guess there's
Hello Benjamin,
On Wed, Jun 17, 2009 at 3:08 AM, Benjamin
Herrenschmidt wrote:
> On Wed, 2009-06-17 at 02:56 +0200, Leon Woestenberg wrote:
>> I use pci_map_sg(), have the device perform either DMA master reads or
>> writes to the bus address using PCIe.
>> After tha
Hello all,
On Wed, Jun 17, 2009 at 2:37 AM, FUJITA
Tomonori wrote:
> On Wed, 17 Jun 2009 10:18:45 +1000
> Benjamin Herrenschmidt wrote:
>
>> On Tue, 2009-06-16 at 20:02 +0200, Arnd Bergmann wrote:
>> > On Tuesday 16 June 2009, Scott Wood wrote:
>> > > > If the
>> > > > device is the only one, you
Hello,
On Tue, Jun 16, 2009 at 6:30 PM, David Hawkins wrote:
>> Most MPC8xxx board designs I have seen suffer from this possible dead
>> lock:
>> - NOR Flash is put in erase mode or write mode
>> - Hardware watchdog triggers
>> - HRESET# is asserted by the processor, during which the configuration
Hello,
this is a hardware, even board issue, but I hope to find the right
target audience here.
In our MPC83xx design I would like to prevent dead lock in case where
a field upgrade is performed, i.e. NOR Flash is erased or written, and
the MPC83xx built-in hardware watchdog triggers.
In u-boot
/prod_summary.jsp?code=MPC8315E&nodeId=0162468rH3bTdGJk191439&fpsp=1&tab=Design_Tools_Tab#
Split out patches available from http://www.bitshrine.org/gpp/
On Tue, Jun 9, 2009 at 11:26 AM, Leon
Woestenberg wrote:
> Adding the sata_fsl.c developers to the recipients:
>
> On Mon, Jun 8,
Adding the sata_fsl.c developers to the recipients:
On Mon, Jun 8, 2009 at 4:59 PM, Leon
Woestenberg wrote:
> Hello,
>
> using 2.6.30-rc6, I get the following problems when I read from a SSD
> disk, connected to the
> 3.0 Gb SATA controller of the MPC8315E SoC rev 1.0 running L
Hello,
using 2.6.30-rc6, I get the following problems when I read from a SSD
disk, connected to the
3.0 Gb SATA controller of the MPC8315E SoC rev 1.0 running Linux 2.6.30-rc6.
Below see the output from two dd read runs.
The disk behaves fine on a x86 box.
What I can do to (help) pin-point the
The PCIe MSI interrupts are missing from the device tree source, and
thus were not enabled. This patch adds them.
v2 of the patch fixes inconsistent white space, reported by David Gibson.
Tested to work on MPC8315E-RDB with custom FPGA PCIe device.
Signed-off-by: Leon Woestenberg
Tested-by
The PCIe MSI interrupts are missing from the device tree source, and
thus were not enabled. This patch adds them.
Tested to work on MPC8315E-RDB with custom FPGA PCIe device.
Signed-off-by: Leon Woestenberg
Tested-by: Leon Woestenberg
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts
b/arch
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts
b/arch/powerpc/boot/dts/mpc8315erdb.dts
index 3f4c5fb..4f04667 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -322,6 +322,21 @@
reg = <0x700 0x100>;
Hello,
On Sun, May 24, 2009 at 8:38 AM, Michael Ellerman
wrote:
> On Sun, 2009-05-24 at 00:12 +0200, Leon Woestenberg wrote:
>> Hello,
>>
>> On Sat, May 23, 2009 at 10:58 PM, Leon Woestenberg
>> wrote:
>> > using this tree:
>> > git://git.kernel.o
Hello,
On Sat, May 23, 2009 at 1:55 AM, Jeremy Fitzhardinge wrote:
> Ian Campbell wrote:
>>
>> On Thu, 2009-05-21 at 14:27 -0400, Becky Bruce wrote:
>>
>>>
>>> I can work with that, but it's going to be a bit inefficient, as I
>>> actually need the dma_addr_t, not the phys_addr_t, so I'll have t
Hello,
On Sat, May 23, 2009 at 10:58 PM, Leon Woestenberg
wrote:
> using this tree:
> git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
>
> pci_enable_msi() fails on my MPC8315E-RDB board with PCIe device in
I found that the DTS for the MPC8315E-RDB is missing the
Hello Chris,
On Mon, May 18, 2009 at 8:06 PM, Chris Plasun wrote:
> Scott Wood wrote:
>> On Sun, May 17, 2009 at 01:45:30AM -0700, Chris Plasun wrote:
>>> (I haven't found any answers in the archives)
>>> How would I access a NTFS shared directory from a Freescale MPC8313?
>>> Will Samba run on a
Hello Stefan,
On Mon, Dec 1, 2008 at 8:46 PM, Stefan Roese wrote:
> On Monday 01 December 2008, Leon Woestenberg wrote:
>> >> Now, if I re-program the end-point FPGA during the u-boot boot
>> >> time-out, Linux will recognize the end-point.
>> >
>>
Hello,
On Mon, Jan 12, 2009 at 4:07 PM, Kumar Gala wrote:
> On Jan 12, 2009, at 1:55 AM, Li Yang wrote:
>>> -Original Message-
>> Freescale BSP is for customer who needs the out-of-box experience. It's
>> better tested, but doesn't update very frequently. I would suggest the
>> customer
Hello Anton,
On Wed, Jan 7, 2009 at 12:42 AM, Anton Vorontsov
wrote:
> On Tue, Jan 06, 2009 at 11:33:35PM +0100, Leon Woestenberg wrote:
>> So to summarize, we need u-boot to initialize the PCIe controller, in
>> order for Linux to further take it over.
>>
>> What
Hello Anton,
On Tue, Jan 6, 2009 at 10:15 PM, Anton Vorontsov
wrote:
> On Tue, Jan 06, 2009 at 02:38:57PM -0600, Kumar Gala wrote:
Is u-boot PCIe initialization required for this kernel patch to work?
>>>
>>> Yup.
>>
>> Really? what for?
>
> Hm. U-Boot should initialize SerDes and PCI-E con
Hello Anton,
On Mon, Jan 5, 2009 at 7:01 PM, Anton Vorontsov
wrote:
> On Mon, Jan 05, 2009 at 11:46:45AM -0600, Scott Wood wrote:
>>
>> Why? Unless the BSP u-boots do something insane, I think we should try
>> to have the upstream kernel boot on the u-boot that comes on the board
>> (it's not ni
Hello,
On Mon, Jan 5, 2009 at 7:01 PM, Anton Vorontsov
wrote:
> On Mon, Jan 05, 2009 at 11:46:45AM -0600, Scott Wood wrote:
> [...]
>> > My statement was to convey that the kernel.org kernel should only
>> > worry itself with the denx.de u-boot (w/regards to compatibility).
>>
>> Why? Unless the
Hello,
On Mon, Jan 5, 2009 at 11:07 PM, Leon Woestenberg
wrote:
>>
>> 2.6.28 works fine here... using
>> arch/powerpc/configs/83xx/mpc8315_rdb_defconfig and
>> arch/powerpc/boot/dts/mpc8315erdb.dts
>> Hope this helps,
>>
> Thanks for the report, I wen
Hello Anton,
On Mon, Jan 5, 2009 at 5:58 PM, Anton Vorontsov
wrote:
> On Sun, Jan 04, 2009 at 01:45:15AM +0100, Leon Woestenberg wrote:
>> Earlier release kernels booted for me, and I use the device tree
>> compiled from the device tree source that comes with the tree.
>>
Hello Frank,
On Sun, Jan 4, 2009 at 1:22 PM, Frank Lautenbach
wrote:
> can you please unsubscribe me from this mailing list?
> Frank
Every email from the list comes with this footer:
> ___
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https:
Hello,
On Sun, Jan 4, 2009 at 1:33 AM, Steve DeLaney wrote:
>
> we are booting 2.6.26 on MPC8349-MITXE
> do you need a device tree? this can be tftp loaded, or flashed in the board
> and
> cp.b from flash to ram before booting.
>
Earlier release kernels booted for me, and I use the device tree
Hello,
I cannot get my 2.6.28 kernel to boot. The board resets after u-boot
starts the kernel.
I would like to verify if someone got it booting already?
Regards,
Leon.
TFTP from server 192.168.1.24; our IP address is 192.168.1.15
Filename 'uImage-mpc8315e-rdb.bin'.
Load address: 0x40
Load
Felix,
On Sat, Dec 20, 2008 at 7:51 AM, Felix Radensky wrote:
>
> I've found the cause of the delay. It was a stupid error on my part, not
> related to ndfc driver, which is fine. Thanks a lot for you work on this.
>
Could you share the error?* (I'm sure I can easily exceed your level
of stupidit
Hello,
On Wed, Dec 3, 2008 at 8:40 AM, Trent Piepho <[EMAIL PROTECTED]> wrote:
> On Wed, 3 Dec 2008, Sean MacLennan wrote:
>>> Yes, I would recommend to do it this way if possible. A small NOR for
>>> U-Boot and environment and everything else in NAND. This makes things
>>> much easier. But I unde
Hello all,
On Mon, Dec 1, 2008 at 9:12 AM, Benjamin Herrenschmidt
<[EMAIL PROTECTED]> wrote:
> On Fri, 2008-11-28 at 13:50 +0100, Leon Woestenberg wrote:
>>
>> AMCC PPC460EX canyonlands board with an FPGA PCIe end point:
>>
>> u-boot sees the end point, but L
Hello,
AMCC PPC460EX canyonlands board with an FPGA PCIe end point:
u-boot sees the end point, but Linux does not:
U-Boot 1.3.3-00249-ga524e11 (Jun 30 2008 - 16:05:51)
CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200, OPB=100, EBC=100 MHz)
<...>
Board: Canyonlands - AMCC PPC460EX Evaluation
Hello all,
On Wed, Nov 26, 2008 at 7:26 PM, Leon Woestenberg
<[EMAIL PROTECTED]> wrote:
> On Wed, Nov 26, 2008 at 4:25 PM, Leon Woestenberg
> <[EMAIL PROTECTED]> wrote:
>> The non-detected end point boot:
>>
>> pci 0001:80:00.0: scanning behind bridge, config
On Wed, Nov 26, 2008 at 4:25 PM, Leon Woestenberg
<[EMAIL PROTECTED]> wrote:
> The non-detected end point boot:
>
> pci 0001:80:00.0: scanning behind bridge, config bf8180, pass 0
> PCI: Scanning bus 0001:81
> PCI: Fixups for bus 0001:81
>
Further debugging.
drivers/pc
Hello,
I enabled more DEBUG output, the online files have been updated. Snippets:
The detected end point boot:
pci 0001:80:00.0: scanning behind bridge, config bf8180, pass 0
PCI: Scanning bus 0001:81
pci 0001:81:00.0: found [1a0b:5331] class 00ff00 header type 00
pci 0001:81:00.0: reg 10 64bit
Hello,
On Wed, Nov 26, 2008 at 3:20 PM, Norbert van Bolhuis
<[EMAIL PROTECTED]> wrote:
>
> Thanks for the answer, but that's not it.
>
> I checked the jiffies variable, it increases about 250 times
> per second.
> So the (mpc83xx_defconfig) kernel perception (#define CONFIG_HZ 250) is OK.
>
> It m
Hello,
AMCC PPC460EX Canyonlands development board with PCI Express x1 card
in PCIe x4 slot labeled 'PCIE-1'. The PCI Express card has a
soft-programmable PCIe end point.
Problem: The end point with only non-prefetchable BAR does not appear
behind the PPC SoC internal bridge. It does show up on t
Hello Laurent,
On Mon, Oct 13, 2008 at 3:12 PM, Bill Gatliff <[EMAIL PROTECTED]> wrote:
> At least until someone plugs in that expansion module!
>
Bill's remark made a neuron connection in my head:
Can you detect if the module is inserted or not? (By reading a known
state of some pin)?
You could
Hi Laurent,
On Mon, Oct 13, 2008 at 1:04 PM, Laurent Pinchart
<[EMAIL PROTECTED]> wrote:
> There are no internal pull-up or pull-down resistors on the MPC8248 GPIO
> pins. I know our hardware engineer has a valid point theoretically. Does the
> point stand practically, or does the MPC8248
> "st
Hello Laurent,
On Mon, Oct 13, 2008 at 11:56 AM, Laurent Pinchart
<[EMAIL PROTECTED]> wrote:
> our hardware engineer asked me to make sure all unused GPIO pins are
> configured as outputs to avoid floating inputs. He got theory on his side
> (floating inputs can lead to higher current consumptio
Hello all,
On Thu, Oct 9, 2008 at 1:41 PM, Dominik Bozek <[EMAIL PROTECTED]> wrote:
> Paul Mackerras wrote:
>> Dominik Bozek writes:
>>> Actually I made couple of other tests on that mpc8313. Most of them are
>>> to ugly to publish them, but... My problem is that I have to boost the
>>> gigabit in
Kumar, John,
On Mon, Oct 6, 2008 at 5:09 PM, Kumar Gala <[EMAIL PROTECTED]> wrote:
> On Oct 6, 2008, at 8:42 AM, Leon Woestenberg wrote:
>> can Freescale or any of the powerpc maintainers indicate to what
>> extend PCI Express support for the MPC8315E processor has be
Hello all,
can Freescale or any of the powerpc maintainers indicate to what
extend PCI Express support for the MPC8315E processor has been merged
to Linux mainline, or what is still needs review or attention?
I could find u-boot and Linux patches provided by Freescale in their
open-source patch
André,
On Tue, Sep 30, 2008 at 12:05 AM, Leon Woestenberg
<[EMAIL PROTECTED]> wrote:
>> Since you also have to assert HRESET when you assert PORESET
>>
> But when I assert PORESET, the processor will assert HRESET itself
> AFAIK, so why do this?
>
>> you can wire
ottky diode.
>
Ooh, analog electronics, long time ago. Let me think: arrow of diode
symbol pointing from HRESET# to PORESET#, right, so that PORESET#
going low will pull HRESET# low enough, right?
> Hope this helps.
>
Yes it does, thanks.
Regards, Leon.
> Leon Woestenberg wrote:
>&g
Hello all,
not Linux related per se*, but I wonder how your board designs deal
with the reset circuitry for embedded PowerPC processors (MPC8313E in
my case).
My requirement is that both a processor-external hard reset and
processor-internal hard reset must both reset the boot device NOR
FlashROM,
Hello,
did anyone yet perform benchmarks on a combination of PCIe device
(off-the-shelf or custom) doing bulk data transfers, and bringing this
off the chip via GbE or SATA using a recent Linux kernel?
Also, can someone suggest a readily available PCIe device that has a
driver that is supported u
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