On 6/19/23 17:55, Philippe Mathieu-Daudé wrote:
Instead of including helper-sme.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 1 -
target/arm/tcg/sme_helper.c
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote:
Instead of including helper-mve.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 2 --
target/arm/tcg/mve_helper.c
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote:
+++ b/target/arm/tcg/crypto_helper.c
@@ -12,12 +12,17 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
#include "crypto/aes.h"
#include "crypto/sm4.h"
#include
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote:
helper.h is used by all units, but not all require the crypto
definitions. Move them to a new header; the next commit will
remove it from the common helper.h.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 37
From: Zhao Liu
Hi all,
This is my v3 patch series based on 48ab886d3da4f ("Merge tag 'pull-
target-arm-20230619' of https://git.linaro.org/people/pmaydell/qemu-arm
into staging").
Compared with v2 [1], v3 introduces 2 helpers to wrap the calculation of
threads/cores per socket so that smbios
From: Zhao Liu
smp.sockets is the number of sockets which is configured by "-smp" (
otherwise, the default is 1). Trying to recalculate it here with another
rules leads to errors, such as:
1. 003f230e37d7 ("machine: Tweak the order of topology members in struct
CpuTopology") changes the
From: Zhao Liu
>From SMBIOS 3.0 specification, core count field means:
Core Count is the number of cores detected by the BIOS for this
processor socket. [1]
Before 003f230e37d7 ("machine: Tweak the order of topology members in
struct CpuTopology"), MachineState.smp.cores means "the number of
From: Zhao Liu
The number of cores/threads per socket are needed for smbios, and are
also useful for other modules.
Provide the helpers to wrap the calculation of cores/threads per socket
so that we can avoid calculation errors caused by other modules miss
topology changes.
Suggested-by: Igor
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote:
Instead of including helper-sve.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 1 -
target/arm/tcg/sve_helper.c
From: Zhao Liu
>From SMBIOS 3.0 specification, thread count field means:
Thread Count is the total number of threads detected by the BIOS for
this processor socket. It is a processor-wide count, not a
thread-per-core count. [1]
So here we should use threads per socket other than threads per
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote:
Instead of including helper-gvec.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 1 -
On 6/20/23 12:12, Nicholas Piggin wrote:
On Wed Jun 7, 2023 at 12:09 AM AEST, Cédric Le Goater wrote:
On 6/5/23 13:23, Nicholas Piggin wrote:
Previous RFC here
https://lists.gnu.org/archive/html/qemu-ppc/2023-05/msg00453.html
This series drops patch 1 from the previous, which is more of
a
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote:
helper.h is used by all units, but not all require the generic
vector definitions. Move them to a new header; the next commit
will remove it from the common helper.h.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h |
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote:
Extract 1600 lines from the big enough translate.c.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate-gvec.c | 1644 +++
target/arm/tcg/translate.c | 1630 --
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote:
We want to extract gvec helpers to a new translate-gvec.c
file. Some helpers will still be accessed out of it, from
the current translate.c. Expose their prototype.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate.h | 5 +
On 6/19/23 17:54, Philippe Mathieu-Daudé wrote:
Instead of including helper-neon.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 1 -
target/arm/tcg/neon_helper.c
On 20/6/23 12:03, Richard Henderson wrote:
On 6/19/23 19:14, Alex Bennée wrote:
+We don't currently generate the API documentation for QDEV due to QEMU
+macros confusing the kerneldoc tool. For now see the headers in
+``include/hw/qdev-core.h``
+
+..
+ kernel-doc:: include/hw/qdev-core.h
I'm
On 6/19/23 17:42, Philippe Mathieu-Daudé wrote:
Instead of including helper-vfp.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 1 -
target/arm/tcg/mve_helper.c
On 6/19/23 17:42, Philippe Mathieu-Daudé wrote:
Keep the VFP helpers in the same file, guarding them with #ifdef'ry.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/helper-a64.c | 87 --
target/arm/vfp_helper.c | 93
On 20/6/23 10:39, Frédéric Pétrot wrote:
Fix arch name in the define that prevents multiple inclusions.
Signed-off-by: Frédéric Pétrot
---
host/include/x86_64/host/atomic128-ldst.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 20/6/23 07:59, Cédric Le Goater wrote:
Nick has great knowledge of the PowerPC CPUs, software and hardware.
Add him as a reviewer on CPU TCG modeling.
Cc: Nicholas Piggin
Signed-off-by: Cédric Le Goater
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Philippe
On Wed Jun 7, 2023 at 12:09 AM AEST, Cédric Le Goater wrote:
> On 6/5/23 13:23, Nicholas Piggin wrote:
> > Previous RFC here
> >
> > https://lists.gnu.org/archive/html/qemu-ppc/2023-05/msg00453.html
> >
> > This series drops patch 1 from the previous, which is more of
> > a standalone bugfix.
>
On 6/19/23 19:14, Alex Bennée wrote:
+As class initialisation cannot fail devices have an two additional
+methods to handle the creation of dynamic devices. The ``realize``
Beginning with "as" feels like a continuation from something that has been omitted.
You've skipped over describing
On 6/19/23 19:14, Alex Bennée wrote:
+We don't currently generate the API documentation for QDEV due to QEMU
+macros confusing the kerneldoc tool. For now see the headers in
+``include/hw/qdev-core.h``
+
+..
+ kernel-doc:: include/hw/qdev-core.h
I'm confused. Isn't that exactly what you're
On 6/19/23 19:14, Alex Bennée wrote:
Fix up the kerneldoc markup and start documenting the various fields
in QDEV related structures. Unfortunately this is not enough include
the documentation because kerneldoc currently chokes on some of our
macros such as:
/**
* @gpios: list of
On 6/19/23 19:14, Alex Bennée wrote:
Mention that QOM-ified devices already have support for registering
the description.
Signed-off-by: Alex Bennée
---
include/migration/vmstate.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 6/19/23 19:14, Alex Bennée wrote:
+QEMU is a large and mature project with a number of complex subsystems
+that can be overwhelming to understand. The development documentation
+is not comprehensive but hopefully presents enough of a starting point
+to get you started. If there are areas that
at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230620
for you to fetch changes up to d7ee93e24359703debf4137f4cc632563aa4e8d1:
cputlb: Restrict SavedIOTLB to system emulation (2023-06-20 10:02:14 +0200)
tcg: Define
This patch includes:
- XVSAT.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 ++
target/loongarch/helper.h| 9 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 86
target/loongarch/insns.decode
This patch includes:
- XVSHUF.{B/H/W/D};
- XVPERM.W;
- XVSHUF4i.{B/H/W/D};
- XVPERMI.{W/D/Q};
- XVEXTRINS.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 21 +++
target/loongarch/helper.h| 21 +++
This patch includes:
- VPCNT.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 +
target/loongarch/helper.h| 5 +
target/loongarch/insn_trans/trans_lasx.c.inc | 5 +
target/loongarch/insns.decode| 5 +
This patch includes:
- XVMUL.{B/H/W/D};
- XVMUH.{B/H/W/D}[U];
- XVMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 38 +++
target/loongarch/helper.h| 30 ++
This patch includes:
- XVLD[X], XVST[X];
- XVLDREPL.{B/H/W/D};
- XVSTELM.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 24 +
target/loongarch/helper.h| 3 +
target/loongarch/insn_trans/trans_lasx.c.inc | 97
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index c9f9cbb19d..aeccbb42e6 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -392,6 +392,7 @@ static void
On Tue Jun 20, 2023 at 7:27 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 6/5/23 16:53, Nicholas Piggin wrote:
> > PPC TCG now supports multi-threaded CPU configuration for non-hypervisor
> > state. This requires PIR and TIR be set, because that's how sibling thread
> > matching is done.
> >
> >
On Tue Jun 20, 2023 at 3:59 PM AEST, Cédric Le Goater wrote:
> Nick has great knowledge of the PowerPC CPUs, software and hardware.
> Add him as a reviewer on CPU TCG modeling.
Reviewed-by: Nicholas Piggin
>
> Cc: Nicholas Piggin
> Signed-off-by: Cédric Le Goater
> ---
> MAINTAINERS | 1 +
>
Hi,
> > The guest driver should be able to restore resources after resume.
>
> Thank you for your suggestion!
> As far as I know, resources are created on host side and guest has no backup,
> if resources are destroyed, guest can't restore them.
> Or do you mean guest driver need to send
This patch includes:
- XVINSGR2VR.{W/D};
- XVPICKVE2GR.{W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 54
target/loongarch/insns.decode| 13 +
3 files
This patch includes:
- XVSRLN.{B.H/H.W/W.D};
- XVSRAN.{B.H/H.W/W.D};
- XVSRLNI.{B.H/H.W/W.D/D.Q};
- XVSRANI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 16 +++
target/loongarch/helper.h| 16 +++
This patch includes:
- XVLDI.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 7 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 21
target/loongarch/insns.decode| 5 -
3 files changed, 32 insertions(+), 1 deletion(-)
This patch includes:
- XVABSD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 +++
target/loongarch/helper.h| 9 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 81
target/loongarch/insns.decode
This patch includes:
- XVSSRLN.{B.H/H.W/W.D};
- XVSSRAN.{B.H/H.W/W.D};
- XVSSRLN.{BU.H/HU.W/WU.D};
- XVSSRAN.{BU.H/HU.W/WU.D};
- XVSSRLNI.{B.H/H.W/W.D/D.Q};
- XVSSRANI.{B.H/H.W/W.D/D.Q};
- XVSSRLNI.{BU.H/HU.W/WU.D/DU.Q};
- XVSSRANI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
This patch includes:
- XVHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU};
- XVHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17
target/loongarch/helper.h| 18
This patch includes:
- XVSLL[I].{B/H/W/D};
- XVSRL[I].{B/H/W/D};
- XVSRA[I].{B/H/W/D};
- XVROTR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 36
target/loongarch/insn_trans/trans_lasx.c.inc | 36
This patch includes:
- XVSRLR[I].{B/H/W/D};
- XVSRAR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 18
target/loongarch/helper.h| 18
target/loongarch/insn_trans/trans_lasx.c.inc | 18
target/loongarch/insns.decode
This patch includes:
- XVBITSEL.V;
- XVBITSELI.B;
- XVSET{EQZ/NEZ}.V;
- XVSETANYEQZ.{B/H/W/D};
- XVSETALLNEZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 19 +
target/loongarch/helper.h| 11 +++
This patch includes:
- XVMAX[I].{B/H/W/D}[U];
- XVMIN[I].{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 33
target/loongarch/helper.h| 18 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 180 +++
This patch includes:
- XVSEQ[I].{B/H/W/D};
- XVSLE[I].{B/H/W/D}[U];
- XVSLT[I].{B/H/W/D/}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 43 ++
target/loongarch/helper.h| 23 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 154
This patch includes:
- XV{AND/OR/XOR/NOR/ANDN/ORN}.V;
- XV{AND/OR/XOR/NOR}I.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 12 ++
target/loongarch/helper.h| 2 +
target/loongarch/insn_trans/trans_lasx.c.inc | 42
On Tue Jun 20, 2023 at 3:59 PM AEST, Cédric Le Goater wrote:
> Fred and Nick have been hacking baremetal POWER systems (OPAL) for
> many years. They use and modify the QEMU models regularly. Add them as
> PowerNV reviewers.
>
Reviewed-by: Nicholas Piggin
> Cc: Frédéric Barrat
> Cc: Nicholas
This patch includes:
- XVSLLWIL.{H.B/W.H/D.W};
- XVSLLWIL.{HU.BU/WU.HU/DU.WU};
- XVEXTL.Q.D, VEXTL.QU.DU.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9
target/loongarch/helper.h| 9
target/loongarch/insn_trans/trans_lasx.c.inc | 21
This patch includes:
- XVPACK{EV/OD}.{B/H/W/D};
- XVPICK{EV/OD}.{B/H/W/D};
- XVILV{L/H}.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 27
target/loongarch/helper.h| 27
target/loongarch/insn_trans/trans_lasx.c.inc | 27
This patch includes:
- XVREPLVE.{B/H/W/D};
- XVREPL128VEI.{B/H/W/D};
- XVREPLVE0.{B/H/W/D/Q};
- XVINSVE0.{W/D};
- XVPICKVE.{W/D};
- XVBSLL.V, XVBSRL.V.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 29 +++
target/loongarch/helper.h| 5 +
This patch includes:
- VEXT2XV.{H/W/D}.B, VEXT2XV.{HU/WU/DU}.BU;
- VEXT2XV.{W/D}.B, VEXT2XV.{WU/DU}.HU;
- VEXT2XV.D.W, VEXT2XV.DU.WU.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 13 ++
target/loongarch/helper.h| 13 ++
This patch includes:
- XVMADD.{B/H/W/D};
- XVMSUB.{B/H/W/D};
- XVMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 34 ++
target/loongarch/helper.h| 30 ++
This patch includes:
- XVADDA.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 +++
target/loongarch/helper.h| 5 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 41
target/loongarch/insns.decode
This patch includes:
- XVREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 10 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 16
target/loongarch/insns.decode| 8
3 files changed, 34
This patch includes:
- XVSSRLRN.{B.H/H.W/W.D};
- XVSSRARN.{B.H/H.W/W.D};
- XVSSRLRN.{BU.H/HU.W/WU.D};
- XVSSRARN.{BU.H/HU.W/WU.D};
- XVSSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSSRARNI.{B.H/H.W/W.D/D.Q};
- XVSSRLRNI.{BU.H/HU.W/WU.D/DU.Q};
- XVSSRARNI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
Signed-off-by: Song Gao
---
linux-user/loongarch64/signal.c | 1 +
target/loongarch/cpu.c | 1 +
target/loongarch/cpu.h | 14 +
target/loongarch/gdbstub.c | 1 +
target/loongarch/internals.h| 22 --
target/loongarch/lsx_helper.c | 1 +
This patch includes:
- XVCLO.{B/H/W/D};
- XVCLZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 +
target/loongarch/helper.h| 9 +
target/loongarch/insn_trans/trans_lasx.c.inc | 9 +
This patch includes:
- XVADD.{B/H/W/D/Q};
- XVSUB.{B/H/W/D/Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 23
target/loongarch/insn_trans/trans_lasx.c.inc | 59
target/loongarch/insns.decode| 23
This patch includes:
- XVFCMP.cond.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 94
target/loongarch/helper.h| 5 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 32 +++
target/loongarch/insns.decode
This patch includes:
- XVF{ADD/SUB/MUL/DIV}.{S/D};
- XVF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- XVF{MAX/MIN}.{S/D};
- XVF{MAXA/MINA}.{S/D};
- XVFLOGB.{S/D};
- XVFCLASS.{S/D};
- XVF{SQRT/RECIP/RSQRT}.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 46 +
This patch includes:
- XVNEG.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 10 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 20
target/loongarch/insns.decode| 7 +++
3 files changed, 37 insertions(+)
This patch includes:
- XVDIV.{B/H/W/D}[U];
- XVMOD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 +++
target/loongarch/helper.h| 17 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 17 +++
This patch includes:
- XVSRLRN.{B.H/H.W/W.D};
- XVSRARN.{B.H/H.W/W.D};
- XVSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSRARNI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 16 ++
target/loongarch/helper.h| 16 ++
This patch includes:
- XVFCVT{L/H}.{S.H/D.S};
- XVFCVT.{H.S/S.D};
- XVFRINT[{RNE/RZ/RP/RM}].{S/D};
- XVFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- XVFTINT[RZ].{WU.S/LU.D};
- XVFTINT[{RNE/RZ/RP/RM}].W.D;
- XVFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- XVFFINT.{S.W/D.L}[U];
- X[CVFFINT.S.L, VFFINT{L/H}.D.W.
This patch includes:
- XVBITCLR[I].{B/H/W/D};
- XVBITSET[I].{B/H/W/D};
- XVBITREV[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 25 ++
target/loongarch/helper.h| 27 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 246
This patch includes:
- XVAVG.{B/H/W/D/}[U];
- XVAVGR.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 ++
target/loongarch/helper.h| 18 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 162 +++
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 2 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 10 ++
3 files changed, 14 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
This patch includes:
- XVFRSTP[I].{B/H}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 ++
target/loongarch/helper.h| 5 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 5 ++
target/loongarch/insns.decode| 5 ++
This patch includes:
- XVMSKLTZ.{B/H/W/D};
- XVMSKGEZ.B;
- XVMSKNZ.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 7 ++
target/loongarch/helper.h| 7 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 7 ++
target/loongarch/insns.decode
This patch includes:
- XVSIGNCOV.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 +++
target/loongarch/helper.h| 5 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 41
target/loongarch/insns.decode
This patch includes:
- XVSADD.{B/H/W/D}[U];
- XVSSUB.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 +
target/loongarch/insn_trans/trans_lasx.c.inc | 17 +
target/loongarch/insns.decode| 18
Hi,
This series adds LoongArch LASX instructions.
About test:
We use RISU test the LoongArch LASX instructions.
QEMU:
https://github.com/loongson/qemu/tree/tcg-old-abi-support-lasx
RISU:
https://github.com/loongson/risu/tree/loongarch-suport-lasx
Please review, Thanks.
Song Gao (46):
This patch includes:
- XVEXTH.{H.B/W.H/D.W/Q.D};
- XVEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 +
target/loongarch/helper.h| 9 +
target/loongarch/insn_trans/trans_lasx.c.inc | 20 ++
This patch includes:
- XVADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 43 ++
target/loongarch/helper.h| 45 ++
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_lasx.c.inc | 6 ++
target/loongarch/lasx_helper.c | 6 ++
target/loongarch/meson.build | 1 +
target/loongarch/translate.c | 1 +
4 files changed, 14 insertions(+)
create mode
This patch includes:
- XVADDI.{B/H/W/D}U;
- XVSUBI.{B/H/W/D}U.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 14
target/loongarch/insn_trans/trans_lasx.c.inc | 37
target/loongarch/insns.decode| 12 ++-
3 files
On 20/06/2023 09:55, Duan, Zhenzhong wrote:
>> -Original Message-
>> From: Joao Martins
>> Sent: Tuesday, June 20, 2023 4:23 PM
>> To: Duan, Zhenzhong ; Avihai Horon
>> ; qemu-devel@nongnu.org
>> Cc: alex.william...@redhat.com; c...@redhat.com; Peng, Chao P
>>
>> Subject: Re: [PATCH v2]
On 6/5/23 16:53, Nicholas Piggin wrote:
PPC TCG now supports multi-threaded CPU configuration for non-hypervisor
state. This requires PIR and TIR be set, because that's how sibling thread
matching is done.
spapr's nested-HV capability does not currently coexist with SMT. This
is quite
On Sun, Jun 11, 2023 at 01:47:51AM +0200, Henrik Carlqvist wrote:
> I have now changed the patch to instead use
>
> -global escc.chnA-sunkbd-layout=
>
> and documented in docs/system/keyboard.rst which I have linked from
> target-sparc.rst. Unfortunately, I am not very used to these .rst files
Hi Gerd Hoffmann
On 2023/6/19 20:51, Gerd Hoffmann wrote:
> Hi,
>> Adding a new command requires new feature flag (and maybe it should be in
>> the <0x1000 range instead)
>>
>> But I am not sure we need a new message at the virtio-gpu level. Gerd, wdyt?
>>
>> Maybe it's not a good place to
On 6/20/23 07:59, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 6/20/23 07:59, Cédric Le Goater wrote:
The 'bamboo' machine was used as a KVM platform in the early days (~2008).
It clearly doesn't support it anymore.
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc440_bamboo.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
On 6/20/23 07:59, Cédric Le Goater wrote:
The 'pegasos2' machine never supported KVM. This piece of code was
inherited from another model.
Cc: BALATON Zoltan
Signed-off-by: Cédric Le Goater
---
hw/ppc/pegasos2.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
Reviewed-by:
On 6/20/23 07:59, Cédric Le Goater wrote:
The 'prep' machine never supported KVM. This piece of code was
probably inherited from another model.
Cc: Hervé Poussineau
Signed-off-by: Cédric Le Goater
---
hw/ppc/prep.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
On 6/20/23 07:59, Cédric Le Goater wrote:
The 'sam460ex' machine never supported KVM. This piece of code was
inherited from another model.
Cc: BALATON Zoltan
Signed-off-by: Cédric Le Goater
---
hw/ppc/sam460ex.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
On 6/20/23 07:59, Cédric Le Goater wrote:
Fred discusses frequently with the IBM HW designers, he is fluent in
XIVE logic, add him as a reviewer.
Cc: Frédéric Barrat
Signed-off-by: Cédric Le Goater
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
r~
On 6/20/23 07:59, Cédric Le Goater wrote:
Nick has great knowledge of the PowerPC CPUs, software and hardware.
Add him as a reviewer on CPU TCG modeling.
Cc: Nicholas Piggin
Signed-off-by: Cédric Le Goater
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
On 6/20/23 07:59, Cédric Le Goater wrote:
Fred and Nick have been hacking baremetal POWER systems (OPAL) for
many years. They use and modify the QEMU models regularly. Add them as
PowerNV reviewers.
Cc: Frédéric Barrat
Cc: Nicholas Piggin
Signed-off-by: Cédric Le Goater
---
MAINTAINERS | 2 ++
On 6/20/23 07:59, Cédric Le Goater wrote:
When the Timer Control and Timer Status registers are modified, avoid
calling the KVM backend when not available
Signed-off-by: Cédric Le Goater
---
target/ppc/kvm.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/ppc/kvm.c
On 6/19/23 17:42, Philippe Mathieu-Daudé wrote:
In order to restrict lookup_cp_reg() and set_rmode() helpers
to VFP translation, un-inline gen_lookup_cp_reg and gen_set /
gen_restore_rmode.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate.h | 22 +++---
On Tue, 20 Jun 2023 12:48:05 +0530
Ani Sinha wrote:
> When a device has an upstream PCIE port, we can only use slot 0. Non-zero
> slots
> are invalid.
> This change ensures that we throw an error if the user
> tries to hotplug a device with an upstream PCIE port to a non-zero slot.
Isn't the
On 6/20/23 10:39, Frédéric Pétrot wrote:
Fix arch name in the define that prevents multiple inclusions.
Signed-off-by: Frédéric Pétrot
---
host/include/x86_64/host/atomic128-ldst.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Whoopsie.
Reviewed-by: Richard Henderson
r~
>-Original Message-
>From: Joao Martins
>Sent: Tuesday, June 20, 2023 4:23 PM
>To: Duan, Zhenzhong ; Avihai Horon
>; qemu-devel@nongnu.org
>Cc: alex.william...@redhat.com; c...@redhat.com; Peng, Chao P
>
>Subject: Re: [PATCH v2] vfio/migration: Refactor and fix print of "Migration
On Tue, Jun 20, 2023 at 09:48:02AM +0200, Philippe Mathieu-Daudé wrote:
> Although the PPC target only supports the TCG and KVM
> accelerators, QEMU supports more. We can no assume that
> '!kvm == tcg', so test for the correct accelerator. This
> also eases code review, because here we don't care
Fix arch name in the define that prevents multiple inclusions.
Signed-off-by: Frédéric Pétrot
---
host/include/x86_64/host/atomic128-ldst.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/host/include/x86_64/host/atomic128-ldst.h
kvmclock_create() is only implemented in hw/i386/kvm/clock.h.
Restrict the "hw/kvm/clock.h" header to i386 by moving it to
hw/i386/.
Signed-off-by: Philippe Mathieu-Daudé
---
RFC: No other arch had to implement this for 12 years,
safe enough to restrict to x86?
---
{include/hw =>
We shouldn't call kvmclock_create() when KVM is not available
or disabled:
- check for kvm_enabled() before calling it
- assert KVM is enabled once called
Since the call is elided when KVM is not available, we can
remove the stub (it is never compiled).
Signed-off-by: Philippe Mathieu-Daudé
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