csrind, PRIV_VERSION_1_12_0, ext_smcsrind),
This is actually part of the unpriv spec, so it's a bit weird that it
depends on the priv spec. But that's how it's all set up.
But shouldn't this be PRIV_VERSION_1_13_0?
Alistair
7d2f2 100644
> --- a/target/riscv/pmu.c
> +++ b/target/riscv/pmu.c
> @@ -204,6 +204,7 @@ static void riscv_pmu_icount_update_priv(CPURISCVState
> *env,
> }
>
> if (env->virt_enabled) {
> +g_assert(env->priv <= PRV_S);
Don't we need this assert for !env->virt_enabled as well?
Alistair
ppe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> docs/about/deprecated.rst | 13 -
> docs/about/removed-features.rst | 8
> target/riscv/cpu-qom.h | 1 -
> target/riscv/cpu.c | 28
>
ion per machine now.
>
> Signed-off-by: Thomas Huth
Reviewed-by: Alistair Francis
Alistair
> ---
> tests/avocado/riscv_opensbi.py | 63 --
> tests/functional/meson.build | 8
> tests/functional/test_riscv_opensbi.py | 36 +
On Wed, Jul 24, 2024 at 10:56 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 7/19/24 6:34 AM, Alistair Francis wrote:
> > On Tue, Jul 9, 2024 at 3:37 AM Daniel Henrique Barboza
> > wrote:
> >>
> >> Add a simple guideline to use the existi
}
> +
> +TCGv data_low = get_gpr(ctx, a->rs2, EXT_NONE);
> +TCGv data_high = get_gpr(ctx, a->rs2 + 1, EXT_NONE);
> +TCGv addr = get_address(ctx, a->rs1, a->imm);
> +TCGv_i64 tmp = tcg_temp_new_i64();
> +
> +tcg_gen_concat_tl_i64(tmp, d
> target/riscv: Correct SXL return value for RV32 in RV64 QEMU
> target/riscv: Detect sxl to set bit width for RV32 in RV64
> target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
> target/riscv: Enable RV32 CPU support in RV64 QEMU
Tha
w
> - Simplify writing of tdata3
>
> Alvin Chang (2):
> target/riscv: Preliminary textra trigger CSR writting support
> target/riscv: Add textra matching condition for the triggers
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> tar
them.
> >
> > Suggested-by: Alistair Francis
> > Signed-off-by: LIU Zhiwei
>
> That is both false (trans_fld is used from trans_c_fld), and not the takeaway
> you should
> have gotten (the operation of "fld" should not depend on the encoding).
>
> Perhap
On Tue, Jul 23, 2024 at 9:33 AM Atish Kumar Patra wrote:
>
> On Sat, Jul 20, 2024 at 8:19 AM Peter Maydell
> wrote:
> >
> > On Thu, 18 Jul 2024 at 03:15, Alistair Francis wrote:
> > >
> > > From: Atish Patra
> > >
> > > The timer is
On Thu, Jul 18, 2024 at 12:10 PM Alistair Francis wrote:
>
> From: LIU Zhiwei
>
> Zama16b is the property that misaligned load/stores/atomics within
> a naturally aligned 16-byte region are atomic.
>
> According to the specification, Zama16b applies only to AMOs, loads
break;
> +default:
> + g_assert_not_reached();
> +}
> +
> +if (textra != tdata3) {
> +qemu_log_mask(LOG_GUEST_ERROR,
> + "different value 0x" TARGET_FMT_lx " write to
> tdata3\n",
> + textra);
> +}
You don't need this, you have already reported on all of the possible
differences
With the above removed
Reviewed-by: Alistair Francis
Alistair
:0014.
> +
> +To include the device in the 'virt' machine:
> +
> +.. code-block:: bash
> +
> + $ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...)
We should add a sentence saying what this does. As in what should a
user expect after they have done this
Alistair
> +
>
ines for initialization". It emulates what we expect from the
> software/OS when initializing the IOMMU.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Frank Chang
Acked-by: Alistair Francis
Alistair
> ---
> tests/qtest/libqos/riscv-iommu.h | 29 +++
ations.
>
> Signed-off-by: Tomasz Jeznach
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Frank Chang
Acked-by: Alistair Francis
Alistair
> ---
> hw/riscv/riscv-iommu-bits.h | 43 +++-
> hw/riscv/riscv-iommu.c | 129 ++
s 'not implemented'.
>
> There are some artifacts included in the cache that predicts s-stage and
> g-stage elements, although we don't support it yet. We'll introduce them
> next.
>
> Signed-off-by: Tomasz Jeznach
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Frank Cha
d-off-by: Tomasz Jeznach
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/meson.build | 2 +-
> hw/riscv/riscv-iommu-pci.c | 178 +
> 2 files changed, 179 i
iltering - address pattern */
> +uint64_t msiptp;/* MSI redirection page table pointer */
> +};
> +
> +/* IOMMU index for transactions without process_id specified. */
> +#define RISCV_IOMMU_NOPROCID 0
> +
> +static void riscv_iommu_notify(RISCVIOMMUState *
ation'")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20240715090455.145888-1-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
docs/about/deprecated.rst | 11 +++
hw/riscv/virt.c | 9 +
2 files changed, 20 ins
te update codes.
For example: One use-case which inspired this change is
to update mode-specific instruction and cycle counters
which requires information of both prev mode and current
mode.
Signed-off-by: Rajnesh Kanwal
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID:
From: Atish Patra
Create a new config for Smcntrpmf extension so that it can be enabled/
disabled from the qemu commandline.
Signed-off-by: Atish Patra
Acked-by: Alistair Francis
Message-ID: <20240711-smcntrpmf_v7-v8-13-b7c38ae7b...@rivosinc.com>
Signed-off-by: Alistair Francis
---
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Message-ID: <20240709113652.1239-7-zhiwei_...@linux.alibaba.com>
Signed-off-by: Alistair Francis
---
target/riscv/translate.c| 21 +
target/riscv/insn_trans/trans_rva.c.in
.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Atish Patra
Message-ID: <20240711-smcntrpmf_v7-v8-12-b7c38ae7b...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/pmu.c | 56 --
1 file changed, 44 insertions(+), 12 deletions(-)
diff
From: Atish Patra
scounteren/hcountern are also WARL registers similar to mcountern.
Only set the bits for the available counters during the write to
preserve the WARL behavior.
Signed-off-by: Atish Patra
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID
From: Daniel Henrique Barboza
Two new regs added: ztso and zacas.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20240709085431.455541-1-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
target/riscv/kvm/kvm-cpu.c | 2 ++
1 file chan
and will cause any attendant side effects.
So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.
Signed-off-by: Yu-Ming Chang
Signed-off-by: Alvin Chang
Reviewed-by: Alistair Francis
Message-ID
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Message-ID: <20240709113652.1239-8-zhiwei_...@linux.alibaba.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 20 +++
target
From: Jiayi Li
Base on the riscv-privileged spec, vstvec substitutes for the usual stvec.
Therefore, the encoding of the MODE should also be restricted to 0 and 1.
Signed-off-by: Jiayi Li
Reviewed-by: Alistair Francis
Reviewed-by: LIU Zhiwei
Message-ID: <20240701022553.1982-1-l
711-smcntrpmf_v7-v8-10-b7c38ae7b...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 75 --
target/riscv/pmu.c | 3 +-
2 files changed, 54 insertions(+), 24 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Message-ID: <20240709113652.1239-10-zhiwei_...@linux.alibaba.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvzabha.c.in
: <20240711-smcntrpmf_v7-v8-11-b7c38ae7b...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/pmu.h | 2 ++
target/riscv/csr.c | 5 -
target/riscv/pmu.c | 30 +++---
3 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/target/riscv/pmu.h b/target
Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Deepak Gupta
Message-ID: <20240709113652.1239-5-zhiwei_...@linux.alibaba.com>
Signed-off-by: Alistair Francis
---
disas/riscv.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
to not write any register.
In current implementation, C.MOP.n only has an check function, without any
other more behavior.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Deepak Gupta
Message-ID: <20240709113652.1239-4-zhiwei_...@linux.alibaba.com>
Signed-off-by: Al
operation for the
purposes of RVWMO—i.e., it will execute atomically.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Message-ID: <20240709113652.1239-6-zhiwei_...@linux.alibaba.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
target/riscv
SR
b752099 include: sbi: Introduce common endianess conversion macro
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20240715171521.179517-1-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
.../opensbi-riscv32-generic-fw_dynamic.bin| Bin 267416
to be enabled.
The cycle/instret are still computed using host ticks when icount
is not enabled. Otherwise, they are computed using raw icount which
is more accurate in icount mode.
Co-Developed-by: Rajnesh Kanwal
Signed-off-by: Rajnesh Kanwal
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair
From: Kaiwen Xue
This adds the definitions for ISA extension smcntrpmf.
Signed-off-by: Kaiwen Xue
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-ID: <20240711-smcntrpmf_v7-v8-4-b7c38ae7b...@rivosinc.com>
Signed-off-by: Alistair F
saved when the counter is stopped.
Thus, save the value of the counter during the inhibit update
operation and return that value during the read if corresponding bit
in mcountihibit is set.
Acked-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Atish Patra
Message-ID
From: Atish Patra
mhpmeventhX CSRs are available for RV32. The predicate function
should check that first before checking sscofpmf extension.
Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support")
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
From: Atish Patra
Currently, the INH fields are set in mhpmevent uncoditionally
without checking if a particular priv mode is supported or not.
Suggested-by: Alistair Francis
Signed-off-by: Atish Patra
Acked-by: Alistair Francis
Message-ID: <20240711-smcntrpmf_v7-v8-6-b7c38a
From: Kaiwen Xue
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Kaiwen Xue
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Message-ID: <20240711-smcntrpmf_v7-v8-3-b7c38a
From: Balaji Ravikumar
Add disassembly support for these instructions from Zawrs:
* wrs.sto
* wrs.nto
Signed-off-by: Balaji Ravikumar
Signed-off-by: Rob Bradford
Acked-by: Alistair Francis
Message-ID: <20240705165316.127494-1-rbradf...@rivosinc.com>
Signed-off-by: Alistair F
and 7.
These 40 MOPs initially are defined to simply write zero to x[rd],
but are designed to be redefined by later extensions to perform some
other action.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Deepak Gupta
Message-ID: <20240709113652.1239-2-zhiw
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Message-ID: <20240709113652.1239-11-zhiwei_...@linux.alibaba.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Message-ID: <20240709113652.1239-9-zhiwei_...@linux.alibaba.com>
Signed-off-by: Alistair Francis
---
target/riscv/translate.c| 13 +
target/riscv/insn_trans/trans_rvzacas.c.in
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Deepak Gupta
Message-ID: <20240709113652.1239-3-zhiwei_...@linux.alibaba.com>
Signed-off-by: Alistair Francis
---
disas/riscv.c | 98 +++
1 file chang
-by: Atish Patra
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Kaiwen Xue
Acked-by: Alistair Francis
Message-ID: <20240711-smcntrpmf_v7-v8-5-b7c38ae7b...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 12
target/riscv/csr.c
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Message-ID: <20240709113652.1239-12-zhiwei_...@linux.alibaba.com>
Signed-off-by: Alistair Francis
---
disas/riscv.c | 60 +++
1 file changed, 60 insertions(+)
diff
The following changes since commit 58ee924b97d1c0898555647a31820c5a20d55a73:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2024-07-17 15:40:28 +1000)
are available in the Git repository at:
https://github.com/alistair23/qemu.git
c: Conor Dooley
> Cc: Anup Patel
> Fixes: b1f1e9dcfa ("hw/riscv/virt.c: aplic DT: rename prop to 'riscv,
> delegation'")
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Alistair Francis
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
>
> v2:
&g
et/riscv/cpu.h| 20 ++-
> target/riscv/cpu_bits.h | 41 +
> target/riscv/cpu_cfg.h| 1 +
> target/riscv/cpu_helper.c | 66 +++
> target/riscv/csr.c| 437
> +-
> target/riscv/machine.c| 5 +-
> target/
On Fri, Jul 12, 2024 at 8:34 AM Atish Patra wrote:
>
> Create a new config for Smcntrpmf extension so that it can be enabled/
> disabled from the qemu commandline.
>
> Signed-off-by: Atish Patra
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 1 +
On Fri, Jul 12, 2024 at 8:34 AM Atish Patra wrote:
>
> Currently, the INH fields are set in mhpmevent uncoditionally
> without checking if a particular priv mode is supported or not.
>
> Suggested-by: Alistair Francis
> Signed-off-by: Atish Patra
Thanks!
Acked-by: Alistair
o actual
> effects on the counting of cycle and instret counters.
>
> Signed-off-by: Atish Patra
> Reviewed-by: Daniel Henrique Barboza
> Signed-off-by: Kaiwen Xue
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_bits.h | 12
On Fri, Jul 12, 2024 at 8:33 AM Atish Patra wrote:
>
> From: Kaiwen Xue
>
> This adds the properties for ISA extension smcntrpmf. Patches
> implementing it will follow.
>
> Signed-off-by: Kaiwen Xue
> Reviewed-by: Daniel Henrique Barboza
> Signed-off-by: Atish Pa
ion'. 'riscv,delegate' is then marked for future
> deprecation and its use is being discouraged.
>
> Cc: Conor Dooley
> Cc: Anup Patel
> Fixes: b1f1e9dcfa ("hw/riscv/virt.c: aplic DT: rename prop to 'riscv,
> delegation'")
> Signed-off-by: Daniel Henrique Barboza
Thanks
ion'. 'riscv,delegate' is then marked for future
> deprecation and its use is being discouraged.
>
> Cc: Conor Dooley
> Cc: Anup Patel
> Fixes: b1f1e9dcfa ("hw/riscv/virt.c: aplic DT: rename prop to 'riscv,
> delegation'")
> Signed-off-by: Daniel Henrique Barboza
Re
On Tue, Jun 4, 2024 at 7:15 PM Yu-Ming Chang via wrote:
Something is strange with your `From` email address.
This seems to be a common problem with the Andes emails, do you mind
fixing this?
Alistair
>
> Both CSRRS and CSRRC always read the addressed CSR and cause any read side
>
entation here.
The WID of M-mode for example is set by an external environment. How
are users going to set that in QEMU?
Are the Smwg, Smwgd, and Sswg extensions enabled? Or is it hard coded
one world per hart?
We should make it clear to users how this is setup as the spec leaves
a lot o
h -x and default to 'false'.
> */
> DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
> +DEFINE_PROP_UINT32("mwid", RISCVCPU, cfg.mwid, UINT32_MAX),
> +DEFINE_PROP_UINT32("mwidlist", RISCVCPU, cfg.mwidlist, UINT32_MAX),
The
want to maintain bistability.
I understand this doesn't break the build, but it's a bit strange to
allow users to enable something when at this point it doesn't yet work
Alistair
> +
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/c
X_VERSAL_TRNG
> bool
>
> +config RISCV_WORLDGUARD
> +bool
We should ensure this is enabled as well so that it is built by default
Alistair
> +
> source macio/Kconfig
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 86596a3888..a75668ff86 100644
; +/*
> + * RISC-V WorldGuard: the 5-bit WID of memory access.
> + */
> +uint8_t world_id;
Everything else is using `unsigned int` so I think we should as well
Alistair
> } MemTxAttrs;
>
> /* Bus masters which don't specify any attributes will get this,
> --
> 2.17.1
>
>
target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
> target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
> target/riscv: Correct SXL return value for RV32 in RV64 QEMU
> target/riscv: Detect sxl to set bit width for RV32 in RV64
> target/riscv: Correct mcau
ith
> its nonfault parameter set to true.
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/vector_helper.c | 34 ++
> 1 file changed, 18 insertions(+), 16 deletions(-)
>
> diff --git a/t
nstead of assemble code.
>
> This patch set has been queued to alistair/riscv-to-apply.next, but it is
> still not
> merged by the master branch. I think we had better fix it before merging into
> the
> master.
>
> v3->v4:
> 1. Fix zimop opcode and disassemb
On Mon, Jul 8, 2024 at 11:21 PM LIU Zhiwei wrote:
>
> From: TANG Tiancheng
>
> Ensure mcause high bit is correctly set by using 32-bit width for RV32
> mode and 64-bit width for RV64 mode.
>
> Signed-off-by: TANG Tiancheng
> Reviewed-by: Liu Zhiwei
Reviewed-by: Ali
t;
> Signed-off-by: TANG Tiancheng
> Reviewed-by: Liu Zhiwei
> Acked-by: Alistair Francis
> Reviewed-by: Alistair Francis
Something is wrong here, it should only be an Ack
Alistair
them here.
>
> Signed-off-by: Alvin Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/debug.c | 63 +++-
> target/riscv/debug.h | 3 +++
> 2 files changed, 65 insertions(+), 1 deletion(-)
>
> diff --git a/target/r
_action(CPURISCVState *env, target_ulong trigger_index)
> {
> trigger_action_t action = get_trigger_action(env, trigger_index);
> @@ -441,8 +504,10 @@ static void type2_reg_write(CPURISCVState *env,
> target_ulong index,
> }
> break;
> case TDAT
th
> as well.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Alistair
> ---
> tests/qtest/bios-tables-test.c | 14 --
> 1 file changed, 14 deletions(-)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-table
On Tue, Jul 9, 2024 at 6:55 PM Daniel Henrique Barboza
wrote:
>
> Two new regs added: ztso and zacas.
>
> Signed-off-by: Daniel Henrique Barboza
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/kvm/kvm-cpu.c | 2 ++
> 1 file changed, 2 inserti
On Tue, Jul 9, 2024 at 6:55 PM Daniel Henrique Barboza
wrote:
>
> Two new regs added: ztso and zacas.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/kvm/kvm-cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
>
On Wed, Jun 26, 2024 at 3:53 PM Ethan Chen wrote:
>
> On Wed, Jun 26, 2024 at 11:22:46AM +1000, Alistair Francis wrote:
> >
> > On Mon, Jun 24, 2024 at 11:47 AM Ethan Chen wrote:
> > >
> > > Hi Alistair,
> > >
> > > IOPMP can
ting the commit message to describe
what exactly this fixes (as in what issue you had) and why this fixes
it
Alistair
>
> Signed-off-by: Zhiwei Jiang
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/r
Signed-off-by: Yu-Ming Chang
> Signed-off-by: Alvin Chang
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> Hi Alistair,
> This fixed the issue of riscv_csrrw_debug().
>
> Best regards,
> Yuming
>
> target/riscv/cpu.h | 4 +++
> target/risc
Signed-off-by: Yu-Ming Chang
> Signed-off-by: Alvin Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> Hi Alistair,
> This fixed the issue of riscv_csrrw_debug().
>
> Best regards,
> Yuming
>
> target/riscv/cpu.h | 4 +++
> target/riscv/csr.
f the GNU General Public License along
> with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_ZCMLSD(ctx) do {\
> +if (!ctx->cfg_ptr->ext_zcmlsd) \
> +return false; \
> +} while (0)
> +
mented in bios-tables-test.c,
> > > > > > generate the expected ACPI AML data files for RISC-V using the
> > > > > > rebuild-expected-aml.sh script and update the
> > > > > > bios-tables-test-allowed-diff.h.
> > > > > >
> > >
t;
> Signed-off-by: TANG Tiancheng
> Reviewed-by: Liu Zhiwei
Acked-by: Alistair Francis
Alistair
> ---
> tests/avocado/boot_linux_console.py | 37 +
> 1 file changed, 37 insertions(+)
>
> diff --git a/tests/avocado/boot_linux_console.py
&g
On Thu, Jul 4, 2024 at 12:55 AM LIU Zhiwei wrote:
>
> From: TANG Tiancheng
>
> Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs
> in RV64 QEMU.
>
> Signed-off-by: TANG Tiancheng
> Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
Al
/cpu_helper.c
> @@ -887,12 +887,14 @@ static int get_physical_address(CPURISCVState *env,
> hwaddr *physical,
>
> CPUState *cs = env_cpu(env);
> int va_bits = PGSHIFT + levels * ptidxbits + widened;
> +int sxlen = 16UL << riscv_cpu_sxl(env);
A leftover U
On Sat, Jul 6, 2024 at 2:54 AM Rob Bradford wrote:
>
> From: Balaji Ravikumar
>
> Add disassembly support for these instructions from Zawrs:
>
> * wrs.sto
> * wrs.nto
>
> Signed-off-by: Balaji Ravikumar
> Signed-off-by: Rob Bradford
Thanks!
Applied to
On Sat, Jul 6, 2024 at 2:54 AM Rob Bradford wrote:
>
> From: Balaji Ravikumar
>
> Add disassembly support for these instructions from Zawrs:
>
> * wrs.sto
> * wrs.nto
>
> Signed-off-by: Balaji Ravikumar
> Signed-off-by: Rob Bradford
Acked-by: Alistair Fran
r to review since
> we'll have a more complete picture. Patch 3 will end up gaining +381 lines
> though.
Squashing is probably the way to go
Alistair
5;
>
> so presumably the intention was that we put enough words
> in the bitfield for the number of sources we have, so that
> the array access wouldn't overrun. Maybe we got the
> calculation wrong?
Yeah, the calculation is wrong here.
We have
s->bitfield_words = (s->num_sour
4")
> Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 87742047ce..49de81be7e 100644
> --- a/target/
On Mon, Jul 1, 2024 at 3:42 PM Jiayi Li wrote:
>
> Base on the riscv-privileged spec, vstvec substitutes for the usual stvec.
> Therefore, the encoding of the MODE should also be restricted to 0 and 1.
>
> Signed-off-by: Jiayi Li
Thanks!
Applied to riscv-to-apply
On Mon, Jul 1, 2024 at 3:42 PM Jiayi Li wrote:
>
> Base on the riscv-privileged spec, vstvec substitutes for the usual stvec.
> Therefore, the encoding of the MODE should also be restricted to 0 and 1.
>
> Signed-off-by: Jiayi Li
Reviewed-by: Alistair Francis
Alistair
> -
implements socket support and exposes SPDM for a NVMe device.
1: https://github.com/DMTF/libspdm
v8:
- Fixup i386 failures (thanks to Wilfred)
- Passes CI on GitLab:
https://gitlab.com/alistair23/qemu/-/tree/mainline/alistair/spdm-socket.next?ref_type=heads
v7:
- Fixup checkpatch failures
- Fixup test
From: Wilfred Mallawa
Setup Data Object Exchange (DOE) as an extended capability for the NVME
controller and connect SPDM to it (CMA) to it.
Signed-off-by: Wilfred Mallawa
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Cameron
Acked-by: Klaus Jensen
---
docs/specs/index.rst
-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
[ Changes by WM
- Bug fixes from testing
]
Signed-off-by: Wilfred Mallawa
[ Changes by AF:
- Convert to be more QEMU-ified
- Move to backends as it isn't PCIe specific
]
Signed-off-by: Alistair Francis
---
MAINTAINERS | 6
Add all of the defined protocols/features from the PCIe-SIG r6.0
"Table 6-32 PCI-SIG defined Data Object Types (Vendor ID = 0001h)"
table.
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Cameron
Reviewed-by: Wilfred Mallawa
---
include/hw/pci/pcie_doe.h | 2 ++
1 file
> > processor : 0
> > hart: 0
> > isa :
> > rv32imafdch_zicbom_zicboz_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfa_zba_zbb_zbc_zbs_sstc
> > mmu : sv32
>
> Please provide an Avocado test (i.e. checking /proc/cpuinfo
> contains "isa : rv32"). See for reference
> tests/avocado/boot_linux_console.py.
Awesome! Thanks for this, this is very exciting.
I agree we should add an Avacado test, that way this will be regularly
tested as it's something that seems prone to breakage.
Alistair
>
> Thanks!
>
late(cs->as, pte_addr, , ,
> false, MEMTXATTRS_UNSPECIFIED);
> if (memory_region_is_ram(mr)) {
> @@ -1126,6 +1128,11 @@ restart:
> *pte_pa = pte = updated_pte;
> #else
> target_ulong old_pte = qatomic_cmpxchg(pte
On Mon, Jul 1, 2024 at 1:40 PM LIU Zhiwei wrote:
>
> From: TANG Tiancheng
>
> Ensure pmp_size is correctly determined using mxl for RV32
> in RV64 QEMU.
>
> Signed-off-by: TANG Tiancheng
> Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
Alistair
> --
fw_dynmaic_info32 struct for this purpose.
>
> Signed-off-by: TANG Tiancheng
> Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/boot.c | 35 ++---
> hw/riscv/sifive_u.c | 3 ++-
> include
Do you mind rebasing on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next and
re-sending
Alistair
> ---
> disas/riscv.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 90d6b26de9..e79788ea0a 100644
> --- a/disas/riscv.c
On Wed, Jun 26, 2024 at 7:43 PM Rob Bradford wrote:
>
> From: Balaji Ravikumar
>
> Add disassembly support for these instructions from Zawrs:
>
> * wrs.sto
> * wrs.nto
>
> Signed-off-by: Balaji Ravikumar
> Signed-off-by: Rob Bradford
Acked-by: Alistair Fran
e gen_cmpxchg before adding amocas.[b|h]
> target/riscv: Add amocas.[b|h] for Zabha
> target/riscv: Expose zabha extension as a cpu property
> disas/riscv: Support zabha disassemble
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> disas/riscv.c
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