The spapr virtual hypervisor does not require the hdecr timer.
Remove it.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/ppc.c| 2 +-
hw/ppc/spapr_cpu_core.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
The radix on vhyp MMU uses a single-level radix table walk, with the
partition scope mapping provided by the flat QEMU machine memory.
A subsequent change will use the two-level radix walk on vhyp in some
situations, so provide a helper which can abstract that logic.
Reviewed-by: Cédric Le Goater
SynDbg commands can come from two different flows:
1. Hypercalls, in this mode the data being sent is fully
encapsulated network packets.
2. SynDbg specific MSRs, in this mode only the data that needs to be
transfered is passed.
Signed-off-by: Jon Doron
---
docs/hyperv.txt |
Invalid or missing partition table entry exceptions should cause HV
interrupts. HDSISR is set to bad MMU config, which is consistent with
the ISA and experimentally matches what POWER9 generates.
Reviewed-by: Fabiano Rosas
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Nicholas Piggin
---
In prepartion for implementing a full partition table option for
vhyp, update the get_pate method to take an lpid and return a
success/fail indicator.
The spapr implementation currently just asserts lpid is always 0
and always return success.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas
Introduce virtual hypervisor methods that can support a "Nested KVM HV"
implementation using the bare metal 2-level radix MMU, and using HV
exceptions to return from H_ENTER_NESTED (rather than cause interrupts).
HV exceptions can now be raised in the TCG spapr machine when running a
nested KVM HV
Machines which don't emulate the HDEC facility are able to use the
timer for something else. Provide functions to start and stop the
hdecr timer.
Signed-off-by: Nicholas Piggin
---
hw/ppc/ppc.c | 21 +
include/hw/ppc/ppc.h | 3 +++
2 files changed, 24 insertions(+)
The virtual hypervisor currently always intercepts and handles
hypercalls but with a future change this will not always be the case.
Add a helper for the test so the logic is abstracted from the mechanism.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.
This implements the Nested KVM HV hcall API for spapr under TCG.
The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
L1 is switched back in returned from the hcall when a HV exception
is sent to the vhyp. Register state is copied in and out according to
the nested KVM HV hcall API
On 16/02/2022, Emanuele Giuseppe Esposito wrote:
On 04/02/2022 11:07, Jon Doron wrote:
SynDbg commands can come from two different flows:
1. Hypercalls, in this mode the data being sent is fully
encapsulated network packets.
2. SynDbg specific MSRs, in this mode only the data that needs to
This moves the logic to reset the QEMU exception state into its own
function.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 41
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/target/ppc/excp_
On 16/02/2022, Emanuele Giuseppe Esposito wrote:
On 04/02/2022 11:07, Jon Doron wrote:
SynIc can be enabled regardless of the SControl mechanisim which can
register a GSI for a given SintRoute.
This behaviour can achived by setting enabling SIMP and then the guest
will poll on the message slo
On Dienstag, 15. Februar 2022 08:01:37 CET Greg Kurz wrote:
> On Mon, 14 Feb 2022 17:43:51 +0300
>
> Vitaly Chikunov wrote:
> > Why g_new0 and not just g_malloc0? This is smallest code change, which
> > seems appropriate for a bug fix.
>
> I prefer g_new0() for the exact reasons that are provide
On 16/02/2022, Emanuele Giuseppe Esposito wrote:
+
+static uint16_t handle_recv_msg(HvSynDbg *syndbg, uint64_t outgpa,
+uint32_t count, bool is_raw, uint32_t options,
+uint64_t timeout, uint32_t *retrieved_count)
+{
+uint16_t r
On 2/16/22 11:25, Nicholas Piggin wrote:
Introduce virtual hypervisor methods that can support a "Nested KVM HV"
implementation using the bare metal 2-level radix MMU, and using HV
exceptions to return from H_ENTER_NESTED (rather than cause interrupts).
HV exceptions can now be raised in the TCG
On 16/02/2022, Emanuele Giuseppe Esposito wrote:
On 04/02/2022 11:07, Jon Doron wrote:
Add all required definitions for hyperv synthetic debugger interface.
Signed-off-by: Jon Doron
---
include/hw/hyperv/hyperv-proto.h | 52
target/i386/kvm/hyperv-proto.h
> +static DisasJumpType op_sel(DisasContext *s, DisasOps *o)
> +{
> +DisasCompare c;
> +disas_jcc(s, &c, get_field(s, m4));
> +tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b,
> +o->in1, o->in2);
> +free_compare(&c);
> +return DISAS_NEXT;
> +}
On 2/16/22 11:25, Nicholas Piggin wrote:
This implements the Nested KVM HV hcall API for spapr under TCG.
The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
L1 is switched back in returned from the hcall when a HV exception
is sent to the vhyp. Register state is copied in and o
bdrv_refresh_limits() recurses down to the node's children. That does
not seem necessary: When we refresh limits on some node, and then
recurse down and were to change one of its children's BlockLimits, then
that would mean we noticed the changed limits by pure chance. The fact
that we refresh th
Add a parameter to optionally open a QMP connection when creating a
QemuStorageDaemon instance.
Signed-off-by: Hanna Reitz
---
tests/qemu-iotests/iotests.py | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/tests/qemu-iotests/iotests.py b/tests/
Hi,
v1 with detailed reasoning:
https://lists.nongnu.org/archive/html/qemu-block/2022-02/msg00508.html
This series makes bdrv_refresh_limits() non-recursive so that it is
sufficient for callers to ensure that the node on which they call it
will not receive concurrent I/O requests (instead of ensu
Test the following scenario:
1. Some block node (null-co) attached to a user (here: NBD server) that
performs I/O and keeps the node in an I/O thread
2. Repeatedly run blockdev-add/blockdev-del to add/remove an overlay
to/from that node
Each blockdev-add triggers bdrv_refresh_limits(), and b
Hi,
> Given the semantic differences from 'i440fx', changing the default
> machine type has effects that are equivalent to breaking command
> line syntax compatibility, which is something we've always tried
> to avoid.
And if we are fine breaking backward compatibility I'd rather *not* pick
a
On 2/15/22 4:32 PM, Andrew Jones wrote:
On Tue, Feb 15, 2022 at 04:19:01PM +0800, Gavin Shan wrote:
The issue isn't related to CPU topology directly. It's actually related
to the fact: the default NUMA node ID will be picked for one particular
CPU if the associated NUMA node ID isn't provided by
On 16.02.22 11:31, David Hildenbrand wrote:
>> +static DisasJumpType op_sel(DisasContext *s, DisasOps *o)
>> +{
>> +DisasCompare c;
>> +disas_jcc(s, &c, get_field(s, m4));
>> +tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b,
>> +o->in1, o->in2);
>> +
On 15.02.22 21:27, David Miller wrote:
> tests/tcg/s390x/mie3-compl.c: [N]*K instructions
> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
> tests/tcg/s390x/mie3-sel.c: SELECT instruction
>
(I know, a lot of mails from my side :) )
1. I think we usually use the prefix in the subject "tests/tcg
On 16.02.22 10:57, David Hildenbrand wrote:
> On 15.02.22 21:27, David Miller wrote:
>> tests/tcg/s390x/mie3-compl.c: [N]*K instructions
>> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
>> tests/tcg/s390x/mie3-sel.c: SELECT instruction
>>
>> Signed-off-by: David Miller
>> ---
>> tests/tcg/s39
* Gerd Hoffmann (kra...@redhat.com) wrote:
> Hi,
>
> > Given the semantic differences from 'i440fx', changing the default
> > machine type has effects that are equivalent to breaking command
> > line syntax compatibility, which is something we've always tried
> > to avoid.
>
> And if we are fi
On Tue, Feb 15, 2022 at 10:18:12AM -0800, Elena wrote:
> On Mon, Feb 14, 2022 at 02:37:21PM +, Stefan Hajnoczi wrote:
> > On Mon, Feb 07, 2022 at 11:22:18PM -0800, Elena Ufimtseva wrote:
> > > Signed-off-by: Elena Ufimtseva
> > > ---
> > > meson.build| 15 ++-
> > > qapi/
> /* Really format SS_b, but we pack both lengths into one argument
> @@ -735,6 +753,9 @@
> /* PACK UNICODE */
> C(0xe100, PKU, SS_f, E2, la1, a2, 0, 0, pku, 0)
> +/* POPULATION COUNT */
> +C(0xb9e1, POPCNT, RRE, PC, 0, r2_o, r1, 0, popcnt, nz64)
You actually need RRF
On Tue, Feb 15, 2022 at 10:16:04AM -0800, Elena wrote:
> On Mon, Feb 14, 2022 at 02:52:29PM +, Stefan Hajnoczi wrote:
> > On Mon, Feb 07, 2022 at 11:22:14PM -0800, Elena Ufimtseva wrote:
> > > This patchset is an RFC version for the ioregionfd implementation
> > > in QEMU. The kernel patches ar
On Wed, Feb 16, 2022 at 11:01:24AM +, Dr. David Alan Gilbert wrote:
> * Gerd Hoffmann (kra...@redhat.com) wrote:
> > Hi,
> >
> > > Given the semantic differences from 'i440fx', changing the default
> > > machine type has effects that are equivalent to breaking command
> > > line syntax comp
On 16/02/2022 12.01, Dr. David Alan Gilbert wrote:
* Gerd Hoffmann (kra...@redhat.com) wrote:
Hi,
Given the semantic differences from 'i440fx', changing the default
machine type has effects that are equivalent to breaking command
line syntax compatibility, which is something we've always
Excerpts from Cédric Le Goater's message of February 16, 2022 8:52 pm:
> On 2/16/22 11:25, Nicholas Piggin wrote:
>> This implements the Nested KVM HV hcall API for spapr under TCG.
>>
>> The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
>> L1 is switched back in returned from t
On 15/02/2022 23.10, Eric Blake wrote:
On Tue, Feb 15, 2022 at 02:20:31PM +0100, Thomas Huth wrote:
Instead of failing the iotests if GNU sed is not available (or skipping
them completely in the check-block.sh script), it would be better to
simply skip the bash-based tests that rely on GNU sed,
Am Mittwoch, 16. Februar 2022, 01:09:04 CET schrieb Atish Patra:
> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> property. It used to parse only the single letter base extensions
> until now. A generic ISA extension parsing framework was proposed[1]
> recently that can parse mult
We need a newer compiler to build upcoming tests that test for z15
features with -march=z15. So let's do it similar to arm64 and powerpc,
using an environment based on debian11 to build tests only.
Cc: Thomas Huth
Cc: Cornelia Huck
Cc: Richard Henderson
Cc: "Alex Bennée"
Cc: "Philippe Mathieu-
On 2/16/22 08:19, Gerd Hoffmann wrote:
> On Tue, Feb 15, 2022 at 07:37:40PM +, Joao Martins wrote:
>> On 2/15/22 09:53, Gerd Hoffmann wrote:
>>> What is missing:
>>>
>>> * Some way for the firmware to get a phys-bits value it can actually
>>>use. One possible way would be to have a paravi
Queued
* Vivek Goyal (vgo...@redhat.com) wrote:
> Hi,
>
> This is V6 of the patches. I posted V5 here.
>
> https://listman.redhat.com/archives/virtio-fs/2022-February/msg00012.html
>
> This patch series basically allows client to send a security context
> (which is expected to be xattr securit
ping
https://patchew.org/QEMU/20220113152836.60398-1-yaroshchuk2...@gmail.com/
чт, 13 янв. 2022 г. в 18:28, Vladislav Yaroshchuk :
> On Apple hosts we can read AppleSMC OSK key directly from host's
> SMC and forward this value to QEMU Guest.
>
> New 'hostosk' property is added:
> * `-device isa-a
* Vivek Goyal (vgo...@redhat.com) wrote:
> On Tue, Feb 15, 2022 at 07:15:29PM +0100, Greg Kurz wrote:
> > Honor the expected behavior of syncfs() to synchronously flush all data
> > and metadata to disk on linux systems.
> >
> > If virtiofsd is started with '-o announce_submounts', the client is
>
Looks straight forward to me.
[...]
>
> +int kvm_set_ioregionfd(struct kvm_ioregion *ioregionfd)
> +{
> +KVMState *s = kvm_state;
> +int ret = -1;
> +
> +ret = kvm_vm_ioctl(s, KVM_SET_IOREGION, ioregionfd);
> +if (ret < 0) {
> +error_report("Failed SET_IOREGION syscall r
On Tue, 8 Feb 2022, BALATON Zoltan wrote:
On Tue, 25 Jan 2022, BALATON Zoltan wrote:
v2 - Fixed checkpatch errors
Hello,
Ping?
Ping^2
https://patchew.org/QEMU/cover.1643117600.git.bala...@eik.bme.hu/
Regards,
BALATON Zoltan
I have these patches from last October when we've looked at wha
Excerpts from Nicholas Piggin's message of February 16, 2022 9:38 pm:
> Excerpts from Cédric Le Goater's message of February 16, 2022 8:52 pm:
>> On 2/16/22 11:25, Nicholas Piggin wrote:
>>> This implements the Nested KVM HV hcall API for spapr under TCG.
>>>
>>> The L2 is switched in when the H_E
Hi,
while researching the different "sed" options on our supported build
platform today, I started "make vm-build-haiku.x86_64" in my QEMU build
directory for the first time since many months again. And I had to discover
that this is completely out of date. The image does not contain any ve
Hi,
> What I overlooked was the emphasis you had on desktops (qemu default bigger
> than
> host-advertised), where I am thinking mostly in servers.
Yep, on servers you have the reverse problem that phys-bits=40 might be
too small for very large guests.
> > To make things even worse: The defa
Instead of failing the iotests if GNU sed is not available (or skipping
them completely in the check-block.sh script), it would be better to
simply skip the bash-based tests that rely on GNU sed, so that the other
tests could still be run. Thus we now explicitely use "gsed" (either as
direct progra
David Gibson writes:
> On Tue, Feb 15, 2022 at 06:41:47PM -0300, Fabiano Rosas wrote:
>> These will need to be accessed from other files once we move the CPUs
>> code to separate files.
>>
>> Signed-off-by: Fabiano Rosas
>> ---
>> target/ppc/cpu.h | 57
On Wed, Feb 16, 2022 at 12:13 PM Richard W.M. Jones
wrote:
> On Tue, Feb 15, 2022 at 05:24:14PM -0600, Eric Blake wrote:
> > Oh. The QMP command (which is immediately visible through
> > nbd-server-add/block-storage-add to qemu and qemu-storage-daemon)
> > gains "multi-conn":"on", but you may be
David Gibson writes:
> On Tue, Feb 15, 2022 at 06:41:43PM -0300, Fabiano Rosas wrote:
>> The important part of this function is that it applies to non-embedded
>> CPUs, not that it also applies to the 601. We removed support for the
>> 601 anyway, so rename this function.
>>
>> Signed-off-by: Fa
Eric Blake writes:
> According to the NBD spec, a server advertising
> NBD_FLAG_CAN_MULTI_CONN promises that multiple client connections will
> not see any cache inconsistencies: when properly separated by a single
> flush, actions performed by one client will be visible to another
> client, rega
huang...@chinatelecom.cn writes:
> From: Hyman Huang(黄勇)
>
> Implement dirtyrate calculation periodically basing on
> dirty-ring and throttle virtual CPU until it reachs the quota
> dirty page rate given by user.
>
> Introduce qmp commands "set-vcpu-dirty-limit",
> "cancel-vcpu-dirty-limit", "que
On Fri, Feb 11, 2022 at 3:41 AM Weiwei Li wrote:
>
> 在 2022/2/11 上午12:34, Christoph Muellner 写道:
> > The RISC-V base cache management operation ISA extension has been
> > ratified [1]. This patch adds support for the defined instructions.
> >
> > The cmo.prefetch instructions are nops for QEMU (n
Rohit Kumar writes:
> Qemu might crash when provided incomplete '-global' option.
> For example:
> qemu-system-x86_64 -global driver=isa-fdc
> qemu-system-x86_64: ../../devel/qemu/qapi/string-input-visitor.c:394:
> string_input_visitor_new: Assertion `str' failed.
> Aborted (c
On 2/16/22 10:56, Peter Maydell wrote:
Hi; this fails to build on OpenBSD (on the tests/vm/ setup).
Meson thinks it's found OpenGL:
OpenGL support (epoxy) : YES 1.5.4
but either it's wrong or else it's not putting the right
include directory onto the path, because the compiler
fails
David Hildenbrand writes:
> On 15.02.22 21:27, David Miller wrote:
>> tests/tcg/s390x/mie3-compl.c: [N]*K instructions
>> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
>> tests/tcg/s390x/mie3-sel.c: SELECT instruction
>>
>> Signed-off-by: David Miller
>> ---
>> tests/tcg/s390x/Makefile.t
On Wed, 16 Feb 2022 11:30:12 +0100
Christian Schoenebeck wrote:
> On Dienstag, 15. Februar 2022 08:01:37 CET Greg Kurz wrote:
> > On Mon, 14 Feb 2022 17:43:51 +0300
> >
> > Vitaly Chikunov wrote:
> > > Why g_new0 and not just g_malloc0? This is smallest code change, which
> > > seems appropriat
On 16.02.22 15:19, Alex Bennée wrote:
>
> David Hildenbrand writes:
>
>> On 15.02.22 21:27, David Miller wrote:
>>> tests/tcg/s390x/mie3-compl.c: [N]*K instructions
>>> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
>>> tests/tcg/s390x/mie3-sel.c: SELECT instruction
>>>
>>> Signed-off-by: Davi
On Wed, 16 Feb 2022 at 14:03, Paolo Bonzini wrote:
>
> On 2/16/22 10:56, Peter Maydell wrote:
> > Hi; this fails to build on OpenBSD (on the tests/vm/ setup).
> >
> > Meson thinks it's found OpenGL:
> > OpenGL support (epoxy) : YES 1.5.4
> >
> > but either it's wrong or else it's not pu
David Hildenbrand writes:
> We need a newer compiler to build upcoming tests that test for z15
> features with -march=z15. So let's do it similar to arm64 and powerpc,
> using an environment based on debian11 to build tests only.
>
> Cc: Thomas Huth
> Cc: Cornelia Huck
> Cc: Richard Henderson
On 16/2/22 10:21, Cédric Le Goater wrote:
From: Joel Stanley
This helps quieten booting the current Rainier kernel.
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm
On 16/2/22 10:21, Cédric Le Goater wrote:
From: Joel Stanley
Just a stub that indicates the system has booted in secure boot mode.
Used for testing the driver:
https://lore.kernel.org/all/20211019080608.283324-1-j...@jms.id.au/
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
-
On 16/2/22 10:21, Cédric Le Goater wrote:
From: Joel Stanley
It was scheduled for removal in 7.0.
Signed-off-by: Joel Stanley
Message-Id: <20220216080947.65955-1-j...@jms.id.au>
Signed-off-by: Cédric Le Goater
---
docs/about/deprecated.rst | 7 -
docs/system/arm/aspeed.rst | 1 -
On 16/2/22 11:19, Richard Henderson wrote:
On 2/16/22 04:01, Philippe Mathieu-Daudé via wrote:
GCC 10.1 introduced the -moutline-atomics option on Aarch64.
This options is enabled by default, and triggers a link failure:
Undefined symbols for architecture arm64:
"___aarch64_cas1_acq_rel
On Fri, Feb 11, 2022 at 08:26:10AM +0100, Klaus Jensen wrote:
> On Jan 26 18:11, Lukasz Maniak wrote:
> > Changes since v3:
> > - Addressed comments to review on pcie: Add support for Single Root I/O
> > Virtualization (SR/IOV)
> > - Fixed issues reported by checkpatch.pl
> >
> > Knut Omang (2):
On 16/2/22 13:54, Thomas Huth wrote:
Instead of failing the iotests if GNU sed is not available (or skipping
them completely in the check-block.sh script), it would be better to
simply skip the bash-based tests that rely on GNU sed, so that the other
tests could still be run. Thus we now explicit
On 16/2/22 14:54, Joseph Fitzgerald (KM1P) wrote:
Thank you for this trouble report.
We recommend that Philippe subscribe to the qemu mailing list via a
"real" mailing address rather than his f4...@amsat.org mail
alias/forwarding address.
Sigh, OK :(
There is some combination of the Free So
On Wed, Feb 16, 2022 at 12:39:06PM +0100, Thomas Huth wrote:
> > > -$SED -re 's/[0-9]{4}-[0-9]{2}-[0-9]{2}
> > > [0-9]{2}:[0-9]{2}:[0-9]{2}/-mm-dd hh:mm:ss/'
> > > +gsed -re 's/[0-9]{4}-[0-9]{2}-[0-9]{2}
> > > [0-9]{2}:[0-9]{2}:[0-9]{2}/-mm-dd hh:mm:ss/'
> >
> > GNU sed recommend
On 16/2/22 11:30, Christian Schoenebeck wrote:
On Dienstag, 15. Februar 2022 08:01:37 CET Greg Kurz wrote:
On Mon, 14 Feb 2022 17:43:51 +0300
Vitaly Chikunov wrote:
Why g_new0 and not just g_malloc0? This is smallest code change, which
seems appropriate for a bug fix.
I prefer g_new0() for
g (2022-02-15
> 19:30:33 +)
>
> are available in the Git repository at:
>
> g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220216
>
> for you to fetch changes up to 7035b8420fa52e8c94cf4317c0f88c1b73ced28d:
>
> docs/system: r
702/providers/libvirt.box";
-csum = "41c38b316e0cbdbc66b5dbaf3612b866700a4f35807cb1eb266a5bf83e9e68d5"
+link =
"https://app.vagrantup.com/haiku-os/boxes/r1beta3-x86_64/versions/20220216/providers/libvirt.box";
+csum = "e67d4aacbcc687013d5cc91990ddd86cc5d70a
* Peter Xu (pet...@redhat.com) wrote:
> It'll be easier to read the name rather than index of sub-cmd when debugging.
>
> Signed-off-by: Peter Xu
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/savevm.c | 3 ++-
> migration/trace-events | 2 +-
> 2 files changed, 3 insertions(+), 2
* Peter Xu (pet...@redhat.com) wrote:
> The enablement of postcopy listening has a few steps, add a few tracepoints to
> be there ready for some basic measurements for them.
>
> Signed-off-by: Peter Xu
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/savevm.c | 9 -
> migrati
The RISC-V base cache management operation ISA extension has been
ratified [1]. This patchset adds support for the defined instructions.
As the exception behavior of these instructions depend on the PMP
configuration, the first patch introduces a new API to probe the access
of an address range wit
The existing probe_access* functions do not allow to specify the
access size and a non-faulting behavior at the same time.
This is resolved by adding a generalization of probe_access_flags()
that takes an additional size parameter.
The semantics is basically the same as probe_access_flags(),
but
The RISC-V base cache management operation ISA extension has been
ratified. This patch adds support for the defined instructions.
The cmo.prefetch instructions are nops for QEMU (no emulation of the memory
hierarchy, no illegal instructions, no permission faults, no traps),
therefore there's only
February 16, 2022 6:31 AM, "Thomas Huth" wrote:
>
> while researching the different "sed" options on our supported build platform
> today, I started
> "make vm-build-haiku.x86_64" in my QEMU build directory for the first time
> since many months again.
> And I had to discover that this is comple
On Tue, Feb 8, 2022 at 9:25 AM Jason Wang wrote:
>
>
> 在 2022/2/1 下午7:45, Eugenio Perez Martin 写道:
> > On Sun, Jan 30, 2022 at 7:50 AM Jason Wang wrote:
> >>
> >> 在 2022/1/22 上午4:27, Eugenio Pérez 写道:
> >>> SVQ is able to log the dirty bits by itself, so let's use it to not
> >>> block migration.
Christian,
On Wed, Feb 16, 2022 at 11:30:12AM +0100, Christian Schoenebeck wrote:
> On Dienstag, 15. Februar 2022 08:01:37 CET Greg Kurz wrote:
> > On Mon, 14 Feb 2022 17:43:51 +0300
> >
> > Vitaly Chikunov wrote:
> > > Why g_new0 and not just g_malloc0? This is smallest code change, which
> > >
On Tue, Feb 15, 2022, 6:57 PM Philippe Mathieu-Daudé
wrote:
> On 16/2/22 00:53, John Snow wrote:
> > On Tue, Feb 15, 2022 at 5:55 PM Eric Blake wrote:
> >>
> >> On Tue, Feb 15, 2022 at 05:08:50PM -0500, John Snow wrote:
> >> print(enboxify(msg, width=72, name="commit message"))
> >>> ┏━ comm
On Mittwoch, 16. Februar 2022 17:09:56 CET Vitaly Chikunov wrote:
> Christian,
>
> On Wed, Feb 16, 2022 at 11:30:12AM +0100, Christian Schoenebeck wrote:
> > On Dienstag, 15. Februar 2022 08:01:37 CET Greg Kurz wrote:
> > > On Mon, 14 Feb 2022 17:43:51 +0300
> > >
> > > Vitaly Chikunov wrote:
>
The top level init_proc calls register_generic_sprs but also registers
some other SPRs outside of that function. Let's group everything into
a single place.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 58 ---
1 file
The /* XXX : not implemented */ comments all over cpu_init are
confusing and ambiguous.
Do they mean not implemented by QEMU, not implemented in a specific
access mode? Not implemented by the CPU? Do they apply to just the
register right after or to a whole block? Do they mean we have an
action to
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 41 ++---
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 330b765ba9..29f25e093f 100644
--- a/target/ppc/cpu_
Now that the 601 was removed, all of our CPUs have a timebase, so that
can be moved into the common function.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 98 ---
1 file changed, 18 insertions(+), 80 deletions(-)
dif
The goal of this series is to do some untangling of SPR registration
code in cpu_init.c and prepare for moving the CPU initialization into
separate files for each CPU family.
After this series we'll have only cpu-specific SPR code in cpu_init.c,
i.e. code that can be split and moved as a unit into
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 28 +---
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 711834a4c1..cae4ab69fe 100644
--- a/target/ppc/cpu_init.c
+++ b/t
The G2LE CPU initialization code is the same as the G2. Use the latter
for both.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 42 +-
1 file changed, 1 insertion(+), 41 deletions(-)
diff --git a/target/ppc/cpu_init.c
Make sure that every register_*_sprs function only has calls to
spr_register* to register individual SPRs. Do not allow nesting. This
makes the code easier to follow and a look at init_proc_* should
suffice to know what SPRs a CPU has.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
We're considering these two to be in different CPU families (6xx and
7xx), so keep their SPR registration separate.
The code was copied into register_G2_sprs and the common function was
renamed to apply only to the 755.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_
Move some of the 440 registers that are being repeated in the 440*
CPUs to register_440_sprs.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 100 +++---
1 file changed, 26 insertions(+), 74 deletions(-)
diff --git a/target
This is just to have 755-specific registers contained into a function,
intead of leaving them open-coded in init_proc_755. It makes init_proc
easier to read and keeps later patches that touch this code a bit
cleaner.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init
This function registers just one SPR and has only two callers, so open
code it.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_ini
Initial intent for the spr_tcg header was to expose the spr_read|write
callbacks that are only used by TCG code. However, although these
routines are TCG-specific, the KVM code needs access to env->sprs
which creation is currently coupled to the callback registration.
We are probably not going to
We're considering these two to be from different CPU families, so
duplicate some code to keep them separate.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 107 +++---
1 file changed, 91 insertions(+), 16 deletions(-)
diff
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 1eef006a04..330b765ba9 100644
--- a/target/ppc/cpu_init.c
+++ b/targ
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 68 +++
1 file changed, 11 insertions(+), 57 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 131c2da4c2..ea4ed19bde 100644
--- a/target/ppc/cp
This is done to improve init_proc readability and to make subsequent
patches that touch this code a bit cleaner.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 43 ---
1 file changed, 24 insertions(+), 19 deletions(-)
The 745 and 755 can share the HID registration, so move it all into
register_755_sprs, which applies for both CPUs.
Also rename that function to register_745_sprs, since the 745 is the
earliest of the two. This will help with separating 755-specific
registers in a subsequent patch.
Signed-off-by:
These will need to be accessed from other files once we move the CPUs
code to separate files.
The check_pow_hid0 and check_pow_hid0_74xx are too specific to be
moved to a header so I'll deal with them later when splitting this
code between the multiple CPU families.
Signed-off-by: Fabiano Rosas
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