On 21/06/11 12:48, Luis Cupido wrote:
Yes that right. Is clear that I would have a 10ns jitter,
So the catch would be to find a scheme to spread spurs out or to push
them away from carrier. Then they would not bother me (would not pass
the PLL).
You want to consider a phase-accumulator with a
Magnus,
It crossed my mind of messing somehow with the phase
accumulator metrics but did not figure a way...
that is a good suggestion I will investigate in that direction...
(or maybe... if you do have a bit of free time to drop me
a couple of lines more, could you please detail
a bit more as
Dear Luis,
On 07/21/2011 05:30 PM, Luis Cupido wrote:
Magnus,
It crossed my mind of messing somehow with the phase
accumulator metrics but did not figure a way...
that is a good suggestion I will investigate in that direction...
(or maybe... if you do have a bit of free time to drop me
a
IMHO, that would require a sine table with a steerable number
of entries. Very problematic for a tunable DDS, but doable
for a fixed frequency application, although address mirroring
for ROM size reduction would require real address comparators
instead just using the 2 MSBs as a selector.
The
Gerhard.
This was an old thing I asked a month ago or so...
Only the MSB of the accumulator is used to serve
as reference to a pll. No sin or DAC involved ;-)
Luis Cupido.
ct1dmk
On 7/21/2011 6:10 PM, dk...@arcor.de wrote:
IMHO, that would require a sine table with a steerable number
of
Your algorithm looks very much like the solution to the problem how to
find divider values in a rf receiver having a very low IF and *not* full
length divider chains for dividing all the needed reference frequencies.
So how to find two values connected.
Interesting.
- Henry
--
On 07/21/2011 07:10 PM, dk...@arcor.de wrote:
IMHO, that would require a sine table with a steerable number
of entries. Very problematic for a tunable DDS, but doable
for a fixed frequency application, although address mirroring
for ROM size reduction would require real address comparators
On 07/21/2011 08:44 PM, Jim Lux wrote:
On 7/21/11 8:30 AM, Luis Cupido wrote:
Magnus,
It crossed my mind of messing somehow with the phase
accumulator metrics but did not figure a way...
that is a good suggestion I will investigate in that direction...
(or maybe... if you do have a bit of free
Thanks Jim,
Joseph already pointed me to a pdf in a previous post.
Now it is digestion time... should I say congestion !!!
those MASH delta-sigmas are killing me...
lc.
ct1dmk.
On 6/23/2011 4:30 AM, Jim Lux wrote:
On 6/22/11 3:36 PM, Luis Cupido wrote:
I knew I must not have been the fist
I knew I must not have been the fist one to be looking for such.
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919
(unfortunately I'm not ieee member and $30 looks more like a
book price to me... not an article... bahhh!)
Luis Cupido.
ct1dmk.
On 6/21/2011 11:48 AM, Luis Cupido
Subject:Re: [time-nuts] DDS'ery narrow scoped.
Sent by:time-nuts-boun...@febo.com
On 6/22/11 3:36 PM, Luis Cupido wrote:
I knew I must not have been the fist one to be looking for such.
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919
(unfortunately I'm not ieee member and $30 looks more like a
book price to me... not an article... bahhh!)
Luis Cupido.
Hello,
El 21/06/2011 02:19, Luis Cupido escribió:
Imagine an FPGA and a square wave coming out.
Just that. Nothing more.
(That is what I had in mind when querying about the MSB usage in
the first place.)
My first approach was the ACC MSB
(and that is working already on the bench.)
I
But I forgot to add that the resultant jitter will be also the sampling
rate period (10ns at 100MHz), so I think that the output will not be too
clean... so I'm afraid it will not be a great improvement over using
only the MSB :)
Regards,
Javier
El 21/06/2011 08:37, Javier Herrero escribió:
-Ursprüngliche Nachricht-
Von: time-nuts-boun...@febo.com
[mailto:time-nuts-boun...@febo.com] Im Auftrag von John Miles
Gesendet: Dienstag, 21. Juni 2011 00:52
An: 'Discussion of precise time and frequency measurement'
Betreff: Re: [time-nuts] DDS'ery
I'm not familiar with Altera's DDS
An: Discussion of precise time and frequency measurement
Betreff: [time-nuts] DDS'ery narrow scoped.
Folks,
Many thanks to you all, for the info.
This is indeed a great forum.
My aplic. is a DDS signal that
will serve as reference for a pll with a relatively
narrow loop filter. As I said
, 07731
732-886-5960 office
908-902-3831 cell
-Original Message-
From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On
Behalf Of Ulrich Bangert
Sent: Tuesday, June 21, 2011 5:03 AM
To: 'Discussion of precise time and frequency measurement'
Subject: Re: [time-nuts] DDS'ery
to provide SFDR up to 150 dB (and I'd notice it if I were
getting much less than that in practice.)
has pushed me up! When I tell the compiler to generate me a 150 dB SFDR
DDS
then it produces an block with 28 (!) bits output witdh for the DAC. So, I
am asking myself what wonder-chips
-boun...@febo.com
[mailto:time-nuts-boun...@febo.com] Im Auftrag von John Miles
Gesendet: Dienstag, 21. Juni 2011 00:52
An: 'Discussion of precise time and frequency measurement'
Betreff: Re: [time-nuts] DDS'ery
I'm not familiar with Altera's DDS options, but I will say
that Xilinx's DDS compiler
Hi Ulrich,
Loop bandwidth could be in the KHz region
or even less.
I could choose more or less freely from Hz to many KHz
but there are obvious tradeoffs and it is hard to decide.
The phase noise of the VCO when I go too narrow versus
the ammount of spurs when I go too wide.
Application is the
Yes that right. Is clear that I would have a 10ns jitter,
So the catch would be to find a scheme to spread spurs out or to push
them away from carrier. Then they would not bother me (would not pass
the PLL).
lc
ct1dmk.
On 6/21/2011 7:43 AM, Javier Herrero wrote:
But I forgot to add that
I've played with the core from altera for a while, but since I was only
interested in 1 bit I'm now playing with my own code. Trivial variations
on the plain old clocked accumulator architecture.
lc
On 6/21/2011 7:37 AM, Javier Herrero wrote:
What it the topology you're using now? Also, I
Auftrag von John Miles
Gesendet: Dienstag, 21. Juni 2011 00:52
An: 'Discussion of precise time and frequency measurement'
Betreff: Re: [time-nuts] DDS'ery
I'm not familiar with Altera's DDS options, but I will say
that Xilinx's DDS compiler is superb. It can be configured
to provide SFDR up to 150
Clever! At least for your spectral measurements the signal never leaves the
digital domain. What is the width of the multipliers involved in the mixing?
Can you give me a clue, which ADCs you are working with in the front end?
In this application, DDS artifacts would ultimately show up as
time and frequency measurement
time-nuts@febo.com
Datum: 20.06.2011 22:26
Betreff: Re: [time-nuts] DDS'ery
With the coordic (yeah, sometimes cordic), you need to build it a few more
bits wider than the DAC. Then it closely matches the lookup table. One of
the best references for the coordic I
On 6/21/11 6:14 AM, dk...@arcor.de wrote:
There is an excellent article about cordic on
http://www.andraka.com/files/crdcsrvy.pdf
Yes..good explanation..
So, in the general case where you might want to rotate by an arbitrary
angle at each time step, where the angle doesn't happen
-Original Message-
From: time-nuts-boun...@febo.com [mailto:time-nuts-
boun...@febo.com] On Behalf Of Ulrich Bangert
Sent: Tuesday, June 21, 2011 4:37 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] DDS'ery
Clever! At least for your spectral
On 06/21/2011 04:29 PM, Jim Lux wrote:
On 6/21/11 6:14 AM, dk...@arcor.de wrote:
There is an excellent article about cordic on
http://www.andraka.com/files/crdcsrvy.pdf
Yes..good explanation..
So, in the general case where you might want to rotate by an arbitrary
angle at each time step,
Folks, a quick one...
A DDS, that is an accumulator with a DAC followed by a low pass filter
and comparator (zero crossing) to produce a square wave to drive a PLL
or a MIXER or else (at logic levels).
Isn't it the very same thing as just using the most significant bit of
the accumulator.
In message 4dff5d29.2070...@mail.ua.pt, Luis Cupido writes:
Isn't it the very same thing as just using the most significant bit of
the accumulator.
Indeed it is, and that's how programmable digital clocks often work.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
p...@freebsd.org
Forgot the sine table...
I meant obviously ...an accumulator 'sine table' and DAC...
lc.
On 6/20/2011 3:46 PM, Luis Cupido wrote:
Folks, a quick one...
A DDS, that is an accumulator with a DAC followed by a low pass filter
and comparator (zero crossing) to produce a square wave to drive a PLL
Hello,
No, it is not the same. If you just use the MSB of the accumulator, it
has a lot of period jitter. It can be unnoticeable if the ration between
reference frequency and output frequency is very high.
Think on the process inversely: draw a sine wave, and sample it at for
example 4.3
In message 4dff5f2f.7050...@hvsistemas.es, Javier Herrero writes:
No, it is not the same. If you just use the MSB of the accumulator, it =
has a lot of period jitter. It can be unnoticeable if the ration between =
reference frequency and output frequency is very high.
In practice, this jitter is
Luis:
No, not the same.
The most significant bit out of the accumulator has the alias information
on it (Fs +/- Fo), so it still needs to be run through the low pass filter
to clean off the alias signals. The alias signals manifest themselves
as jitter,
so no amount of just clipping will
The jitter when taking only the MSB is same as the DDS clock period. I
don't think that squaring the filtered sinewave you will get that jitter
(of course, if you square the sinewave with no filtering, you will get
the same jitter that taking only the MSB). In fact, it is the reason
that
Thanks for the comments...
Yes the key is obviously the low pass filtering
one has the other doesn't.
I had mainly in my mind a PLL following that ACC.
so actually driving a phase comparator of
a PLL (narrow enough loop bw) that problem would
not exist. Ok great.
Good point on the mixer we got
Well, if we really need to filter it out
we better filter the MSB and square it
again...
Why having a DAC for ???
Right ?
Luis Cupido.
ct1dmk.
___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
To reduce the spurii due to quantization distortion. Here is an
explanation, in Section 4
http://www.analog.com/static/imported-files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf
Regards,
Javier
El 20/06/2011 17:39, Luis Cupido escribió:
Well, if we really need to filter it out
we better
: Re: [time-nuts] DDS'ery
Luis:
No, not the same.
The most significant bit out of the accumulator has the alias information
on it (Fs +/- Fo), so it still needs to be run through the low pass filter
to clean off the alias signals. The alias signals manifest themselves
as jitter,
so no amount
Gracias, Javier.
As you read in my previous email I'm basically
worried about close-in spurs (those that
will pass through the PLL loop filter).
will digest that 4th section... tks.
...
Since I'm inside an FPGA... I'm eager to get
spurs down without leaving the digital world...
Anyone knows
On Mon, 20 Jun 2011 16:39:16 +0100
Luis Cupido cup...@mail.ua.pt wrote:
Well, if we really need to filter it out
we better filter the MSB and square it
again...
Why having a DAC for ???
Right ?
If you filter a square wave, you have a lot more harmonics than
if you filter a signal that
De nada, Luis :)
I've been playing around a bit with Altera NCO IP (in fact, I need to
implement a digital NCO quite shortly for a project, although in this
case close-in spurs are more tolerable than in other applications). A
lot of information in the application note for ADI is also
On 6/20/11 7:46 AM, Luis Cupido wrote:
Folks, a quick one...
A DDS, that is an accumulator with a DAC followed by a low pass filter
and comparator (zero crossing) to produce a square wave to drive a PLL
or a MIXER or else (at logic levels).
Isn't it the very same thing as just using the most
On 6/20/11 8:39 AM, Luis Cupido wrote:
Well, if we really need to filter it out
we better filter the MSB and square it
again...
Why having a DAC for ???
Spur content heading into the filter.. the sine table and DAC greatly
reduces the harmonic content of the output, which makes filtering
On 6/20/11 9:46 AM, Luis Cupido wrote:
Gracias, Javier.
As you read in my previous email I'm basically
worried about close-in spurs (those that
will pass through the PLL loop filter).
will digest that 4th section... tks.
...
Since I'm inside an FPGA... I'm eager to get
spurs down without
12:04:24
To: time-nuts@febo.com
Reply-To: Discussion of precise time and frequency measurement
time-nuts@febo.com
Subject: Re: [time-nuts] DDS'ery
On 6/20/11 9:46 AM, Luis Cupido wrote:
Gracias, Javier.
As you read in my previous email I'm basically
worried about close-in spurs (those
Jim Lux wrote:
On 6/20/11 9:46 AM, Luis Cupido wrote:
Gracias, Javier.
As you read in my previous email I'm basically
worried about close-in spurs (those that
will pass through the PLL loop filter).
will digest that 4th section... tks.
...
Since I'm inside an FPGA... I'm eager to get
spurs
...@earthlink.net
Sender: time-nuts-boun...@febo.com
Date: Mon, 20 Jun 2011 12:04:24
To:time-nuts@febo.com
Reply-To: Discussion of precise time and frequency measurement
time-nuts@febo.com
Subject: Re: [time-nuts] DDS'ery
On 6/20/11 9:46 AM, Luis Cupido wrote:
Gracias, Javier.
As you read in my
-To: Discussion of precise time and frequency measurement
time-nuts@febo.com
Subject: Re: [time-nuts] DDS'ery
Inside an FPGA, CORDIC can be implemented performing quite fast. An
open-source implementation of CORDIC algorithm and a DDS using look-up
table or CORDIC can be found in OpenCores
On Mon, 20 Jun 2011 20:26:46 +
li...@lazygranch.com wrote:
With the coordic (yeah, sometimes cordic), you need to build it
a few more bits wider than the DAC. Then it closely matches the lookup
table. One of the best references for the coordic I found was a PhD
dissertation at Stanford.
Not even remotely. Try it.
-- john, KE5FX
-Original Message-
From: time-nuts-boun...@febo.com [mailto:time-nuts-
boun...@febo.com] On Behalf Of Poul-Henning Kamp
Sent: Monday, June 20, 2011 8:04 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts
Kinali
To: li...@lazygranch.com
To: Discussion of precise time and frequencymeasurement
Subject: Re: [time-nuts] DDS'ery
Sent: Jun 20, 2011 2:35 PM
On Mon, 20 Jun 2011 20:26:46 +
li...@lazygranch.com wrote:
With the coordic (yeah, sometimes cordic), you need to build it
a few more bits wider than
-boun...@febo.com [mailto:time-nuts-
boun...@febo.com] On Behalf Of Luis Cupido
Sent: Monday, June 20, 2011 9:46 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] DDS'ery
Gracias, Javier.
As you read in my previous email I'm basically
worried about close
Unfortunately, my google skills fail me to locate a digital copy of this
dissertation.
My Google-fu is pretty decent. You can apparently order a PDF for web download
for $37 from:
http://proquest.umi.com/pqdlink?did=753152421Fmt=7clientId
=79356RQT=309VName=PQD
I say apparently because I
On 6/20/11 12:17 PM, li...@lazygranch.com wrote:
Just a FYI, you don't have to use sine lookup tables. You can generate sine and
cosine on the fly with a coordic. Perhaps not easy at RF speed, but very common
in audio DSP.
It's a tradeoff.. To do CORDIC you need four multiplies and 2 adds,
Folks,
Many thanks to you all, for the info.
This is indeed a great forum.
My aplic. is a DDS signal that
will serve as reference for a pll with a relatively
narrow loop filter. As I said before.
Most replies presume the analog world with DAC
filters etc etc. But that I know ;-)
I'm digging
measurementtime-nuts@febo.com
Reply-To: Discussion of precise time and frequency measurement
time-nuts@febo.com
Subject: Re: [time-nuts] DDS'ery
On 6/20/11 12:17 PM, li...@lazygranch.com wrote:
Just a FYI, you don't have to use sine lookup tables. You can generate sine
and cosine
of precise time and frequency measurement
Subject: Re: [time-nuts] DDS'ery
I don't have the algorithm in front of me, but I don't recall any
multiplication, just addition and magnitude comparison.
-Original Message-
From: Jim Lux jim...@earthlink.net
Sender: time-nuts-boun...@febo.com
That is maybe interesting to you:
http://www.holmea.demon.co.uk/Projects.htm#Frac
- Henry
--
ehydra.dyndns.info
Luis Cupido schrieb:
P.S. At the moment I'm testing on the bench with a real FPGA cyclone III
with a 48bit dds at 100MHz fclock and at circa 6 and 18MHz output and it
is not that
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