J.D. Bakker wrote:
At 23:49 +1200 14-08-2010, Bruce Griffiths wrote:
J.D. Bakker wrote:
At 19:01 +1200 14-08-2010, Bruce Griffiths wrote:
J.D. Bakker wrote:
However the ultimate test (other than breadboarding it) is to
actually simulate the sampling process and look at the deviation of
the
Hi
I think that adding ADC zero and gain drift would be a good idea.
Considering that the hardware will be doing an early/on-time/late
calibration cycle every second in between PPS pulses, it should be
relatively safe to assume that drift will be calibrated out, no? If
you keep the ADC/uC
At 23:49 +1200 14-08-2010, Bruce Griffiths wrote:
J.D. Bakker wrote:
At 19:01 +1200 14-08-2010, Bruce Griffiths wrote:
J.D. Bakker wrote:
However the ultimate test (other than breadboarding it) is to
actually simulate the sampling process and look at the deviation of
the sampled voltages
Hi
I think that adding ADC zero and gain drift would be a good idea.
Bob
On Aug 15, 2010, at 9:19 PM, J.D. Bakker j...@lartmaker.nl wrote:
At 23:49 +1200 14-08-2010, Bruce Griffiths wrote:
J.D. Bakker wrote:
At 19:01 +1200 14-08-2010, Bruce Griffiths wrote:
J.D. Bakker wrote:
However
J.D. Bakker wrote:
At 08:30 +1200 14-08-2010, Bruce Griffiths wrote:
J.D. Bakker wrote:
4) If the ADC(s) have a sufficiently wide full power bandwidth then
one could just sample a pair of quadrature phased 250kHz sinewaves.
As someone who's used to thinking in I/Q I must say I've always
At 19:01 +1200 14-08-2010, Bruce Griffiths wrote:
J.D. Bakker wrote:
At 08:30 +1200 14-08-2010, Bruce Griffiths wrote:
Using a synchroniser allows the TAC output range to be combined
with the coarse timestamp derived by sampling a counter clocked by
the same clock as the synchroniser.
I
J.D. Bakker wrote:
At 19:01 +1200 14-08-2010, Bruce Griffiths wrote:
J.D. Bakker wrote:
At 08:30 +1200 14-08-2010, Bruce Griffiths wrote:
Using a synchroniser allows the TAC output range to be combined
with the coarse timestamp derived by sampling a counter clocked by
the same clock as the
Yet another option is to sample the output of a simple 1us time constant
RC low pass filter and fit an exponential to the sampled data and
calculate the threshold crossing from this.
If the aberrations are sufficiently low over the range of time intervals
measured (0.5us to 1us with a
Thank you for your comments. Replies inline:
At 11:37 +1200 13-08-2010, Bruce Griffiths wrote:
1) Use a 74AHC05 for Q1 and Q2.
I was looking at the 74LVC1G07. It's a single gate, so probably less
package parasitics to worry about. Output capacitance is actually
specified (5pF typ); charge
At 21:08 -0400 12-08-2010, Bob Paddock wrote:
On Thu, Aug 12, 2010 at 6:45 PM, J.D. Bakker j...@lartmaker.nl wrote:
To start with the context: I'm planning to use a microcontroller with a
built-in dual 12-bit 2MSPS ADC.
That sounds like it is an Atmel XMega part. Do make sure you read the
Hi
Doing the ADC with the micro based parts I'm familiar with would be a
challenge. Lots of other options there though.
Bob
On Aug 13, 2010, at 1:59 AM, Bruce Griffiths bruce.griffi...@xtra.co.nz wrote:
Yet another option is to sample the output of a simple 1us time constant RC
low pass
At 08:30 +1200 14-08-2010, Bruce Griffiths wrote:
J.D. Bakker wrote:
4) If the ADC(s) have a sufficiently wide full power bandwidth
then one could just sample a pair of quadrature phased 250kHz
sinewaves.
As someone who's used to thinking in I/Q I must say I've always
liked the elegance of
Hello all,
I'm working on Yet Another DIY GPSDO, and one of the issues I've been
looking into is a TAC/TDC to do sawtooth correction on the
measurement of the GPS PPS signal. I'd like to stick with a 3.3V
supply for most of the circuit, and several of the TAC designs that
have been discussed
Some options:
1) Use a 74AHC05 for Q1 and Q2.
2) Switch the current source at the emitter node and only turn on the
current source when charging the capacitor.
This will increase the available TAC output voltage range and/or improve
the linearity by eliminating the diode.
However the
Another method is to attenuate (to within the ADC input range) the PPS
signal to be timestamped, low pass filter it and capture a 2MSPS sample
burst centred around the low pass filter output transition midpoint.
You can then use WKS interpolation to time stamp the transition midpoint
(when it
On Thu, Aug 12, 2010 at 6:45 PM, J.D. Bakker j...@lartmaker.nl wrote:
To start with the context: I'm planning to use a microcontroller with a
built-in dual 12-bit 2MSPS ADC.
That sounds like it is an Atmel XMega part. Do make sure you read the data
sheet errata section, as some parts in the
Hi
Would't you want 2 or more samples during the transition?
Bob
On Aug 12, 2010, at 8:25 PM, Bruce Griffiths bruce.griffi...@xtra.co.nz wrote:
Another method is to attenuate (to within the ADC input range) the PPS signal
to be timestamped, low pass filter it and capture a 2MSPS sample
Yes, with a 2MSPS ADC and 1-2us transition times one gets 2-4 samples
during the transition.
Worst case with a 1us filter (10%-90%) output transition time there may
be one sample at the midpoint and samples close to the 10% and 90%
amplitude points.
2us transition times are probably close to
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