Am 16.09.2012 21:46, schrieb Richard (Rick) Karlquist:
Again, a really high speed comparator necessarily has a really broad
bandwidth, meaning its noise bandwidth is large. This means more
noise and more jitter than a lower speed comparator. The comparator
cited is much faster than necessary f
On 9/16/2012 12:03 PM, Gerhard Hoffmann wrote:
Am 20.07.2012 00:57, schrieb Richard (Rick) Karlquist:
A fast comparator seems like a good idea, and it
is simple, however it is actually the last thing
you want to use. High thermal sensitivity and high jitter.
Rick
On 7/19/2012 1:35 PM, Dan K
Am 20.07.2012 00:57, schrieb Richard (Rick) Karlquist:
A fast comparator seems like a good idea, and it
is simple, however it is actually the last thing
you want to use. High thermal sensitivity and high jitter.
Rick
On 7/19/2012 1:35 PM, Dan Kemppainen wrote:
Or use a fast comparator such as
ly 23, 2012 8:37 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Zero-Crossing Detector Design?
Hi Bob,
No, never tried but it looks a good idea.
Our boards all have 5v so there was never any pressure...
... for a 0.5v in the tail resistor to vcc and 0.7v of
Of ct1dmk
Sent: Monday, July 23, 2012 7:26 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Zero-Crossing Detector Design?
For the specific application of driving an FPGA clock pin (that has an
enormous input bandwidth) many things can go wrong.
All fine about the
Subject: Re: [time-nuts] Zero-Crossing Detector Design?
For the specific application of driving an FPGA clock pin (that has an
enormous input bandwidth) many things can go wrong.
All fine about the advantages and disadvantages of
the gate with resistor feedback, all I can say is that over here I it
was
For the specific application of driving an FPGA clock pin (that has an
enormous input bandwidth) many things can go wrong.
All fine about the advantages and disadvantages of
the gate with resistor feedback, all I can say is that over here I it
was not the best solution
we found over many FPGA bo
On 7/22/2012 2:41 PM, Bob Camp wrote:
Hi
The feedback inverter is indeed a problem with fast logic, just bias it to mid
point off the supply instead.
1. Do not use CMOS inverters. Even though so much has been published on
using these in linear mode by
adding a feedback resistor, they c
Narrow filters have high tempco on their group delay, so that's no good either.
Didier KO4BB
Bill Fuqua wrote:
>Wow, I have not checked this list for some time. But there is a lot
>said
>about zero crossing detectors.
>Lots and lots of replies, so many that I have not looked at all of
>them.
>
Hi
The feedback inverter is indeed a problem with fast logic, just bias it to mid
point off the supply instead.
Narrow filters can be both a good and a bad thing at the same time. They clean
up the signal, but the also have delay. If they are narrow enough they have
lots of delay. That would b
Wow, I have not checked this list for some time. But there is a lot said
about zero crossing detectors.
Lots and lots of replies, so many that I have not looked at all of them.
1. Do not use CMOS inverters. Even though so much has been published on
using these in linear mode by
adding a fee
Hi
There are papers on limiters in radio IF's going back at least into the 1930's.
That's a long... list.
Bob
On Jul 22, 2012, at 3:36 PM, ehydra wrote:
> Maybe, it is on my list for the university IEEE download for months.
>
> And this is the only reference?
> I have seen some similar issues
Maybe, it is on my list for the university IEEE download for months.
And this is the only reference?
I have seen some similar issues in a few BPSK receiver papers. Not for
time-nuting but for S/N.
- Henry
Magnus Danielson schrieb:
On 07/22/2012 01:39 AM, Bob Camp wrote:
HI
The Collins pap
On 07/22/2012 01:39 AM, Bob Camp wrote:
HI
The Collins paper that Bruce referred to is the standard work on limiters /
jitter / bandwidth. It can't and doesn't address all the possible issues in a
full blown design. The math for the basic approach is all there though.
Indeed. It's a good and
HI
The Collins paper that Bruce referred to is the standard work on limiters /
jitter / bandwidth. It can't and doesn't address all the possible issues in a
full blown design. The math for the basic approach is all there though.
Bob
On Jul 21, 2012, at 6:45 PM, ehydra wrote:
> Interesting d
Interesting discussion but I must say I had several times a
brain-problem here ;-)
Am I right that for that this is in general not fully understood? Are
there interesting papers?
I'm interested here for two points:
1. What is the right threshold for a comparator and on what it depends?
Looks l
Only for the Nuts,
ZCD have been discussed at great length this time and before, and bandwidth
can be a major issue, but still much is being left out.
With a little care, one can easily get to 1ns type accuracy, with the
various suggestions,
but that only gives 1e-9 / sec of accuracy, not even c
Good, I've learned also that bandwidth can matter and that a ZCD test can
done by comparison: feed the counter or TSC or TimePod or 'scope with your
source signal and 2 cables, then insert the ZCD and see the difference.
Actually I'm interested in a ZCD to feed the FPGA from the OCXO, I'm using
a 7
> I see that from one way or the other, we always end up in a TimePod. OK,
> then the TimePod has no comparator, no trigger but has A to D conversions.
> Is the A/D conversion process supposed to be threshold-free?
Hey, everybody needs at least one or two TimePods. :) You can use a TimePod
or TS
On 07/21/2012 03:30 AM, Hal Murray wrote:
albertson.ch...@gmail.com said:
Maybe, but it is absolutely needed if there is any noise on the signal.
A
perfect comparator with zero hysteresis would dither on every zero
crossing.
On 07/21/2012 01:41 AM, Hal Murray wrote:
Hysterssis will elimina
> albertson.ch...@gmail.com said:
>>> Maybe, but it is absolutely needed if there is any noise on the signal.
A
>>> perfect comparator with zero hysteresis would dither on every zero
crossing.
> On 07/21/2012 01:41 AM, Hal Murray wrote:
>> Hysterssis will eliminate spikes or double pulses that
On 07/21/2012 01:41 AM, Hal Murray wrote:
albertson.ch...@gmail.com said:
Hysteresis does nothing to eliminate jitter or temperature
Maybe, but it is absolutely needed if there is any noise on the signal. A
perfect comparator with zero hysteresis would dither on every zero crossing.
Hyst
On 07/21/2012 01:28 AM, Azelio Boriani wrote:
Yes, using a 'scope and the persistence it seems possible to "visualize"
the results.
Exactly.
It's very instructive to see the traces separate appart as result of
deterministic jitter, or just see the soft edges from the random jitter.
I forgot
albertson.ch...@gmail.com said:
>> Hysteresis does nothing to eliminate jitter or temperature
> Maybe, but it is absolutely needed if there is any noise on the signal. A
> perfect comparator with zero hysteresis would dither on every zero crossing.
Hysteresis doesn't eliminate the dither from
Yes, using a 'scope and the persistence it seems possible to "visualize"
the results.
On Sat, Jul 21, 2012 at 1:03 AM, Magnus Danielson <
mag...@rubidium.dyndns.org> wrote:
> On 07/21/2012 12:09 AM, Azelio Boriani wrote:
>
>> OK, very interesting. Now is it possible to measure/verify this? I thin
On 07/21/2012 12:09 AM, Azelio Boriani wrote:
OK, very interesting. Now is it possible to measure/verify this? I think
that using any test equipment, the comparator-style approach is
unavoidable: the trigger of the scope or the counter cannot be an
amplifier/limiter.
If you like to verify what
I see that from one way or the other, we always end up in a TimePod. OK,
then the TimePod has no comparator, no trigger but has A to D conversions.
Is the A/D conversion process supposed to be threshold-free? Maybe, in this
case, the DTMD is the only analog and threshold-free way.
On Sat, Jul 21,
Hi
Simple test:
1) Run sine wave into a power splitter
2) Run one port to your limiter / zero crossing detector / what ever
3) Run other port from the power splitter into the "reference" port on a DTMD,
5125, or (better yet) TimePod.
4) Route the output of the limiter to the "input" port on t
OK, very interesting. Now is it possible to measure/verify this? I think
that using any test equipment, the comparator-style approach is
unavoidable: the trigger of the scope or the counter cannot be an
amplifier/limiter. How to tell what is up to my design under test and what
is the trigger contri
On 07/20/2012 07:42 AM, Chris Albertson wrote:
On Thu, Jul 19, 2012 at 5:47 PM, Rick Karlquist wrote:
Hysteresis does nothing to eliminate jitter or temperature
Maybe, but it is absolutely needed if there is any noise on the
signal. A perfect comparator with zero hysteresis would dither o
On Thu, Jul 19, 2012 at 5:47 PM, Rick Karlquist wrote:
>
> Hysteresis does nothing to eliminate jitter or temperature
Maybe, but it is absolutely needed if there is any noise on the
signal. A perfect comparator with zero hysteresis would dither on
every zero crossing.
Chris Albertson
Redondo
On 7/19/12 4:09 PM, Magnus Danielson wrote:
On 07/20/2012 12:33 AM, li...@lazygranch.com wrote:
Are you speaking of slew rate limiting in the strict sense of the
word, that is a current starved input stage due to the presence of a
compensation cap? Or are you using the term slew more vaguely.
The reason I suggested using a schmidt trigger gate is that a schmidt
trigger gate switches states at different points at its input. That is, the
input positive going switch point is higher than the negative going switch
point, maybe half a volt or so. So, driving this gate with a volt RMS or
Chris Albertson wrote:
>
>
> The comparator will work but you need some positive feedback to create
> hysteresis. The problem is the hysteresis cause the output square
> wave to be not quite 50% duty cycle. But maybe you don't care if the
> goal is to count cycles. or if you only look at (say) r
On Thu, Jul 19, 2012 at 3:57 PM, Richard (Rick) Karlquist
wrote:
> A fast comparator seems like a good idea, and it
> is simple, however it is actually the last thing
> you want to use. High thermal sensitivity and high jitter.
The comparator will work but you need some positive feedback to cre
Hi
I think I'd call that a limiter rather than a zero crossing detector, that is
indeed a bit picky.
I think you will have better luck with a fixed bias on the input to the first
inverter rather than with the 1 meg feedback resistor. With the feedback
resistor the inverter tends to self oscill
Michael wrote:
One circuit I was recommended when I was looking for ideas uses a 1M
resistor to feed the output of the inverter back to the input to self-bias
That works OK, but you have to be careful. Without an input signal,
there can be excessive quiescent current through the inverter (Vc
On 07/19/2012 07:36 PM, Al Wolfe wrote:
Chris,
The simplest zero crossing detector would be to feed your 1 volt, 10
mHz from the XL-DC into the input of an IC with schmidt trigger inputs.
You would need to provide a series coupling cap and probably some DC
bias from a pot to adjust symmetry o
square wave somewhere inside the box before it is converted to a sine wave
that could be used for your application.
Al
Subject: [time-nuts] Zero-Crossing Detector Design?
Can anyone suggest a good reference design for a zero-crossing detector? I
am trying to home an ADC sampler trigger to the
On 07/20/2012 01:19 AM, li...@lazygranch.com wrote:
That was worth the elaboration. 2*pi*f*A is the classic design criteria used to
insure your amplifier has sufficient slew rate for the task, where I am using
slew in the strict sense of the word. Generally we use dv/dt when referring to
the s
That was worth the elaboration. 2*pi*f*A is the classic design criteria used to
insure your amplifier has sufficient slew rate for the task, where I am using
slew in the strict sense of the word. Generally we use dv/dt when referring to
the signal and slew when referring to the amplifier.
Hey,
On 07/20/2012 12:57 AM, Richard (Rick) Karlquist wrote:
A fast comparator seems like a good idea, and it
is simple, however it is actually the last thing
you want to use. High thermal sensitivity and high jitter.
Once your signal has past by a comparator, you can't "treat it" to
remove the noi
On 07/20/2012 12:33 AM, li...@lazygranch.com wrote:
Are you speaking of slew rate limiting in the strict sense of the word, that is
a current starved input stage due to the presence of a compensation cap? Or are
you using the term slew more vaguely.
I am speaking neither.
If you have a sine
A fast comparator seems like a good idea, and it
is simple, however it is actually the last thing
you want to use. High thermal sensitivity and high jitter.
Rick
On 7/19/2012 1:35 PM, Dan Kemppainen wrote:
Or use a fast comparator such as an ADCMP600 series. Much lower delays,
and faster risin
, 20 Jul 2012 00:15:58
To:
Reply-To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Zero-Crossing Detector Design?
On 07/19/2012 11:53 PM, ehydra wrote:
> On the Bruce page there is a table with increasing stage amplification
> from low-level to the
, 20 Jul 2012 00:15:58
To:
Reply-To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Zero-Crossing Detector Design?
On 07/19/2012 11:53 PM, ehydra wrote:
> On the Bruce page there is a table with increasing stage amplification
> from low-level to the
I always add " site:febo.com " to my google time-nut searches. It
cuts out the sites that copy or refer to the list. You may also want to
click on " More search tools" in the left column and then click on
Verbatim. That stops google from substituting things in your search
string. Sometime
On 07/19/2012 11:53 PM, ehydra wrote:
On the Bruce page there is a table with increasing stage amplification
from low-level to the output.
If this is the optimum for low jitter how does it connect to the
well-known rf design philosophy to have the highest amplification at the
first stage, not the
Hi
The numbers change rather dramatically if you are looking at the 1 to 10 Hz
sine wave out of a beat note system…
Bob
On Jul 19, 2012, at 3:47 PM, Bruce Griffiths wrote:
> The problem of optimal zero crossing detector design was essentially solved
> by Oliver Collins in the 1990's.
> Essent
On the Bruce page there is a table with increasing stage amplification
from low-level to the output.
If this is the optimum for low jitter how does it connect to the
well-known rf design philosophy to have the highest amplification at the
first stage, not the last stage, to have maximum S/N ?
Thank you, Bruce!!! That is exactly the information I was looking for. I
sincerely appreciate the help.
-CH
On Jul 19, 2012, at 12:47, Bruce Griffiths wrote:
> The problem of optimal zero crossing detector design was essentially solved
> by Oliver Collins in the 1990's.
> Essentially a series
Actually, I being new to the list, I do not feel I the correct verbiage. That
said, I will do better on keeping the noise down. Again, my thanks.
-CH
On Jul 19, 2012, at 12:23, paul swed wrote:
> you can search time-nuts there has been a number of very good discussions
> on this.
> Sorry to sa
The problem of optimal zero crossing detector design was essentially
solved by Oliver Collins in the 1990's.
Essentially a series of cascaded limiter stages with appropriate gain
and bandwidth distribution are used.
With a 10MHz 1V rms signal only 2-3 stages suffices.
However unless you need fs
Yes, there are no FAQ but you can search the archive. I don't know how to
search the archive because usually I start with google, adding "time-nuts"
to narrow down the search.
On Thu, Jul 19, 2012 at 9:23 PM, paul swed wrote:
> you can search time-nuts there has been a number of very good discus
you can search time-nuts there has been a number of very good discussions
on this.
Sorry to say how you search is equally a good question.
On Thu, Jul 19, 2012 at 3:19 PM, Chris Hoffman, KG6O wrote:
> Thank you, Azelio! I don't suppose there's an impromptu FAQ page out
> there, is there?
>
> -CH
Thank you, Azelio! I don't suppose there's an impromptu FAQ page out there, is
there?
-CH
On Jul 19, 2012, at 11:58, Azelio Boriani wrote:
> This is sort of a FAQ: the argument was already discussed here. One of the
> most interesting idea (in my opinion) is to use an RS485 line receiver like
This is sort of a FAQ: the argument was already discussed here. One of the
most interesting idea (in my opinion) is to use an RS485 line receiver like
the ST3485, MAX483, ADM485. They are actually transceivers so they must be
tied permanently in RX. Since they are differential you can also put a 1:
Can anyone suggest a good reference design for a zero-crossing detector? I am
trying to home an ADC sampler trigger to the 1VRMS (50ohm) 10MHz sin from my
XL-DC... And now I'm thinking that I should just home the uC clock to it, as
well.
Essentially, I believe that I'm looking for an efficient,
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