Jeff Epler wrote:
> On Mon, Aug 25, 2008 at 09:01:27PM -0500, Jon Elson wrote:
> 
>>This is the parallel port (EPP) version.
> 
> 
> With at least a few systems, the problem goes deeper than this: the FPGA
> firmware is programmed each time over the parallel-port in SPP mode.
> One machine we had at CNC Workshop wouldn't even complete this step
> successfully with the example "blink the LED" FPGA firmware.
Yes, I saw you struggling with it there.  The problem is these 
FPGAs are very fast, and a 1 or 2 ns bounce on the config clock 
or JTAG clock line could be interpreted as two clocks.  They 
assume that you are filtering whatever signals you are sending 
to the FPGA or that they are being sent from a microprocessor a 
few inches away, not from a long cable.  I know that downloading 
Xilinx FPGAs and even CPLDs using the parallel port can be a 
problem, and some motherboards just don't work.  Open up a 
Xilinx DLC5 (Parallel Cable III) or look up the schematic on 
their web site to see some of the filtering junk they need to 
do.  An IEEE-1284 cable should be better than the usual printer 
cable, at least for the strobe lines, but they STILL suffer from 
a lot of crosstalk.  I have built some custom gadgets at work 
that use IEEE-1284 over 30+ foot cables.  I made my own cables 
out of twisted-pair ribbon cable, with a separate pair for each 
signal, including all the data lines.  This works flawlessly.

I'd be willing to bet a meal at the next Workshop that this is 
either a crosstalk or reflection problem on whatever signal is 
used to clock the config data into the FPGA.  A custom cable, or 
just pluging the board right into the par port connector on the 
computer might prove it, although that doesn't FIX the problem 
in a practical way.  It may need RC filters and a Schmitt 
trigger on the board to really fix it.

Jon

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