On Tue, Aug 26, 2008 at 12:08:10PM -0500, Jon Elson wrote: > I'd be willing to bet a meal at the next Workshop that this is > either a crosstalk or reflection problem on whatever signal is > used to clock the config data into the FPGA. [...] I don't doubt *at all* that you're right about all these sources of problems on the pluto-p board. The board seems to be designed to minimize component count, which means that NONE of the methods you describe to mitigate or fix noise/crosstalk/bounce are on it.
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