At 12:35 PM 6/16/01 -0700, Jim McGrath wrote:
>Abd ul-Rahman Lomax wrote:
[...]
> > I'd think of using component classes to
> > determine the connection type and then I'd place blowout pads to disconnect
> > the appropriate pads according to layer. These blowout pads could be part
> > of the footprints for this customer [....]
>
>If I understand, this works for through hole comps (which should work I never
>considered it) but what about the vias? Even if I use a free pad I don't
>have the
>control I need. I really don't want to add extra pins to a lib part in the
>case
>of a SMT component.
With free pads you can have as much control as you have with component
pads. Give the free pad a name according to how you want it treated.
Suppose we wanted a via to be direct connect instead of thermally relieved.
Use a free pad instead of a via. A free pad is basically a smart via, that
is, it has additional attributes; in this case the attribute of interest is
its name. If we name it "DC" we can set a pad scope design rule for Free-DC
to give all such pads thermal reliefs. (The example is a bit strange: vias
should normally be direct connect...)
>The editing of plane hits needs to be done at board level. I have a lib part
>that is say, an soic16. Ground isn't always on the same pin so I need the
>flexibility in the interconnect stage (actually this affects the footprint
>for the
>thru hole described above as well).
I still think that there might be a value in putting extra through pads in
an SMT part. These pads could manually be edited to the appropriate pin
number so that they would be assigned the ground net, and they could be
moved around (after unlocking primitives, and then relocking). They could
likewise be deleted if not needed.
However, another way to go would be to disconnect the plane ties. Once the
board is designed, the set of pads that need to be disconnected from a
plane would be highlighted (using a sequence of global edits or the
selection wizard). Component and pad classes would also help with this.
Then one would move around the board popping inner plane "pads" on the
highlighted pads, which would disconnect the through-pad from the plane. A
disadvantage, however, would be that DRC would no longer detect that a pad
was disconnected from ground by an incorrectly placed blowout pad. Mr.
McGrath's technique of manipulating the gerbers has the advantage that it
is correct by procedure; it is a single procedure, which can be done carefully.
> > That the board work might mean that all this effort is *harmless*. But it
> > is expensive to add two layers.
>
>I try so save the customer dollars in Fab by reducing layers etc. that is
>part of
>my value. But this has been discussed and they are adamant that the removal of
>the additional gnd layers is not an option.
Since my suspicions as to why they might want to be doing this have been
confirmed, I'll now say that they are absolutely right, using extra ground
planes is a common and accepted technique for clean high-speed design of
boards of high layer count. In most cases the VCC plane functions as if it
were ground as well, especially if it is physically close to the ground
plane, so it could be said that even a four-layer board (two signal, two
inner power) has two ground planes. But the problem with such a four-layer
board is, that if it is standard board thickness (0.065 inch), and if the
traces must be narrow, and if they must be 50 ohm traces, the spacing
between the inner planes becomes too large. So even in this case, one might
bring the power planes close together, like 5 mils apart, and add two
ground planes at the appropriate depth underneath the surface signal
traces. These planes serve for tight ground return for signal traces.
What is *not* standard is keeping the planes separate as Mr. McGrath has
described. I've always seen, with the extra planes, ground vias and
"return" vias connecting to all ground planes. Maintaining separate planes
for power and for signal return strikes me as possibly being a vestige of
old thinking. Those planes are going to be fairly well-coupled anyway; but
the return current will follow the closest path in relation to the signal
trace. Disconnecting the return vias from the ground plane will have, I'd
predict, no measureable effect on signal integrity.
To remind our readers, this is the scheme Mr. McGrath described:
(I'll add some details that he did not explicitly mention; he can correct
me if I got it wrong.)
There is an inner pair of layers used for GND and POWER. Assuming this is a
six-layer board, these are layers 3 and 4
Layers 2 and 5 are also ground planes. (Four more signal layers can be
added to the board, two between original layers 2 and 3, and two more
between original layers 4 and 5. Adding only two can run into some
impedance problems, but I won't go any deeper into that). And then he wrote
in his description:
>The IC's and connectors, etc. hit all three planes
>Filter Caps only connect to the inner most ground plane
>and any signal that must pass through the "core power/ground" pair
>must have a return ground via that only connects to the 2 outer most
>ground planes.
This is rather obviously a six-layer stack, because it only considers the
possibility that signals are running on the two outer layers. The placing
of the return via allows the return current to follow the signal current.
That current will run in the plane under the signal trace; wherever it must
detour a substantial distance, impedance will increase and reflections and
noise radiation will result. When a signal moves from layer 1 to layer 6,
if there were no signal via and if there were only two planes (i.e., four
layer board), the return current would move through interplane capacitance
to the other power plane, assuming that the planes are close enough, or it
would detour to the closest bypass capacitor. If edge rates are not too
high, it may be sufficient to have bypass capacitors placed such that every
signal via is not far from one. For maximum integrity, one places a return
via paired with the signal via. On a four layer board, that obviously won't
work, because the via would short the power and ground plane together. But
a bypass capacitor, at least at lower rates, serves this purpose.
Adding the two additional ground planes allows vias to be used for
establishing tight return path. But what is unorthodox is keeping the
ground via disconnected from the power ground plane. The planes are already
stitched together by all the IC grounds. Adding the extra ground path will
do no harm, I'd predict. And it makes design a lot easier.
But there are other ways to go. Since this design does not appear to have
additional, separate power and ground, noise isolation does not appear to
be the issue. If there is a tight coupling between the power and ground
planes, such as will be produced by having a gap between them of 5 mils or
even less, either plane can serve as a return path with little effect on
impedance. But one would still make the boards six layers. Signal traces
would be run on layers 2 and 5, at the appropriate distance above the power
and ground planes. Traces on layers 1 and 6 will need to be wider to keep
impedance constant. A signal moving between layer 1 and 2 is not changing
return plane, and likewise with 5 and 6. Signals moving from one side of
the board to the other (between 1 or 2 and 5 or 6) will switch planes, but
the interplane capacitance, and, to a lesser extent, the bypass capacitors,
will normally provide sufficient coupling. Only to wring the last drop of
integrity from a design would one go to the stackup described. It's very
likely overkill; but, then again, this is what engineers are for (to decide
if it is or is not overkill).
My complain is that our field is *very much* long on theory and opinion and
short on actual experiment. There are a few people out there working to
change this; I read as much as I can find of their work. Even it is fairly
primitive, compared to how much money is being spent on high-speed design.
Every company just wants to get its designs out the door, so they will
overdesign and make their magic incantations (after all, it can't hurt --
they think), but they won't actually find out what is needed, because it is
always considered too expensive to do so. Yes, it's too expensive, if one
is only going to do one design. But if a company is going to do hundreds or
thousands of designs, perhaps it would be worthwhile actually determining
what works and what does not, what is needed and what is overkill. Some of
the magic tricks, very likely, actually harm signal integrity, but no one
checks. If the design works, that's enough; on to the next one. If it
doesn't work, there is mass panic and even more magic and money is tossed
into the board. Eventually -- usually -- the board finally works, and no
one knows if it was the extra two layers or maybe it was moving that IC.
I've seen boards with termination resistors stuck all over them, trying to
dampen reflections. And then the design is sold to another company and it
is someone else's problem. And no one really knows anything more than they
knew when they started, except perhaps how to fix problems that should not
arise in the first place if the design is done correctly.
I did a lot of two-layer digital design, with gridded power. It's a miracle
that these boards worked; actually a testimony to digital noise immunity.
We *expected* digital boards to be noisy, and they lived up to our
expectations. I bought and assembled an Altair 8800 computer, the
proverbial original home computer, back in 1975. One of the first things I
did with it, once I expanded the memory from 256 bytes to 1K, was to
program it with a series of loops so that it would play Sailor's Hornpipe
through any nearby AM radio tuned to a multiple of the clock frequency.
High Speed Digital Design, a Handbook of Black Magic, by Johnson and
Graham, was a real eye-opener. I'd love to quote some of it here, but time
constraints ....
> > If I were working for the client here, I'd suggest that they have a board
> > fabbed both ways, one as described and the other without manipulation: the
> > vias connect to all layers, as do the bypass caps and other parts. One
> > experiment is worth a thousand engineers theorizing until their heads hurt.
>
>I get the point but I don't work for that many customers with pockets
>That deep.
And they will stay that way, or at least that kind of thinking will weigh
in that direction (shallow pockets). They are obviously doing many designs.
The cost of making a prototype board, especially if it is relatively small,
would be only a few hundred dollars at one of the places that makes onesies
and twosies for cheap. More significant, as pointed out by another writer,
would be the engineer's time to evaluate the boards. But if they don't
already have the equipment and skills to do that evaluation, one wonders
what in the world they are doing attempting high-speed design. No, I think
they could do it.
But the thinking Mr. McGrath is describing is very common. Obviously, it's
not his job, as a contract designer (that what he is, I understand) to do
this kind of testing. But it is our job as designers to know about this
stuff, we can't depend on the engineers to spoon-feed it to us. Is keeping
those vias isolated doing any good or is it harmful? It is definitely
harmful in terms of the time it takes to do the design, but that harm is
not large (though it is repeated with every design). But relying on the
extra planes -- and they *are* extra planes -- if they are not needed is
costing them handsomely, in the long run. If the same or better results
could be gained with four layers with heavy distribution of bypass
capacitors -- which is good for other reasons as well--, or with six layers
with two outer routing layers on each side (as described in Johnson and
Graham in figure 5.26, take out the inner four layers), either board cost
will be cut in half or design flexibility will greatly increase.
By the way, I landed a major client at one time by mentioning to the
engineer that I was reading Johnson and Graham. "So am I," he said, and
then we had a lot to talk about....
For our non-engineer designers, there is a lot of math in Johnson and
Graham's book, but there is also a lot which does not require following the
calculations....
[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433
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