re: http://www.garlic.com/~lynn/2017c.html#81 GREAT presentation on the history of the mainframe http://www.garlic.com/~lynn/2017c.html#82 Great mainframe history(?) http://www.garlic.com/~lynn/2017c.html#83 Great mainframe history(?) http://www.garlic.com/~lynn/2017c.html#84 Great mainframe history(?) http://www.garlic.com/~lynn/2017c.html#85 Great mainframe history(?) http://www.garlic.com/~lynn/2017c.html#86 GREAT presentation on the history of the mainframe http://www.garlic.com/~lynn/2017c.html#87 GREAT presentation on the history of the mainframe http://www.garlic.com/~lynn/2017c.html#88 GREAT presentation on the history of the mainframe http://www.garlic.com/~lynn/2017c.html#89 GREAT presentation on the history of the mainframe http://www.garlic.com/~lynn/2017c.html#94 GREAT presentation on the history of the mainframe http://www.garlic.com/~lynn/2017c.html#95 GREAT presentation on the history of the mainframe http://www.garlic.com/~lynn/2017d.html#1 GREAT presentation on the history of the mainframe http://www.garlic.com/~lynn/2017d.html#3 GREAT presentation on the history of the mainframe
even more 3090 trivia: before starting work on LLNL fibre channel standard (pair of fibre-optic dedicated to transmission in each direction, original getting 1gbit/sec concurrent, full-duplex, 2gbit/sec aggregate) ... LANL started standardization of the Cray 100mbyte/sec parallel channel. HIPPI https://en.wikipedia.org/wiki/HIPPI there then forms some competition between LLNL FCS and LANL HIPPI, where HIPPI is being extended to serial HIPPI fiber optic and 200MB/s. 3090 added vector processing as part of playing in the supercomputer market ... however that required that they also be able to support 100mbyte/sec (and/or 1gbit/sec) I/O. 3090 was barely able to get up to 4.5mbyte/sec transfers ... so what to do? turns out that physical memory packaging had created a problem for 3090 and to address the problem they came up with memory hierarchy with extended store ... wide, fast bus with instructions to syncronously move 4k bytes between processor memory and extended store memory (although the memory chip technology was the same). The extended store interface turns out to be the only part of 3090 capable of handling the data rate. There is kludge that hooks HIPPI I/O interface into reserved addresses in the extended store bus ... and a sort of PC I/O paradigm using sort of peek/poke convention for doing I/O (extended store bus instructions moving data to/from these reserved addresses). That enables being to attach things like 40mbyte/sec disk arrays to 3090. There was lab. in kinstaon that worked with these kinds of applications ... but it was populated with dozen FPS (floating point systems) boxes that included 40mbyte/sec disk array support as part of native environment. one of projects I had was HSDT and was suppose to get $20M from the director of NSF to interconnect the NSF supercomputer centers (or at least before congress cuts the budget). However, one of my internal HSDT links was into the (IBM) kingston datacenter that had all these FPS boxes. some past HSDT posts http://www.garlic.com/~lynn/subnetwork.html#hsdt some past 3090 extended store posts http://www.garlic.com/~lynn/2006.html#16 Would multi-core replace SMPs? http://www.garlic.com/~lynn/2008i.html#10 Different Implementations of VLIW http://www.garlic.com/~lynn/2013g.html#41 A History Of Mainframe Computing http://www.garlic.com/~lynn/2013h.html#3 The cloud is killing traditional hardware and software http://www.garlic.com/~lynn/2013i.html#50 The Subroutine Call http://www.garlic.com/~lynn/2013m.html#99 SHARE Blog: News Flash: The Mainframe (Still) Isn't Dead http://www.garlic.com/~lynn/2017b.html#69 The ICL 2900 past posts mentioning FPS boxes (and 40mbyte/sec disk arrays in the mid-80s) http://www.garlic.com/~lynn/2000c.html#5 TF-1 http://www.garlic.com/~lynn/2000c.html#61 TF-1 http://www.garlic.com/~lynn/2001b.html#56 Why SMP at all anymore? http://www.garlic.com/~lynn/2001d.html#32 Imitation... http://www.garlic.com/~lynn/2001m.html#25 ESCON Data Transfer Rate http://www.garlic.com/~lynn/2002e.html#31 Hardest Mistake in Comp Arch to Fix http://www.garlic.com/~lynn/2002i.html#12 CDC6600 - just how powerful a machine was it? http://www.garlic.com/~lynn/2002j.html#30 Weird http://www.garlic.com/~lynn/2003b.html#29 360/370 disk drives http://www.garlic.com/~lynn/2003g.html#68 IBM zSeries in HPC http://www.garlic.com/~lynn/2003m.html#20 360 Microde Floating Point Fix http://www.garlic.com/~lynn/2006m.html#4 The Power of the NORC http://www.garlic.com/~lynn/2006o.html#1 harris http://www.garlic.com/~lynn/2009j.html#54 A Complete History Of Mainframe Computing http://www.garlic.com/~lynn/2010b.html#72 Happy DEC-10 Day http://www.garlic.com/~lynn/2010f.html#61 Handling multicore CPUs; what the competition is thinking http://www.garlic.com/~lynn/2011h.html#74 Vector processors on the 3090 http://www.garlic.com/~lynn/2011n.html#36 Last Word on Dennis Ritchie http://www.garlic.com/~lynn/2012n.html#28 390 vector instruction set reuse, was 8-bit bytes http://www.garlic.com/~lynn/2013g.html#41 A History Of Mainframe Computing http://www.garlic.com/~lynn/2013g.html#44 What Makes code storage management so cool? http://www.garlic.com/~lynn/2014b.html#4 IBM Plans Big Spending for the Cloud ($1.2B) http://www.garlic.com/~lynn/2014b.html#5 IBM Plans Big Spending for the Cloud ($1.2B) http://www.garlic.com/~lynn/2014j.html#35 curly brace languages source code style quides http://www.garlic.com/~lynn/2014j.html#36 curly brace languages source code style quides -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
