On Tue, Feb 2, 2010 at 1:16 PM, Luca Barbieri <l...@luca-barbieri.com> wrote:
>>  Personally I'm
>> going to take a break from this thread, spend a couple of days looking
>> at i965, etc, to see what can be done to improve things there, and
>> maybe come back with an alternate proposal.
>
> Yes, I think that the most important step is to precisely determine
> how both hardware (and especially the newer cards you mentioned) works
> and how shader APIs (especially DirectX) are defined.
>

On AMD r6xx and newer asics, the hardware provides 8 bit semantic ids
that are used for vertex fetches and shader to shader routing.  See:
http://www.x.org/docs/AMD/R6xx_R7xx_3D.pdf
pages 10-11, 16-17
The driver can define the ids to whatever it wants and then data will
be routed based on those ids.  E.g.,

#define POSITION     1
#define COLOR0       2
#define TEXCOORD0 3
etc.

then in your fetch shader:
vfetch POSITION
vfetch TEXCOORD0
vfetch COLOR0

and in your vs output:
export COLOR0
export TEXCOORD0
export POSITION

and in your ps inputs:
input TEXCOORD0
input COLOR0

etc.

The ordering doesn't matter all routing is done by semantic id.
There's no need to recompile your vertex shaders or pixel shaders, you
just adjust the fetch shader and sematic exports/imports state
accordingly.

The current r600 classic mesa driver just uses a hardcoded mapping
right now, but it would make sense to use semantic ids in the gallium
driver.

Alex

> Once the workings of both are known and agreed upon, the best solution
> should be hopefully be clear.
>
> In addition to looking at hardware such as i965, it would be awesome
> to find some clear and unambiguous documentation on DirectX shader
> semantics. and agree on its interpretation.
>
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