On Mar 3, 3:32 pm, Cactus <rieman...@googlemail.com> wrote:
> On Mar 3, 3:07 pm, Jeff Gilchrist <jeff.gilchr...@gmail.com> wrote:
>
> > On Tue, Mar 3, 2009 at 9:58 AM, Bill Hart <goodwillh...@googlemail.com>
> > wrote:
> > > So I hope we are not just looking at architecture differences
> > > between your core2 and that machine here.
>
> > There are architectural changes between the 65nm and 45nm Core2
> > processors, and the Xeon's tend to have much larger cache sizes so
> > that might be playing a role.
>
> > Brian, what are the specs for your Core 2 machine? I will see if I
> > can find a Core2 machine that I can test both the Linux code and
> > Windows code on the same system. I'm not sure where to grab the
> > mpirbench or the cycle test code, I don't seem to see it anywhere
> > obvious inside trunk/.
>
> My machine is a Dell M65 portable as follows:
>
> Intel Mobile Core 2 Duo T7400 running at 2.16GHz
>
> Merom at 65nm, family 6, model F, stepping 6
>
> L1 2 x 32 KBytes data
> L1 2 x 3 2KBytes instructions
> L2 4096 KBytes
>
> Memory 2GBytes DDR2
>
> Brian
I have now graphed results for mpn_add_n on four systems: JM and my
K8's, Bill's Linux Core2 and my Windows Core2. I have uploaded
mpn_add_n.pdf with the results which show that my Windows results are
anomalous. K8 -> 1.7 cycles/limb, Linux Core2 -> 2.3 cycles/limb,
Windows Core2 -> 4.3 cycles/limb.
What is odd is that the assembler code files for this function are
identical in the AMD and Core2 builds. And if I run my AMD binary on
my Core2 it runs at 4.3 cycles/limb.
So is this something to do with the way mobile Core2 machines are
configured to cut power when not under load?
Does power saving cause this sort of effect - the difference in the
results is much smaller when the high cost benchmarks are run (mul and
sqr).
Brian
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