On Dienstag, 27. Februar 2018 01:23:08 CET Christopher Head wrote: > Second, I discovered that, in both algorithm-driven mode and direct > programming mode, the loop writes to CR, then writes one halfword of data > to the target address, then checks BSY and the error flags in SR. However, > this seems unnecessary. CR doesn’t magically change on its own; PG and > PSIZE can be set once and then many writes performed in a block, increasing > efficiency. Also, it is not necessary to check BSY after each write. Step 3 > of the Flash programming sequence is to “perform the data write > operation(s)”, which can be plural. If you manage to deliver data too fast, > the Flash hardware stalls the AHB or AXI bus cycles doing the subsequent > writes, which eventually translates into a WAIT JTAG response (in the > direct programming case) or a CPU execution stall (in the algorithm-driven > case), which is a reasonable flow control mechanism. The error bits in SR > are also cumulative. Taken together, all this means that one can simply > write CR once, write all the data, and then check SR afterwards, waiting > for the last write to finish and examining the error flags. Once modifying > the code to do this, I then discovered that direct-mode programming with > these changes is actually faster than algorithm-based programming without > them (I was not able to successfully modify the algorithm to omit these > extra operations, but I can’t see it making a whole lot of difference to > the execution time in algorithm mode.
I'm guessing that the BUSY check was done to explicitly to avoid a JTAG WAIT, which was an error condition not long ago. It might still break with SWD. -- Mit freundlichen Grüßen/Best regards, Matthias Welwarsky Project Engineer SYSGO AG Office Mainz Am Pfaffenstein 14 / D-55270 Klein-Winternheim / Germany Phone: +49-6136-9948-0 / Fax: +49-6136-9948-10 VoIP: SIP:m...@sysgo.com E-mail: matthias.welwar...@sysgo.com / Web: http://www.sysgo.com _________________________________________________________________________________ Web: https://www.sysgo.com Blog: https://www.sysgo.com/blog Events: https://www.sysgo.com/events Newsletter: https://www.sysgo.com/newsletter _________________________________________________________________________________ Handelsregister/Commercial Registry: HRB Mainz 90 HRB 8066 Vorstand/Executive Board: Etienne Butery (CEO), Kai Sablotny (COO) Aufsichtsratsvorsitzender/Supervisory Board Chairman: Marc Darmon USt-Id-Nr./VAT-Id-No.: DE 149062328 ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ OpenOCD-devel mailing list OpenOCD-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openocd-devel
