On Dienstag, 27. Februar 2018 23:23:47 CET Christopher Head wrote: > On February 27, 2018 2:42:25 AM PST, Matthias Welwarsky <matthias.welwar...@sysgo.com> wrote: > >I'm guessing that the BUSY check was done to explicitly to avoid a JTAG > >WAIT, > >which was an error condition not long ago. It might still break with > >SWD. > > Ah, I didn’t know that WAIT was ever considered an error. From reading the > ARM debug infrastructure spec, it looked more like a flow control > mechanism. I see now that OpenOCD appears to enable ORUNDETECT (at least I > think it does, based on dap_dp_init in arm_adi_v5.c).
Before 0.10.0, WAIT was indeed an error condition. I wrote the support for WAIT for JTAG transport, it's a bit tricky since for performance reasons, we have to use deep queues and ORUNDETECT which considerably changes the DAP behaviour due to its 'stickyness' and requires a complex machinery to detect and replay the transactions following and including the one causing the WAIT. With an active probe that has knowledge of the DAP protocol it's dead simple, but for USB-connected shift registers - not so. > According to the ADI specification, SWD also has a WAIT response, which it > issues in case a previous transaction is outstanding. It says just the same > as JTAG: if WAIT is received, normally a debugger just resends the same > transaction. Although using sticky overrun mode changes the format a bit so > that WAIT is followed by a data packet, which it would not be with > ORUNDETECT cleared, and you have to clear the sticky status bit. I never got the opportunity to extend the WAIT code to also cover SWD. I simply don't have a platform using SWD transport that is not using CMSIS-DAP or another high-level adapter. But if you have the motivation - just go ahead, I'll be happy to assist. BR, Matthias -- Mit freundlichen Grüßen/Best regards, Matthias Welwarsky Project Engineer SYSGO AG Office Mainz Am Pfaffenstein 14 / D-55270 Klein-Winternheim / Germany Phone: +49-6136-9948-0 / Fax: +49-6136-9948-10 VoIP: SIP:m...@sysgo.com E-mail: matthias.welwar...@sysgo.com / Web: http://www.sysgo.com _________________________________________________________________________________ Web: https://www.sysgo.com Blog: https://www.sysgo.com/blog Events: https://www.sysgo.com/events Newsletter: https://www.sysgo.com/newsletter _________________________________________________________________________________ Handelsregister/Commercial Registry: HRB Mainz 90 HRB 8066 Vorstand/Executive Board: Etienne Butery (CEO), Kai Sablotny (COO) Aufsichtsratsvorsitzender/Supervisory Board Chairman: Marc Darmon USt-Id-Nr./VAT-Id-No.: DE 149062328 ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ OpenOCD-devel mailing list OpenOCD-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openocd-devel
