On 01.03.2018 10:25, Matthias Welwarsky wrote:
WAITs are very strange. It looks like the stalled access to flash
blocks also JTAG access to RAM.
And SWD access doesn't suffer this silicon bug... who knows... maybe
some NOPs in algo busy wait loop would fix it.
BTW The programming algo should avoid bus stalling, shouldn't it?
I was wondering about this.
It's not really all that wonderous, since it's the DAP that stalls, and the
DAP is single-issue. So of course once you run into a WAIT condition, it will
only clear when the DAP has completed the access that caused it, and
to complete it, you have to, well, wait. Note that when you receive the WAIT,
it is the _previous_ access that is still pending, not the one you received
the WAIT for.
But the write algo is designed to avoid WAIT condition. And why WAIT
does not appear
when SWD transport is used?
To complicate things further: the same test on STM32F413-nucleo runs
*without any problems*.
What OpenOCD version do you use? It looks like your version misses
Matthias' WAIT handling
if you get such errors like algo timeout.
I don't think algo-timeout has to do with the DAP stalling. Isn't algo-timeout
just that the algorithm running on the core is not reporting back to the
debugger? The debugger is waiting for the target to execute a breakpoint so
that it gets back control, right?
I meant possible errors induced from sticky state to target handling.
Maybe nonsense, ok.
Christopher, did you get algo timeouts and unpowered dbg regions on FTDI?
OMG, we all forget about the important thing: JTAG clock to bus clock
ratio!!!
I run the example app on the F722nucleo (which sets up some faster
clock), halt and *without* reset init
test flashing - no WAITs this time!
And it explains why STM32F4 worked - reset init sets up 64 MHz clock
(unlike STM32F7 where the out-of-reset HSI 16 MHz clock is used).
Seems like in this particular case the rule "adapter_khz <= F_CPU/6" is
not sufficient.
Not surprisingly if we want fast algo programming we also need
reasonably fast CPU clock.
Tom
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