On March 1, 2018 2:55:37 AM PST, Tomas Vanek via OpenOCD-devel <openocd-devel@lists.sourceforge.net> wrote: >I meant possible errors induced from sticky state to target handling. >Maybe nonsense, ok. >Christopher, did you get algo timeouts and unpowered dbg regions on >FTDI
Yes, I got those messages when using the original, unmodified algorithm on FTDI. I also got those messages when using ByteBlaster, but only after modifying the algorithm to remove the CR/SR accesses from the loop; with those in the loop, ByteBlaster gave me lots of WAITs but generally no errors. >OMG, we all forget about the important thing: JTAG clock to bus clock >ratio!!! >I run the example app on the F722nucleo (which sets up some faster >clock), halt and *without* reset init >test flashing - no WAITs this time! >And it explains why STM32F4 worked - reset init sets up 64 MHz clock >(unlike STM32F7 where the out-of-reset HSI 16 MHz clock is used). >Seems like in this particular case the rule "adapter_khz <= F_CPU/6" is > >not sufficient. >Not surprisingly if we want fast algo programming we also need >reasonably fast CPU clock Interesting! I had used F4 in the past and I think it didn’t print WAIT messages, whereas WAIT messages showed up for F7. I never reported them because I thought WAIT was just normal flow control. I tried, on the F7, switching to 64 MHz clock, as the F4 does, just now as an experiment, using the FTDI. I got a lot of WAITs, but it did program successfully. I only got 36 kilobytes per second, a poor comparison to the 135 I managed earlier in direct mode, but at least it worked. The other target in the multitarget chain doesn’t seem to be working so well, but I will leave further investigation there until the big event handler multitarget brokenness stuff is fixed (I intend to try out the pending patches but have not had time yet). By the way, where did the clock/6 come from? I don’t think I saw it in the ADI spec, the Cortex-M7 user guide or reference manual, or the F7 reference manual or datasheet. Just curious. Side note, I saw that the F4 config file sets the upper four bits of RCC_PLLCFGR to zero, but the reference manual says they should be kept at their reset value and that the reset value of the register is 0x24003010. Maybe it doesn’t matter, but what if ST put something important but not user-pokable there? -- Christopher Head
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