On February 27, 2018 1:28:01 AM PST, Freddie Chopin <freddie_cho...@op.pl> wrote: >5.3.13 Memory characteristics >Table 48. Flash memory programming >(numbers don't have to match your version of datasheet exactly)
Oh, that is very interesting. I missed that table the first time. When I looked at the reference manual, the table in there makes it look like it could be unsafe to use too small a parallelism setting (e.g. 16× at 3.3V might damage the Flash), but the datasheet suggests it’s fine. And yes, it seems they contradict in that the RM says 32×@3.3 is optimal while the DS says it is prohibited. Regardless, I think we should just let the board file choose. Any objections to using the bus width number for this purpose? I was thinking we could use the chip width parameter in future to support STM32H7, where writes have to be 128 bits wide in order to prevent ECC errors—we could set chip width to 1 for F2/F4/F7 and 16 for H7, and the Flash code could recognize that difference and act accordingly; meanwhile bus width could be 1, 2, 4, or 8 to set the parallelism. -- Christopher Head
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