Not saying it isn't valid, just saying that when single-layer pads were introduced, it was for the purpose of using them new-fangled SMT components, and them thangs don't need no holes! Vias, located somewhere else, provide interplane connectivity...
However, it does stand to reason that iff a designer has specified a defacto single layer pad (though defined as multilayer), then the DRC should route around the feature to the limits of a given layer's pad specification. In that vein, what Steve H. was saying about appropriately sizing the pads to the same size as the desired hole is a more sound method than mine, because the autorouting operation would route an embedded layer's tracks away from the copper collar formed by the via if a layer's pad were the same size as the drill hole, whereas it might route through the space the hole will eventually occupy if my method was used. I admit, I rarely if ever use the autorouter, so that sort of a situation isn't something I usually pay attention to, but it's a good thing to learn the easy way, as opposed to the hard... I personally have never had any problems with my method, but I'm a big enough man to admit that I can see the hole in it... On the topic of software restricting what you can and can't do...I think I'll leave that to PCAD and ORCad and be happy that Protel allows the designer to choose to violate zie rules at his/her discretion, instead of dictating what I can and can't do. Nothing worse for productivity to a c5reator than working in someone else's tight little box. aj >-----Original Message----- >From: [EMAIL PROTECTED] >[mailto:[EMAIL PROTECTED] On Behalf Of Brooks,Bill >Sent: Monday, October 24, 2005 3:42 PM >To: 'Protel EDA Discussion List' >Subject: RE: [PEDA] Strange feature.. DRC misses an error condition. > >Actually a top side pad with a plated hole that has no pad on >the back side is a valid condition... if the software will let >you define it as such. >So DRC should check the clearance of the plated hole to planes >in the board and traces on inner layers or the back of the >board if you have a reason to define this sort of structure. >Otherwise, the software should restrict the use of such structures. > > I have heard of one and a half sided boards, meaning single >sided and plated through... This was done by some companies in >the past to avoid damage to the back side pads during auto >insertion of axial and radial leaded parts... the leads would >sometimes catch on the inner side of the pads near the hole >when the lead was forced into the hole by machines from the >top side and would rip the pad off the back of the board. The >plating protected the back side pad and the customer didn't >want pads on the top because they would short to components or >violate voltage spacing... > >DRC should be able to detect any traces that short to a plated >thru hole... >or violate voltage spacing from a plated through hole...and >not just a pad. > >My 2 cents... > >Bill Brooks > > >-----Original Message----- >From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] >Sent: Monday, October 24, 2005 11:03 AM >To: [email protected] >Subject: RE: [PEDA] Strange feature.. DRC misses an error condition. > >My memory as well...by design, single-layer pads were >considered to be SMT components, as therefore use of a hole >with such a pad was considered non-sequitur (illogical). >Frankly, I don't think it's a bug, at least for the time in >which single-layer pads were introduced to Protel, back when >microvias were little more than a twinkle in the IC designers eyes. > >Instead, the logical thing to do is place a multi-layer pad, >define the desired hole size, and define all unused pad layers >to a diameter of zero (0) for pad width. > >Since hole plating is executed only after the drill operation >has been completed, any hole defined as a plated hole will be >left unmasked and so will become plated. > >If plating of the hole is undesired, a note in your >instructions should be sufficient to avoid plating. > >aj > > > > >____________________________________________________________ >You are subscribed to the PEDA discussion forum > >To Post messages: >mailto:[email protected] > >Unsubscribe and Other Options: >http://techservinc.com/mailman/listinfo/peda_techservinc.com > >Browse or Search Old Archives (2001-2004): >http://www.mail-archive.com/[email protected] > >Browse or Search Current Archives (2004-Current): >http://www.mail-archive.com/[email protected] > > This e-mail transmission and its attachments may contain information from Avtron Manufacturing, Inc. that is proprietary, privileged and/or confidential and is intended exclusively for the person(s) to whom it is addressed. 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