My memory as well...by design, single-layer pads were considered to be
SMT components, as therefore use of a hole with such a pad was
considered non-sequitur (illogical). Frankly, I don't think it's a bug,
at least for the time in which single-layer pads were introduced to
Protel, back when microvias were little more than a twinkle in the IC
designers eyes.

Instead, the logical thing to do is place a multi-layer pad, define the
desired hole size, and define all unused pad layers to a diameter of
zero (0) for pad width. 

Since hole plating is executed only after the drill operation has been
completed, any hole defined as a plated hole will be left unmasked and
so will become plated. 

If plating of the hole is undesired, a note in your instructions should
be sufficient to avoid plating.

aj


>-----Original Message-----
>From: [EMAIL PROTECTED] 
>[mailto:[EMAIL PROTECTED] On Behalf Of Abd ulRahman Lomax
>Sent: Monday, October 24, 2005 12:16 PM
>To: Protel EDA Discussion List
>Subject: Re: [PEDA] Strange feature.. DRC misses an error condition.
>
>At 12:20 PM 10/21/2005, Brooks,Bill wrote:
>>We had a part mis-defined with a PAD that was a 'toplayer' pad (not a 
>>'multilayer pad') that had a drill hole defined in it... not on 
>>purpose, but by accident.
>>
>>Now DRC did not pick up any shorts with planes or traces 
>running under 
>>this pad [...] Has anyone ever run across this before?
>
>I do recall there being error conditions with single-layer 
>pads with holes. It appears that the programmers designed 
>single-layer pads to not have holes, an easy mistake to make. 
>If you wanted to put a hole in a single-layer pad (for 
>example, for microvias-in-pad), you would place an extra pad, 
>multilayer, with the hole. Because the hole does exist on 
>other layers, it is an error to define the pad as being Top or 
>Bottom. But an easy one to make; it could be argued that the 
>programmers should have made it impossible to create this 
>condition, using an error dialog ("which do you want, a hole 
>or a single-layer pad with no hole"), and also a default 
>design rule that can't be turned off (there are a few of 
>these), to deal with imports containing this little beastie.
>
>Or, if you really do want a single-layer pad with a hole and 
>that's that, as long as the hole being in the center of the 
>pad is okay, then you would use a multilayer pad with a 
>padstack, and defined the pads on the other layers to be 
>small. I'd still recommend making them larger than the hole, 
>just because I get nervous about DRC's ability to correctly 
>measure clearances around such an animal. Whenever one strays 
>from common practice, there is a risk of running into a rare bug.
>
>In particular, holes are generally drilled 3 mils oversize or 
>so (diametric), and then plated back, so this reduces 
>clearance to hole metal by 1.5 mils as against the nominal 
>hole size, which is what Protel would know about. I've argued 
>in the past that DRC should factor for this, but I don't think 
>it ever has. (There would be a design rule specifying drill 
>oversize; it would be simple for this to be a default 1.5 mils 
>radial, and then this correction would always be applied to 
>holes for DRC purposes.)
>
>I'd think it possible to set up a design rule or rules to 
>detect any top/bottom layer pads with holes. It would take a 
>little experimenting, which I can't do right now.... Such a 
>rule could then become part of a standard design rule set.
>
>
>
> 
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