On 13/10/26 10:38, Peter Maydell wrote:
Implement the redirection of the ICC_CR0_EL1 encoding to the
hypervisor guest's view ICV_CR0_EL1. This has only one bit in it,
the enable (EN) bit, which is stored in ICH_VMCR_EL2.EN at the
same bit location (0).
Signed-off-by: Peter Maydell <[email protected]>
---
target/arm/tcg/gicv5-cpuif.c | 41 +++++++++++++++++++++++++-----------
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c
index b183c8a6e79..247cefd9e68 100644
--- a/target/arm/tcg/gicv5-cpuif.c
+++ b/target/arm/tcg/gicv5-cpuif.c
@@ -67,6 +67,9 @@ FIELD(ICC_HPPIR_EL1, ID, 0, 24)
FIELD(ICC_HPPIR_EL1, TYPE, 29, 3)
FIELD(ICC_HPPIR_EL1, HPPIV, 32, 1)
+FIELD(ICH_VMCR_EL2, EN, 0, 1)
+FIELD(ICH_VMCR_EL2, VMPR, 27, 5)
s/VMPR/VPMR/ "Virtual Priority Mask Register"
